Method for manufacturing package carrier, package carrier, and electronic device
By employing electroplating to fill through-holes and etching to remove the conductive layer during the manufacturing process of OLED display packaging substrates, the shear stress problem caused by grinding was solved, improving product yield and reducing costs, thus achieving a more efficient manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-24
AI Technical Summary
In the manufacturing process of existing OLED display products, the removal of the copper layer on the surface of the substrate body through grinding can easily generate large shear stress, resulting in low product yield and high cost.
After electroplating to fill the through-holes, the conductive layer on the substrate surface is removed by etching, avoiding the grinding process and ensuring the stability and precision of the connection structure and wiring structure.
It improved product process yield, reduced manufacturing costs, and improved the performance of the packaging substrate by reducing connection resistance through precise etching control.
Smart Images
Figure CN121729082A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to a method for manufacturing a packaging substrate, the packaging substrate, and an electronic device. Background Technology
[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.
[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention
[0004] To overcome the aforementioned shortcomings in the prior art, the purpose of this application is to provide a method for manufacturing a packaging carrier board, the method comprising: A substrate body is provided; the substrate body includes a first surface and a second surface disposed opposite to each other; A through hole is formed in the substrate body, extending from the first surface to the second surface; A first conductive layer is formed to fill the through-hole and cover at least a portion of the first surface and at least a portion of the second surface; The first conductive layer outside the via is removed by etching, forming a connection structure located within the via. A trace structure is formed on both sides of the substrate body, and the trace structure located at least partially on the first surface is electrically connected to the trace structure located at least partially on the second surface through the connection structure.
[0005] In some possible implementations, the step of forming a first conductive layer that fills the via and covers the first surface and the second surface includes: A first electroplating seed layer is formed, which covers at least a portion of the first surface, at least a portion of the second surface, and at least a portion of the inner wall of the through hole. A first conductive layer is formed by electroplating based on the first electroplating seed layer, filling the through hole and covering the first surface and the second surface; The step of forming wiring structures on both sides of the substrate body includes: A second electroplating seed layer is formed, which covers the side of the first electroplating seed layer away from the substrate body and covers the surface of the connection structure exposed from the through hole; Electroplating barrier layers covering at least a portion of the second electroplating seed layer are formed on both sides of the substrate body; each of the electroplating barrier layers on both sides of the substrate body includes a trace defining groove that exposes the second electroplating seed layer; the orthographic projection of the end of the through hole near the first surface on the first surface is located within the orthographic projection of the trace defining groove on the first surface on the substrate body; the orthographic projection of the end of the through hole near the second surface on the second surface is located within the orthographic projection of the trace defining groove on the second surface on the substrate body. Electroplating is performed on the second electroplating seed layer exposed by the wiring limiting groove to form a wiring structure located in the wiring limiting groove. The wiring structure located at least partially on the first surface side is electrically connected to the wiring structure located at least partially on the second surface side through the connection structure. Remove the electroplating barrier layer, and remove the first electroplating seed layer and the second electroplating seed layer that are not covered by the wiring structure.
[0006] In some possible implementations, the first electroplating seed layer includes an adhesion layer and an electroplating electrode layer; the step of forming the adhesion layer includes: An adhesive layer is formed that at least covers a portion of the first surface, a portion of the second surface, and the surface of the connection structure portion exposed at the through-hole; An electroplated electrode layer is formed covering the adhesion layer; the adhesion force between the adhesion layer and the substrate body is greater than the adhesion force between the electroplated electrode layer and the substrate body, and the conductivity of the electroplated electrode layer is greater than the conductivity of the adhesion layer. The step of removing the first conductive layer other than the via includes: Remove the first conductive layer outside the through hole and the electroplated electrode layer outside the through hole; The step of forming the second electroplating seed layer includes: A second electroplating seed layer is formed, covering the side of the adhesive layer away from the substrate body and covering the surface of the connection structure exposed from the through hole; the adhesion force between the adhesive layer and the substrate body is greater than the adhesion force between the second electroplating seed layer and the substrate body, and the conductivity of the second electroplating seed layer is greater than the conductivity of the adhesive layer. Preferably, the material of the adhesion layer includes titanium, the material of the electroplating electrode layer includes copper, and the material of the second electroplating seed layer includes copper.
[0007] In some possible implementations, the step of removing the first conductive layer other than the via includes: The first conductive layer outside the via is etched away, and at least a portion of the first conductive layer located within the via is also removed.
[0008] In some possible implementations, the step of etching away the first conductive layer outside the via and removing at least a portion of the first conductive layer within the via includes: The first conductive layer is etched in a first stage using a first etching solution, and then the first conductive layer is etched in a second stage using a second etching solution. The etching rate of the first conductive layer by the first etching solution is greater than the etching rate of the first conductive layer by the second etching solution. Preferably, the first etching solution comprises a mixture of phosphoric acid and hydrogen peroxide; the second etching solution comprises an organic acid etching solution; Preferably, the etching rate of the first etching solution on the first conductive layer is 200 A / s to 300 A / s; and the etching rate of the second etching solution on the first conductive layer is 50 A / s to 100 A / s.
[0009] In some possible implementations, the step of forming electroplating barrier layers covering at least a portion of the second electroplating seed layer on both sides of the substrate body includes: Dry film photoresist is prepared on the side of the second electroplating seed layer away from the substrate body; The dry film photoresist is exposed and developed to form the trace defining groove.
[0010] In some possible implementations, the thickness of the trace structure is 18 to 22 micrometers in the direction away from the substrate body.
[0011] Another object of this application is to provide a packaging carrier board, which is manufactured by the packaging carrier board manufacturing method provided in this application.
[0012] Another object of this application is to provide a packaging carrier board, the packaging carrier board comprising: A substrate body, the substrate body including a first surface and a second surface disposed opposite to each other, the substrate body including a through hole extending from the first surface to the second surface; The connection structure located within the through hole and the trace structure located on both sides of the substrate body, wherein at least part of the trace structure located on the first surface side is electrically connected to at least part of the trace structure located on the second surface side through the connection structure; The packaging carrier also includes an adhesive layer comprising a first portion and a second portion. The first portion of the adhesive layer is located between the inner wall of the through hole and the connection structure, and the second portion of the adhesive layer is located between the trace structure and the surface of the substrate body. The second portion of the adhesive layer is connected to the first portion and exposes the connection structure located within the through hole.
[0013] Another object of this application is to provide an electronic device that includes the packaging substrate provided in this application, or includes a packaging substrate made by the manufacturing method of the packaging substrate provided in this application.
[0014] Compared with the prior art, this application has the following beneficial effects: The packaging substrate manufacturing method, packaging substrate, and electronic device provided in this application involve electroplating and filling the through-holes on both sides of a glass through-hole substrate, followed by etching to remove the first conductive layer on the substrate surface. Compared to methods that generate significant shear stress when removing the first conductive layer on the substrate surface through grinding, the method provided in this application eliminates the need for grinding, effectively improving product process yield and reducing costs. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic flowchart illustrating the steps of the manufacturing method for the packaging carrier provided in this embodiment; Figure 2 This is one of the schematic diagrams illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 3 This is the second schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 4 This is the third schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 5 This is the fourth schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 6 Fifth of a series of schematic diagrams illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 7 This is a schematic diagram of the wiring limiting groove of the packaging carrier provided in this embodiment; Figure 8This is the sixth schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 9 This is the seventh schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 10 This is a top view of the packaging carrier provided in this embodiment; Figure 11 This is a cross-sectional schematic diagram of the packaging carrier provided in this embodiment.
[0017] Icons: 110 - Substrate body; 1101 - Through hole; 120 - First electroplating seed layer; 121 - Adhesion layer; 1211 - First part; 1212 - Second part; 122 - Electroplating electrode layer; 130 - First conductive layer; 140 - Second electroplating seed layer; 150 - Electroplating barrier layer; 1501 - Trace limiting groove; 201 - Connection structure; 202 - Trace structure. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.
[0023] In some chip packaging structures, in order to enable the chips and circuits on both sides of the packaging substrate to be interconnected, through-glass vias (TGVs) are formed through the substrate body by laser or etching, and wiring structures are formed on the surface of the substrate body at both ends of the TGVs. The wiring structures on both sides are connected by the metal filled in the TGVs.
[0024] The inventors discovered that in some related technologies, the manufacturing process of a glass through-hole encapsulation substrate usually involves first creating through-holes on the substrate body, then forming a copper layer in the through-holes and on the surface of the substrate body through electroplating, then removing the copper layer on the surface of the substrate body through grinding, and finally creating a wiring structure on the substrate surface.
[0025] When removing the copper layer from the surface of the substrate by grinding, the grinding action will generate large shear stress. With masks required on both sides of the substrate, the risk of breakage of the packaging carrier is high and the product yield is low.
[0026] In view of this, this embodiment provides a solution that can improve the yield of TGV process packaging substrate manufacturing. The solution provided in this embodiment will be described in detail below.
[0027] Please see Figure 1 , Figure 1 This embodiment provides a method for manufacturing a packaging carrier board, which may include the following steps.
[0028] Step S110: Provide a substrate body 110. The substrate body 110 may include a first surface and a second surface disposed opposite to each other.
[0029] In this embodiment, please refer to Figure 2 The material of the substrate body 110 may include glass.
[0030] In step S120, a through hole 1101 is formed in the substrate body 110, extending from the first surface to the second surface.
[0031] Alternatively, in some possible implementations, the via 1101 can be formed by laser-induced etching.
[0032] Specifically, in step S120, the substrate body 110 can first be patterned by laser irradiation, causing localized modification of the glass material in the substrate body 110 in areas irradiated by the laser relative to areas not irradiated by the laser. Then, the modified areas are etched using hydrofluoric acid (HF) or potassium hydroxide (KOH) solution. Due to the difference in chemical activity between the modified and unmodified areas, anisotropic etching can be achieved during the etching process, removing the modified areas and forming the through hole 1101.
[0033] In other possible implementations, through-hole 1101 can also be formed by laser melting, focused discharge, plasma etching or electrochemical discharge machining.
[0034] Step S130: A first conductive layer 130 is formed to fill the via 1101 and cover at least a portion of the first surface and at least a portion of the second surface.
[0035] In this embodiment, the first conductive layer 130 can be formed by electroplating. The first conductive layer 130 can fill the through hole 1101 and cover the first and second surfaces of the substrate body 110.
[0036] In step S140, the first conductive layer 130 outside the via 1101 is removed by etching to form a connection structure 201 located within the via 1101.
[0037] In this embodiment, please refer to Figure 3 The first conductive layer 130 can be thinned by wet etching, thereby removing the first conductive layer 130 outside the via 1101 and retaining the first conductive layer 130 inside the via 1101 as the connection structure 201.
[0038] In step S150, wiring structures 202 are formed on both sides of the substrate body 110. The wiring structure 202 located at least partially on the first surface is electrically connected to the wiring structure 202 located at least partially on the second surface through the connection structure 201.
[0039] Based on the above design, compared with the solution that generates large shear stress when removing the first conductive layer 130 on the surface of the substrate body 110 by grinding, the packaging carrier fabrication method provided in this embodiment does not require grinding when removing the first conductive layer 130 on the surface of the substrate body 110, which can effectively improve the product process yield and reduce costs.
[0040] In some possible implementations, both the connection structure 201 and the wiring structure 202 can be formed by electroplating. Before electroplating, a seed layer for electroplating as an electroplating electrode needs to be formed first.
[0041] Specifically, step S130 may include the following sub-steps.
[0042] Step S131: A first electroplating seed layer 120 is formed, which covers at least a portion of the first surface, at least a portion of the second surface, and the inner wall of the through hole 1101.
[0043] Please see Figure 4 In this embodiment, the first electroplating seed layer 120 can be sputtered by physical vapor deposition (PVD). The first electroplating seed layer 120 covering the inner wall of the through hole 1101, the first electroplating seed layer 120 covering the first surface, and the first electroplating seed layer 120 covering the second surface are interconnected.
[0044] Step S132: Electroplating a first conductive layer 130 to form a filled through-hole 1101 and cover the first and second surfaces based on the first electroplating seed layer 120.
[0045] Please see Figure 5 In this embodiment, taking copper as the material of the first conductive layer 130, the electroplating seed layer can be used as the electroplating cathode, and the electrode containing metallic copper can be used as the anode. When energized, the copper atoms of the anode lose electrons and become copper ions that dissolve into the solution. The copper ions in the solution containing copper ions gain electrons on the electroplating seed layer, which is the cathode, and undergo a reduction reaction, thereby reducing the copper ions to copper atoms and gradually depositing them on the surface of the electroplating seed layer.
[0046] In step S132, the deposited copper gradually fills the via 1101 and covers the first electroplating seed layer 120 located on the first and second surfaces.
[0047] Next, after the first conductive layer 130 of the first surface and the second surface is removed by etching in step S140, the first electroplating seed layer 120 of the first surface and the second surface will be exposed, and the two ends of the connection structure 201 formed in the through hole 1101 will also be exposed.
[0048] Then, step S150 may include the following sub-steps.
[0049] In step S151, a second electroplating seed layer 140 is formed. The second electroplating seed layer 140 covers the side of the first electroplating seed layer 120 away from the substrate body 110 and covers the surface of the connection structure 201 exposed from the through hole 1101.
[0050] Please see again Figure 5In step S151, a second electroplating seed layer 140 can be formed by physical vapor deposition. The second electroplating seed layer 140 will cover the first electroplating seed layer 120 and the exposed ends of the connecting structure 201.
[0051] In step S152, electroplating barrier layers 150 covering at least a portion of the second electroplating seed layer 140 are formed on both sides of the substrate body 110. The electroplating barrier layers 150 on both sides of the substrate body 110 may include trace defining grooves 1501 that expose the second electroplating seed layer 140. The orthographic projections of both ends of the through hole 1101 on the first surface are within the orthographic projection of the trace defining groove 1501 on the substrate body 110.
[0052] That is, the orthographic projection of the end of the through hole 1101 near the first surface on the first surface is located within the orthographic projection of the trace limiting groove 1501 on the first surface on one side of the first surface, and the orthographic projection of the end of the through hole 1101 near the second surface on the second surface is located within the orthographic projection of the trace limiting groove 1501 on the second surface on one side of the second surface.
[0053] Optionally, please see Figure 6 In this embodiment, a dry film photoresist is prepared on the side of the second electroplating seed layer 140 away from the substrate body 110, that is, dry film photoresist is attached to both sides of the substrate body 110. Then, the dry film photoresist is exposed and developed to form a trace defining groove 1501. The trace defining groove 1501 is used to define the position of the trace structure 202 formed in the subsequent electroplating process.
[0054] Please see below. Figure 7 Since the trace structure 202 located on the first surface and the trace structure 202 located on the second surface are electrically connected through the connection structure 201 located in the through hole 1101, the orthographic projection of the trace limiting groove 1501 located on the first surface or the second surface at least partially on both sides of the substrate body 110 at least partially coincides with the orthographic projection of the same through hole 1101 on the first surface or the second surface.
[0055] It should be noted that, in this embodiment, in order to ensure that the subsequent formed trace structure 202 can make stable contact with the connection structure 201, the width of the trace limiting groove 1501 in the direction parallel to the substrate body 110 needs to be greater than the width of the through hole 1101.
[0056] By setting the patterned shape of the trace limiting groove 1501, a connection area can be formed at the position where the trace structure 202 needs to be connected to the connection structure 201. In the direction parallel to the substrate body 110, the area of the orthographic projection of the connection area on the first surface or the second surface is greater than the area of the orthographic projection of the through hole 1101 on the first surface or the second surface.
[0057] In step S153, a wiring structure 202 located within the wiring limiting groove 1501 is formed by electroplating the second electroplating seed layer 140 exposed by the wiring limiting groove 1501. The wiring structure 202 located at least partially on the first surface side is electrically connected to the wiring structure 202 located at least partially on the second surface side through the connection structure 201.
[0058] In this embodiment, the second electroplating seed layer 140 can be used as the electroplating cathode, and the wiring structure 202 can be formed in the wiring limiting groove 1501 by electroplating.
[0059] Specifically, since the electroplating barrier layer 150 covers part of the surface of the second electroplating seed layer 140, the second electroplating seed layer 140 covered by the electroplating barrier layer 150 will not come into contact with the solution containing copper ions, and therefore will not deposit metal during the electroplating process; while the second electroplating seed layer 140 exposed through the trace defining groove 1501 will come into contact with the solution containing copper ions, and therefore metal can be deposited in the trace defining groove 1501 to form the trace structure 202.
[0060] In this embodiment, the wiring structure can be formed simultaneously on the first and second surfaces by electroplating in the same step. This reduces the manufacturing process, improves manufacturing efficiency, and lowers manufacturing costs.
[0061] Step S154: Remove the electroplating barrier layer 150, and remove the first electroplating seed layer 120 and the second electroplating seed layer 140 that are not covered by the trace structure 202.
[0062] In this embodiment, after the trace structure 202 is formed by electroplating, the electroplating barrier layer 150 can be removed, and then the first electroplating seed layer 120 and the second electroplating seed layer 140 not covered by the trace structure 202 can be removed by etching, so that the trace structures 202 will not be short-circuited to each other.
[0063] In some possible implementations, in order to ensure the adhesion between the electroplating seed layer and the substrate body 110 and to ensure that the electroplating seed layer has good conductivity, the first electroplating seed layer 120 may include an adhesion layer 121 and an electroplating electrode layer 122.
[0064] Please see Figure 8 In step S131, an adhesion layer 121 may be formed first, covering at least a portion of the first surface, a portion of the second surface, and a portion of the surface of the connection structure 201 exposed at the through hole 1101, and then an electroplated electrode layer 122 covering the adhesion layer 121 may be formed.
[0065] The adhesion force between the adhesive layer 121 and the substrate body 110 is greater than the adhesion force between the electroplated electrode layer 122 and the substrate body 110, and the conductivity of the electroplated electrode layer 122 is greater than the conductivity of the adhesive layer 121. Optionally, the stability of the adhesive layer 121 is greater than the stability of the electroplated electrode layer 122, that is, the etching resistance of the adhesive layer 121 is greater than the etching resistance of the electroplated electrode layer 122. For example, the material of the adhesive layer 121 may include titanium, and the material of the electroplated electrode layer 122 may include copper.
[0066] Thus, by first setting an adhesive layer 121 with good adhesion, the bonding force between the entire first electroplating seed layer 120 and the substrate body 110 can be guaranteed, preventing the first electroplating seed layer 120 from falling off. Then, an electroplating electrode layer 122 with good conductivity is set on the adhesive layer 121, which can ensure the overall conductivity of the entire first electroplating seed layer 120, so that metal can be deposited more quickly on the surface of the first electroplating seed layer 120 during the subsequent electroplating process.
[0067] In step S140, while the first conductive layer 130 outside the via 1101 is removed by etching, the electroplated electrode layer 122 outside the via 1101 is also removed. However, since the material of the adhesion layer 121 is different from that of the electroplated electrode layer 122, by selecting a suitable etching solution, the adhesion layer 121 can be retained while etching the first conductive layer 130 and the electroplated electrode layer 122.
[0068] In step S151, a second electroplating seed layer 140 may be formed covering the side of the adhesion layer 121 away from the substrate body 110 and covering the surface of the connection structure 201 exposed from the through hole 1101. That is, the second electroplating seed layer 140 is formed based on the adhesion layer 121.
[0069] Please see Figure 9 The second electroplating seed layer 140 covers the adhesion layer 121 located on the first and second surfaces, and covers the two ends of the connection structure 201 exposed from the through hole 1101.
[0070] The adhesion force between the adhesive layer 121 and the substrate body 110 is greater than the adhesion force between the second electroplating seed layer 140 and the substrate body 110, and the conductivity of the second electroplating seed layer 140 is greater than the conductivity of the adhesive layer 121.
[0071] For example, the material of the adhesion layer 121 may include titanium, and the material of the second electroplating seed layer 140 may include copper.
[0072] Thus, in the prior art, the method of removing the surface copper layer by grinding is difficult to control the grinding depth precisely, and can only remove the electroplating electrode layer 122 and the adhesion layer 121 in the electroplating seed layer at the same time. However, in this embodiment, the etching method can precisely remove only the electroplating electrode layer 122 and retain the adhesion layer 121. Therefore, when setting the electroplating seed layer for the second time, it is not necessary to set the adhesion layer 121 again, which reduces the process difficulty and saves manufacturing costs.
[0073] Furthermore, the two ends of the connection structure 201 will no longer be covered with the adhesion layer 121, and the connection structure 201 with better conductivity, the second electroplating seed layer 140 and the wiring structure 202 can directly contact each other, thereby effectively reducing the connection resistance.
[0074] See also some possible implementations. Figure 5 or Figure 8 In step S140, a slight over-etching method can be used to ensure that the first conductive layer 130 on the first and second surfaces is completely removed. In this case, the first conductive layer 130 located in the via 1101 may also be partially removed. By controlling the etching time, the depth to which the first conductive layer 130 located in the via 1101 is etched away can be controlled. The depression formed at this location due to the removal of the first conductive layer 130 can be filled by the subsequently formed second electroplating seed layer 140 and wiring structure 202.
[0075] In some possible implementations, in step S140, a first etching solution can be used to perform a first stage etching on the first conductive layer 130, and then a second etching solution can be used to perform a second stage etching on the first conductive layer 130. The etching rate of the first etching solution on the first conductive layer 130 is greater than the etching rate of the second etching solution on the first conductive layer 130.
[0076] Optionally, the first etching solution may include a mixture of phosphoric acid and hydrogen peroxide; the second etching solution may include an organic acid etching solution.
[0077] Optionally, the etching rate of the first etchant on the first conductive layer 130 is 200 A / s to 300 A / s; and the etching rate of the second etchant on the first conductive layer 130 is 50 A / s to 100 A / s.
[0078] Therefore, by first using an etching solution with a high etching rate, etching efficiency can be guaranteed, and then using an etching solution with a lower etching rate, the etching depth can be precisely controlled.
[0079] In this embodiment, the first conductive layer 130 formed by electroplating in step S130 needs to completely fill the through hole 1101. Therefore, the thickness of the first conductive layer 130 is usually large. Furthermore, since the conductive layer 130 is simultaneously electroplated on the first surface, the second surface, and inside the through hole, the flatness of the conductive layer 130 at the opening of the through hole may differ significantly from the flatness at other locations on the first and second surfaces. Therefore, the first conductive layer 130 formed by electroplating in step S130 cannot be directly used to form the wiring structure 202. Therefore, in this embodiment, the first conductive layer 130 located on the first and second surfaces needs to be removed in sub-step S140, and then a wiring structure 202 with a smaller thickness and better flatness is formed in step S150.
[0080] In some possible implementations, the thickness of the trace structure 202 in the direction away from the substrate body 110 is 18 micrometers to 22 micrometers. For example, the thickness of the trace structure 202 is 19 micrometers, 20 micrometers, or 21 micrometers.
[0081] In this embodiment, the connection structure 201 and the wiring structure 202 are formed by two electroplating processes, which can ensure that the connection structure 201 can completely fill the through hole 1101, and also ensure that the wiring structure 202 is not too thick, thus affecting the subsequent film layer setting.
[0082] In some possible implementations, after step S150, a first rewiring structure layer and a second rewiring structure layer may also be formed; the first rewiring structure layer is located on the side of the first surface away from the second surface, and at least a portion of the first rewiring traces in the first rewiring structure layer are in contact with the trace structure 202 located on the first surface; the second rewiring structure layer is located on the side of the second surface away from the first surface, and at least a portion of the second rewiring traces in the second rewiring structure layer are in contact with the trace structure 202 located on the second surface.
[0083] Specifically, the first rewiring structure layer may include at least one first insulating layer and at least one first rewiring trace layer. The first insulating layer may be formed on the side of the first trace structure away from the substrate body 110. Then, a through-hole is formed that penetrates the first insulating layer and exposes at least a portion of the trace structure located on the first surface. Finally, the first rewiring structure layer is formed on the side of the first insulating layer away from the substrate body 110, with at least a portion of the first rewiring traces in the first rewiring structure layer extending into the through-hole and contacting the first traces.
[0084] By analogy, the first insulation layer and the first rewiring can be set layer by layer to form a multi-layer rewiring structure.
[0085] The second rewiring structure layer may include at least one second insulating layer and at least one second rewiring trace layer. The second insulating layer may be first formed on the side of the second trace structure away from the substrate body 110. Then, a third via is formed that penetrates the second insulating layer and exposes at least a portion of the trace structure located on the second surface. Finally, the second rewiring structure layer is formed on the side of the second insulating layer away from the substrate body 110, with at least a portion of the second rewiring traces in the second rewiring structure layer extending into the third via and contacting the second traces.
[0086] Similarly, a second insulation layer and a second layer of wiring can be set up layer by layer to form a multi-layer rewiring structure.
[0087] Optionally, the first insulating layer and the second insulating layer can be formed by methods such as lamination or coating.
[0088] The first and second layers of wiring can be formed through processes such as PVD sputtering, resist coating, photolithography, development, electroplating, resist removal, and etching. The materials for the first and second layers of wiring can include at least one of copper, aluminum, nickel, and silver.
[0089] In some possible implementations, solder mask layers may be formed on the side of the first wiring structure layer away from the substrate body 110 and on the side of the second wiring structure layer away from the substrate body 110, respectively, and the solder mask layers may be etched to form solder openings that expose at least a portion of the first wiring traces or the second wiring traces.
[0090] Next, the first and second layer wiring traces exposed by the solder opening are surface treated to form a surface trimming section. The materials for the surface trimming section may include organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel and electroless palladium immersion gold (ENEPIG), chemical tin (chemical and electroplating), etc.
[0091] Finally, solder ball bumps can be formed within the soldering opening. For the side of the package substrate that needs to connect to other printed circuit boards, the material for the solder ball bumps can include tin, tin-silver alloy, a mixture of copper and tin-silver alloy, or a mixture of copper, nickel, and tin-silver alloy. For the side of the package substrate that needs to connect to the chip, the fabrication process for forming the solder ball bumps can use the C4 (Controlled Collapse Chip Connection) process, or copper pillars can be formed instead of solder ball bumps.
[0092] This embodiment also provides a packaging carrier board, which can be manufactured using the packaging carrier board manufacturing method provided in this embodiment.
[0093] This embodiment also provides a packaging carrier board; please refer to [link / reference]. Figure 10 and Figure 11 , Figure 11 for Figure 10 The cross-sectional view at position II shown in the figure indicates that the packaging carrier provided in this embodiment may include a substrate body 110, a connection structure 201, and a wiring structure 202.
[0094] The substrate body 110 may include a first surface and a second surface disposed opposite to each other, and the substrate body 110 may include a through hole 1101 extending from the first surface to the second surface.
[0095] In this embodiment, the material of the substrate body 110 may include glass. The through hole 1101 may be formed by laser-induced wet etching; or the through hole 1101 may also be formed by laser melting, focused discharge, plasma etching, electrochemical discharge processing, etc., and no specific limitation is made in this embodiment.
[0096] The connection structure 201 is located inside the through hole 1101, and the trace structure 202 is located on both sides of the substrate body 110. The trace structure 202 located at least partially on the first surface is electrically connected to the trace structure 202 located at least partially on the second surface through the connection structure 201.
[0097] The packaging substrate may also include an adhesive layer 121, which may include a first portion 1211 and a second portion 1212. The first portion 1211 of the adhesive layer 121 is located between the inner wall of the through hole 1101 and the connection structure 201. The second portion 1212 of the adhesive layer 121 is located between the wiring structure 202 and the surface of the substrate body 110. The second portion 1212 of the adhesive layer 121 is connected to the first portion 1211 and exposes the connection structure 201 located in the through hole 1101.
[0098] For example, the encapsulation substrate may also include a first electroplating seed layer 120 and a second electroplating seed layer 140. The first electroplating seed layer 120 may include an adhesive layer 121 and an electroplating electrode layer 122. The adhesive layer 121 may include a first portion 1211 and a second portion 1212. The first portion 1211 of the adhesive layer 121 and the electroplating electrode layer 122 are located between the inner wall of the through hole 1101 and the connection structure 201. The electroplating electrode layer 122 wraps the connection structure 201, and the first portion 1211 of the adhesive layer 121 wraps the electroplating electrode layer 122.
[0099] The second portion 1212 of the adhesion layer 121 and the second electroplating seed layer 140 are located between the surface of the wiring structure 202 and the substrate body 110 and are stacked in a direction away from the substrate body 110. The second portion 1212 of the adhesion layer 121 is connected to the first portion 1211 and exposes the connection structure 201 located in the through hole 1101. The second electroplating seed layer 140 is in contact with the connection structure 201.
[0100] The electroplated electrode layer 122, the second electroplating seed layer 140, the wiring structure 202, and the connection structure 201 are made of the same material. In this way, the connection structure 201, the second electroplating seed layer 140, and the wiring structure 202, which have good conductivity, are in direct contact, which can reduce the connection resistance.
[0101] In some possible implementations, the material of the adhesion layer 121 may include titanium, and the materials of the electroplated electrode layer 122, the second electroplating seed layer 140, the wiring structure 202, and the connection structure 201 may include copper.
[0102] In some possible implementations, the thickness of the trace structure 202 in the direction away from the substrate body 110 is 18 micrometers to 22 micrometers. For example, the thickness of the trace structure 202 is 19 micrometers, 20 micrometers, or 21 micrometers.
[0103] In some possible implementations, the packaging carrier provided in this embodiment may also include a first rewiring structure layer and a second rewiring structure layer.
[0104] The first routing structure layer is located on the side of the first surface away from the second surface, and at least a portion of the first routing traces in the first routing structure layer are in contact with the routing structure 202 located on the first surface; the second routing structure layer is located on the side of the second surface away from the first surface, and at least a portion of the second routing traces in the second routing structure layer are in contact with the routing structure 202 located on the second surface.
[0105] For example, the first rewiring structure layer may include at least one first insulating layer and at least one first rewiring trace layer, wherein the at least one first rewiring trace layer is electrically connected to the trace structure located on the first surface through a through-hole penetrating the at least one first insulating layer. Multiple first rewiring trace layers and multiple first insulating layers may cooperate to form a multilayer rewiring structure.
[0106] The second rewiring structure layer may include at least one second insulating layer and at least one second rewiring trace layer. The at least one second rewiring trace layer is electrically connected to the trace structure located on the second surface through a through-hole penetrating the at least one second insulating layer. Multiple second rewiring trace layers and multiple second insulating layers can be combined to form a multi-layer rewiring structure.
[0107] In some possible implementations, a solder mask layer may be provided on the side of the first rewiring structure layer away from the substrate body 110 and the side of the second rewiring structure layer away from the substrate body 110, respectively. The solder mask layer may include solder joint openings that expose at least a portion of the first rewiring traces and / or the second rewiring traces. Solder ball bumps or copper pillars may also be provided in at least a portion of the solder joint openings.
[0108] In this embodiment, the first and second rewiring structure layers can be subsequently used to connect with other circuit boards and chips, thereby enabling the rewiring or connection of the corresponding chip pins.
[0109] Another object of this application is to provide an electronic device that includes the packaging substrate provided in this application, or includes a packaging substrate made by the manufacturing method of the packaging substrate provided in this application.
[0110] The electronic device may also include at least one chip, which is electrically connected to other chips or other circuit structures via the packaging substrate provided in this embodiment.
[0111] In summary, the packaging substrate manufacturing method, packaging substrate, and electronic device provided in this application involve double-sided electroplating to fill the through-holes in a glass through-hole substrate, followed by etching to remove the surface copper layer. Compared to methods that remove the surface copper layer by grinding, which generates significant shear stress, the solution provided in this application eliminates the need for grinding, effectively improving product process yield and reducing costs.
[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0113] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A method for manufacturing a packaging carrier board, characterized in that, The method includes: A substrate body is provided; the substrate body includes a first surface and a second surface disposed opposite to each other; A through hole is formed in the substrate body, extending from the first surface to the second surface; A first conductive layer is formed to fill the through-hole and cover at least a portion of the first surface and at least a portion of the second surface; The first conductive layer outside the via is removed by etching, forming a connection structure located within the via. A trace structure is formed on both sides of the substrate body, and the trace structure located at least partially on the first surface is electrically connected to the trace structure located at least partially on the second surface through the connection structure.
2. The method according to claim 1, characterized in that, The step of forming a first conductive layer that fills the through-hole and covers the first surface and the second surface includes: A first electroplating seed layer is formed, which covers at least a portion of the first surface, at least a portion of the second surface, and at least a portion of the inner wall of the through hole. A first conductive layer is formed by electroplating based on the first electroplating seed layer, filling the through hole and covering the first surface and the second surface; The step of forming wiring structures on both sides of the substrate body includes: A second electroplating seed layer is formed, which covers the side of the first electroplating seed layer away from the substrate body and covers the surface of the connection structure exposed from the through hole; Electroplating barrier layers covering at least a portion of the second electroplating seed layer are formed on both sides of the substrate body; each of the electroplating barrier layers on both sides of the substrate body includes a trace defining groove that exposes the second electroplating seed layer, the orthographic projection of the end of the through hole near the first surface on the first surface is located within the orthographic projection of the trace defining groove on the first surface on one side of the first surface, and the orthographic projection of the end of the through hole near the second surface on the second surface is located within the orthographic projection of the trace defining groove on the second surface on one side of the second surface; Electroplating is performed on the second electroplating seed layer exposed by the wiring limiting groove to form a wiring structure located in the wiring limiting groove. The wiring structure located at least partially on the first surface side is electrically connected to the wiring structure located at least partially on the second surface side through the connection structure. Remove the electroplating barrier layer, and remove the first electroplating seed layer and the second electroplating seed layer that are not covered by the wiring structure.
3. The method according to claim 2, characterized in that, The first electroplating seed layer includes an adhesion layer and an electroplating electrode layer; the step of forming the adhesion layer includes: An adhesive layer is formed that at least covers a portion of the first surface, a portion of the second surface, and the surface of the connection structure portion exposed at the through-hole; An electroplated electrode layer is formed covering the adhesion layer; the adhesion force between the adhesion layer and the substrate body is greater than the adhesion force between the electroplated electrode layer and the substrate body, and the conductivity of the electroplated electrode layer is greater than the conductivity of the adhesion layer. The step of removing the first conductive layer other than the via includes: Remove the first conductive layer outside the through hole and the electroplated electrode layer outside the through hole; The step of forming the second electroplating seed layer includes: A second electroplating seed layer is formed, covering the side of the adhesive layer away from the substrate body and covering the surface of the connection structure exposed from the through hole; the adhesion force between the adhesive layer and the substrate body is greater than the adhesion force between the second electroplating seed layer and the substrate body, and the conductivity of the second electroplating seed layer is greater than the conductivity of the adhesive layer. Preferably, the material of the adhesion layer includes titanium, the material of the electroplating electrode layer includes copper, and the material of the second electroplating seed layer includes copper.
4. The method according to claim 1, characterized in that, The step of removing the first conductive layer other than the via includes: The first conductive layer outside the via is etched away, and at least a portion of the first conductive layer located within the via is also removed.
5. The method according to claim 1, characterized in that, The step of etching away the first conductive layer outside the via and removing at least a portion of the first conductive layer located within the via includes: The first conductive layer is etched in a first stage using a first etching solution, and then the first conductive layer is etched in a second stage using a second etching solution. The etching rate of the first conductive layer by the first etching solution is greater than the etching rate of the first conductive layer by the second etching solution. Preferably, the first etching solution comprises a mixture of phosphoric acid and hydrogen peroxide; the second etching solution comprises an organic acid etching solution; Preferably, the etching rate of the first etching solution on the first conductive layer is 200 A / s to 300 A / s; and the etching rate of the second etching solution on the first conductive layer is 50 A / s to 100 A / s.
6. The method according to claim 2, characterized in that, The step of forming electroplating barrier layers covering at least a portion of the second electroplating seed layer on both sides of the substrate body includes: Dry film photoresist is prepared on the side of the second electroplating seed layer away from the substrate body; The dry film photoresist is exposed and developed to form the trace defining groove.
7. The method according to claim 1, characterized in that, The thickness of the trace structure is 18 micrometers to 22 micrometers in the direction away from the substrate body.
8. A packaging carrier board, characterized in that, The encapsulation substrate is manufactured by the method described in any one of claims 1-7.
9. A packaging carrier board, characterized in that, The packaging carrier includes: A substrate body, the substrate body including a first surface and a second surface disposed opposite to each other, the substrate body including a through hole extending from the first surface to the second surface; The connection structure located within the through hole and the trace structure located on both sides of the substrate body, wherein at least part of the trace structure located on the first surface side is electrically connected to at least part of the trace structure located on the second surface side through the connection structure; The packaging carrier also includes an adhesive layer comprising a first portion and a second portion. The first portion of the adhesive layer is located between the inner wall of the through hole and the connection structure, and the second portion of the adhesive layer is located between the trace structure and the surface of the substrate body. The second portion of the adhesive layer is connected to the first portion and exposes the connection structure located within the through hole.
10. An electronic device, characterized in that, The electronic device includes the encapsulation substrate as described in claim 8 or 9, or the electronic device includes an encapsulation substrate made by the manufacturing method of the encapsulation substrate as described in any one of claims 1-7.
Citation Information
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