High-temperature-resistant gold-palladium alloy bump packaging method

Abstract

The invention relates to a high-temperature-resistant gold-palladium alloy bump packaging method, which comprises the following steps: S1, bump manufacturing: metal bumps are manufactured on the surface of a chip by adopting an electroplating mode, the metal bumps are made of gold-palladium alloy, then the chip with bumps is obtained by annealing, electroplating liquid comprises main salt, conductive salt, a film hardness regulator, a crystallization regulator and a pH regulator, and the metal bumps are prepared by adopting a high-temperature-resistant gold-palladium alloy bump packaging method; the main salt comprises potassium gold cyanide and potassium tetracyanopalladate, and the conducting salt comprises phosphate and oxalate; s2, manufacturing a bonding pad: preparing a substrate, and manufacturing the bonding pad of which the pattern is matched with that of the metal bump on the substrate; s3, inversely mounting the chip: enabling one surface of the bump of the chip to face a bonding pad on the substrate, and welding the metal bump and the bonding pad into a whole after the metal bump and the bonding pad are accurately aligned to obtain the substrate with the chip; and S4, bottom filling: filling glue is injected into a gap between the chip and the substrate along the edge of the chip, then the filling glue is baked and cured, and a product is obtained. According to the invention, the gold-palladium alloy bump with high hardness, fine grain structure and high-temperature stability is obtained.

Description

Technical Field

[0001] This invention relates to the field of electroplating technology, and in particular to a method for high-temperature resistant gold-palladium alloy bump packaging. Background Technology

[0002] In integrated circuit packaging technology, gold bump packaging is a manufacturing technology that uses gold bump bonding to replace wire bonding to achieve electrical interconnection between the chip and the substrate. It is an extension of the wafer manufacturing process and the basis and prerequisite for implementing flip chip (FC) packaging technology.

[0003] The flip-chip packaging process involves forming metal bumps on the chip's I / O pads, then creating a matching pad pattern on the substrate surface. The chip is flipped 180° so the bumps face down and precisely aligned with the substrate pads, then soldered together. Next, epoxy resin underfill is injected along the chip edge, filling the gap between the chip and substrate through capillary action. The underfill is then baked and cured. Finally, after outer layer encapsulation, slitting, surface treatment, and final testing, the individual packaged product is obtained. Some metal bumps are made of gold. Gold bump packaging offers advantages such as low resistance, low signal loss, and high current carrying capacity; however, gold is expensive, has relatively low hardness, and its manufacturing process is complex.

[0004] Chinese patent CN102677110A proposes a composite electroplating solution system containing gold and palladium salts, which forms a gold-palladium alloy coating through co-deposition, effectively reducing the amount of precious metal gold used and thus alleviating cost pressure to some extent. This technical solution does achieve controllable alloy deposition within a specific process window and initially demonstrates mechanical performance superior to pure gold bumps. However, as packaging technology evolves towards higher temperature tolerance, more stringent mechanical reliability, and finer geometric dimensions, the electrochemical deposition mechanism and microstructure characteristics upon which such traditional gold-palladium alloy coatings rely reveal deep-seated structural defects. Specifically, gold-palladium alloys obtained by conventional electroplating processes typically exhibit coarse columnar crystals or non-uniform polycrystalline structures with disordered grain boundaries and high residual stress. Simultaneously, due to the lack of effective control over grain refinement and phase structure, although the resulting coating achieves gold-palladium mixing in composition, its hardness improvement is extremely limited, generally failing to break through the 80HV engineering practicality threshold. This level of hardness makes the bump surface highly susceptible to scratches, deformation, and even localized fractures during subsequent packaging processes—especially in mechanical contact and thermal cycling processes such as wafer dicing, chip pick-and-place, and underfill curing. Such mechanical damage not only directly affects the geometric integrity of the bumps but also causes unexpected fluctuations in the contact interface resistance, leading to signal transmission distortion or uneven current distribution, and in severe cases, device failure. Fundamentally, the problem stems from the insufficient control of existing electroplating systems over the evolution of alloy microstructure: on the one hand, while traditional combinations of chelating agents and conductive salts can maintain plating solution stability, they cannot effectively inhibit abnormal grain growth; on the other hand, the lack of effective second-phase dispersion strengthening or solid solution strengthening mechanisms in the plating layer prevents the full release of palladium's solid solution strengthening potential. Consequently, even attempts to increase hardness by adjusting the gold-palladium ratio often result in a sharp decrease in ductility or a deterioration in plating efficiency, leading to a performance trade-off. Furthermore, without a targeted annealing process in the subsequent heat treatment stage, the alloy phase structure cannot achieve an ordered transformation, failing to form high-hardness intermetallic compounds or fine-grained strengthening structures, thus significantly diminishing the improvement in mechanical properties brought about by heat treatment. Therefore, without sacrificing electrical performance and process compatibility, the key to overcoming the current bottlenecks in flip-chip packaging technology lies in how to construct a gold-palladium alloy bump that combines high hardness, high thermal stability, and good microstructural uniformity through precise design of the electroplating solution composition and synergistic optimization of the heat treatment process.

[0005] Therefore, how to develop a high-temperature resistant gold-palladium alloy bump packaging method that can systematically control the microstructure of gold-palladium alloy bumps, significantly improve their hardness to above 90HV, and ensure that they maintain structural integrity during high-temperature packaging processes has become a key challenge and an urgent technical problem for those skilled in the art. Summary of the Invention

[0006] This invention provides a high-temperature resistant gold-palladium alloy bump packaging method, aiming to solve the problems of mechanical damage and electrical performance degradation caused by insufficient hardness, coarse microstructure, and poor thermal stability of existing gold-palladium alloy bumps during flip chip packaging. To achieve the above-mentioned objective, this invention constructs a gold-palladium alloy bump with high hardness, fine-grained uniform microstructure, and excellent high-temperature structural stability by precisely controlling the composition of the electroplating solution, optimizing the electroplating process parameters, and coordinating the design of subsequent heat treatment regimes.

[0007] This invention achieves the above objective through the following technical solution: a high-temperature resistant gold-palladium alloy bump encapsulation method, comprising the following steps: S1. Bump Fabrication: Metal bumps are fabricated on the surface of the chip using electroplating. The material of the metal bumps is a gold-palladium alloy. After annealing, a chip with bumps is obtained. The electroplating solution includes a main salt, a conductive salt, a film hardness regulator, a crystallization regulator, and a pH regulator. The main salt includes potassium gold cyanide and potassium tetracyanopallate. The conductive salt includes phosphate and oxalate. The height of the metal bump platform relative to the chip surface is 6 μm, and the flatness deviation is within 2 μm. S2. Pad fabrication: Prepare a substrate and fabricate pads on the substrate that match the pattern of the metal bumps. S3. Chip flipping: Apply solder paste to the surface of the pads, so that the bump side of the chip faces the pads on the substrate. After the metal bumps are precisely aligned with the pads, they are soldered into a whole to obtain a chip substrate. S4. Bottom filling: Inject filler adhesive into the gap between the chip and the substrate along the edge of the chip, and then bake the filler adhesive to cure it to obtain the product.

[0008] Specifically, the concentration of potassium gold cyanide is 1~30 g / L, the concentration of potassium tetracyanopallate is 2~10 g / L, the concentration of phosphate is 5~200 g / L, and the concentration of oxalate is 2~150 g / L.

[0009] Specifically, the membrane hardness regulator is dextrin, and the concentration of dextrin is 0.05~100g / L.

[0010] Specifically, the crystallization regulator uses a Tl compound, a Pb compound, or an As compound at a concentration of 0.1~200 mg / L.

[0011] Specifically, the pH adjuster controls the pH to be between 6.0 and 13.0.

[0012] Specifically, the electroplating in step S1 adopts a direct current electroplating process with a voltage of 1.5-3V and a current density of 0.5-3.0A / dm². 2 The electroplating time is 30-90 minutes.

[0013] Specifically, the annealing in step S1 is carried out under an inert atmosphere, with an annealing temperature of 200-400℃ and an annealing time of 30-60 minutes.

[0014] The beneficial effects of the technical solution of this invention are: This invention systematically solves the technical contradiction between insufficient hardness and poor thermal stability of traditional gold-palladium alloy bumps by multi-dimensional synergistic design of electroplating solution components, precise control of electroplating kinetic parameters, and directional guidance of heat treatment phase change path. For the first time, it achieves controllable fabrication of high-temperature resistant gold-palladium alloy bumps with hardness ≥90HV, uniform and fine microstructure, and strong process compatibility, providing key material and process support for next-generation high-power, high-frequency, and high-reliability flip-chip packaging. Attached Figure Description

[0015] Figure 1 This is a stacked diagram of a gold-palladium alloy bump encapsulation structure.

[0016] The numbers in the diagram represent: 1-Chip, 2-Metal bump, 3-Substrate, 4-Pad, 5-Solder paste, 6-Filling adhesive. Detailed Implementation

[0017] The following detailed description of each step, in conjunction with specific embodiments, will ensure that those skilled in the art can fully reproduce the technical solution of the present invention based on this description.

[0018] Example: S1. Bump Fabrication: Metal bumps 2 are fabricated on the surface of chip 1 using electroplating. The material of metal bump 2 is a gold-palladium alloy, followed by annealing to obtain a chip with bumps. The electroplating solution includes a main salt, a conductive salt, a film hardness regulator, a crystallization regulator, and a pH regulator. The main salt includes potassium gold cyanide and potassium tetracyanopallate, and the conductive salt includes phosphate and oxalate.

[0019] In the electroplating solution preparation step, deionized water is first prepared as the solvent matrix, with a resistivity of not less than 18.2 MΩ·cm, to ensure the purity of the solution system and avoid interference from impurity ions in the electroplating process. Subsequently, the main salt components, conductive salt, and functional regulator are added sequentially, while simultaneously adjusting the pH of the solution to the target range. The main salt components include potassium gold cyanide and potassium tetracyanopallate, with the concentration of potassium gold cyanide controlled between 1 and 30 g / L, and the concentration of potassium tetracyanopallate controlled between 2 and 10 g / L. In this embodiment, the amount of potassium gold cyanide added is 15 g / L, and the amount of potassium tetracyanopallate added is 6 g / L. This ratio allows gold and palladium atoms to maintain a stable reduction potential difference during co-deposition, thereby ensuring the uniform distribution of alloy components at the microscale and effectively suppressing the formation of local gold-rich or palladium-rich regions.

[0020] The conductive salt is composed of both inorganic and organic acid conductive salts. The inorganic acid conductive salt is potassium dihydrogen phosphate (KH2PO4), with a concentration set at 5–200 g / L, but actually chosen at 80 g / L. The organic acid conductive salt is sodium oxalate (SO4), with a concentration set at 2–150 g / L, but actually chosen at 40 g / L. KH2PO4 dissociates into phosphate and potassium ions in solution, significantly improving the conductivity of the plating bath and suppressing concentration polarization. Sodium oxalate, through the formation of weak complexes between its oxalate anions and metal cations, regulates the discharge kinetics of metal ions. The synergistic effect of these two salts not only enhances ion migration rates but also promotes a more uniform diffusion layer thickness at the deposition interface, thereby guiding metal deposition towards a layered growth pattern and effectively suppressing the formation of dendrite morphology.

[0021] Furthermore, two types of functional regulators were introduced into the electroplating solution: film hardness regulators and crystallization regulators. The film hardness regulator was selected from water-soluble polysaccharides, specifically dextrin, with a molecular weight distribution between 10,000 and 50,000 D, and a concentration set at 0.05–100 g / L, with 5 g / L actually chosen. After adsorption at the cathode interface, dextrin molecules form a dynamic shielding layer. This shielding layer undergoes local reconstruction with changes in the electric field strength, thereby limiting the rapid deposition rate of metal ions at specific active sites. This mechanism effectively promotes the continuous generation of new crystal nuclei while inhibiting the abnormal growth of existing grains, ultimately resulting in a deposition structure of high-density nuclei and fine grains. The crystallization regulator could be a Tl compound, a Pb compound, or an As compound, with a concentration of 0.1–200 mg / L; thallium nitrate was actually chosen, and its concentration was strictly controlled at 50 mg / L. Thallium ions preferentially adsorb onto high surface energy crystal planes on the cathode surface through an underpotential deposition mechanism, selectively suppressing the growth rate of these crystal orientations, thereby inducing the crystal to develop in a balanced manner along multiple equivalent orientations other than low energy directions, forming an equiaxed fine-grained structure.

[0022] All the above components were dissolved sequentially in deionized water in the following order: first, the main salt was added, followed by the conduction salt after complete dissolution, and then the functional regulator was added. During dissolution, continuous stirring was maintained at a rate of 300 rpm for 60 minutes to ensure thorough dispersion of each component and prevent localized overconcentration. Subsequently, the pH of the solution was precisely adjusted to 8.5 by adding a pH adjuster (potassium hydroxide solution, phosphoric acid / potassium dihydrogen phosphate buffer system, and dilute hydrochloric acid). Real-time monitoring with an online pH meter ensured that pH fluctuations did not exceed ±0.2 throughout the preparation and subsequent use. This pH value, within the preferred range of 6.0-13.0, maintains the chemical stability of the gold-palladium cyanide complex, preventing the decomposition of free cyanide ions into highly toxic HCN gas under acidic conditions, while also ensuring the effective adsorption activity of dextrin and thallium ions at the cathode interface, avoiding deactivation or precipitation of the regulator due to pH deviation.

[0023] After preparing the electroplating solution, the electroplating deposition step begins. First, the silicon wafer undergoes pretreatment: standard RCA cleaning and dilute hydrofluoric acid etching are performed sequentially to remove the native oxide layer. Then, a titanium / copper seed layer is sputtered in a physical vapor deposition (PVD) system, with a titanium layer thickness of 100 nm and a copper layer thickness of 300 nm. Next, negative photoresist is used for patterning exposure and development to form an opening pattern of a bump array, with an opening diameter of 80 μm and a spacing of 150 μm. The treated wafer is then immersed as the cathode in the prepared electroplating solution. The anode is a high-purity platinum sheet with an area twice that of the cathode to ensure uniform current distribution. The electroplating power supply uses a DC constant current mode, with a current density set to 0.5-3.0 A / dm². 2 The corresponding tank voltage is stabilized at 1.5-3V. The electroplating time is controlled at 30-90 minutes, during which the solution temperature is maintained at 45℃, controlled by a circulating water bath system, with a temperature difference not exceeding ±1℃. Under these process conditions, gold-palladium alloy is deposited layer by layer in the photoresist opening area using a co-deposition method, ultimately forming metal bump 2 with a height (the height of the metal bump platform surface relative to the chip surface protrusion) of 6μm and a flatness deviation within 2μm. The deposited layer of metal bump 2 is continuous and dense, without pores, cracks, or inclusions, and the surface roughness Ra is less than 0.3μm. The current density is selected between 0.5-3.0 A / dm³. 2 Within the specified process window, this avoids both the increased porosity caused by slow deposition rates at low current densities and the tendency for columnar crystal growth induced by increased concentration polarization at high current densities. The product of plating time and current density determines the total electrical input, thereby precisely controlling the height of the metal bump 2 to meet the dual requirements of mechanical support strength and electrical connection reliability for flip-chip interconnects.

[0024] After electroplating, the wafer undergoes sequential processes of resist removal, seed layer etching, and cleaning to obtain an exposed gold-palladium alloy bump array. It then proceeds to the heat treatment annealing step. The wafer is placed in a tube annealing furnace, with high-purity argon gas (any inert gas atmosphere) purging the furnace chamber as a protective atmosphere at a flow rate of 5 L / min. The oxygen content is confirmed to be below 5 ppm by an online oxygen analyzer. The annealing temperature is set to 350℃, with a heating rate of 10℃ / min. After reaching the target temperature, it is held for 45 minutes, then cooled in the furnace to below 100℃ before being removed.

[0025] S2. Pad fabrication: Prepare substrate 3 and fabricate pads 4 on substrate 3 that match the pattern of metal bump 2.

[0026] S3, Chip flipping: Apply solder paste 5 to the surface of pad 4, so that the bump side of chip 1 faces the pad 5 on substrate 3. After the metal bump 2 and pad 5 are precisely aligned, they are soldered into a whole to obtain a chip substrate.

[0027] S4. Bottom Filling: Inject filler 6 into the gap between chip 1 and substrate 3 along the edge of the chip, and then bake and cure the filler 6 to obtain the product, such as... Figure 1 As shown.

[0028] If the flatness deviation between chip 1 and substrate 3 is greater than 2μm, more than 90% of the bumps will fail to contact the substrate pads 4, resulting in "poor soldering." Consequently, the packaged chip will have no electrical signal conduction. Therefore, the metal bumps 2 need to be fabricated to a height of at least 6μm. This is something that existing technology cannot achieve. Therefore, the main improvement of this invention is in the gold-palladium alloy electroplating in step S1. Steps S2-S4 are standard steps in flip-chip packaging processes and will not be described in detail.

[0029] To verify the actual performance of the technical solution of this invention, comparative tests were conducted between the embodiments and the comparative examples. The embodiments used the aforementioned preferred parameter combination: dextrin 5g / L, thallium nitrate 50mg / L, pH 8.5, and current density 1.8A / dm³. 2 Electroplating time: 60 min; Annealing temperature: 350℃; Holding time: 45 min.

[0030] Comparative Example 1: The same ratio of main salt to conductive salt was used, but dextrin and thallium nitrate were omitted, the pH was adjusted to 8.5, and the remaining electroplating and annealing parameters were the same as in the example.

[0031] Comparative Example 2: The electroplating solution formulation and electroplating parameters of the embodiment were used, but the heat treatment annealing step was omitted. All samples were subsequently encapsulated under the same conditions: epoxy molding compound was used for encapsulation, and after the bottom filler glue cured, reliability testing was performed.

[0032] Reliability testing included two parts: first, a temperature cycling test, with conditions ranging from -55℃ to 125℃, 500 cycles, a heating / cooling rate of 20℃ / min, and a holding time of 15min; second, a high-temperature and high-humidity storage test, with conditions of 85℃ / 85%RH for 1000 hours. The contact resistance and shear strength of the bumps were measured before and after the tests. Contact resistance was measured using the four-probe method, and shear strength was measured according to the JEDEC JESD22-B117 standard, with the shear height set to 25% of the bump height and the shear rate at 100μm / s.

[0033] The test results are summarized in the table below: Sample number Average grain size (nm) Hardness (HV) Contact resistance change rate (%) after 500 temperature cycles Shear strength retention rate (%) after 1000 hours of high temperature and high humidity Example 150 95 3.2 92.5 Comparative Example 1 420 78 12.7 76.3 Comparative Example 2 160 82 9.8 81.6

[0034] Data shows that the embodiment significantly outperforms the two comparative examples in terms of grain refinement, hardness improvement, and long-term reliability. Comparative Example 1, lacking functional modifiers, suffers from coarse grains and insufficient hardness, making it prone to grain boundary slip and microcrack initiation under thermomechanical stress, resulting in a significant increase in contact resistance and a substantial decrease in shear strength. Comparative Example 2, while possessing a fine-grained structure, has not undergone annealing treatment, leaving residual stress unreleased and failing to form an ordered strengthening phase. Its creep resistance is weak, leading to slow plastic deformation under high temperature and humidity conditions, resulting in deteriorated interconnect reliability.

[0035] The packaging method described in this invention is fully compatible with standard semiconductor manufacturing processes. The chemicals used in the electroplating solution are all industrial-grade, readily available raw materials, requiring no special customization. The electroplating equipment is a conventional DC electroplating tank, and heat treatment can be completed in existing tube furnaces or rapid thermal annealing (RTA) equipment. The process window is wide, and batch-to-batch repeatability is excellent. Statistical analysis shows that the standard deviation of bump height in ten consecutive batches is less than 1.2 micrometers, and the hardness fluctuation range is controlled within ±3 HV, indicating excellent process stability.

[0036] In summary, this invention constructs an interfacial dynamic environment conducive to fine-grained co-deposition through multi-dimensional synergistic design of the main salt, conductive salt, and functional modifier in the electroplating solution; it achieves precise control of bump geometry by accurately controlling the electroplating current density and time; and it obtains gold-palladium alloy bumps with high hardness, fine-grained structure, and high-temperature stability by inducing ordered phase precipitation and stress release through directional heat treatment. This technical solution provides a mass-producible, low-cost, and high-performance interconnect solution for high-power, high-frequency, and high-reliability flip-chip packaging without altering existing production line layouts.

[0037] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method for high-temperature resistant gold-palladium alloy bump packaging, characterized in that... The steps include: S1. Bump Fabrication: Metal bumps are fabricated on the surface of the chip using electroplating. The material of the metal bumps is a gold-palladium alloy. After annealing, a chip with bumps is obtained. The electroplating solution includes a main salt, a conductive salt, a film hardness regulator, a crystallization regulator, and a pH regulator. The main salt includes potassium gold cyanide and potassium tetracyanopallate. The conductive salt includes phosphate and oxalate. The height of the metal bump platform relative to the chip surface is 6 μm, and the flatness deviation is within 2 μm. S2. Pad fabrication: Prepare a substrate and fabricate pads on the substrate that match the pattern of the metal bumps. S3. Chip flipping: Apply solder paste to the surface of the pads, so that the bump side of the chip faces the pads on the substrate. After the metal bumps are precisely aligned with the pads, they are soldered into a whole to obtain a chip substrate. S4. Bottom filling: Inject filler adhesive into the gap between the chip and the substrate along the edge of the chip, and then bake the filler adhesive to cure it to obtain the product.

2. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The concentration of potassium gold cyanide is 1~30 g / L, the concentration of potassium tetracyanopallate is 2~10 g / L, the concentration of phosphate is 5~200 g / L, and the concentration of oxalate is 2~150 g / L.

3. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The membrane hardness regulator is dextrin, and the concentration of dextrin is 0.05~100g / L.

4. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The crystallization regulator uses a Tl compound, a Pb compound, or an As compound at a concentration of 0.1~200 mg / L.

5. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The pH adjuster controls the pH to be between 6.0 and 13.

0.

6. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The electroplating in step S1 uses a direct current electroplating process with a voltage of 1.5-3V and a current density of 0.5-3.0A / dm³. 2 The electroplating time is 30-90 minutes.

7. The high-temperature resistant gold-palladium alloy bump encapsulation method according to claim 1, characterized in that: The annealing in step S1 is carried out under an inert atmosphere, at a temperature of 200-400℃, and for a time of 30-60 minutes.

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