Temperature detection circuit, chip and electronic equipment

Abstract

The invention provides a temperature detection circuit, a chip and an electronic device, and the circuit comprises a front-end circuit which is configured to generate a reference current, a first group of temperature currents which are positively correlated with the temperature, and a second group of temperature currents which are negatively correlated with the temperature; selecting a first target current and a second target current from the first group of temperature currents and the second group of temperature currents based on the type of the chip to be tested; the charging and discharging circuit is configured to generate two reference voltages by using the reference current provided by the front-end circuit and the two target currents based on the level state of the feedback signal under the condition that the feedback signal provided by the analog-to-digital conversion circuit is received; and the analog-to-digital conversion circuit is configured to generate a feedback signal and a pulse width modulation signal with temperature information based on the two reference voltages provided by the charging and discharging circuit. Through the configuration of the front-end circuit, the temperature detection circuit has universality.

Description

Technical Field

[0001] This application relates to the field of temperature detection technology, and in particular to a temperature detection circuit, chip, and electronic device. Background Technology

[0002] Temperature detection circuits are commonly used for chip temperature monitoring. Their core principle lies in utilizing the inherent temperature characteristics of semiconductor devices to directly convert thermal quantities into electrical quantities. These electrical quantities are then processed by the analog-to-digital converter within a microcontroller unit (MCU), and finally, the corresponding temperature value is calculated by software. However, the temperature detection circuits provided in related technologies often have a single-architecture design, meaning they only support the detection of specific chips. This limits their practical application. Summary of the Invention

[0003] This application provides a temperature detection circuit, chip, and electronic device that can match the requirements of different chips for temperature detection circuits, making the temperature detection circuit universally applicable.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a temperature detection circuit, including: a front-end circuit, a charging / discharging circuit, and an analog-to-digital converter circuit; the output terminal of the front-end circuit is connected to the input terminal of the charging / discharging circuit, and the input terminal and feedback terminal of the analog-to-digital converter circuit are respectively connected to the output terminal and control terminal of the charging / discharging circuit; wherein: The front-end circuit is configured to generate a reference current, a first set of temperature currents, and a second set of temperature currents. The first set of temperature currents is a set of at least two currents that are positively correlated with temperature, and the second set of temperature currents is a set of at least two currents that are negatively correlated with temperature. Based on the type of the chip under test, a first target current and a second target current are selected from the first set of temperature currents and the second set of temperature currents. The type of the chip under test includes multiple types that are distinguished according to the temperature detection accuracy requirements. The charging and discharging circuit is configured to receive a reference current, a first target current, and a second target current provided by the front-end circuit; and, upon receiving a feedback signal provided by the analog-to-digital conversion circuit, to generate a first reference voltage and a second reference voltage based on the level state of the feedback signal using the reference current, the first target current, and the second target current. The analog-to-digital converter circuit is configured to receive a first reference voltage and a second reference voltage provided by the charging and discharging circuit, and to compare and perform logical operations based on the first reference voltage and the second reference voltage to generate a feedback signal and a pulse width modulation signal with temperature information.

[0005] Secondly, embodiments of this application provide a chip including the temperature detection circuit as described in the first aspect.

[0006] Thirdly, embodiments of this application provide an electronic device, including the chip as described in the second aspect.

[0007] This application provides a temperature detection circuit, chip, and electronic device. A front-end circuit generates a reference current, a first set of temperature currents, and a second set of temperature currents. The first set of temperature currents is a set of at least two currents positively correlated with temperature, and the second set of temperature currents is a set of at least two currents negatively correlated with temperature. A suitable target current combination is selected based on the type of chip under test. The types of chips under test include various types differentiated according to temperature detection accuracy requirements, thus matching the needs of different types of chips. Utilizing the charging and discharging properties of the charging and discharging circuit, upon receiving a feedback signal from the analog-to-digital conversion circuit, the circuit charges and discharges using the reference current, the first target current, and the second target current based on the level state of the feedback signal, and outputs a first reference voltage and a second reference voltage. The analog-to-digital conversion circuit, through comparison and logical operations based on the first and second reference voltages, generates a feedback signal that can precisely control the charging and discharging duration of the charging and discharging circuit, thereby adjusting the pulse width of the generated pulse width modulation signal carrying temperature information to improve the accuracy of temperature detection. In other words, this application embodiment can make the temperature detection circuit universal while improving the accuracy of temperature detection. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 This is a schematic diagram of the structure of a temperature detection circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of a front-end circuit provided in an embodiment of this application. Figure 1 ; Figure 3 This is a schematic diagram of a front-end circuit provided in an embodiment of this application. Figure 2 ; Figure 4 This is a schematic diagram of a front-end circuit provided in an embodiment of this application. Figure 3 ; Figure 5 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of a voltage reference circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of a switching branch provided in an embodiment of this application; Figure 8 This is a schematic diagram of a charging and discharging circuit provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an analog-to-digital converter circuit provided in an embodiment of this application; Figure 10 This is a schematic diagram of the first architecture of a temperature detection circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of a second architecture of a temperature detection circuit provided in an embodiment of this application; Figure 12 This is a schematic diagram of a third architecture of a temperature detection circuit provided in an embodiment of this application; Figure 13 This is a schematic diagram of the fourth architecture of a temperature detection circuit provided in the embodiments of this application; Figure 14 This is a schematic diagram of temperature curves for a first architecture and a second architecture provided in the embodiments of this application; Figure 15 These are schematic diagrams of temperature profiles for a third and a fourth architecture provided in embodiments of this application; Figure 16 This is a schematic diagram of the structure of a chip provided in an embodiment of this application; Figure 17 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0012] In the following description, references to "some embodiments," "this embodiment," "this application embodiment," and examples, etc., describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0013] The descriptions such as "first," "second," and "third" appearing in the embodiments of this application do not have a specific meaning (such as no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application), but are merely for the purpose of clearly describing the embodiments of this application and do not constitute any limitation on the embodiments of this application.

[0014] To address the limitation of temperature detection circuits in the prior art, which only support the detection of specific chips, this application provides the following temperature detection circuit, chip, and electronic device. The temperature detection circuit includes a front-end circuit, a charging / discharging circuit, and an analog-to-digital converter circuit. The output terminal of the front-end circuit is connected to the input terminal of the charging / discharging circuit, and the input terminal and feedback terminal of the analog-to-digital converter circuit are respectively connected to the output terminal and control terminal of the charging / discharging circuit. The front-end circuit is configured to generate a reference current, a first set of temperature currents, and a second set of temperature currents. The first set of temperature currents is a set of at least two currents positively correlated with temperature, and the second set of temperature currents is a set of at least two currents negatively correlated with temperature. Based on the type of the chip under test, a first target current and a second target current are selected from the first group of temperature currents and the second group of temperature currents; a charging and discharging circuit is configured to receive a reference current, a first target current and a second target current provided by the front-end circuit; and, upon receiving a feedback signal provided by the analog-to-digital conversion circuit, to generate a first reference voltage and a second reference voltage based on the level state of the feedback signal using the reference current, the first target current and the second target current; an analog-to-digital conversion circuit is configured to receive the first reference voltage and the second reference voltage provided by the charging and discharging circuit, and to generate a feedback signal and a pulse width modulation signal with temperature information based on a comparison and logical operation of the first reference voltage and the second reference voltage. This application embodiment generates a reference current, a first set of temperature currents, and a second set of temperature currents through a front-end circuit. It selects a suitable target current combination based on the type of chip under test, thus matching the needs of different types of chips. Utilizing the charging and discharging properties of the charging and discharging circuit, upon receiving a feedback signal from the analog-to-digital converter circuit, it charges and discharges using the reference current, the first target current, and the second target current based on the level of the feedback signal, and outputs a first reference voltage and a second reference voltage. The analog-to-digital converter circuit, through comparison and logical operations based on the first and second reference voltages, generates a feedback signal that can precisely control the charging and discharging duration of the charging and discharging circuit. This, in turn, can adjust the pulse width of the generated pulse width modulation signal carrying temperature information, thereby improving the accuracy of temperature detection. In other words, this application embodiment not only makes the temperature detection circuit universal but also improves the accuracy of temperature detection.

[0015] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0016] In embodiments of this application, a temperature detection circuit is provided, such as... Figure 1 As shown, the temperature detection circuit 10 provided in this embodiment includes: a front-end circuit 101, a charging and discharging circuit 102, and an analog-to-digital conversion circuit 103.

[0017] Specifically, the output terminal of the front-end circuit 101 is connected to the input terminal of the charging and discharging circuit 102, the output terminal of the charging and discharging circuit 102 is connected to the input terminal of the analog-to-digital conversion circuit 103, and the feedback terminal of the analog-to-digital conversion circuit 103 is connected to the control terminal of the charging and discharging circuit 102.

[0018] The front-end circuit 101 is configured to generate a reference current, a first set of temperature currents, and a second set of temperature currents; and select a first target current and a second target current from the first set of temperature currents and the second set of temperature currents based on the type of the chip under test.

[0019] For example, the type of chip under test can include multiple types distinguished according to the temperature detection accuracy requirements, such as four types in total: Type 1, Type 2, Type 3, and Type 4.

[0020] For example, the first set of temperature currents is a collection of at least two types of currents that are positively correlated with temperature, and the second set of temperature currents is a collection of at least two types of currents that are negatively correlated with temperature. In an optional embodiment, the first set of temperature currents may include a first type of current Iptat that is positively correlated with temperature and a second type of current Iptat_v that is positively correlated with temperature.

[0021] It should be noted that both the first type of current Iptat and the second type of current Iptat_v are currents that are positively correlated with temperature, the difference being that the voltage source that generates the current is different.

[0022] In one alternative embodiment, the second set of temperature currents may include a third type of current Ictat_v1 that is negatively correlated with temperature and a fourth type of current Ictat_v2 that is negatively correlated with temperature.

[0023] It should be noted that both the third type of current Ictat_v1 and the fourth type of current Ictat_v2 are currents that are negatively correlated with temperature, the difference being that the voltage source that generates the current is different.

[0024] The charging and discharging circuit 102 is configured to receive a reference current, a first target current, and a second target current provided by the front-end circuit 101; and, upon receiving a feedback signal FBDAC provided by the analog-to-digital conversion circuit 103, to generate a first reference voltage and a second reference voltage based on the level state of the feedback signal FBDAC using the reference current, the first target current, and the second target current.

[0025] It should be noted that the first target current and the second target current are two currents that have an opposite relationship with temperature. For example, if the first target current is selected from the first group of temperature currents that are positively correlated with temperature, then the second target current needs to be selected from the second group of temperature currents that are negatively correlated with temperature; if the first target current is selected from the second group of temperature currents that are negatively correlated with temperature, then the second target current needs to be selected from the first group of temperature currents that are positively correlated with temperature.

[0026] In one example, when the feedback signal FBDAC is at a high level, the charging and discharging circuit 102 is in a discharging mode, and when the feedback signal FBDAC is at a low level, the charging and discharging circuit 102 is in a charging mode.

[0027] In another example, when the feedback signal FBDAC is at a high level, the charging / discharging circuit 102 is in charging mode, and when the feedback signal FBDAC is at a low level, the charging / discharging circuit 102 is in discharging mode.

[0028] This application does not impose any particular limitation on the relationship between the level state of the feedback signal FBDAC and the operating mode of the charging and discharging circuit 102. The following example illustrates the relationship between the charging and discharging circuit 102 in the discharging mode when the level state of the feedback signal FBDAC is high and in the charging mode when the level state of the feedback signal FBDAC is low.

[0029] The analog-to-digital converter circuit 103 is configured to receive a first reference voltage and a second reference voltage provided by the charging and discharging circuit 102, and to perform comparisons and logical operations based on the first reference voltage and the second reference voltage to generate a feedback signal FBDAC and a pulse width modulation signal DOUT with temperature information.

[0030] In one example, a pulse width modulation signal DOUT carrying temperature information can be sent to a counter. The counter counts the total number of high-level pulse width modulation signals DOUT carrying temperature information within a set time period. After obtaining the total number, the total number is divided by the acquisition accuracy of the temperature detection circuit 10 (e.g., 11-bit sampling accuracy, i.e., 2^35). ^11 =2048) to obtain the variable u in the temperature calculation formula, thereby realizing the measurement of the temperature of the chip under test.

[0031] For example, the temperature calculation formula can refer to the following formula (1): (1) Where T represents temperature; A represents the first temperature coefficient (for example, it could be 600°C); B represents the second coefficient (for example, it could be -273°C); and u is a variable.

[0032] It is understood that in this embodiment, a reference current, a first set of temperature currents, and a second set of temperature currents are generated by the front-end circuit. The first set of temperature currents is a set of at least two currents positively correlated with temperature, and the second set of temperature currents is a set of at least two currents negatively correlated with temperature. A suitable target current combination is selected based on the type of chip under test, thus matching the needs of different types of chips. Utilizing the charging and discharging properties of the charging and discharging circuit, upon receiving a feedback signal from the analog-to-digital converter circuit, charging and discharging are performed using the reference current, the first target current, and the second target current, based on the level of the feedback signal, and a first reference voltage and a second reference voltage are output. The analog-to-digital converter circuit, through comparison and logical operations based on the first and second reference voltages, generates a feedback signal that can precisely control the charging and discharging duration of the charging and discharging circuit, thereby adjusting the pulse width of the generated pulse width modulation signal carrying temperature information to improve the accuracy of temperature detection. In other words, this embodiment not only makes the temperature detection circuit universal but also improves the accuracy of temperature detection.

[0033] As an optional embodiment, such as Figures 2-4 As shown, the front-end circuit 101 of the temperature detection circuit 10 provided in this application embodiment may include a bandgap reference circuit 101A, a voltage reference circuit 101B, a voltage-to-current conversion circuit 101C, and a register 101D.

[0034] Specifically, the bandgap reference circuit 101A and the voltage reference circuit 101B are connected to the voltage input terminal of the voltage-to-current conversion circuit 101C, and the current output terminal of the voltage-to-current conversion circuit 101C is connected to the register 101D.

[0035] Among them, the bandgap reference circuit 101A is configured to generate a reference voltage VBG, a first voltage Vadvbe that is positively correlated with temperature, a second voltage Vbe1 that is negatively correlated with temperature, and a first type current Iptat in the first group of temperature currents.

[0036] The voltage reference circuit 101B is configured to generate a third voltage VSENSE that is negatively correlated with temperature.

[0037] The voltage-to-current conversion circuit 101C is configured to receive a reference voltage VBG and convert it into a reference current Iref; receive a first voltage Vadvbe and convert it into a second type current Iptat_v; receive a second voltage Vbe1 and convert it into a third type current Ictat_v1; and receive a third voltage VSENSE and convert it into a fourth type current Ictat_v2.

[0038] Understandably, based on the foregoing, the reference voltage VBG is a temperature-independent voltage; the first voltage Vadvbe is a temperature-positive voltage; the second voltage Vbe1 and the third voltage VSENSE are both temperature-negative voltages; the reference current Iref is a temperature-independent current; the second type current Iptat_v is a temperature-positive current; and the third type current Ictat_v1 and the fourth type current Ictat_v2 are both temperature-negative currents.

[0039] Register 101D is configured to receive and store a reference current Iref, a first type current Iptat, a second type current Iptat_v, a third type current Ictat_v1, and a fourth type current Ictat_v2; and to select a first target current and a second target current from the first group of temperature currents and the second group of temperature currents based on the type of the chip under test and send them to the charge-discharge circuit 102, and to send the reference current Iref to the charge-discharge circuit 102.

[0040] It is understood that, in the embodiments of this application, the front-end circuit can generate a reference voltage, a voltage positively correlated with temperature, a voltage negatively correlated with temperature, and a current positively correlated with temperature through a bandgap reference circuit. It can also generate another voltage negatively correlated with temperature through a voltage reference circuit. Furthermore, it can convert different types of voltages into corresponding current signals through a voltage-to-current conversion circuit, generating currents that match the various types of chips under test. The registers then classify and store the signals and select appropriate target currents based on the type of chip under test, thereby providing diverse current inputs for the subsequent charging and discharging process and improving the flexibility and adaptability of the temperature detection circuit.

[0041] As an optional embodiment, such as Figure 3 and Figure 4 As shown, the voltage-to-current conversion circuit 101C in the temperature detection circuit 10 provided in this application embodiment may include a first conversion branch 101C1, a second conversion branch 101C2, a third conversion branch 101C3, and a fourth conversion branch 101C4.

[0042] Specifically, the first output terminal of the bandgap reference circuit 101A is connected to the first conversion branch 101C1, the second output terminal of the bandgap reference circuit 101A is connected to the second conversion branch 101C2, the third output terminal of the bandgap reference circuit 101A is connected to the third conversion branch 101C3, and the output terminal of the voltage reference circuit 101B is connected to the fourth conversion branch 101C4.

[0043] Specifically, the first output terminal of the bandgap reference circuit 101A is used to output the reference voltage VBG; the second output terminal of the bandgap reference circuit 101A is used to output the first voltage Vadvbe; the third output terminal of the bandgap reference circuit 101A is used to output the second voltage Vbe1; the fourth output terminal of the bandgap reference circuit 101A is used to output the first type current Ipat; and the output terminal of the voltage reference circuit 101B is used to output the third voltage VSENSE.

[0044] The first conversion branch 101C1 is configured to receive the reference voltage VBG provided by the bandgap reference circuit 101A and convert the reference voltage VBG into a reference current Iref; the second conversion branch 101C2 is configured to receive the first voltage Vadvbe provided by the bandgap reference circuit 101A and convert the first voltage Vadvbe into a second type current Iptat_v; the third conversion branch 101C3 is configured to receive the second voltage Vbe1 provided by the bandgap reference circuit 101A and convert the second voltage Vbe1 into a third type current Ictat_v1; and the fourth conversion branch 101C4 is configured to receive the third voltage VSENSE provided by the voltage reference circuit 101B and convert the third voltage VSENSE into a fourth type current Ictat_v2.

[0045] It is understood that in this embodiment, the voltage-to-current conversion circuit consists of four independent conversion branches, which respectively process different voltage signals from the bandgap reference circuit and the voltage reference circuit, converting them into corresponding current signals. This design facilitates expansion and maintenance, while ensuring that each type of voltage signal can be accurately converted into the corresponding current signal, reducing the occurrence of misconversion, improving the accuracy of each current path, and enhancing the overall stability and reliability of the temperature detection circuit.

[0046] As an optional embodiment, such as Figure 4 As shown, the front-end circuit 101 in the temperature detection circuit 10 provided in this application embodiment may further include a first gain circuit KI1, a second gain circuit KI2, a third gain circuit KI3 and a fourth gain circuit KI4.

[0047] Specifically, the first gain circuit KI1 is connected to the second conversion branch 101C2 and configured to adjust the second type of current, that is, to output a second type of current K1*Iptat_v with a first ratio to the register 101D; the second gain circuit KI2 is connected to the third conversion branch 101C3 and configured to adjust the third type of current, that is, to output a third type of current K2*Ictat_v1 with a second ratio to the register 101D; the third gain circuit KI3 is connected to the fourth output terminal of the bandgap reference circuit 101A and configured to adjust the first type of current, that is, to output a first type of current K3*Iptat with a third ratio to the register 101D; the fourth gain circuit KI4 is connected to the fourth conversion branch 101C4 and configured to adjust the ratio of the fourth type of current, that is, to output a fourth type of current K4*Ictat_v2 with a fourth ratio to the register 101D.

[0048] The gain (i.e. ratio) of the four gain circuits is set according to the requirements of the chip under test for temperature detection accuracy and response speed. They can be the same or different. This application does not make any special limitation on this. The following example illustrates the situation by taking the first ratio K1, the second ratio K2, the third ratio K3 and the fourth ratio K4 as different.

[0049] In one example, the individual gain circuits are implemented using the integral gain KI in a proportional-integral-differential controller, or simply a PID controller.

[0050] For example, the integral gain KI in a PID controller is expressed by the following formula: Where R is resistance, L is inductance, and Fcc is controller frequency, the first ratio K1 of the first gain circuit KI1, the second ratio K2 of the second gain circuit KI2, the third ratio K3 of the third gain circuit KI3, and the first ratio K4 of the fourth gain circuit KI4 can be changed by adjusting one or more of the resistance value of the resistor, the inductance value of the inductor, and the frequency of the controller.

[0051] In another example, each gain circuit can provide feedback on the magnitude of the adjusted current via an adjustable resistor, or configure the magnitude of the adjusted current via a gain coefficient.

[0052] It is understood that, in the embodiments of this application, by setting a gain circuit to proportionally adjust the current signals of each channel, the current combination can be further optimized to meet the requirements of different types of chips for temperature detection accuracy and response speed, and further enhance the ability of the temperature detection circuit to adapt to different application scenarios.

[0053] As an optional embodiment, such as Figure 5 As shown, the bandgap reference circuit 101A in the front-end circuit 101 provided in this application embodiment may include a second switching element M1, a third switching element M2, a fourth switching element M3, a fifth switching element M4, a sixth switching element M5, a seventh switching element Q1, an eighth switching element Q2, a third comparator U3, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0054] For example, the model number of the third comparator U3 can be BGR_OP. In one embodiment, the first input terminal of the third comparator U3 can be a non-inverting input terminal (i.e., the "+" terminal), and the second input terminal can be an inverting input terminal (i.e., the "-" terminal); in another embodiment, the first input terminal of the third comparator U3 can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. This application does not make any special limitation in this regard. The following description will be based on the example of the first input terminal of the third comparator U3 being the non-inverting input terminal and the second input terminal of the third comparator U3 being the inverting input terminal.

[0055] In one embodiment, the second switching element M1, the third switching element M2, the fourth switching element M3, the fifth switching element M4, and the sixth switching element M5 can be metal-oxide-semiconductor field-effect transistors (MOSFETs), abbreviated as MOS transistors. In another embodiment, the second switching element M1, the third switching element M2, the fourth switching element M3, the fifth switching element M4, and the sixth switching element M5 can be bipolar junction transistors (BJTs), abbreviated as transistors. This application does not make any special limitation, and the following description will exemplify the situation by using MOSFETs as an example.

[0056] Among them, MOSFETs are divided into N-type MOSFETs and P-type MOSFETs. The following example uses the second switching element M1, the third switching element M2, the fourth switching element M3 and the fifth switching element M4 as P-type MOSFETs, and the sixth switching element M5 as an N-type MOSFET for illustrative purposes.

[0057] It should be noted that for an N-type MOSFET, the control terminal is the gate of the N-type MOSFET, the first terminal is the drain of the N-type MOSFET, and the second terminal is the source of the N-type MOSFET; for a P-type MOSFET, the control terminal is the gate of the P-type MOSFET, the first terminal is the source of the P-type MOSFET, the second terminal is the drain of the P-type MOSFET, and the third terminal is the substrate of the P-type MOSFET.

[0058] In one embodiment, the seventh switching element Q1 and the eighth switching element Q2 can be MOSFETs; in another embodiment, the seventh switching element Q1 and the eighth switching element Q2 can be BJTs. This application does not impose any particular limitation on these embodiments, and the following description will exemplify the situation where both the seventh switching element Q1 and the eighth switching element Q2 are BJTs.

[0059] Among them, BJT transistors can be divided into NPN transistors and PNP transistors. This application does not make any special limitation on whether the seventh switching element Q1 and the eighth switching element Q2 are PNP transistors or NPN transistors. The following will be illustrated by taking the seventh switching element Q1 and the eighth switching element Q2 as PNP transistors.

[0060] It should be noted that for a PNP transistor, the first terminal is the emitter, the second terminal is the collector, and the control terminal is the base.

[0061] Specifically, the first terminals of the second switching element M1, the third switching element M2, the fourth switching element M3, and the fifth switching element M4 are all connected to the first voltage source Vddh1; the control terminal of the second switching element M1 is connected to the control terminal of the third switching element M2, and the control terminal of the second switching element M1 is connected to the second terminal of the second switching element M1; the second terminal of the third switching element M2 is connected to the first terminal of the first resistor R1 and the second terminal of the second resistor R2, and the first terminal of the first resistor R1 serves as the first output terminal of the bandgap reference circuit 101A, outputting the reference voltage VBG. The third terminal of the third switching element M2 is connected to the control terminal of the fourth switching element M3; the second terminal of the fourth switching element M3 is connected to the first terminal of the fourth resistor R4, and the first terminal of the fourth resistor R4 serves as the second output terminal of the bandgap reference circuit 101A, outputting the first voltage Vadvbe; the third terminal of the fourth switching element M3 is connected to the control terminal of the fifth switching element M4; the second terminal of the fifth switching element M4 serves as the fourth output terminal of the bandgap reference circuit 101A, outputting the first type current Iptat.

[0062] The second end of the first resistor R1 is connected to the first input terminal of the third comparator U3 and the first end of the seventh switching element Q1, and the first end of the seventh switching element Q1 serves as the third output terminal of the bandgap reference circuit 101A, outputting the second voltage Vbe1; the second end of the second resistor R2 is connected to the second input terminal of the third comparator U3 and the first end of the third resistor R3, respectively; the second end of the third resistor R3 is connected to the first end of the eighth switching element Q2, and the first end of the eighth switching element Q2 can output the third voltage Vbe2, which is negatively correlated with temperature; the second end of the fourth resistor R4 is connected to the power supply voltage source VSS.

[0063] Among them, the first voltage source Vddh1 can provide positive voltage; the power supply voltage source VSS can provide ground voltage or negative voltage.

[0064] The second terminal of the seventh switching element Q1 is connected to the control terminal of the seventh switching element Q1 and then connected to the power supply voltage source VSS; the second terminal of the eighth switching element Q2 is connected to the control terminal of the eighth switching element Q2 and then connected to the power supply voltage source VSS.

[0065] The output of the third comparator U3 is connected to the control terminal of the sixth switching element M5; the first terminal of the sixth switching element M5 is connected to the second terminal of the second switching element M1; the second terminal of the sixth switching element M5 is connected to the power supply voltage source VSS.

[0066] The following is a brief explanation of the bandgap reference circuit 101A.

[0067] It is known that the base-emitter voltage Vbe of a bipolar transistor is inversely proportional to the absolute temperature, as shown in the following formula (2): (2) Where VT represents thermal voltage, a temperature-dependent parameter; Ic is the collector current of the bipolar transistor; and Is is the saturation current of the bipolar transistor.

[0068] In the bandgap reference circuit 101A, the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor is not affected by Ic and Is, and is proportional to the absolute temperature. It can be referred to the following formula (3): (3) Where N represents the third coefficient; I5 represents the current flowing through the first resistor R1; and I6 represents the current flowing through the second resistor R2.

[0069] By linearly combining the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor and the second voltage Vbe1 which is negatively correlated with temperature, a temperature-independent voltage, namely the reference voltage VBG, can be obtained. The expression for the reference voltage VBG can be found in the following formula (4): (4) Where 'a' represents the fourth coefficient.

[0070] from Figure 5 As can be seen from this, the reference voltage VBG also satisfies the following formula (5): (5) By observing formulas (4) and (5), we can obtain another expression for a*dVbe, as shown in formula (6): (6) The expression for the current I5 flowing through the first resistor R1 can be found in the following formula (7): (7) According to the characteristics of the current mirror circuit, the magnitude of the first type current Iptat, which is positively correlated with temperature, is the same as the current I5 flowing through the first resistor R1. Therefore, the first type current Iptat also satisfies the expression of the above formula (7).

[0071] The expression for the first voltage Vadvbe, which is positively correlated with temperature, can be found in the following formula (8): (8) Where I7 represents the current flowing through the fourth resistor R4.

[0072] To make the first voltage Vadvbe, which is positively correlated with temperature, and a*dVbe equal, another expression for the first voltage Vadvbe can be found in the following formula (9): (9) It is understood that, in the embodiments of this application, the complexity of the temperature detection circuit can be reduced by defining the specific structure of the bandgap reference circuit to generate a voltage that matches different types of chips and a temperature-positive current.

[0073] As an optional embodiment, such as Figure 6 As shown, the voltage reference circuit 101B in the front-end circuit 101 provided in this application embodiment may include a power supply voltage source VSS and an eleventh switching element Q3.

[0074] The eleventh switching element Q3 can be a MOSFET, a BJT, etc. This application does not make any special limitation on it. The following will take the eleventh switching element Q3 as a PNP type transistor as an example for illustrative purposes.

[0075] It should be noted that for a PNP transistor, the first terminal is the emitter, the second terminal is the collector, and the control terminal is the base.

[0076] Specifically, the control terminal of the eleventh switching element Q3 and the second terminal of the eleventh switching element Q3 are connected and connected to the power supply voltage source VSS; the first terminal of the eleventh switching element Q3 serves as the output terminal of the voltage reference circuit 101B, outputting a third voltage VSENSE that is negatively correlated with temperature.

[0077] It is understood that, in the embodiments of this application, a third voltage negatively correlated with temperature can be generated by using a reasonable connection power supply voltage source and switching elements, which can reduce the complexity of the temperature detection circuit.

[0078] As an optional embodiment, each of the four conversion branches—the first conversion branch 101C1, the second conversion branch 101C2, the third conversion branch 101C3, and the fourth conversion branch 101C4—in the temperature detection circuit 10 provided in this application includes a fourth comparator U4, a ninth switching element M6, a tenth switching element M7, and a fifth resistor R5. For ease of illustration, as shown... Figure 7 As shown, taking switching branch 1021 as an example, the specific connection relationship of each switching branch is explained.

[0079] Specifically, regarding the model number of the fourth comparator U4, for example, when conversion branch 1021 is applied to the first conversion branch 101C1, the model number of the fourth comparator U4 is Iref amp. That is, when the input voltage type of the fourth comparator U4 is the reference voltage VBG, the model number of the fourth comparator is Iref amp. As another example, when conversion branch 1021 is applied to the second conversion branch 101C2, the third conversion branch 101C3, and the fourth conversion branch 101C4, the model number of the fourth comparator U4 is V2I amp. That is, when the input voltage type of the fourth comparator U4 is a first voltage Vadvbe that is positively correlated with temperature, a second voltage Vbe1 that is negatively correlated with temperature, and a third voltage VSENSE that is negatively correlated with temperature, the model number of the fourth comparator U4 is V2I amp.

[0080] In one embodiment, the first input terminal of the fourth comparator U4 can be a non-inverting input terminal (i.e., the "+" terminal), and the second input terminal can be an inverting input terminal (i.e., the "-" terminal). In another embodiment, the first input terminal of the fourth comparator U4 can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. This application does not impose any particular limitation on this, and the following description will use the example of the first input terminal of the fourth comparator U4 being the non-inverting input terminal and the second input terminal of the fourth comparator U4 being the inverting input terminal as an example.

[0081] Specifically, regarding the model of the fifth resistor R5, when the conversion branch 1021 is applied to the first conversion branch 101C1, the model of the fifth resistor R5 is RIref; when the conversion branch 1021 is applied to the second conversion branch 101C2, the third conversion branch 101C3, and the fourth conversion branch 101C4, the model of the fifth resistor R5 is RV2I.

[0082] Among them, the ninth switching element M6 and the tenth switching element M7 can be MOSFETs, BJTs, etc.; the following example will be given with both the ninth switching element M6 and the tenth switching element M7 being N-type MOSFETs.

[0083] It should be noted that for an N-type MOSFET, the control terminal is the gate of the N-type MOSFET, the first terminal is the drain of the N-type MOSFET, and the second terminal is the source of the N-type MOSFET.

[0084] Specifically, the first input terminal of the fourth comparator U4 is connected to the first terminal of the fifth resistor R5 and can accept the second reference voltage Vinp; the second terminal of the fifth resistor R5 is connected to the power supply voltage source VSS; the output terminal Vout4 of the fourth comparator U4 is connected to the control terminal of the ninth switching element M6 and the control terminal of the tenth switching element M7 respectively; the first terminals of the ninth switching element M6 and the tenth switching element M7 are both connected to the second voltage source Vddh2; the second terminal of the ninth switching element M6 is connected to the first terminal of the fifth resistor R5.

[0085] The second voltage source, Vddh2, can provide a positive voltage.

[0086] In the case where the conversion branch 1021 is applied to the first conversion branch 101C1, the second input terminal of the fourth comparator U4 is connected to the first output terminal of the bandgap reference circuit 101A, and the current I4 output from the second terminal of the tenth switching element M7 is the reference current Iref.

[0087] In the case where the conversion branch 1021 is applied to the second conversion branch 101C2, the second input terminal of the fourth comparator U4 is connected to the second output terminal of the bandgap reference circuit 101A, and the current I4 output by the second terminal of the tenth switching element M7 is the second type current Iptat_v.

[0088] In the case where the conversion branch 1021 is applied to the third conversion branch 101C3, the second input terminal of the fourth comparator U4 is connected to the third output terminal of the bandgap reference circuit 101A, and the current I4 output by the second terminal of the tenth switching element M7 is the third type current Ictat_v1.

[0089] In the case where the conversion branch 1021 is applied to the fourth conversion branch 101C4, the second input terminal of the fourth comparator U4 is connected to the output terminal of the voltage reference circuit 101B, and the current I4 output from the second terminal of the tenth switching element M7 is the fourth type current Ictat_v2.

[0090] It is understood that, in the embodiments of this application, by defining the circuit structure of the conversion branch and how to connect it with the bandgap reference circuit under different conditions to generate the corresponding current, it can be ensured that each type of voltage is unique when converted into the corresponding current, which can reduce the occurrence of misconversion and improve the overall reliability of the temperature detection circuit. In addition, the voltage-to-current function can be realized with only one comparator, two switching elements and one resistor, which can reduce the complexity of the temperature detection circuit.

[0091] As an optional embodiment, such as Figure 8 and Figure 9 As shown, the charging and discharging circuit 102 in the temperature detection circuit 10 provided in this embodiment includes a first comparator U1, a first current branch 102A1, a second current branch 102A2, a third current branch 102A3, a first switching element K1, a first energy storage element C1, and a third reference voltage source Vref.

[0092] The first current branch 102A1 receives the first target current I1, the second current branch 102A2 receives the second target current I2, and the third current branch 102A3 receives the reference current Iref. The third reference voltage source Vref is a reference voltage source, and its voltage value is pre-configured and adapted to the detection thresholds of different chip types. The following explanation uses the voltage value of the third reference voltage source Vref as an example of the third reference voltage.

[0093] In one embodiment, the first input terminal of the first comparator U1 can be a non-inverting input terminal (i.e., the "+" terminal), and the second input terminal can be an inverting input terminal (i.e., the "-" terminal). In another embodiment, the first input terminal of the first comparator U1 can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. This application does not impose any particular limitation on this, and the following description will use the example of the first input terminal of the first comparator U1 being the non-inverting input terminal and the second input terminal of the first comparator U1 being the inverting input terminal as an example.

[0094] In one example, the first energy storage element C1 can be a capacitor.

[0095] In one example, the first switching element K1 can be an electrically controlled electronic switch.

[0096] Specifically, the first input terminal of the first comparator U1 is connected to the output terminal of the third reference voltage source Vref, and the second input terminal of the first comparator U1 is connected to the first terminal of the first switching element K1, the first terminal of the first energy storage element C1, the output terminal of the first current branch 102A1, and the output terminal of the second current branch 102A2, respectively. The output terminal Vout1 of the first comparator U1 is connected to the second terminal of the first energy storage element C1. The first power supply output terminal a1 and the second power supply output terminal a2 of the first comparator U1 are connected to the two input terminals of the analog-to-digital converter circuit 103, respectively. The second terminal of the first switching element K1 is connected to the output terminal of the third current branch 102A3, and the control terminal of the first switching element K1 is connected to the feedback terminal of the analog-to-digital converter circuit 103 as the control terminal of the charging and discharging circuit 102, for receiving the feedback signal FBDAC.

[0097] Continue as Figure 8 and Figure 9 As shown, taking the charging and discharging circuit 102 as an example of a partial circuit in the temperature detection circuit 10, in order to ensure the integrity of the charging and discharging circuit 102, as an optional embodiment, the end of the third current branch 102A3 that is not connected to the second terminal of the first switching element K1 can be connected to the power supply voltage source VSS; the end of the second current branch 102A2 that is not connected to the second input terminal of the first comparator U1 can be connected to the power supply voltage source VSS; and the end of the first current branch 102A1 that is not connected to the second input terminal of the first comparator U1 can be connected to the third voltage source Vddh3. The third voltage source Vddh3 is used to provide the operating voltage for the first comparator U1 and will not change the magnitude of the acquired first target current I1, second target current I2, and reference current Iref. It is understandable that when the charging / discharging circuit 102 is connected to the front-end circuit 101, the ends of the third current branch 102A3 not connected to the second terminal of the first switching element K1, the second current branch 102A2 not connected to the second input terminal of the first comparator U1, and the first current branch 102A1 not connected to the second input terminal of the first comparator U1 can be adaptively adjusted. The third voltage source Vddh3 can provide a positive voltage.

[0098] The charging and discharging circuit 102 is configured to, when the feedback signal FBDAC is at the first level, disconnect the first switching element K1 and charge the first energy storage element C1 using the difference between the first target current I1 and the second target current I2, so as to increase the input voltage V1 at the second input terminal of the first comparator U1; or, when the feedback signal FBDAC is at the second level, turn on the first switching element K1 and control the first energy storage element C1 to discharge based on the difference between the first target current I1, the second target current I2 and the reference current Iref, so as to decrease the input voltage V1 at the second input terminal of the first comparator U1.

[0099] In one example, the first level state of the feedback signal FBDAC is low, and the second level state of the feedback signal FBDAC is high; in another example, the first level state of the feedback signal FBDAC is high, and the second level state of the feedback signal FBDAC is low. This application does not impose any particular limitation on this, and the following explanation will use the example of the first level state of the feedback signal FBDAC being low and the second level state of the feedback signal FBDAC being high.

[0100] The first comparator U1 is configured such that, when the third reference voltage is greater than the input voltage V1, the first reference voltage OUTN1 output through the first power supply output terminal a1 of the first comparator U1 is greater than the second reference voltage OUTP1 output through the second power supply output terminal a2 of the first comparator U1; or, when the third reference voltage is less than the input voltage V1, the first reference voltage OUTN1 output through the first power supply output terminal a1 of the first comparator U1 is less than the second reference voltage OUTP1 output through the second power supply output terminal a2 of the first comparator U1.

[0101] It is understood that in the embodiments of this application, the charging and discharging circuit controls the charging and discharging behavior of the energy storage element through a comparator and dynamically adjusts the charging and discharging mode according to the feedback signal, which can make the charging and discharging process more precise and controllable, and is beneficial to improving the stability and sensitivity of temperature detection.

[0102] As an optional embodiment, such as Figure 9 As shown, the analog-to-digital conversion circuit 103 in the temperature detection circuit 10 provided in this application embodiment can be a Σ-Δ analog-to-digital converter (Sigma Delta Analog to Digital Converter), including a second comparator U2 and a signal logic circuit 103A.

[0103] In one embodiment, the first input terminal of the second comparator U2 can be a non-inverting input terminal (i.e., the "+" terminal), and the second input terminal can be an inverting input terminal (i.e., the "-" terminal). In another embodiment, the first input terminal of the second comparator U2 can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. This application does not impose any particular limitation on this, and the following description will use the example of the first input terminal of the second comparator U2 being the non-inverting input terminal and the second input terminal of the second comparator U2 being the inverting input terminal as an example.

[0104] Specifically, the first input terminal of the second comparator U2 is connected to the second power supply output terminal a2 of the first comparator U1 as the first input terminal of the analog-to-digital converter circuit 103, the second input terminal of the second comparator U2 is connected to the first power supply output terminal a1 of the first comparator U1 as the second input terminal of the analog-to-digital converter circuit 103, the output terminal Vout2 of the second comparator U2 is connected to the input terminal of the signal logic circuit 103A, and the feedback terminal of the signal logic circuit 103A is connected to the control terminal of the first switching element K1 as the feedback terminal of the analog-to-digital converter circuit 103.

[0105] The second comparator U2 is configured to compare the first reference voltage OUTN1 and the second reference voltage OUTP1, and output a first signal to the signal logic circuit 103A when the first reference voltage OUTN1 is greater than the second reference voltage OUTP1; or output a second signal to the signal logic circuit 103A when the first reference voltage OUTN1 is less than the second reference voltage OUTP1.

[0106] For example, the first signal is "1" and the second signal is "0".

[0107] The signal logic circuit 103 is configured to generate a feedback signal FBDAC at a first level state based on a first signal, and send it to the control terminal of the first switching element K1 through the feedback terminal of the signal logic circuit 103A to control the first switching element K1 to open; and to generate a feedback signal FBDAC at a second level state based on a second signal, and send it to the control terminal of the first switching element K1 through the feedback terminal of the signal logic circuit 103A to control the first switching element K1 to close.

[0108] The signal logic circuit 103 is further configured to combine the first signal and the second signal to generate a pulse width modulation signal DOUT with temperature information, and output it through the output terminal of the signal logic circuit 103A.

[0109] It is understood that in the embodiments of this application, the analog-to-digital conversion circuit generates a feedback signal to control the switching state of the charging and discharging circuit by comparing the first reference voltage and the second reference voltage, and generates a pulse width modulation signal with temperature information through logic operations to achieve efficient conversion of analog signals to digital signals, thereby supporting high-precision temperature detection.

[0110] The following is combined with Figures 10-13 The process of using the temperature detection circuit 10 provided in the embodiments of this application to perform temperature detection on different types of chips under test is described.

[0111] If the type of chip under test is type 1, such as Figure 10 The temperature detection circuit 10 shown has a first architecture 1011 in which register 101D selects a third type current Ictat_v1 from the second group of temperature currents as the first target current I1, and selects a first type current Iptat from the first group of temperature currents as the second target current I2.

[0112] It is understandable that without the second gain circuit KI2 and the third gain circuit KI3, the third type current Ictat_v1 and the first type current Iptat selected by register 101D are both unproportioned; with the second gain circuit KI2 and the third gain circuit KI3, the third type current Ictat_v1 and the first type current Iptat selected by register 101D are both proportional, that is, the third type current K2*Ictat_v1 with the second proportion is used as the first target current I1, and the first type current K3*Iptat with the third proportion is used as the second target current I2.

[0113] Combination Figure 9 In general, after selecting the first target current I1 and the second target current I2, register 101D outputs the first target current I1 to the first current branch I02A1 in the charging and discharging circuit 102, that is, I1=K2*Ictat_v1 at this time; outputs the second target current I2 to the second current branch I02A2 in the charging and discharging circuit 102, that is, I2=K3*Iptat at this time; and outputs the reference current Iref to the third current branch 102A3 in the charging and discharging circuit 102.

[0114] At this time, the charge-discharge circuit 102 obeys the law of charge conservation, and the expression of the law of charge conservation can be referred to as the following formula (10): (10) Where μ represents the duty cycle of the digital signal output by the first comparator U1; Idischarge represents the discharge current of the charging and discharging circuit 102; and Icharge represents the charging current of the charging and discharging circuit 102.

[0115] It is understandable that, for the charging and discharging circuit 102, when the first switching element K1 is closed, the charging and discharging circuit 102 is in the discharging working mode; when the first switching element K1 is open, the charging and discharging circuit 102 is in the charging working mode.

[0116] For the first architecture 1011, the expression for the discharge current Idischarge of the charging and discharging circuit 102 can be found in the following formula (11): (11) The expression for the charging current Icharge of the charging and discharging circuit 102 can be found in the following formula (12): (12) Since the superposition of the first type current Iptat, which is positively correlated with temperature, and the third type current Ictat_v1, which is negatively correlated with temperature, can cancel out temperature drift and achieve a reference current Iref with a near-zero temperature coefficient, that is, under the first architecture 1011, the expression for the reference current Iref can be referred to as the following formula (13): (13) Substituting formulas (11) and (12) into formula (10), we can obtain the duty cycle μ of the digital signal output by the first comparator U1 under the first architecture 1011. The duty cycle μ of the digital signal output by the first comparator U1 under the first architecture 1011 is called the first duty cycle μ1. The expression for the first duty cycle μ1 can be found in the following formula (14): (14) Based on the relationship between the first type current Iptat, the third type current Ictat_v1, and the reference current Iref in formula (13), formula (14) can be transformed to obtain the following formula (15): (15) Combination Figure 5 and Figure 7In this case, since the third type current Ictat_v1 is the second voltage Vbe1 output from the third output terminal of the bandgap reference circuit 101A, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied in the third conversion branch 101C3. The third conversion branch 101C3 converts the second voltage Vbe1 into the third type current Ictat_v1 for output. That is, when the input voltage Vinn of the conversion branch 1021 is the second voltage Vbe1 (i.e., Vinn = Vbe1), I4 = Ictat_v1.

[0117] Depend on Figure 7 It can be seen that the formula for calculating the current I4 is as follows (16): (16) As can be seen from the previous introduction, under the first architecture 1011, Vinn=Vbe1, I4=Ictat_v1 in the third conversion branch 101C3, and the fifth resistor R5 is of type RV2I. Therefore, under the first architecture 1011, for the third conversion branch 101C3, formula (16) can be transformed into the following formula (17): (17) Combination Figure 5 and Figure 7 In this context, since the reference current Iref is the reference voltage VBG output from the first output terminal of the bandgap reference circuit 101A, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied in the first conversion branch 101C1. The first conversion branch 101C1 then converts the reference voltage VBG into the reference current Iref for output. That is, when the input voltage Vinn of the conversion branch 1021 is the reference voltage VBG (i.e., Vinn = VBG), I4 = Iref.

[0118] As can be seen from the preceding introduction, in the first architecture 1011, Vinn=VBG, I4=Iref in the first conversion branch 101C1, and the fifth resistor R5 is of type Rref. Therefore, in the first architecture 1011, for the first conversion branch 101C1, formula (16) can be transformed into the following formula (18): (18) Substituting formulas (17) and (18) into formula (15), we can obtain another expression for the first duty cycle μ1, which can be found in formula (19) below: (19) Understandably, when the chip under test is of type 1, selecting the third type current Ictat_v1 from the second group of temperature currents as the first target current I1, and selecting the first type current Iptat from the first group of temperature currents as the second target current I2, this combination can meet the high-precision detection requirements of the chip under test in the low-temperature range, that is, it can improve the detection accuracy of the temperature detection circuit in the low-temperature range.

[0119] When the type of chip under test is type 2, such as Figure 11 The second architecture 1012 of the temperature detection circuit 10 shown has a register 101D that selects a fourth type current Ictat_v2 from the second group of temperature currents as the first target current I1, and selects a first type current Iptat from the first group of temperature currents as the second target current I2.

[0120] Understandably, without the third gain circuit KI3 and the fourth gain circuit KI4, the fourth type current Ictat_v2 and the first type current Iptat selected by register 101D are both unproportioned; with the fourth gain circuit KI4 and the third gain circuit KI3, the fourth type current Ictat_v2 and the first type current Iptat selected by register 101D are both proportional, that is, the fourth type current K4*Ictat_v2 with the fourth proportion is used as the first target current I1, and the first type current K3*Iptat with the third proportion is used as the second target current I2.

[0121] Combination Figure 9 For example, after selecting the first target current I1 and the second target current I2, register 101D outputs the first target current I1 to the first current branch I02A1 in the charging and discharging circuit 102, that is, I1=K4*Ictat_v2 at this time; outputs the second target current I2 to the second current branch I02A2 in the charging and discharging circuit 102, that is, I2=K3*Iptat at this time; and outputs the reference current Iref to the third current branch 102A3 in the charging and discharging circuit 102.

[0122] For the second architecture 1012, the expression for the discharge current Idischarge of the charging and discharging circuit 102 can be found in the following formula (20): (20) The expression for the charging current Icharge of the charging and discharging circuit 102 can be found in the following formula (21): (twenty one) Since the superposition of the first type current Iptat, which is positively correlated with temperature, and the fourth type current Ictat_v2, which is negatively correlated with temperature, can cancel out temperature drift and achieve a reference current Iref with a near-zero temperature coefficient, that is, under the second architecture 1012, the expression for the reference current Iref can be referred to as the following formula (22): (twenty two) Substituting formulas (20) and (21) into formula (10), we can obtain the duty cycle μ of the digital signal output by the first comparator U1 under the second architecture 1012. The duty cycle μ of the digital signal output by the first comparator U1 under the second architecture 1012 is called the second duty cycle μ2. The expression for the second duty cycle μ2 can be found in the following formula (23): (twenty three) Based on the relationship between the first type current Iptat, the fourth type current Ictat_v2, and the reference current Iref in formula (22), formula (23) can be transformed to obtain the following formula (24): (twenty four) Combination Figure 6 and Figure 7 In this context, since the fourth type current Ictat_v2 is the third voltage VSENSE output from the output terminal of the voltage reference circuit 101B, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied to the fourth conversion branch 101C4. The fourth conversion branch 101C4 then converts the third voltage VSENSE into the fourth type current Ictat_v2 for output. That is, when the input voltage Vinn of the conversion branch 1021 is the third voltage VSENSE (i.e., Vinn = VSENSE), I4 = Ictat_v2.

[0123] As can be seen from the previous introduction, in the second architecture 1012, Vinn=VSENSE, I4=Ictat_v2 in the fourth conversion branch 101C4, and the fifth resistor R5 is of type RV2I. Therefore, in the second architecture 1012, for the fourth conversion branch 101C4, formula (16) can be transformed into the following formula (25): (25) Combination Figure 5 and Figure 7In this context, since the reference current Iref is the reference voltage VBG output from the first output terminal of the bandgap reference circuit 101A, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied in the first conversion branch 101C1. The first conversion branch 101C1 then converts the reference voltage VBG into the reference current Iref for output. That is, when the input voltage Vinn of the conversion branch 1021 is the reference voltage VBG (i.e., Vinn = VBG), I4 = Iref.

[0124] As can be seen from the previous introduction, in the second architecture 1012, Vinn=VBG, I4=Iref in the first conversion branch 101C1, and the fifth resistor R5 is of type Rref. Therefore, in the second architecture 1012, for the first conversion branch 101C1, formula (16) can be transformed into the following formula (26): (26) Substituting formulas (25) and (26) into formula (24), we can obtain another expression for the second duty cycle μ2, which can be found in formula (27) below: (27) It is understandable that when the chip under test is of type 2, selecting the fourth type current Ictat_v2 from the second group of temperature currents as the first target current I1, and selecting the first type current Iptat from the first group of temperature currents as the second target current I2, can meet the testing requirements of the chip under test to balance both detection accuracy and power consumption.

[0125] When the type of chip under test is type 3, such as Figure 12 The third architecture 1013 of the temperature detection circuit 10 shown has a register 101D that selects a second type current Iptat_v from the first group of temperature currents as the first target current I1, and selects a third type current Ictat_v1 from the second group of temperature currents as the second target current I2.

[0126] It is understandable that, without the first gain circuit KI1 and the second gain circuit KI2, the second type current Iptat_v and the third type current Ictat_v1 selected by register 101D are both unproportioned; with the first gain circuit KI1 and the second gain circuit KI2, the second type current Iptat_v and the third type current Ictat_v1 selected by register 101D are both proportional, that is, the second type current K1*Iptat_v with the first proportion is used as the first target current I1, and the third type current K2*Ictat_v1 with the second proportion is used as the second target current I2.

[0127] Combination Figure 9 In general, after selecting the first target current I1 and the second target current I2, register 101D outputs the first target current I1 to the first current branch I02A1 in the charging and discharging circuit 102, that is, I1=K1*Iptat_v at this time; outputs the second target current I2 to the second current branch I02A2 in the charging and discharging circuit 102, that is, I2=K2*Ictat_v1 at this time; and outputs the reference current Iref to the third current branch 102A3 in the charging and discharging circuit 102.

[0128] For the third architecture 1013, the expression for the discharge current Idischarge of the charging and discharging circuit 102 can be found in the following formula (28): (28) The expression for the charging current Icharge of the charging and discharging circuit 102 can be found in the following formula (29): (29) Since the superposition of the second type current Iptat_v1, which is positively correlated with temperature, and the third type current Ictat_v1, which is negatively correlated with temperature, can cancel out temperature drift and achieve a reference current Iref with a near-zero temperature coefficient, that is, under the third architecture 1013, the expression for the reference current Iref can be referred to the following formula (30): (30) Substituting formulas (28) and (29) into formula (10), we can obtain the duty cycle μ of the digital signal output by the first comparator U1 under the third architecture 1013. The duty cycle μ of the digital signal output by the first comparator U1 under the third architecture 1013 is called the third duty cycle μ3. The expression for the third duty cycle μ3 can be found in the following formula (31): (31) Based on the relationship between the second type current Iptat_v1, the third type current Ictat_v1, and the reference current Iref in formula (30), formula (31) can be transformed to obtain the following formula (32): (32) Combination Figure 5 and Figure 7In this context, since the second type current Iptat_v is the first voltage Vadvbe output from the second output terminal of the bandgap reference circuit 101A, when the conversion branch 1021 is applied in the second conversion branch 101C2, the second conversion branch 101C2 converts the first voltage Vadvbe into the second type current Iptat_v for output. That is, when the input voltage Vinn of the conversion branch 1021 is the first voltage Vadvbe (i.e., Vinn = Vadvbe), I4 = Iptat_v.

[0129] As can be seen from the previous introduction, in the second architecture 1012, Vinn=Vadvbe, I4=Iptat_v in the fourth conversion branch 101C4, and the fifth resistor R5 is of type RV2I. Therefore, in the third architecture 1013, for the second conversion branch 101C2, formula (16) can be transformed into the following formula (33): (33) Combination Figure 5 and Figure 7 In this context, since the reference current Iref is the reference voltage VBG output from the first output terminal of the bandgap reference circuit 101A, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied in the first conversion branch 101C1. The first conversion branch 101C1 then converts the reference voltage VBG into the reference current Iref for output. That is, when the input voltage Vinn of the conversion branch 1021 is the reference voltage VBG (i.e., Vinn = VBG), I4 = Iref.

[0130] As can be seen from the previous introduction, in the second architecture 1012, Vinn=VBG, I4=Iref in the first conversion branch 101C1, and the fifth resistor R5 is of type Rref. Therefore, in the second architecture 1012, for the first conversion branch 101C1, formula (16) can be transformed into the following formula (34): (34) Substituting formulas (33) and (34) into formula (32), we can obtain another expression for the third duty cycle μ3, which can be found in formula (35) below: (35) It is understandable that when the chip under test is of type three, selecting the second type current Iptat_v from the first group of temperature currents as the first target current I1, and selecting the third type current Ictat_v1 from the second group of temperature currents as the second target current I2, this combination can meet the chip under test's detection requirements for a wide temperature range.

[0131] When the type of the chip under test is type four, such as Figure 13 The fourth architecture 1014 of the temperature detection circuit 10 shown has a register 101D that selects a first type of current Iptat from the first group of temperature currents as the first target current I1, and selects a third type of current Ictat_v1 from the second group of temperature currents as the second target current I2.

[0132] It is understandable that, without the third gain circuit KI3 and the second gain circuit KI2, the first type current Iptat and the third type current Ictat_v1 selected by register 101D are both unproportioned; with the third gain circuit KI3 and the second gain circuit KI2, the first type current Iptat and the third type current Ictat_v1 selected by register 101D are both proportional, that is, the first type current K3*Iptat with the third proportion is used as the first target current I1, and the third type current K2*Ictat_v1 with the second proportion is used as the second target current I2.

[0133] Combination Figure 9 For example, after selecting the first target current I1 and the second target current I2, register 101D outputs the first target current I1 to the first current branch I02A1 in the charging and discharging circuit 102, that is, I1=K3*Iptat at this time; outputs the second target current I2 to the second current branch I02A2 in the charging and discharging circuit 102, that is, I2=K2*Ictat_v1 at this time; and outputs the reference current Iref to the third current branch 102A3 in the charging and discharging circuit 102.

[0134] For the fourth architecture 1014, the expression for the discharge current Idischarge of the charging and discharging circuit 102 can be found in the following formula (36): (36) The expression for the charging current Icharge of the charging and discharging circuit 102 can be found in the following formula (37): (37) Since the superposition of the first type current Iptat_v, which is positively correlated with temperature, and the third type current Ictat_v1, which is negatively correlated with temperature, can cancel out temperature drift and achieve a reference current Iref with a near-zero temperature coefficient, that is, under the fourth architecture 1014, the expression for the reference current Iref can be referred to as the following formula (38): (38) Substituting formulas (36) and (37) into formula (10), we can obtain the duty cycle μ of the digital signal output by the first comparator U1 under the fourth architecture 1014. The duty cycle μ of the digital signal output by the first comparator U1 under the four architectures 1014 is called the fourth duty cycle μ4. The expression of the fourth duty cycle μ4 can be found in the following formula (39): (39) Based on the relationship between the first type current Iptat_v, the third type current Ictat_v1, and the reference current Iref in formula (38), formula (39) can be transformed to obtain the following formula (40): (40) Combination Figure 5 Since the first type current Iptat is directly output from the fourth output terminal of the bandgap reference circuit 101A, according to the characteristics of the current mirror circuit and formula (9), the expression for the first type current Iptat can be obtained, and the following formula (41) can be referenced: (41) Combination Figure 5 and Figure 7 In this context, since the reference current Iref is the reference voltage VBG output from the first output terminal of the bandgap reference circuit 101A, it enters the second input terminal of the conversion branch 1021 when the conversion branch 1021 is applied in the first conversion branch 101C1. The first conversion branch 101C1 then converts the reference voltage VBG into the reference current Iref for output. That is, when the input voltage Vinn of the conversion branch 1021 is the reference voltage VBG (i.e., Vinn = VBG), I4 = Iref.

[0135] As can be seen from the previous introduction, in the fourth architecture 1014, Vinn=VBG, I4=Iref in the first conversion branch 101C1, and the fifth resistor R5 is of type Rref. Therefore, in the fourth architecture 1014, for the first conversion branch 101C1, formula (16) can be transformed into the following formula (42): (42) Substituting formulas (41) and (42) into formula (40), we can obtain another expression for the fourth duty cycle μ4, which can be found in formula (43) below: (43) Understandably, when the chip under test is of type four, selecting the first type current Iptat from the first group of temperature currents as the first target current I1, and selecting the third type current Ictat_v1 from the second group of temperature currents as the second target current I2, can meet the testing requirements of the chip under test for balancing wide temperature range and high precision.

[0136] It is understandable that different duty cycles μ of the digital signal output by the charging / discharging circuit 102 will result in different high-level widths of the pulse width modulation signal with temperature information output by the signal logic circuit 103A. In other words, different duty cycles of the high-level pulse width modulation signal with temperature information will lead to different total number of high-level pulse width modulation signals with temperature information counted by the counter within the set time. Consequently, the variable u in the temperature calculation formula will be different, and the measured temperature T of each type of chip under test will be different, thus realizing the detection of the temperature of different types of chips.

[0137] It is understood that in the embodiments of this application, the register dynamically selects different current combinations to form a target current group based on different types of chips and inputs it to the charging and discharging circuit. The charging and discharging circuit can achieve the charging and discharging function regardless of which two current combinations form the target current group, so as to adapt to the temperature characteristics of various chips and the requirements for temperature detection accuracy. This can improve the measurement accuracy and applicability of the temperature detection circuit.

[0138] Figure 14 This is a schematic diagram of temperature curves for a first architecture and a second architecture provided in the embodiments of this application, as shown below. Figure 14 As shown, curve A01 represents the relationship between the second voltage Vbe1 or the third voltage VSENSE and temperature. It can be seen that the second voltage Vbe1 or the third voltage VSENSE is negatively correlated with temperature.

[0139] For the first architecture 1011, a second voltage Vbe1 negatively correlated with temperature is generated using a bandgap reference circuit 101A. After passing through the third conversion branch 101C3, a third type of current Ictat_v1 negatively correlated with temperature is generated. For the second architecture 1012, a third voltage VSENSE negatively correlated with temperature is generated using a voltage reference circuit 101B. After passing through the fourth conversion branch 101C4, a fourth type of current Ictat_v2 negatively correlated with temperature is generated.

[0140] Curve A02 represents the relationship between the voltage difference dVbe between the base and emitter voltage Vbe of a bipolar transistor with a fourth coefficient a and temperature. It can be seen that the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor with a fourth coefficient a is positively correlated with temperature.

[0141] Curve A03 represents the relationship between the reference voltage VBG and temperature. In the case of the first architecture 1011, the relationship between the reference voltage VBG, the second voltage Vbe1, and the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor with the fourth coefficient a can be found in the following formula (44): (44) In the case of the second architecture 1012, the relationship between the reference voltage VBG, the third voltage VSENSE, and the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor with the fourth coefficient a can be referred to as the following formula (45): (45) from Figure 14 As can be seen, the reference voltage VBG is constant regardless of the temperature; for example, it is constant at 1.2V.

[0142] Curve A04 represents variable u, from Figure 14 As can be seen, u is negatively correlated with temperature, and the variable u can range from 0 to 100%. For example, as the temperature increases, the variable u can decrease from 90% to 30%.

[0143] Figure 15 These are schematic diagrams of temperature profiles for a third and a fourth architecture provided in embodiments of this application, as shown below. Figure 15 As shown, curve A01 represents the relationship between the second voltage Vbe1 and temperature. It can be seen that the second voltage Vbe1 is negatively correlated with temperature.

[0144] For the third architecture 1013 and the fourth architecture 1014, the bandgap reference circuit 101A generates a second voltage Vbe1 that is negatively correlated with temperature. After passing through the third conversion branch 101C3, it can generate a third type of current Ictat_v1 that is negatively correlated with temperature. For the third architecture 1013, the bandgap reference circuit 101A generates a first voltage Vadvbe that is positively correlated with temperature. After passing through the second conversion branch 101C2, it can generate a second type of current Iptat_v that is positively correlated with temperature. For the fourth architecture 1014, the bandgap reference circuit 101A can directly generate a first type of current Iptat that is positively correlated with temperature.

[0145] Curve A02 represents the relationship between the voltage difference dVbe between the base and emitter voltage Vbe of a bipolar transistor with a fourth coefficient a and temperature. It can be seen that the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor with a fourth coefficient a is positively correlated with temperature.

[0146] Curve A03 represents the relationship between the reference voltage VBG and temperature. In both the third architecture 1013 and the fourth architecture 1014, the relationship between the reference voltage VBG, the second voltage Vbe1, and the voltage difference dVbe between the base and emitter voltage Vbe of the bipolar transistor with the fourth coefficient a is as follows (46): (46) from Figure 15 As can be seen, the reference voltage VBG is constant regardless of the temperature; for example, it is constant at 1.2V.

[0147] Curve A04 represents variable u, from Figure 15 As can be seen, variable u is positively correlated with temperature. For example, as the temperature increases, variable u can increase from 30% to 90%.

[0148] It is understandable that a change in variable u will change the accuracy of temperature detection circuit 10. For example, an increase in variable u will also increase the accuracy of temperature detection circuit 10.

[0149] The following examples illustrate possible implementation schemes of the temperature detection circuit described in one or more of the above embodiments.

[0150] Temperature sensor circuits (i.e., temperature detection circuit 10) are commonly used for temperature detection in chips. The core technology lies in utilizing the inherent temperature characteristics of semiconductor devices to directly convert thermal quantities into electrical quantities, which are then processed by an analog-to-digital converter within the MCU, and finally the corresponding temperature value is calculated by software. However, temperature sensor circuits in related technologies employ a single architecture, which limits their performance.

[0151] This embodiment provides a temperature sensor circuit composed of a voltage and current generation circuit module (i.e., front-end circuit 101), a Σ-Δ analog-to-digital converter (ADC) module (i.e., analog-to-digital conversion circuit 103), and a constant charge circuit module (i.e., charge-discharge circuit 102). The temperature sensor circuit converts temperature information into digital signals, reads the corresponding digital signals using a counter, and then calculates the temperature to be measured. Different chips have different requirements for the accuracy, area, and power consumption of the temperature sensor circuit. The temperature sensor circuit provided in this embodiment allows selection of four different types of current through register configuration. After analog-to-digital conversion (ADC), four digital signals are generated for temperature calculation. Therefore, the temperature sensor circuit provided in this embodiment allows selection of the type (i.e., architecture) of the temperature sensor circuit through registers to match the requirements of different chips.

[0152] The schematic diagram of the temperature sensor circuit provided in this embodiment can be found in the figure.

[0153] The voltage and current generation circuit module (i.e., front-end circuit 101) includes a bandgap reference circuit 101A, a voltage-to-current circuit (i.e., voltage-to-current conversion circuit 101C), and a voltage reference circuit 101B. This module can generate the required voltage and current. Examples include: a temperature-independent reference voltage VBG, temperature-negatively correlated voltages vbe1 and VSENSE, and a temperature-positively correlated voltage Vadvbe; a temperature-independent reference current Iref (i.e., reference current); temperature-negatively correlated currents Ictat_v1 and Ictat_v2; and temperature-positively correlated currents Iptat_v and Iptat.

[0154] The continuous charging circuit module (i.e., charging and discharging circuit 102) controls the charging and discharging of the circuit. The register in the voltage and current generation circuit module selects different types and proportions of current to be connected to the continuous charging circuit module. The feedback digital signal (i.e., feedback signal FBDAC) of the Σ-Δ analog-to-digital converter module (i.e., analog-to-digital converter circuit 103) controls the charging and discharging state of the circuit. The temperature is determined by the time during the charging and discharging of the circuit.

[0155] The Σ-Δ analog-to-digital converter (ADC) module (i.e., ADC 103) includes an integrator and a comparator, which converts the analog signal into a digital signal (i.e., a pulse width modulation signal) containing temperature information. At the same temperature, four different types of temperature sensor circuits convert the analog signal into a digital signal through the Σ-Δ ADC module. The high duty cycle of the digital signal is related to the selected charge / discharge type and ratio, respectively.

[0156] Among them, four different types of temperature sensor circuits can be referenced. Figures 10-13 The main difference lies in the current selection of the continuous charging circuit module, and the charging and discharging time determines the temperature.

[0157] The charging and discharging time corresponds to the high and low of the digital signal. Assuming that the high duty cycle of the output digital signal is μ, it satisfies the law of charge conservation. The law of charge conservation can be found in formula (10).

[0158] Architecture 1 (i.e., the first architecture 1011), such as Figure 10 As shown: (11) (12) (13) Substituting into formula (10), we get: (15) Furthermore: (19) For a detailed derivation process, please refer to the relevant descriptions in the aforementioned embodiments; they will not be repeated here.

[0159] Architecture 2 (i.e., the second architecture 1012), such as Figure 11 As shown: (20) (twenty one) (twenty two) Substituting into formula (10), we get: (twenty four) Furthermore: (27) For a detailed derivation process, please refer to the relevant descriptions in the aforementioned embodiments; they will not be repeated here.

[0160] Architecture 3 (i.e., the third architecture 1013), such as Figure 12 As shown: (28) (29) (30) Substituting into formula (10), we get: (32) Furthermore: (35) For a detailed derivation process, please refer to the relevant descriptions in the aforementioned embodiments; they will not be repeated here.

[0161] Architecture 4 (i.e., the fourth architecture 1014), such as Figure 13 As shown: (36) (37) (38) Substituting into formula (10), we get: (40) Furthermore: (43) For a detailed derivation process, please refer to the relevant descriptions in the aforementioned embodiments; they will not be repeated here.

[0162] The temperature curves for Architecture 1 and Architecture 2 can be referenced. Figure 14 The temperature profiles for Architecture 3 and Architecture 4 can be referenced. Figure 15 Among them, architecture 1 and architecture 2 are negative temperature curves. Architecture 1 uses the vbe1 voltage in the bandgap reference circuit 101A to generate the current Ictat_v1, and architecture 2 uses the VSENSE voltage of the external PNP type switch (i.e., voltage reference circuit 101B) to generate the current Ictat_v2. Architecture 3 and architecture 4 are positive temperature curves. Architecture 3 uses the Vadvbe voltage in the bandgap reference circuit 101A to generate the current Iptat_v, and architecture 4 directly uses the Iptat of the bandgap reference circuit 101A.

[0163] The circuit structure of the voltage and current generation circuit module (i.e., front-end circuit 101) can be referenced. Figure 5 , Figure 6 and Figure 7 .

[0164] For detailed information, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0165] The circuit structure of the continuous charging circuit module (i.e., charging and discharging circuit 102) can be referenced. Figure 8 .

[0166] For detailed information, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0167] It is understandable that the current flowing into V1 is selected by closing the control switch (i.e., the first switching element K1), thereby controlling the charging and discharging state of the capacitor (i.e., the first energy storage element C1). The types of I1 and I2 can be selected through the register, thereby selecting a test temperature for a specific architecture.

[0168] The circuit structure of the Σ-Δ analog-to-digital converter module (i.e., analog-to-digital converter circuit 103) can be referenced. Figure 9 .

[0169] For detailed information, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0170] The analog signal is converted into a digital signal by the comparator inside the Σ-Δ analog-to-digital converter circuit module. The comparator result determines the level of the feedback signal FBDAC. The feedback signal FBDAC controls the opening and closing of the current switch (i.e., the first switching element K1), thereby controlling the charging and discharging of the continuous charging circuit module. After passing through the digital logic unit (i.e., the signal logic circuit 103A), a digital signal with temperature information (i.e., a pulse width modulation signal with temperature information) can be obtained.

[0171] Understandably, under different architectures, the duty cycle μ of the digital signal output by the charging / discharging circuit 102 can be changed by adjusting the corresponding ratio. Different duty cycles μ of the digital signal output by the charging / discharging circuit 102 will result in different high-level widths of the pulse-width modulation (PWM) signal carrying temperature information output by the signal logic circuit 103A, meaning different duty cycles of the high-level PWM signal carrying temperature information. Consequently, the total number of high-level PWM signals carrying temperature information counted by the counter within the set time period will be different.

[0172] A pulse width modulation (PWM) signal carrying temperature information is sent to a counter. The counter counts the total number of high-level pulse width modulation signals carrying temperature information within a set time. After obtaining the total number, the total number is divided by the acquisition accuracy of the temperature detection circuit 10 (e.g., 11-bit sampling accuracy, i.e., 2^35). ^11 =2048) to obtain the variable u in the temperature calculation formula, thereby realizing the measurement of the temperature of the chip under test.

[0173] From formula (1): (1) It can be seen that the total number of high-level pulse width modulation signals with temperature information within the set time of the counter will be different, which will result in different variables u in formula (1). The measured temperature T of each type of chip will be different, thus realizing the detection of the temperature of different types of chips.

[0174] In other words, under different architectures, by adjusting the corresponding ratio, the slope in formula (1) can be changed, and the accuracy of the temperature sensor circuit can be changed.

[0175] The temperature sensor circuit provided in this embodiment can select the type (i.e., architecture) of the temperature sensor circuit through a register to match the requirements of different chips.

[0176] Based on the same inventive concept as the foregoing embodiments, this application also provides a chip. Figure 16 This is a schematic diagram of the structure of a chip provided in an embodiment of this application, such as... Figure 16 As shown, chip 160 includes a temperature detection circuit 10.

[0177] For example, the type of chip 160 can be an MCU.

[0178] It should be noted that a detailed description of the temperature detection circuit 10 can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0179] It should be noted that the chip 160 provided in this application embodiment can achieve the same technical effect as the aforementioned temperature detection circuit 10, and will not be described again here.

[0180] Based on the same inventive concept as the foregoing embodiments, this application also provides an electronic device. Figure 17 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 17 As shown, the electronic device 170 includes a chip 160.

[0181] It should be noted that detailed information about chip 160 can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0182] It should be noted that the electronic device 170 provided in this application embodiment can achieve the same technical effect as the chip 160, which will not be described in detail here.

[0183] It should be noted that the module division in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or have two or more units integrated into one unit. The integrated units can be implemented in hardware, as software functional units, or a combination of software and hardware.

[0184] It should be understood that those skilled in the art will recognize that this application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0185] It should also be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0186] It should be noted that in this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three cases: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0187] It should also be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0188] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and system can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0189] The modules described above as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network units; some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional modules in the embodiments of this application may all be integrated into one processing unit, or each module may be a separate unit, or two or more modules may be integrated into one unit; the integrated modules may be implemented in hardware or in a combination of hardware and software functional units.

[0190] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0191] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A temperature detection circuit, characterized in that, include: The circuit comprises a front-end circuit, a charging / discharging circuit, and an analog-to-digital converter circuit; the output terminal of the front-end circuit is connected to the input terminal of the charging / discharging circuit, and the input terminal and feedback terminal of the analog-to-digital converter circuit are respectively connected to the output terminal and control terminal of the charging / discharging circuit; wherein: The front-end circuit is configured to generate a reference current, a first set of temperature currents, and a second set of temperature currents. The first set of temperature currents is a set of at least two currents that are positively correlated with temperature, and the second set of temperature currents is a set of at least two currents that are negatively correlated with temperature. Based on the type of the chip under test, a first target current and a second target current are selected from the first set of temperature currents and the second set of temperature currents. The type of the chip under test includes multiple types distinguished according to the temperature detection accuracy requirements. The charging and discharging circuit is configured to receive the reference current, the first target current, and the second target current provided by the front-end circuit; and, upon receiving a feedback signal provided by the analog-to-digital conversion circuit, to generate a first reference voltage and a second reference voltage based on the level state of the feedback signal using the reference current, the first target current, and the second target current. The analog-to-digital converter circuit is configured to receive the first reference voltage and the second reference voltage provided by the charging and discharging circuit, and to compare and perform logical operations based on the first reference voltage and the second reference voltage to generate the feedback signal and the pulse width modulation signal with temperature information.

2. The temperature detection circuit according to claim 1, characterized in that, The front-end circuit includes a bandgap reference circuit, a voltage-to-current conversion circuit, a voltage reference circuit, and a register; the bandgap reference circuit and the voltage reference circuit are respectively connected to the voltage input terminal of the voltage-to-current conversion circuit, and the current output terminal of the voltage-to-current conversion circuit is connected to the input terminal of the register; wherein: The bandgap reference circuit is configured to generate a reference voltage, a first voltage positively correlated with temperature, a second voltage negatively correlated with temperature, and a first type of current in the first group of temperature currents; The voltage reference circuit is configured to generate a third voltage that is negatively correlated with temperature. The voltage-to-current conversion circuit is configured to receive the reference voltage, the first voltage, the second voltage, and the third voltage, and to perform voltage-to-current conversion on the reference voltage, the first voltage, the second voltage, and the third voltage respectively, to obtain the reference current, the second type current in the first group of temperature currents, the third type current in the second group of temperature currents, and the fourth type current in the second group of temperature currents. The register is configured to receive and store the reference current, the first type of current, the second type of current, the third type of current, and the fourth type of current; and to select the first target current and the second target current based on the type of the chip under test, and send the reference current, the first target current, and the second target current to the charging and discharging circuit.

3. The temperature detection circuit according to claim 2, characterized in that, The voltage-to-current conversion circuit includes a first conversion branch, a second conversion branch, a third conversion branch, and a fourth conversion branch; wherein: The first conversion branch is connected to the first output terminal of the bandgap reference circuit and is configured to receive the reference voltage provided by the bandgap reference circuit and convert the reference voltage into the reference current. The second conversion branch is connected to the second output terminal of the bandgap reference circuit and is configured to receive the first voltage provided by the bandgap reference circuit and convert the first voltage into the second type of current. The third conversion branch is connected to the third output terminal of the bandgap reference circuit and is configured to receive the second voltage provided by the bandgap reference circuit and convert the second voltage into the third type of current. The fourth conversion branch is connected to the output terminal of the voltage reference circuit and is configured to receive the third voltage provided by the voltage reference circuit and convert the third voltage into the fourth type of current.

4. The temperature detection circuit according to claim 3, characterized in that, The front-end circuit further includes a first gain circuit, a second gain circuit, a third gain circuit, and a fourth gain circuit; wherein: The first gain circuit is connected to the output terminal of the second conversion branch and is configured to adjust the second type of current. The second gain circuit is connected to the output terminal of the third conversion branch and is configured to adjust the third type of current; The third gain circuit is connected to the fourth output terminal of the bandgap reference circuit and is configured to adjust the first type of current. The fourth gain circuit is connected to the output terminal of the fourth conversion branch and is configured to adjust the fourth type of current.

5. The temperature detection circuit according to any one of claims 2 to 4, characterized in that, The register is also configured to select a first target current and a second target current according to the type of the chip under test in the following manner: When the type of the chip under test is the first type, the third type current is selected from the second group of temperature currents as the first target current, and the first type current is selected from the first group of temperature currents as the second target current; or, When the type of the chip under test is the second type, the fourth type current is selected from the second group of temperature currents as the first target current, and the first type current is selected from the first group of temperature currents as the second target current; or, When the type of the chip under test is the third type, the second type current is selected from the first group of temperature currents as the first target current, and the third type current is selected from the second group of temperature currents as the second target current. or, If the type of the chip under test is not the fourth type, the first type of current is selected from the first group of temperature currents as the first target current, and the third type of current is selected from the second group of temperature currents as the second target current.

6. The temperature detection circuit according to claim 5, characterized in that, The charging and discharging circuit includes a first comparator, a first current branch, a second current branch, a third current branch, a first switching element, a first energy storage element, and a third reference voltage source. The third reference voltage source is a reference voltage source, and the voltage value of the third reference voltage source is pre-configured and adapted to the detection threshold of different chip types. The first current branch is used to receive the first target current, the second current branch is used to receive the second target current, and the third current branch is used to receive the reference current. The first input terminal of the first comparator is connected to the output terminal of the third reference voltage source. The second input terminal of the first comparator is connected to the first terminal of the first switching element, the first terminal of the first energy storage element, the output terminal of the first current branch, and the output terminal of the second current branch, respectively. The output terminal of the first comparator is connected to the second terminal of the first energy storage element. The first and second power supply output terminals of the first comparator are correspondingly connected to the two input terminals of the analog-to-digital converter circuit. The second terminal of the first switching element is connected to the output terminal of the third current branch. The control terminal of the first switching element is connected to the feedback terminal of the analog-to-digital converter circuit as the control terminal of the charging and discharging circuit. Wherein: The charging and discharging circuit is configured to, when the feedback signal is at a first level, disconnect the first switching element and charge the first energy storage element using the difference between the first target current and the second target current, so as to increase the input voltage at the second input terminal of the first comparator; or, when the feedback signal is at a second level, turn on the first switching element and control the first energy storage element to discharge based on the difference between the first target current, the second target current, and the reference current, so as to decrease the input voltage at the second input terminal of the first comparator. The first comparator is configured such that, when the voltage value of the third reference voltage source is greater than the input voltage, the first reference voltage output through the first power supply output terminal is greater than the second reference voltage output through the second power supply output terminal; or, when the voltage value of the third reference voltage source is less than the input voltage, the first reference voltage output through the first power supply output terminal is less than the second reference voltage output through the second power supply output terminal.

7. The temperature detection circuit according to claim 6, characterized in that, The analog-to-digital converter circuit includes a second comparator and a signal logic circuit; the first input terminal of the second comparator is connected to the second power supply output terminal of the first comparator as the first input terminal of the analog-to-digital converter circuit, the second input terminal of the second comparator is connected to the first power supply output terminal of the first comparator as the second input terminal of the analog-to-digital converter circuit, and the output terminal of the second comparator is connected to the input terminal of the signal logic circuit; wherein: The second comparator is configured to output a first signal to the signal logic circuit when the first reference voltage is greater than the second reference voltage; or, to output a second signal to the signal logic circuit when the first reference voltage is less than the second reference voltage. The signal logic circuit is configured to generate a feedback signal at a first level state based on the first signal and send it to the control terminal of the first switching element to control the first switching element to open; or, to generate a feedback signal at a second level state based on the second signal and send it to the control terminal of the first switching element to control the first switching element to close. The signal logic circuit is further configured to combine the first signal and the second signal to generate the pulse width modulation signal with temperature information.

8. The temperature detection circuit according to claim 3 or 4, characterized in that, The bandgap reference circuit includes a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, an eighth switching element, a third comparator, a first resistor, a second resistor, a third resistor, and a fourth resistor; wherein: The first terminals of the second, third, fourth, and fifth switching elements are all connected to a first voltage source; the control terminal of the second switching element is connected to the control terminal of the third switching element, and the control terminal of the second switching element is also connected to the second terminal of the second switching element; the second terminal of the third switching element is connected to the first terminal of the first resistor and the second terminal of the second resistor, respectively, and the first terminal of the first resistor serves as the first output terminal of the bandgap reference circuit; the third terminal of the third switching element is connected to the control terminal of the fourth switching element; the second terminal of the fourth switching element is connected to the first terminal of the fourth resistor, and the first terminal of the fourth resistor serves as the second output terminal of the bandgap reference circuit; the third terminal of the fourth switching element is connected to the control terminal of the fifth switching element; the second terminal of the fifth switching element serves as the fourth output terminal of the bandgap reference circuit. The second end of the first resistor is connected to the first input terminal of the third comparator and the first end of the seventh switching element, respectively, and the first end of the seventh switching element serves as the third output terminal of the bandgap reference circuit; the second end of the second resistor is connected to the second input terminal of the third comparator and the first end of the third resistor; the second end of the third resistor is connected to the first end of the eighth switching element; the output terminal of the third comparator is connected to the control terminal of the sixth switching element; the first end of the sixth switching element is connected to the second end of the second switching element; the second end of the fourth resistor, the second end of the sixth switching element, the second end of the seventh switching element, the control terminal of the seventh switching element, the second end of the eighth switching element, and the control terminal of the eighth switching element are respectively connected to a power supply voltage source.

9. The temperature detection circuit according to claim 3, characterized in that, Each conversion branch includes a fourth comparator, a ninth switching element, a tenth switching element, and a fifth resistor; the fourth comparator, the ninth switching element, the tenth switching element, and the fifth resistor constitute a feedback voltage-current conversion structure, and a constant current output is achieved through the feedback regulation of the fourth comparator; The first input terminal of the fourth comparator is connected to the first terminal of the fifth resistor; the second terminal of the fifth resistor is connected to a power supply voltage source; the output terminal of the fourth comparator is connected to the control terminal of the ninth switching element and the control terminal of the tenth switching element, respectively; the first terminals of the ninth and tenth switching elements are both connected to a second voltage source; the second terminal of the ninth switching element is connected to the first terminal of the fifth resistor; wherein: When the conversion branch is the first conversion branch, the second input terminal of the fourth comparator is connected to the first output terminal of the bandgap reference circuit, and the second terminal of the tenth switching element is used to output the reference current; When the conversion branch is the second conversion branch, the second input terminal of the fourth comparator is connected to the second output terminal of the bandgap reference circuit, and the second terminal of the tenth switching element outputs the second type of current; When the conversion branch is the third conversion branch, the second input terminal of the fourth comparator is connected to the third output terminal of the bandgap reference circuit, and the second terminal of the tenth switching element outputs the third type of current; When the conversion branch is the fourth conversion branch, the second input terminal of the fourth comparator is connected to the output terminal of the voltage reference circuit, and the second terminal of the tenth switching element outputs the fourth type of current.

10. A chip, characterized in that, Includes a temperature detection circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, Includes the chip as described in claim 10.

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