Fast-response digital low-dropout regulators for optical I / O chips

Abstract

This invention discloses a fast-response digital low-dropout regulator for optical I / O chips, comprising: voltage difference calculation logic for calculating the voltage difference between the output voltage of the power transistor and the reference voltage; parameter generation logic for obtaining the optimal algorithm tuning parameters of the system based on a genetic algorithm; feedback logic for generating the feedback control quantity of the voltage control loop based on PID tuning of the voltage error; a first adder for summing to generate the total feedback control quantity of the voltage control loop; feedforward logic for generating the feedforward control quantity of the current control loop; and a second adder for summing the number of power switches turned on at the current time t, the total feedback control quantity, and the feedforward control quantity to obtain the number of power switches turned on at the next time t+1 to control the power switch state in the power transistor. This invention aims to proactively compensate for load current fluctuations before a significant voltage drop occurs, achieving superior voltage regulation performance.

Description

Technical Field

[0001] This invention relates to digital low dropout regulators (DLDOs), and more specifically to a fast-response digital low dropout regulator for optical I / O chips. Background Technology

[0002] The integration of heterogeneous computing units, coupled with the growing demands of artificial intelligence workloads, is driving the development of ultra-large-scale system-on-chip (SoC) designs. Increased architectural complexity leads to higher power density, making robust and efficient power supply a key consideration in modern chip design. Dynamic voltage-frequency regulation (DVFS) is the mainstream method for achieving high energy efficiency in such systems. However, the performance of DVFS solutions is limited by response time and efficiency. Digital low-dropout regulators (LDVRegulators) have become the preferred solution for fine-grained voltage regulation due to their stability, small silicon footprint, and compatibility with advanced CMOS processes.

[0003] The core function of a digital low-dropout regulator is to maintain output voltage stability under transient load conditions, which requires generating control commands based on precise monitoring of the chip state. In synchronous digital circuits, path timing is indirectly related to the supply voltage. Therefore, monitoring circuit timing is an effective means of measuring voltage sags and is crucial for dynamic voltage frequency regulation control. Circuit timing monitoring techniques include ring oscillator sensors, critical path replication, and in-situ timing error detection circuits, all of which form the basis for achieving dynamic voltage frequency regulation. However, regardless of the accuracy of these techniques, dynamic voltage frequency regulation is essentially passive. Chip power consumption depends on instruction execution, while on-chip voltage / current sensors can only reflect the processor's past and current states. Therefore, control measures based on such information are inevitably lagging, and the system is forced to endure the resulting voltage drops, performance degradation, and potential functional errors, with the load current exhibiting different states sequentially. In some states, if the output voltage drop exceeds a safe threshold, timing violations will occur on the data path, leading to performance degradation and potential functional errors. Although software- and microarchitecture-based techniques exist to predict workload changes, the real-time power consumption of the CPU still has significant uncertainties. Microarchitectural events such as cache misses, branch prediction errors, data conflicts, and resource contentions introduce significant unpredictability, leading to highly irregular power consumption trajectories. To address the challenge of nonlinear power consumption prediction, recent research has explored methods using neural networks. However, such models are typically trained on finite datasets, making it difficult to generalize to unexpected scenarios (such as sudden user interactions), resulting in poor prediction accuracy. Furthermore, online deployment of neural network models incurs significant area and power overhead. Most critically, voltage regulation requires per-cycle operation, while completing neural network inference within a single clock cycle is computationally impractical. Summary of the Invention

[0004] The technical problem to be solved by this invention is to provide a fast-response digital low-dropout regulator for optical I / O chips, addressing the aforementioned problems of the prior art. This invention aims to solve the inherent response delay problem of traditional digital low-dropout regulators and achieve excellent voltage regulation performance.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A fast-response digital low-dropout regulator for optical I / O chips, comprising:

[0007] Voltage difference calculation logic, used to calculate the voltage difference err between the power transistor's output voltage and the reference voltage;

[0008] The parameter generation logic optimizes the parameters of the feedback and feedforward logics using a genetic algorithm to obtain the optimal parameters, including the PID parameter K of the feedback logic. pv K iv and K dv And the PID parameter K of the feedforward logic pi and K di ;

[0009] Feedback logic is used to determine the PID parameter K. pv K iv and K dv The feedback control quantity of the voltage control loop is generated by PID control using the voltage difference err, the integral of the most recent multiple voltage differences and Σerr, and the change in voltage difference err Δerr.

[0010] The first adder is used to generate the total feedback control quantity of the voltage control loop from the feedback control quantity of the voltage difference err, the integral of the most recent multiple voltage differences and Σerr, and the change in voltage difference err Δerr.

[0011] Feedforward logic is used to determine the PID parameter K separately. pi and K di The number of power switches turned on at the current time t, Non(t), and the change in the number of power switches are used to generate feedforward control quantities for the current control loop through PID control.

[0012] The second adder is used to sum the number of power switches turned on at the current time t (Non(t)), the total feedback control quantity of the voltage control loop, and the feedforward control quantity of each current control loop to obtain the number of power switches turned on at the next time t+1 (Non(t+1)) in order to control the power switch state in the power transistor.

[0013] Optionally, the step of determining the PID parameter K... pv K iv and K dvThe feedback control quantity of the voltage control loop, including K, is generated by PID control using the voltage difference err, the integral of the most recent multiple voltage differences Σerr, and the change in voltage difference err Δerr. pv ×err、K iv ×Σerr and K dv ×Δerr, where K pv K iv and K dv These are the PID parameters for the feedback logic.

[0014] Optionally, the step of determining the PID parameter K... pi and K di The number of power switches on at current time t (Non(t)) and the change in the number of power switches are used by PID control to generate feedforward control quantities for the current control loop, including K. pi × Non(t) and K di ×(Non(t)-Non(t-1)), where K pi and K di These are the PID parameters of the feedforward logic, where Non(t-1) is the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) is the change in the number of power switches turned on at the current time t.

[0015] Optionally, the calculation function expression for the number of power switches Non(t+1) turned on at the next time t+1 is:

[0016] Non(t+1) = Non(t) + K pv ×err+K iv ×Σerr+K dv ×Δerr+K pi ×Non(t)+K di ×(Non(t)-Non(t-1)),

[0017] Among them, K pv K iv and K dv These are the PID tuning parameters for the voltage control loop, K pi and K di These are the proportional and differential parameters of the current control loop, respectively. Non(t-1) is the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) is the change in the number of power switches turned on at the current time t.

[0018] Optionally, optimizing the parameters of the feedback logic and feedforward logic using a genetic algorithm to obtain the optimal parameters includes: adjusting the PID parameter K of the feedback logic... pv K iv and Kdv And the PID parameter K of the feedforward logic pi and K di The five PID parameters are represented as binary integer powers forming a five-dimensional integer vector. This five-dimensional integer vector is used as the chromosome of the genetic algorithm. The genetic algorithm iterates the mutation of the chromosomes in the initial population and calculates the fitness of the chromosomes using a preset fitness function. At the end of the iteration, the chromosome with the best fitness is selected as the optimal PID tuning parameter obtained from the search. The fitness function is the reciprocal of the cumulative voltage error, where the cumulative voltage error is the cumulative value of the voltage difference err between the output voltage of the power transistor and the reference voltage within each time step.

[0019] Optionally, when using a genetic algorithm to iterate the mutation of chromosomes in the initial population, the method includes using tournament selection to select parents. In each round of iteration, k individuals are randomly selected from the population, and then the individual with the highest fitness is selected from these k individuals as the parent. The above parent selection operation is repeated until the required number of parents are selected.

[0020] Optionally, it also includes a PVT sensor for generating a reference voltage, wherein the PVT sensor is used to generate a reference voltage from the PVT environment data of the chip's actual operation and convert it into an encoded signal Vref of the reference voltage before outputting it to the voltage difference calculation logic.

[0021] Optionally, the voltage difference calculation logic is further connected to a time-domain to digital-domain converter for encoding the output voltage. The time-domain to digital-domain converter is used to delay and map the output voltage to the digital domain to obtain the encoded signal Vcode of the output voltage, and then output it to the voltage difference calculation logic.

[0022] Optionally, the feedback control quantity K pv ×err、K iv ×Σerr and K dv All multiplications of ×Δerr are implemented through shift operations.

[0023] Optionally, the feedforward control quantity K pi × Non(t) and K di The multiplication of ×(Non(t)-Non(t-1)) is all implemented through shift operations.

[0024] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: In order to solve the inherent delay problem in feedback-based voltage regulation, the fast-response digital low-dropout regulator of the present invention includes feedforward logic in a standard voltage controller. The feedforward path utilizes the actuator state of the power stage itself—that is, the number of power switches enabled (Non). Predictive feedforward logic based on power switch state is integrated into the traditional voltage PID feedback system of the voltage controller, so that the proposed control law combines the proportional-integral-derivative (PID) voltage controller with the term derived from the actuator state obtained by the feedforward path. This enables proactive compensation of load current fluctuations before a significant voltage drop occurs, achieving excellent voltage regulation performance, thereby meeting the requirements of optical I / O chips for circuit area and compatibility with advanced CMOS processes. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the circuit structure of a fast-response digital low-dropout regulator in an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the execution flow of the genetic algorithm in an embodiment of the present invention, where (a) is a random initial population, (b) is random selection of parent chromosomes, (c) selection of parent chromosomes, (d) crossover operation for offspring, (e) mutation of the crossover offspring, and (f) is the result obtained after repeating steps (b) to (e) 7 times.

[0027] Figure 3 This is a schematic diagram of the iterative process of the genetic algorithm in an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of the encoding circuit of the time-domain to digital-domain converter in an embodiment of the present invention.

[0029] Figure 5 The following are simulation results of the current step model in this embodiment of the invention within a 10-microsecond time window, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current; (c) is the number of active power switches (Non(t)).

[0030] Figure 6 The following are simulation results of the current step model in this embodiment of the invention within a 200 nanosecond time window, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current; (c) is the number of active power switches (Non(t)).

[0031] Figure 7The above are simulation results of the periodic model in the embodiments of the present invention, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current (I). load (c) represents the number of active power switches (Non(t)).

[0032] Figure 8 The simulation results of the hybrid model in this embodiment are for the invention, where (a) is the output voltage, and Vout is the output voltage, V ref为 (a) is the reference voltage; (b) is the load current (I) load (c) represents the number of active power switches (Non(t)).

[0033] Figure 9 This refers to the cumulative voltage error under the three load function modes in the embodiments of the present invention.

[0034] Figure 10 This is a curve showing the voltage encoding of the time-domain to digital-domain converter under typical process boundary conditions as a function of supply voltage and temperature in an embodiment of the present invention.

[0035] Figure 11 The curves showing the voltage encoding of the time-domain to digital-domain converter under three process boundary conditions (TT, FF, SS) at a fixed temperature, as a function of the supply voltage, are shown in the embodiments of the present invention.

[0036] Figure 12 This is the voltage regulation transient waveform under the first load change in the embodiment of the present invention.

[0037] Figure 13 This is the voltage regulation transient waveform under the second type of load change in this embodiment of the invention.

[0038] Legend: 1. Voltage difference calculation logic; 2. Parameter generation logic; 3. Feedback logic; 4. First adder; 5. Feedforward logic; 6. Second adder. Detailed Implementation

[0039] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings of the embodiments of the present invention. Figure 1 As shown, the fast-response digital low-dropout regulator (ASP-DLDO) for optical I / O chips in this embodiment includes:

[0040] Voltage difference calculation logic 1 is used to calculate the voltage difference err between the output voltage of the power transistor and the reference voltage;

[0041] Parameter generation logic 2 is used to optimize the parameters of the feedback logic and feedforward logic using a genetic algorithm to obtain the optimal parameters, including the PID parameter K of the feedback logic. pv K iv and K dv And the PID parameter K of the feedforward logic pi and K di ;

[0042] Feedback logic 3 is used to determine the PID parameter K. pv K iv and K dv The feedback control quantity of the voltage control loop is generated by PID control, which takes the voltage difference err, the integral of the most recent multiple (values ​​can be selected as needed, such as four) voltage differences Σerr, and the change of voltage difference err Δerr.

[0043] The first adder 4 is used to generate the total feedback control quantity of the voltage control loop from the feedback control quantity of the voltage difference err, the integral of the most recent multiple voltage differences and Σerr, and the change in voltage difference err Δerr.

[0044] Feedforward logic 5 is used to determine the PID parameter K based on the input parameters K. pi and K di The number of power switches turned on at the current time t, Non(t), and the change in the number of power switches are used to generate feedforward control quantities for the current control loop through PID control.

[0045] The second adder 6 is used to sum the number of power switches turned on at the current time t (Non(t), the total feedback control quantity of the voltage control loop, and the feedforward control quantity of each current control loop) to obtain the number of power switches turned on at the next time t+1 (Non(t+1)) in order to control the power switch state in the power transistor.

[0046] In this embodiment, feedback logic 3 is based on the PID parameter K. pv K iv and K dv The feedback control quantity of the voltage control loop, including K, is generated by PID control using the voltage difference err, the integral of the most recent multiple voltage differences Σerr, and the change in voltage difference err Δerr. pv ×err、K iv ×Σerr and K dv ×Δerr, where K pv K iv and K dv These are the PID parameters for the feedback logic (proportional gain, integral gain, and derivative gain, respectively). The PID controller in the voltage control loop is a stable and efficient feedback controller. The proportional term K... pv×err is used as the main loop gain to reduce system error; the integral term K iv ×Σerr eliminates steady-state error and stabilizes the output at the target value; differential term K dv ×Δerr detects changes in the slope of the error, enabling predictive control of trends.

[0047] Traditional LDO control methods transfer current to the load through a set of power switches. The output voltage fluctuates with changes in the current load. A voltage comparator compares the output voltage with a reference voltage and feeds the difference back to the controller to drive the power switches (typically PMOS transistors), thereby stabilizing the output voltage. However, in this system, the feedback controller only receives the output voltage deviation as input, completely ignoring the magnitude of the load current. Therefore, this embodiment introduces the load current magnitude as the input for system feedforward regulation. For analog LDOs, it is difficult to observe and quantify the conduction state of the power transistors. For DLDOs, however, the current flowing through the power transistors can be calculated from the input / output voltage and the parallel transistor resistors. In fact, previous studies have used this method to measure load current, although its purpose was for software-level power management and task scheduling. The current calculation formula is as follows:

[0048] I(t)=(Vin-Vout) / Req=(Vin-Vout)×Non(t) / R0;

[0049] Where I(t) is the current at time t, Vin and Vout are the input and output voltages of the digital low-dropout regulator (DLDO), Req is the resistance of the DLDO, Non(t) represents the number of power switches turned on at time t, and R0 is the on-resistance of a single power switch. For a regulated system with a stable output voltage, Vin, Vout, and R0 can be considered constant parameters. Therefore, I(t) and Non(t) are approximately linearly related.

[0050] I(t)=k×Non(t), k=(Vin-Vout) / R0;

[0051] Where k is the linear relationship coefficient.

[0052] This allows us to obtain an approximate current value without additional computational overhead. The next step is to integrate this parameter into the control system.

[0053] This embodiment incorporates a predictive feedforward controller based on power switch states into a traditional voltage PID feedback system. By setting the static operating point using a proportional term and predicting dynamic changes using a derivative term, the transient response performance of the system is significantly improved. Specifically, in this embodiment, feedforward logic 5 is based on the PID parameter K... pi and K diThe number of power switches on at current time t (Non(t)) and the change in the number of power switches are used by PID control to generate feedforward control quantities for the current control loop, including K. pi ×Non(t) and K di ×(Non(t)-Non(t-1)), where K pi and K di These are the PID parameters of the feedforward logic, representing the proportional and derivative parameters of the current control loop, respectively. Non(t-1) is the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) is the change in the number of power switches turned on at the current time t.

[0054] In this embodiment, the function expression for the second adder 6 to sum the number of power switches turned on at the current time t (Non(t), the total feedback control amount of the voltage control loop, and the feedforward control amount of each current control loop) is as follows:

[0055] Non(t+1) = Non(t) + K pv ×err+K iv ×Σerr+K dv ×Δerr+K pi ×Non(t)+K di ×(Non(t)-Non(t-1)),

[0056] Among them, K pv K iv and K dv These are the PID parameters for the feedback logic, K pi and K di These are the PID parameters for the feedforward logic, where Non(t-1) is the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) is the change in the number of power switches turned on at the current time t. Parameter K pv K iv and K dv These are the PID tuning parameters for the voltage control loop. Also, K pi and K di These are the proportional and derivative parameters of the current control loop. The proportional term senses the operating point of the load current, aiming to increase the regulation amplitude when the current is high and decrease it when the current is low, thereby minimizing output voltage oscillations. The derivative term predicts load trends; when the current continues to rise, this term adds a positive compensation value to the system for faster regulation. When the current stabilizes, this term approaches zero, minimizing its impact on the system. These two terms together achieve current-based feedforward regulation. Furthermore, this formula utilizes parameters directly available within the control system to regulate the voltage.

[0057] As an optional implementation, each parameter of the current control loop and voltage control loop can be optimized to maximize the effectiveness of the formula. For example, a genetic algorithm can be used to find the optimal solution for the above five parameters. Specifically, in this embodiment, parameter generation logic 2 optimizes the parameters of the feedback logic and feedforward logic according to the genetic algorithm to obtain the best parameters, including: optimizing the PID parameter K of the feedback logic. pv K iv and K dv And the PID parameter K of the feedforward logic pi and K di The five PID parameters are represented as binary integer powers forming a five-dimensional integer vector. This five-dimensional integer vector is used as the chromosome of the genetic algorithm. The genetic algorithm iterates the mutation of the chromosomes in the initial population and calculates the fitness of the chromosomes using a preset fitness function. At the end of the iteration, the chromosome with the best fitness is selected as the optimal PID tuning parameter obtained from the search. The fitness function is the reciprocal of the cumulative voltage error, where the cumulative voltage error is the cumulative value of the voltage difference err between the output voltage of the power transistor and the reference voltage within each time step.

[0058] In this embodiment, a black-box optimization method based on genetic algorithm (GA) is used to optimize the five parameters K in the fast-response digital low-dropout regulator (ASP-DLDO) for optical I / O chips. pv K iv and K dv K pi and K di Discrete search and optimization are performed. The genetic algorithm directly processes the parameters without relying on the derivative or continuity of the objective function, making it particularly suitable for nonlinear optimization problems in global search scenarios. Furthermore, this algorithm does not perform gradient-based backpropagation calculations, thus avoiding getting trapped in local optima. To maintain hardware compatibility, each parameter is represented as a binary integer power, i.e., the gain value is 2. e (Where e is an integer limited to the range [-10, 10]). Therefore, each chromosome is a five-dimensional integer vector, with each dimension representing the exponent e. The fitness function is calculated by constructing a corresponding controller for each candidate parameter set and running a full-cycle simulation on a given simulation model. During the simulation, the voltage error |Vref is calculated at each time step. The value of Vout(t) is accumulated over the entire running cycle, where Vout(t) is the output voltage and Vref is the reference voltage. The fitness function is the reciprocal of this accumulated error (the goal is to maximize this value). Population initialization uses partially heuristic seed generation, and parental selection (k=4) is used during evolution. Population size is determined by balancing diversity and computational complexity. The tournament selection algorithm selects individuals by comparing their fitness. When using a genetic algorithm to iterate the mutation of chromosomes in the initial population, it includes using tournament selection for parental selection. In each iteration, k individuals are randomly selected from the population (usually the tournament size k=4), and then the individual with the highest fitness is selected from these k individuals as the parent. This selection operation is repeated until the required number of parents are selected. Figure 2 This diagram illustrates the execution flow of the genetic algorithm in this embodiment, where (a) represents the initial random population, (b) represents the random selection of parent chromosomes, (c) represents the selection of parent chromosomes, (d) represents the crossover operation for offspring, and (e) represents the mutation of the crossover offspring. (f) shows the result obtained after repeating steps (b) to (e) seven times. In this embodiment, the crossover operation for offspring selection uses single-point crossover (crossover probability CROSSOVER_PROB = 0.9) to generate offspring, and applies a three-layer mutation strategy to maintain population diversity. This strategy includes regular step-size mutation (±1, probability MUTATION_PROB = 0.35), random large jump mutation (±2, probability BIG_MUTATION_PROB = 0.08), and extremely rare gene reset (RESET_MUTATION_PROB = 0.02). To prevent the loss of high-quality solutions, an elite retention strategy (elitism = 4) is finally adopted to directly copy a specified number of the best individuals from the current generation to the next generation. Each generation sequentially evaluates the entire new population (based on the cumulative absolute error obtained from simulation) and records the optimal solution for that generation. Iteration terminates after a preset number of generations. Figure 3 As shown, its vertical axis represents the integral of the most recent voltage differences and Σerr. Simulation observations show that in this embodiment, the genetic algorithm converges and finds the optimal solution in the 32nd generation.

[0059] like Figure 1 As shown, the fast-response digital low-dropout regulator in this embodiment also includes a PVT sensor for generating a reference voltage. The PVT sensor is used to generate a reference voltage from the PVT environment data of the chip's actual operation and convert it into a reference voltage encoded signal Vref[5:0] and output it to the voltage difference calculation logic.

[0060] like Figure 1As shown, the voltage difference calculation logic in this embodiment is also connected to a time-domain to digital-domain converter for encoding the output voltage. The time-domain to digital-domain converter is used to delay and map the output voltage to the digital domain to obtain the encoded signal Vcode[5:0] of the output voltage and then output it to the voltage difference calculation logic.

[0061] To mitigate the impact of PVT variations on the reference voltage, an on-chip PVT sensor is used to generate a compensation reference. For example... Figure 4As shown, the working principle of the time-domain to digital-domain converter and the encoding circuit of the PVT sensor in this embodiment is as follows: The input clock is input to the clock buffer unit after passing through a D flip-flop. The clock buffer unit includes 64 buffers, and the output of each buffer is connected to a D flip-flop, so that a vector with temperature code characteristics can be output every cycle under the drive of the clock. Then, it is determined whether to invert based on the highest bit, thereby obtaining a 64-bit 0000_0000_00FF_FFFF data C[63:0]. Finally, the output voltage encoding signal Vcode[5:0] is obtained through a 64-bit leading zero counter. The main purpose of the above encoding circuit design is to generate a digital encoding signal Vcode[5:0] related to the PVT (process, voltage, temperature) changes, which is used to compensate for the influence of these factors on the reference voltage. The following is a simplified explanation of its working principle: Input clock processing: The input clock passes through a D flip-flop and enters a link composed of 64 buffers. Generating Temperature Code: The output of each buffer is connected to a D flip-flop. All D flip-flops simultaneously sample the output state of their respective buffers under clock drive, forming a vector C[63:0] with temperature code characteristics. This temperature code reflects the number of buffers through which the signal can propagate within one clock cycle, and this number changes with the PVT condition. Inversion Operation: The highest bit is used to determine whether the temperature code needs to be inverted to ensure that the obtained data format is uniform, such as 0000_0000_00FF_FFFF. Leading Zero Count: Finally, a 64-bit leading zero counter is used to calculate the position of the first '1' in the temperature code, or the number of consecutive '0's, and convert it into the final 6-bit encoded signal Vcode[5:0]. This design utilizes the effect of PVT variation on buffer delay, indirectly obtains PVT information by measuring signal propagation time, and encodes this information into digital signals for subsequent compensation mechanisms. This method can effectively achieve adaptive compensation for PVT variation, improving the stability and reliability of the circuit. The PVT sensor is driven by a stable external reference voltage, and its digital output code Vref[5:0] represents the voltage encoding value under the current PVT condition. This encoding is directly used as a reference value for subsequent voltage regulation. In the adopted architecture, the analog reference voltage is not directly connected to the ASP-DLDO control loop, but only powers the PVT sensor. The sensor periodically samples the PVT state and provides the updated digital reference value to the system. This scheme effectively isolates the regulation system from the drift caused by PVT in the analog reference.

[0062] In the design of the control computation circuit, the genetic algorithm design phase limits the value range of each coefficient to powers of 2. This makes it possible to achieve efficient multiplication operations through bit shifting. The hardware design goal is to complete the voltage error calculation (obtained through TDC encoding and a single subtraction) and the defined operations (six-term addition) within a single clock cycle. Compared to the traditional PID implementation scheme, the overall computational overhead only increases by two adders. Taking a mixed load model simulation as an example, the optimal exponential solution obtained by the algorithm is {3, 2, 7, ...} 6, 3}. Therefore, the five parameters K pv K iv and K dv K pi and K di The coefficient multiplication operation is replaced by a left or right shift operation. The shift operation incurs only negligible power and latency overhead, and only requires bit width truncation before the final addition. After synthesis, placement, and routing, the system achieves a maximum operating frequency of 1.33 GHz, ensuring safe compliance with the design target frequency of 1 GHz. Specifically, in this embodiment, the feedback control quantity K... pv ×err、K iv ×Σerr and K dv The multiplication of ×Δerr is all implemented through shift operations. The feedforward control quantity K pi ×Non(t) and K di The multiplication of ×(Non(t)-Non(t-1)) is all implemented through shift operations.

[0063] To verify the effectiveness of the fast-response digital low-dropout regulator (ASP-DLDO) for optical I / O chips in this embodiment, the ASP-DLDO is constructed based on a linear PMOS transistor model. The capacitor value comprehensively considers the inherent capacitance of the transistors and interconnect structures within the chip, the additional capacitance from the deliberately designed decoupling units, and the design specifications in the EDA power integrity analysis manual. The voltage change dV per cycle is calculated as dV = (I... PMOS –I load ) / C out Calculate ×dt. Where I PMOS I represents the current flowing through the PMOS transistor. load For the load current, C out This is the output capacitor. This embodiment employs a power transistor with 1024 power switches to support a maximum load current of 1A. Furthermore, the voltage values ​​are digitally encoded based on the actual hardware circuit design.

[0064] To cover as many operating conditions as possible, three load function modes were implemented: current step model, periodic model, and hybrid model. Figures 5-9 This diagram illustrates the adjustment process of the ASP-DLDO in three load modes. In each figure, the three signal lines represent the output voltage, load current, and number of active power switches, respectively. Figure 5 The following are the simulation results of the current step model in this embodiment within a 10-microsecond time window, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current; (c) is the number of active power switches. Figure 6 The following are the simulation results of the current step model in this embodiment within a 200 nanosecond time window, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current; (c) is the number of active power switches. Note that in the load step response, the load current varies with signal noise between 0.1A and 0.9A, and the load switching time is 1ns. Under this load model, the time window setting of the genetic algorithm's fitness has a significant impact on parameter optimization. Figure 5 The 10-microsecond time window shown Figure 6 The two time windows, each 200 nanosecond, determine the focus of cumulative error optimization: the former emphasizes global optimization, achieving a stable output voltage but accompanied by a larger voltage drop and a longer settling time; the latter optimizes within a limited time window, achieving minimum voltage drop and fast settling time, but at the cost of increased ripple and a longer settling time. The former achieves a stable output voltage through balanced global optimization, but with a larger voltage drop and a longer settling time; the latter optimizes within a limited time window, achieving minimum voltage drop and fast settling time, but at the cost of increased ripple and steady-state voltage drop. See Table 1 for specific parameters.

[0065] Table 1. Comparison of simulation results under different fitness time windows

[0066]

[0067] Existing high-performance DLDO designs typically focus on scenarios involving rapid current transients. However, such extreme conditions are rare in real-world applications because CPU utilization usually changes at a moderate rate rather than exhibiting instantaneous, full-range jumps. Therefore, this embodiment prioritizes more stochastically fluctuating loads and extended timing windows. Figure 7 This is the simulation result of the periodic model in this embodiment, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current (I). load (c) represents the number of active power switches (Non). Figure 8The following is the simulation result of the hybrid model in this embodiment, where (a) is the output voltage, and V out V is the output voltage. ref (a) is the reference voltage; (b) is the load current (I). load (c) represents the number of active power switches (Non). Figure 7 The load current exhibits a periodic variation, linearly transitioning between 0 and 1 ampere with a 1-microsecond slope. The output voltage remains consistently near the reference voltage, with ripple typically below 10 millivolts. Significant fluctuations only occur at extremely low load currents. Figure 8 A hybrid load current model that more closely reflects real-world CPU usage scenarios is presented. This model exhibits three phases: an extreme fluctuation period, a steady-state period, and a gradual fluctuation period (accompanied by rapid load transients). The output voltage drops by approximately 90mV during the extreme fluctuation period and less than 50mV during the gradual fluctuation period. Inconsistent tracking of load current changes is observed in all scenarios. Furthermore, this embodiment optimizes and simulates the traditional voltage feedback PID algorithm under the same environment. The calculation formula for the PID-DLDO method used for comparison is as follows:

[0068] Non(t+1)=Non(t)+Kpv×err+Kiv×Σerr+Kdv×Δerr;

[0069] The parameters can also be optimized using a genetic algorithm. Figure 9 The cumulative voltage error during the simulation cycle of the ASP-DLDO in this embodiment is compared with that of the PID-DLDO under the three load function modes. The results show that the ASP-DLDO in this embodiment can reduce the cumulative error by 24% to 49%.

[0070] For voltage encoding, this embodiment evaluates and compares two implementation schemes: a time-domain to digital-domain converter (TDC) and a scheme based on a ring oscillator and counter circuit. The design requirement is to output voltage quantization codes per cycle at a frequency of 1 GHz, which means that high-precision, high-accuracy encoded values ​​must be obtained within 1 ns. Assuming the ring oscillator consists of five series inverters (each with a delay of 10 ps), it can only generate ten rising edges per clock cycle, which is insufficient for fine-grained voltage quantization. Therefore, a time-domain to digital-domain converter with a delay chain and an integrated clock buffer (CLKBUF) is used to achieve rising / falling edge balance. Figure 10 and Figure 11 The voltage encoding generated by the time-domain to digital-domain converter under different process, voltage, and temperature (PVT) boundary conditions is demonstrated. Figure 10 Curves showing the voltage encoding as a function of supply voltage and temperature under typical process boundary conditions were plotted. Figure 11The data presents the voltage encoding curves as a function of supply voltage for three process boundary conditions (typical TT, fast FF, and slow process angle SS) at a fixed temperature. The data shows that the voltage encoding is significantly dependent on the PVT variation. This dependence allows for a wider effective encoding range under different operating conditions, thus supporting higher achievable accuracy. For example, the encoding resolution reaches 9.5 mV / bit at the TT process angle. Furthermore, when the process and temperature are constant, the voltage encoding exhibits a highly linear relationship with the supply voltage. Figure 11 The piecewise linear fitting shown allows the maximum error of the encoded value to be controlled within 0.2 mV. This linearity verifies the accuracy of the time-to-digital converter (TDC) used in the software simulation framework.

[0071] This embodiment completes the corresponding hardware circuit mapping and performs simulation based on 28nm CMOS technology. For voltage encoding, this embodiment evaluates and compares two implementation schemes: a circuit based on a delay chain and a time-to-digital converter (TDC), and a scheme based on a ring oscillator and a counter circuit. The design requirement is to output voltage quantization codes per cycle at a frequency of 1GHz, which means that high-precision, high-accuracy encoded values ​​must be obtained within 1ns. Assuming the ring oscillator consists of five series inverters (each with a 10ps delay), it can only generate ten rising edges in a single clock cycle, which is insufficient for fine-grained voltage quantization. Therefore, a TDC circuit with a delay chain and an integrated clock buffer (CLKBUF) is used to achieve rising / falling edge balance.

[0072] The digital portion of the system was synthesized, placed, and routed based on the aforementioned algorithms and circuit design. The analog portion focused on designing the power switch, followed by layout generation and parasitic parameter extraction. The 10nF capacitor was placed off-chip, and the current was modeled using a virtual load. Synopsys' VCS-XA tool was used to perform mixed-signal simulations to evaluate the system's performance under step load and dynamically changing load scenarios. The input and reference voltages were set to 0.8V and 0.7V, respectively, and the circuit operating frequency was 1GHz. Simulation results are as follows: Figure 12 and Figure 13 As shown. Figure 12 The voltage regulation transient waveform under a first load change in this embodiment of the invention shows that when the load current jumps from 0.1A to 0.9A, the voltage drop is 86mV and the recovery time is 9ns. Under the same simulation conditions, the voltage drop of a traditional PID controller is 125mV and the recovery time is 14ns. Therefore, this solution reduces the voltage drop by 31% and shortens the recovery time by 36%. Furthermore, Figure 13 The voltage regulation transient waveform under the second type of load change in this embodiment of the invention is as follows: Figure 13A 1-microsecond random current waveform simulating CPU load changes was applied. The output voltage remained stable near the reference voltage with a ripple of less than 10mV. Although the voltage drop reached 30-40mV during drastic load fluctuations, it recovered quickly. Compared to traditional PID control, this system exhibits a faster voltage response, making it more suitable for managing the diverse and rapidly changing load currents in modern VLSI circuits. To minimize power consumption in the control circuit, the logic operations in this embodiment were performed using the reference voltage instead of the DLDO input voltage. A custom Wallace tree adder summed the six multiplication terms, resulting in a power consumption of 144μW and a quiescent current of 180μA. The performance parameters of the fast-response digital low-dropout regulator (ASP-DLDO) of this embodiment are shown in Table 2.

[0073] Table 2. Comparison of Technical Parameter Results

[0074]

[0075] The technologies / parameters in Table 2 are all well-known technologies or parameters. As can be seen from Table 2, the ASP-DLDO of this embodiment achieved excellent results in the overall FoM (Frame of Mean) index.

[0076] In summary, the fast-response digital low-dropout regulator (ASP-DLDO) of this embodiment effectively alleviates the inherent response delay problem of traditional voltage-mode DLDOs. By identifying the number of effective power switches (Non) as a real-time indicator of load changes, this embodiment uses Non and its derivative as feedforward signals, combined with a standard voltage error PID structure, to construct a lightweight and hardware-efficient predictive compensation mechanism. A genetic algorithm is used to globally optimize the control coefficients, ensuring robust performance over a wide operating range. Experimental results show that compared with traditional PID controllers, the fast-response digital low-dropout regulator (ASP-DLDO) of this embodiment achieves significant improvements in voltage sag and transient response. Under a load step condition of 0.1 to 0.9 A, this design reduces voltage sag by 31% and recovery time by 36%. Furthermore, this architecture fully retains the inherent advantages of a fully digital implementation.

[0077] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A fast-response digital low-dropout regulator for optical I / O chips, characterized in that, include: Voltage difference calculation logic, used to calculate the voltage difference err between the power transistor's output voltage and the reference voltage; The parameter generation logic optimizes the parameters of the feedback and feedforward logics using a genetic algorithm to obtain the optimal parameters, including the PID parameter K of the feedback logic. pv K iv and K dv And the PID parameter K of the feedforward logic pi and K di The optimization to obtain the best parameters includes: adjusting the PID parameter K of the feedback logic. pv K iv and K dv And the PID parameter K of the feedforward logic pi and K di The five PID parameters are represented as binary integer powers to form a five-dimensional integer vector. The five-dimensional integer vector is used as the chromosome of the genetic algorithm. The genetic algorithm is used to mutate and iterate the chromosomes in the initial population. The fitness of the chromosomes is calculated using a preset fitness function. At the end of the iteration, the chromosome with the best fitness is selected as the optimal PID tuning parameter obtained by the search. The fitness function is the reciprocal of the cumulative voltage error. The cumulative voltage error is the cumulative value of the voltage difference err between the output voltage of the power transistor and the reference voltage within each time step. Feedback logic is used to determine the PID parameter K. pv K iv and K dv The feedback control quantity of the voltage control loop is generated by PID control using the voltage difference err, the integral of the most recent multiple voltage differences and Σerr, and the change in voltage difference err Δerr. The first adder is used to generate the total feedback control quantity of the voltage control loop from the feedback control quantity of the voltage difference err, the integral of the most recent multiple voltage differences and Σerr, and the change in voltage difference err Δerr. Feedforward logic is used to determine the PID parameter K separately. pi and K di The number of power switches on at current time t (Non(t)) and the change in the number of power switches are used to generate a feedforward control quantity for the current control loop via PID control. The feedforward control quantity includes K. pi ×Non(t) and K di ×(Non(t)-Non(t-1)), where K pi and K di Here are the PID parameters for the feedforward logic: Non(t-1) represents the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) represents the change in the number of power switches turned on at the current time t. The function expression for calculating the number of power switches turned on at the next time t+1, Non(t+1), is as follows: Not(t+1) = Not(t) + K pv ×err+K iv ×Σerr+K dv ×Δerr+K pi ×Not(t)+K di ×(Not(t)-Not(t-1)), Among them, K pv K iv and K dv These are the PID parameters for the feedback logic, K pi and K di These are the PID parameters of the feedforward logic, where Non(t-1) is the number of power switches turned on at the previous time t-1, and Non(t)-Non(t-1) is the change in the number of power switches turned on at the current time t. The second adder is used to sum the number of power switches turned on at the current time t (Non(t)), the total feedback control quantity of the voltage control loop, and the feedforward control quantity of each current control loop to obtain the number of power switches turned on at the next time t+1 (Non(t+1)) in order to control the power switch state in the power transistor.

2. The fast-response digital low-dropout regulator for optical I / O chips according to claim 1, characterized in that, The PID parameter K pv K iv and K dv The feedback control quantity of the voltage control loop, including K, is generated by PID control using the voltage difference err, the integral of the most recent multiple voltage differences Σerr, and the change in voltage difference err Δerr. pv ×err、K iv ×Σerr and K dv ×Δerr, where K pv K iv and K dv These are the PID parameters for the feedback logic.

3. The fast-response digital low-dropout regulator for optical I / O chips according to claim 1, characterized in that, When using a genetic algorithm to iterate the mutation of chromosomes in the initial population, the method includes using tournament selection for parent selection. In each round of iteration, k individuals are randomly selected from the population, and then the individual with the highest fitness is selected from these k individuals as the parent. The above parent selection operation is repeated until the required number of parents are selected.

4. The fast-response digital low-dropout regulator for optical I / O chips according to claim 3, characterized in that, It also includes a PVT sensor for generating a reference voltage. The PVT sensor is used to generate a reference voltage from the PVT environment data of the chip's actual operation and convert it into an encoded signal Vref of the reference voltage before outputting it to the voltage difference calculation logic.

5. The fast-response digital low-dropout regulator for optical I / O chips according to claim 4, characterized in that, The voltage difference calculation logic is also connected to a time-domain to digital-domain converter for encoding the output voltage. The time-domain to digital-domain converter is used to delay and map the output voltage to the digital domain to obtain the encoded signal Vcode of the output voltage, and then output it to the voltage difference calculation logic.

6. The fast-response digital low-dropout regulator for optical I / O chips according to claim 5, characterized in that, Feedback control quantity K pv ×err、K iv ×Σerr and K dv All multiplications of ×Δerr are implemented through shift operations.

7. The fast-response digital low-dropout regulator for optical I / O chips according to claim 6, characterized in that, Feedforward control quantity K pi ×Non(t) and K di The multiplication of ×(Non(t)-Non(t-1)) is all implemented through shift operations.

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