Chip control method and device

Abstract

The invention provides a chip control method and device, and belongs to the technical field of chips. The method comprises the following steps: generating a target back pressure signal under the condition that the working state of the chip is abnormal, so as to control the request processing speed of the chip through the target back pressure signal. Therefore, the processing speed of the chip during task processing is directly controlled through the target back pressure signal, and the working state of the chip can be quickly adjusted when the working state of the chip is abnormal, so that the control efficiency of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip control method and apparatus. Background Technology

[0002] In chip technology, if a large number of parallel requests occur during chip operation, the chip current will increase. If the chip power consumption remains constant at this time, the chip voltage will drop, and the chip may even malfunction due to low voltage.

[0003] To address the aforementioned technical challenges, in certain scenarios, the chip's power supply voltage and clock frequency can be dynamically adjusted using Dynamic Voltage and Frequency Scaling (DVFS) technology based on the chip's load status, thereby reducing the chip's power consumption.

[0004] In the aforementioned method, DVFS needs to first obtain the chip's load state before each adjustment, and then adjust parameters such as the chip's power supply voltage and clock frequency by sending control commands to the chip. The generation, transmission, and parsing of these control commands all require processing time. Therefore, the DVFS adjustment process for the chip's operating state has a high adjustment delay and low control efficiency. Summary of the Invention

[0005] This application provides a chip control method and apparatus, which can realize rapid control of the chip's operating state to improve chip control efficiency. The technical solution is as follows:

[0006] In a first aspect, this application provides a chip control method, comprising: generating a target backpressure signal when the chip's operating parameters meet the first condition, the first condition indicating an abnormal operating state of the chip; and controlling the chip's request processing speed based on the target backpressure signal, the request processing speed indicating the chip's processing speed when processing tasks.

[0007] According to the method described in this application, when an abnormality occurs in the chip's operating state, a target reverse voltage signal is generated, thereby directly controlling the chip's request processing speed based on the target reverse voltage signal. Since the chip's power consumption, heat, operating voltage, and other state parameters change with the request processing speed, controlling the chip's request processing speed allows for rapid adjustment of the chip's operating state from the source, thereby improving the chip's control efficiency.

[0008] In one possible implementation, the chip includes a buffer for sending requests and a processing unit for processing requests. Based on a target backpressure signal, the chip's request processing speed is controlled by sending the target backpressure signal to the buffer so that the buffer stops sending requests to the processing unit.

[0009] In the above implementation, the target backpressure signal directly suppresses the chip's request-sending buffer, preventing the buffer from sending requests to the processing unit. By controlling the timing of request transmission to the processing unit, unnecessary request transmissions are reduced, lowering the system load and improving control efficiency, thereby further reducing control latency during chip control.

[0010] In one possible implementation, the operating parameters include the operating voltage, and the first condition includes that the chip's operating voltage is less than a low-voltage threshold.

[0011] In the above implementation, the chip's operating voltage directly determines whether the chip can correctly perform its intended functions. If the chip's operating voltage is too low, it may be unable to drive the internal circuitry, meaning the chip will not work. Therefore, whether the chip's operating voltage is below the low-voltage threshold is used as one of the conditions for judging whether the chip is abnormal, in order to ensure that the chip can work normally and improve the accuracy of chip control.

[0012] In one possible implementation, generating the target reverse voltage signal includes: setting random bits in an initial reverse voltage signal to a high level to obtain a reference reverse voltage signal, wherein the initial reverse voltage signal is a multi-bit low-level signal. The target reverse voltage signal is then generated based on the reference reverse voltage signal.

[0013] In the above implementation, when generating the target backpressure signal, a random reference backpressure signal is generated by randomly setting the bits of the initial backpressure signal to a high level. The target backpressure signal is then generated based on this randomly generated reference backpressure signal, thus improving the randomness of the target backpressure signal. This ensures a certain degree of randomness in the control chip's request processing speed, preventing synchronization effects caused by the chip receiving the same target backpressure signal and reacting identically within a fixed period, resulting in a smoother response from the chip system. Furthermore, the randomness of the target backpressure signal allows for some degree of incomplete synchronization or slight deviations during backpressure signal transmission, improving the robustness of the control process.

[0014] In one possible implementation, a reference reverse voltage signal is obtained by setting random bits in the initial reverse voltage signal to a high level. This includes: determining a target number based on operating parameters, where the target number indicates the number of bits in the initial reverse voltage signal that need to be set to a high level; and randomly setting the target number of bits in the initial reverse voltage signal to a high level to obtain the reference reverse voltage signal.

[0015] In the above implementation, by introducing the concept of target quantity, the degree of abnormality indicated by the chip's operating parameters is fully considered when generating the reference reverse voltage signal, so as to adjust the control strength of the request processing speed in combination with the actual state of the chip, thereby improving the flexibility of chip control.

[0016] In one possible implementation, the target back pressure signal is generated based on the reference back pressure signal, including: cyclically shifting the reference back pressure signal to the left and using the shifted-out reference back pressure signal as the target back pressure signal.

[0017] In the above implementation, the target back pressure signal is continuously generated by cyclically shifting left. There is no correlation between the previously output target back pressure signal and the current output target back pressure signal, thus improving the randomness of the control process. This avoids continuously suppressing the chip's request processing speed, which could severely degrade chip performance, thereby improving the chip's stability during control.

[0018] In one possible implementation, the chip further includes a counter whose count value is cyclically decremented. The initial value of the count value is a positive integer. The counter cyclically shifts a reference reverse voltage signal to the left, using the shifted-out reference reverse voltage signal as the target reverse voltage signal. The process includes: obtaining the current count value of the counter; if the current count value is not equal to 0, shifting the reference reverse voltage signal to the left by one bit, using the shifted-out bit value as the target reverse voltage signal, and inserting the shifted-out bit value into the last bit of the reference reverse voltage signal; returning to the step of obtaining the current count value of the counter, until the chip's operating parameters meet a second condition, which indicates that the chip is operating normally; if the current count value is equal to 0, scrambling the reference reverse voltage signal, shifting the scrambled reference reverse voltage signal to the left by one bit, using the shifted-out bit value as the target reverse voltage signal, and inserting the shifted-out bit value into the last bit of the reference reverse voltage signal, and returning to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition.

[0019] In the above implementation, by setting a cyclically decrementing counter and scrambling the reference backvoltage signal when the count value reaches 0, the reference backvoltage signal can be periodically scrambled. This further improves the randomness of the target backvoltage signal, avoids the lock-in phenomenon caused by the target backvoltage signal synchronizing with the request sending cycle, which wastes a lot of resources, and improves the system performance of the chip in the chip control process.

[0020] In one possible implementation, the count value is initialized to a prime number.

[0021] In the above implementation, the initial value of the counter is set to a prime number. Since a prime number can only be divided by 1 and itself, this ensures that the least common multiple of the output period of the target backpressure signal and the request transmission period is relatively large, making it less likely for the output period of the target backpressure signal and the request transmission period to coincide. This improves the randomness of the target backpressure signal, further reducing the probability of livelock, thus avoiding the waste of a large amount of computing resources due to livelock, and improving the chip's resource utilization and stability.

[0022] Secondly, a chip control device is provided, comprising a signal generation circuit and a processing circuit. The signal generation circuit generates a target reverse voltage signal when the chip's operating parameters meet a first condition, the first condition indicating an abnormal operating state of the chip. The processing circuit controls the chip's request processing speed based on the target reverse voltage signal, the request processing speed indicating the chip's processing speed when handling tasks.

[0023] In one possible implementation, the processing circuitry includes a buffer for sending requests and a processing unit for processing requests. Specifically, the processing circuitry sends a target backpressure signal to the buffer, causing the buffer to stop sending requests to the processing unit.

[0024] In one possible implementation, the operating parameters include the operating voltage, and the first condition includes that the chip's operating voltage is less than a low-voltage threshold.

[0025] In one possible implementation, the signal generation circuit includes a first signal generation circuit and a second signal generation circuit. The first signal generation circuit sets random bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal, where the initial reverse voltage signal is a multi-bit low-level signal. The second signal generation circuit generates a target reverse voltage signal based on the reference reverse voltage signal.

[0026] In one possible implementation, the first signal generation circuit is specifically used to: determine the target quantity based on the operating parameters, the target quantity being used to indicate the number of bits in the initial reverse voltage signal that need to be set to a high level; and randomly set the target quantity of bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal.

[0027] In one possible implementation, the second signal generation circuit is specifically used to: cyclically shift the reference back pressure signal to the left, and use the shifted-out reference back pressure signal as the target back pressure signal.

[0028] In one possible implementation, the chip also includes a counter whose count value is cyclically decremented, with an initial value of a positive integer. The second signal generation circuit is specifically used to: obtain the current count value of the counter; if the current count value is not equal to 0, then the reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal, returning to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition, which indicates that the chip is operating normally; if the current count value is equal to 0, then the reference reverse voltage signal is scrambled, the scrambled reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal, returning to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition.

[0029] In one possible implementation, the count value is initialized to a prime number.

[0030] Thirdly, a chip is provided, which includes a chip control device as described in the second aspect or any implementation thereof.

[0031] The technical effects produced by any of the above-mentioned second to third aspects and any of the above-mentioned implementation methods can be referred to the above-mentioned first aspect and the corresponding implementation methods in the first aspect. The repeated parts will not be repeated here. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a chip control scenario provided in an embodiment of this application;

[0033] Figure 2 A schematic diagram of an implementation environment provided for an embodiment of this application;

[0034] Figure 3 A schematic flowchart illustrating a chip control method provided in an embodiment of this application;

[0035] Figure 4 A flowchart illustrating another chip control method provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the architecture of a chip control device provided in an embodiment of this application. Detailed Implementation

[0037] To enable those skilled in the art to better understand the solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0038] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Here, A and B can be single or multiple. "At least one of the following" or similar expressions are used to represent any combination of the listed items. For example, at least one of A, B, and / or C can represent: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, B and C existing simultaneously, A and C existing simultaneously, and A, B, and C existing simultaneously. Here, A, B, and C can be single or multiple.

[0039] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0040] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0041] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0042] In some scenarios, if a chip receives a large number of parallel requests simultaneously, these requests increase the activity of the chip's internal circuitry, causing a sharp rise in the chip's current. Based on electrical principles, if the chip's power consumption remains constant under these conditions, the sudden increase in current will cause a sharp drop in the chip's internal voltage, resulting in voltage collapse. If the chip's voltage becomes too low, it may even malfunction.

[0043] To address the aforementioned and similar issues, DVFS can be introduced in some scenarios to dynamically adjust the chip's power consumption. For example... Figure 1 As shown, the DVFS module can collect the chip's load status and then dynamically adjust the chip's power supply voltage and clock frequency based on the chip's load status, thereby achieving power consumption control of the chip.

[0044] For example, if the DVFS module determines that the chip's operating frequency needs to be reduced based on the chip's load state, it will generate a frequency adjustment control command and send it to the chip's power management module so that the power management module can adjust the chip's operating frequency based on the control command.

[0045] However, when adjusting chip power consumption based on DVFS, DVFS needs to first obtain the chip's load state to determine how to adjust the chip's operating state, thereby generating corresponding control commands and sending them to the chip's power management module. Upon receiving the control command, the power management module parses and executes it to adjust the chip's operating state. This entire adjustment process involves load state detection, control signal generation, transmission, parsing, and execution, which takes a considerable amount of time.

[0046] In emergency situations, such as when a chip's operating state malfunctions, the inability to quickly adjust its operating state can lead to a continuous deterioration of the chip's performance or even complete malfunction. For example, if the chip's current voltage is too low, failure to promptly reduce power consumption could cause the chip to malfunction due to the low voltage. Therefore, current chip control efficiency is poor, hindering the ability to quickly control the chip's operating state.

[0047] Based on this, this application proposes a chip control method that can generate a target reverse voltage signal when the chip's operating parameters meet a first condition, and directly control the chip's request processing speed based on the target reverse voltage signal, thereby enabling rapid control of the chip's operating state and rapid adjustment of the chip's power consumption to improve the chip's control efficiency.

[0048] To facilitate understanding of the technical solutions provided in the embodiments of this application, the implementation environment of the embodiments of this application will be described with examples below:

[0049] The implementation environment of this application embodiment relates to a chip. Figure 2 A schematic diagram of one chip architecture is shown. For example... Figure 2 As shown, chip 20 includes a detection module 21 and a chip control device 22.

[0050] The detection module 21 is connected to the control module 22 and is used to detect the operating parameters of the chip 20. Based on the operating parameters of the chip 20, it generates and sends corresponding signals to the chip control device 22 to indicate the current operating status of the chip 20.

[0051] For example, the detection module 21 can detect the operating parameters of the chip 20. If the operating parameters of the chip 20 meet a first condition, a first signal is sent to the chip control device 22, enabling the chip control device 22 to determine that the current operating parameters of the chip 20 meet the first condition based on the first signal. If the operating parameters of the chip 20 meet a second condition, a second signal is sent to the chip control device 22, enabling the chip control device 22 to determine that the current operating parameters of the chip 20 meet the second condition based on the second signal.

[0052] Optionally, the signal sent by the detection module 21 can be a pulse signal, such as the first signal being a high-level signal and the second signal being a low-level signal.

[0053] Optionally, the type of detection module 21 can be flexibly selected based on actual usage requirements, such as chip type and application scenario. For example, detection module 21 can be a Critical Path Monitor (CPM) module.

[0054] The chip control module 22 is used to control the chip's request processing speed.

[0055] Optional, such as Figure 2 As shown, chip 20 may include processor 23, which is used to send requests to chip control device 22. Chip control device 22 is used to stop processing the requests sent by processor 23 when the operating state of chip 20 meets a first condition, thereby controlling the chip processing speed.

[0056] Optionally, the processor 23 can be flexibly selected based on actual usage requirements, such as chip type and application scenario. For example, the processor 23 can be a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0057] Optional, such as Figure 2 As shown, the chip control device may include a control module 221, a buffer 222, and a processing unit 223.

[0058] The control module 221 is connected to the detection module 21 and the buffer 222 respectively. It receives the first signal sent by the detection module 21, generates a reverse pressure signal based on the first signal, and sends the reverse pressure signal to the buffer 222. The reverse pressure signal suppresses the buffer 222 from sending processing requests, thereby reducing the request processing speed of the chip 20.

[0059] Buffer 222 is connected to processor 23 and processing unit 223 respectively. It is used to receive and store requests sent by processor 23 and send the requests to processing unit 223 to alleviate the problem of inconsistent request generation rate and request processing rate during chip operation. Buffer 222 is also used to control the request sending speed based on the target back pressure signal sent by control module 221 to control the request processing speed of chip 20.

[0060] For example, buffer 222 can receive a target reverse pressure signal. When the received target reverse pressure signal is high, it stops sending requests to the chip; when the received target reverse pressure signal is low, it continues to send requests to the chip, thereby controlling the chip's request processing speed.

[0061] Processor 23 is connected to buffer 222 and is used to send requests to buffer 222. Buffer 222 stores the request upon receiving it from processor 223 and sends it to processing unit 223 when processing is required. Processing unit 223 processes the request upon receipt.

[0062] Optionally, the conditions for sending requests by buffer 222 can be flexibly determined based on actual usage requirements. For example, buffer 222 can send a request to processing unit 223 upon receiving a request acquisition instruction from processing unit 223. As another example, buffer 222 can automatically send the request to processing unit 223 if the amount of data it stores exceeds a data threshold.

[0063] In some embodiments, in order to improve chip performance and request processing efficiency, buffer 222 may include multiple depths, i.e., have multiple storage locations or storage levels, to flexibly store requests sent by processor 23.

[0064] The processing unit 223 is used to receive and process the request sent by the buffer 222.

[0065] Optionally, the chip control device 22 can serve as a specific functional module within the chip 20 to implement a specific function, such as power management, data storage, or data processing. In some scenarios, the chip 20 can include multiple functional modules, each implementing a different function. In this case, target reverse voltage signals can be generated through the control modules within different functional modules to achieve precise control over the request processing speed of different functional modules within the chip.

[0066] The above is an introduction to the implementation environment of the embodiments of this application. The method embodiments of this application are described below.

[0067] Please refer to Figure 3 , Figure 3 This is a schematic flowchart of a chip control method provided in an embodiment of this application. The method can be executed entirely or partially by a chip control device. This embodiment illustrates the method by example, where the chip control device is executed entirely by the chip control device. This chip control device can be chip control device 22 in the aforementioned implementation environment. Other executing entities can refer to the operation of the chip control device for execution. The method includes steps S301 to S302.

[0068] S301: When the chip's operating parameters meet the first condition, a target reverse voltage signal is generated. The first condition is used to indicate that the chip's operating state is abnormal.

[0069] Optionally, the specific types of operating parameters of the chip and the first condition can be determined based on actual control requirements.

[0070] In some embodiments, considering that a low operating voltage may prevent the chip from accurately performing its functions, the chip's operating state can be considered abnormal if its operating voltage is below a low-voltage threshold. In this scenario, the chip's operating parameters may include its operating voltage, with the first condition being that the chip's operating voltage is less than the low-voltage threshold.

[0071] In other embodiments, considering that high chip temperatures may damage the chip hardware, the chip's operating state can be considered abnormal if its operating temperature exceeds a temperature threshold. In this scenario, the chip's operating parameters may include its operating temperature, with the first condition being that the chip's operating temperature is greater than the temperature threshold.

[0072] In some embodiments, considering that a large chip current may lead to a high current load on the chip, making it prone to voltage collapse, the chip's operating state can be considered abnormal if its operating current exceeds a current threshold. In this scenario, the chip's operating parameters may include the operating current, with the first condition being that the chip's operating current is greater than the current threshold.

[0073] In some embodiments, the chip's operating parameters and the first condition can include various types, which can be flexibly selected to interpret actual usage requirements. For example, the chip's operating parameters can simultaneously include the operating voltage and operating temperature mentioned above, and the first condition refers to the chip's operating voltage being less than a low-voltage threshold, and / or the chip's operating temperature being greater than a temperature threshold.

[0074] In some embodiments, the chip control device can acquire the chip's operating parameters to determine whether the chip's operating parameters meet a first condition, and execute steps S301 to S302 if the chip's operating parameters meet the first condition.

[0075] In other embodiments, to reduce the functional complexity of the chip control device, and considering the aforementioned implementation environment, a detection module can be incorporated within the chip. This detection module can send a first signal to the chip control device when the chip's operating parameters meet the first condition. In this way, the chip control device does not need to acquire the chip's operating parameters and compare them with the first condition; it only needs to determine whether it has received the first signal. That is, in this scenario, upon receiving the first signal, the chip control device can assume that the chip's operating parameters meet the first condition and execute steps S301 to S302.

[0076] In some embodiments, the target back pressure signal can be generated based on (1)-(2) below.

[0077] (1) Set the random bits in the initial reverse voltage signal to high level to obtain the reference reverse voltage signal. The initial reverse voltage signal is a low-level signal with multiple bits.

[0078] Optionally, the number of bits in the initial reverse voltage signal can be determined based on actual usage requirements.

[0079] For example, the initial reverse voltage signal can be a 10-bit low-level signal, i.e., 0000000000. Then, random bits of the initial reverse voltage signal are set to high level to obtain a reference reverse voltage signal. For example, setting some bits to 1 can result in a reference reverse voltage signal of 1001110110.

[0080] In some embodiments, a target number can be determined based on operating parameters. The target number indicates the number of bits in the initial reverse voltage signal that need to be set to a high level. The target number of bits in the initial reverse voltage signal are randomly set to a high level to obtain a reference reverse voltage signal.

[0081] Based on the above description, when the chip's operating parameters meet the first condition, it indicates that the chip's current operating state is abnormal. At this point, a target reverse pressure signal can be generated to adjust the chip's request processing speed, thereby restoring the chip's operating state to normal. Considering that the magnitude of the chip's operating parameters typically reflects the degree of abnormality in its operating state, in some embodiments, the degree of abnormality in the chip's operating state can be determined based on the chip's operating parameters. This allows for flexible adjustment of the reverse pressure strength of the target reverse pressure signal, thereby achieving flexible control over the chip's operating state.

[0082] Taking the chip's operating voltage as an example, when the operating voltage is below the low-voltage threshold, it indicates an abnormal operating state. In this case, the lower the operating voltage, the higher the degree of abnormality in the chip's operating state, and the stronger the required target reverse voltage signal is needed for rapid control of the chip's operating state. This means a larger number of high-level reference reverse voltage bits are needed to generate the target reverse voltage signal. Conversely, the higher the operating voltage, the lower the degree of abnormality in the chip's operating state, and the weaker the required target reverse voltage signal. This means a smaller number of high-level reference reverse voltage bits are needed to generate the target reverse voltage signal, thus adjusting the chip's operating state and preventing drastic fluctuations in chip performance caused by a high-strength target reverse voltage signal.

[0083] In some embodiments, a correspondence between the chip's operating parameters and a target quantity can be determined, and the target quantity corresponding to the chip's current operating parameters can be determined based on this correspondence. For example, the optimal back pressure intensity required for chip control under different operating parameter conditions can be determined based on experimental simulation data, thereby obtaining the correspondence between the operating parameters and the target quantity of back pressure intensity.

[0084] Optionally, the correspondence can be in various forms such as a mapping function or a mapping table, and this application embodiment does not limit this.

[0085] For example, this correspondence is a mapping function, which allows the determination of the required target quantity based on the current operating parameters and the mapping function. For instance, taking the chip's operating parameters, including the operating voltage, as an example, if the first condition is that the chip's operating voltage is below 1V and the initial reverse voltage signal has 13 bits, then with the chip's operating voltage at 0.8V, the target quantity determined based on this correspondence can be 3. That is, three bits of the initial reverse voltage signal are randomly set to high level to obtain the reference reverse voltage signal. With the chip's current operating voltage at 0.3V, the target quantity determined based on this correspondence is 9. That is, nine bits of the initial reverse voltage signal are randomly set to high level to obtain the reference reverse voltage signal.

[0086] In some embodiments, after the reference reverse voltage signal is determined, the target quantity can be flexibly adjusted based on changes in the chip's operating parameters. The reference reverse voltage signal is then regenerated based on the adjusted target quantity to improve its flexibility.

[0087] For example, continuing with the above example of operating voltage, when the chip operating voltage is 0.8V, the target quantity is determined to be 3. Three bits of the initial reverse voltage signal are randomly set to high level to obtain a reference reverse voltage signal. This reference reverse voltage signal is then used to generate a target reverse voltage signal to control the chip's request processing speed. However, if during the control process, the chip's operating voltage gradually increases to 0.9V, and if the target quantity corresponding to 0.9V is 2, then two bits of the initial reverse voltage signal can be randomly set to high level to obtain a new reference reverse voltage signal. This new reference reverse voltage signal is used to generate a target reverse voltage signal to control the chip's request processing speed, thereby achieving flexible control of the chip's request processing speed and ensuring chip processing performance during the control process.

[0088] (2) Generate the target back pressure signal based on the reference back pressure signal.

[0089] In some embodiments, the reference back pressure signal can be cyclically shifted to the left, and the shifted-out reference back pressure signal can be used as the target back pressure signal.

[0090] In this embodiment, cyclic left shift means shifting all bits of the reference reverse voltage signal to the left and then wrapping the shifted-out bits back to the right side of the reference reverse voltage signal. That is, during the cyclic left shift, all bits of the reference reverse voltage signal are retained, only the positions of the information in the reference reverse voltage signal change.

[0091] For example, if the reference back pressure signal is 10110010, after performing a cyclic left shift operation, the reference back pressure signal becomes 01100101. The "1" in the highest bit is shifted out and returned to the lowest bit. The "1" shifted out in this cyclic left shift is the target back pressure signal.

[0092] Furthermore, considering that the target reverse pressure signal controls the chip's request processing speed under the condition that the chip's operating parameters meet the first condition, in some embodiments, if the chip's operating parameters no longer meet the first condition during the generation of the target reverse pressure signal, i.e., the chip's current operating state returns to normal, then the target reverse pressure signal can be discontinued.

[0093] S302: Based on the target reverse pressure signal, control the chip's request processing speed. The request processing speed is used to indicate the chip's processing speed when processing tasks.

[0094] The processing speed of a chip when processing tasks can be understood as the number of operations a chip can complete per unit of time. In some embodiments, controlling the chip's request processing speed based on the target backpressure signal can be understood as controlling the timing of the chip's processing requests by sending the target backpressure signal. The specific implementation method can be flexibly selected based on actual usage requirements, such as specific application scenarios and the actual chip architecture.

[0095] For example, in some scenarios, combined with Figure 2 The chip control device includes a control module, a buffer, and a processing unit. The buffer stores requests to be processed; these requests are sent directly from the buffer to the processing unit. In this scenario, the control module can send a target backpressure signal to the buffer to control when the buffer starts sending requests to the chip's processing unit and when it stops. This allows control over the number of requests sent by the buffer to the processing unit per unit time, thereby controlling the number of requests received by the processing unit per unit time and ultimately controlling the request processing speed of the chip.

[0096] For example, the target reverse pressure signal includes both high-level and low-level signals. When the target reverse pressure signal sent to the buffer by the control module is high, the buffer will stop sending requests to the chip. When the target reverse pressure signal sent to the buffer by the control module is low, the buffer will continue sending requests to the chip, thereby controlling the chip's request processing speed based on the target reverse pressure signal.

[0097] In some embodiments, the chip includes a buffer for sending requests and a processing unit for processing requests, and a target backpressure signal can be sent to the buffer to cause the buffer to stop sending requests to the processing unit.

[0098] Optional, combined Figure 2 The buffer mentioned above used for sending requests can be Figure 2 The buffer 222 in the middle, used to process requests, can be a processing unit. Figure 2 The processing unit 223 in the middle.

[0099] Optionally, the buffer may include multiple depths. If the target backpressure signal is generated based on the reference backpressure signal, i.e., the target backpressure signal output by cyclic left shift, the target backpressure signal is cyclically sent to each depth of the buffer in turn to control the request sending at each depth in turn.

[0100] For example, the target backpressure signal can be a cyclically output "110", with each output being 1 bit and the buffer being a 5-depth buffer. In this case, the target backpressure signal can be sent sequentially to the corresponding depth of the buffer with a cycle of "110". For instance, the first output target backpressure signal is the highest bit of the reference backpressure signal (110), i.e., "1". The target backpressure signal is sent to the first depth of the buffer, and the reference backpressure signal is shifted left, becoming "101". The second output target backpressure signal is the highest bit of the reference backpressure signal (101), i.e., "1". The target backpressure signal is sent to the second depth of the buffer, and the reference backpressure signal is shifted left, becoming "011". The third output target backpressure signal is the highest bit of the reference backpressure signal (011), i.e., "0". The target backpressure signal is sent to the third depth of the buffer, and the reference backpressure signal is shifted left, becoming "110". The fourth output target backpressure signal is the highest bit of "110", i.e., "1". The target backpressure signal is sent to the fourth depth of the buffer, and the reference backpressure signal is shifted to the left, changing the reference backpressure signal to "101", and so on.

[0101] In conjunction with the above description, in some embodiments, if the target backpressure signal is a signal that controls a buffer at multiple depths, then the target backpressure signal needs to be sent cyclically to each depth of the buffer. For example, still taking the aforementioned five-depth buffer as an example, if the fifth output target backpressure signal is sent to the fifth depth of the buffer, then the sixth output target backpressure signal will be resent to the first depth of the buffer, and so on, until the chip's operating parameters no longer meet the first condition.

[0102] Considering that the target backpressure signal is usually suppressed by directly suppressing the buffer, if the target backpressure signal is continuously generated and output by simply shifting left in a loop, the sending period of the target backpressure signal may coincide with the request sending period of the buffer, resulting in a lockout phenomenon.

[0103] Livelock occurs when the transmission period of the backpressure signal coincides with the request transmission period of the buffer (or a certain depth within the buffer). If the transmission period of the target backpressure signal and the request transmission period of the buffer are both common multiples, the buffer needs to send a request at the beginning of each cycle, but this request is suppressed by the target backpressure signal, preventing the buffer (or a certain depth within the buffer) from sending a request to the processing unit. Since the buffer typically does not check in real-time whether it can send a request again, it can only send requests to the processing unit based on control signals (such as timed transmissions or request retrieval instructions sent by the processing unit). This results in the buffer being unable to send a request to the processing unit each time it receives a control signal to send a request, due to the suppression by the target backpressure signal, severely impacting the chip's processing performance.

[0104] Therefore, in some embodiments, when the target backpressure signal is output cyclically based on the reference backpressure signal, the reference backpressure signal can be randomly shuffled. Then, the target backpressure signal is output cyclically based on the shuffled reference backpressure signal to increase the randomness of the output target backpressure signal. This reduces the probability of the backpressure cycle of the target backpressure signal coinciding with the request sending cycle at a certain depth of the buffer, thus avoiding a livelock phenomenon.

[0105] For example, the chip also includes a counter. The counter's count value is decremented cyclically, with an initial value of a positive integer, allowing the current count value to be obtained. If the current count value is not equal to 0, the reference reverse voltage signal is shifted left by one bit, the shifted-out bit value is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter, until the chip's operating parameters meet a second condition, which indicates that the chip is operating normally. If the current count value is equal to 0, the reference reverse voltage signal is scrambled, the scrambled reference reverse voltage signal is shifted left by one bit, the shifted-out bit value is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition.

[0106] The cyclic decrementing of the counter's count value means that the counter's count value is decremented by one with each operation. When the count value is reduced to a certain value (such as 0), the count value will return to a specific value (such as the maximum value or the defined initial value).

[0107] Furthermore, scrambling the reference reverse voltage signal means randomly swapping the positions of each bit in the reference reverse voltage signal to obtain the scrambled reference reverse voltage signal. That is, compared to the original reference reverse voltage signal, the number of high-level bits in the scrambled reference reverse voltage signal remains unchanged. For example, if the reference reverse voltage signal is 10011, with three bits being high, then the scrambled reference reverse voltage signal must still maintain three high-level bits. For instance, the scrambled reference reverse voltage signal could be 10101, 00111, etc.

[0108] In some embodiments, during the cyclic decrementing of the counter value, if the counter value reaches 0, when returning the counter value to a specific value, this specific value can be a fixed value or a random value from the data set. Taking a random value from the data set as an example, a specific value set can be provided. When the counter value reaches 0, a specific value is randomly selected from this specific value set as the initial value of the counter, in order to avoid repeatedly disrupting the reference back-voltage signal based on a fixed period, further increasing the randomness of the target back-voltage signal generation.

[0109] In some embodiments, the counter can decrement upon receiving a clock signal. The clock frequency of this clock signal can be the same as or different from the output frequency of the target reverse voltage signal, depending on the specific application requirements.

[0110] For example, the decrement frequency of the counter and the output frequency of the target reverse voltage signal can be the same, such as the clock signal of the counter and the clock signal for left shift of the reference reverse voltage signal using the same clock signal. In this case, the counter count value decrements once for every 1 bit left shift of the reference reverse voltage signal, thereby reducing the complexity of the chip structure and improving control efficiency.

[0111] For example, the decrement period of the counter and the output period of the target reverse voltage signal can be different periods. For instance, the clock signal driving the counter to decrement and the clock signal driving the reference reverse voltage signal to shift left can be clock signals of different frequencies. This further improves the randomness of the reference reverse voltage signal scrambling and reduces the probability of livelock.

[0112] In some embodiments, combined with Figure 2 and Figure 4 The generation of the target reverse voltage signal can be controlled by the chip control device as a whole or in part (e.g., by...). Figure 2 The control module 221 is implemented through the following steps S41-S45. Here, we will illustrate the process using the overall chip control device generating the target reverse voltage signal as an example.

[0113] S41: Under the condition that the chip's operating parameters meet the first condition, randomly set some bits of the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal, and generate a target reverse voltage signal based on the reference reverse voltage signal.

[0114] S42: Get the current count value of the counter.

[0115] S43: Determine if the current count value is equal to 0.

[0116] If the current count value is 0, then execute S441: Shuffle the reference reverse voltage signal and S442: Shift the reference reverse voltage signal to the left.

[0117] If the current count value is not equal to 0, then execute S442 directly: left shift the reference reverse voltage signal.

[0118] S45: Use the left-shifted bits as the target reverse voltage signal.

[0119] Optional, such as Figure 4 As shown, each time the target reverse voltage signal is generated, the chip control device obtains the current count value of the counter and determines whether the current count value is equal to 0. If the current count value is not zero, S442 and S45 are executed directly to generate the target reverse voltage signal. If the current count value is equal to zero, S441 is executed first, and after scrambling the reference reverse voltage signal, S442 and S45 are executed to generate the target reverse voltage signal.

[0120] In addition, such as Figure 4 As shown, the chip control device continuously determines whether the chip's operating parameters meet the second condition, i.e. Figure 4 In step S46, if the second condition is met, the process ends and the target back pressure signal is no longer generated. If the second condition is not met, the process returns to step S42 to select a different method to generate the target back pressure signal based on whether the current count value is equal to 0.

[0121] During the generation of the target reverse voltage signal, the counter continuously decrements. It decrements once each time a first clock signal is received, until it reaches zero, at which point it returns to its initial value and begins the decrementing cycle again. Furthermore, the target reverse voltage signal is also generated based on a clock signal. That is, the chip control device generates a target reverse voltage signal each time it receives a clock signal. This clock signal can be the same as the signal driving the counter's decrement (i.e., both are the first clock signal); or it can be a different clock signal, such as a second clock signal. The relationship between the clock frequency of the second clock signal and the clock frequency of the first clock signal can be flexibly selected based on actual usage requirements, such as the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal.

[0122] In some embodiments, in order to simplify the internal circuit structure of the chip and improve signal transmission efficiency, the counter can also be integrated into the chip control device.

[0123] Furthermore, to further enhance the flexibility of chip control, some embodiments may include a configuration switch signal. When the configuration switch signal is on, such as when it is configured to a high level, the counter will decrement based on the clock signal. When the configuration switch signal is off, such as when it is configured to a low level, the counter will not decrement. This allows for flexible control over whether the reference reverse voltage signal needs to be disrupted. For example, the configuration switch signal can be turned on in response to a first operator command and off in response to a second operator command, thereby enabling flexible adjustment of the target reverse voltage signal generation strategy.

[0124] Furthermore, the execution start condition for generating the target reverse voltage signal is that the operating parameters meet a first condition, while the execution end condition is that the operating parameters meet a second condition. In some embodiments, to avoid conflicts between the execution of the first and second conditions, the operating parameters used in the first and second conditions are typically the same. For example, if the operating parameter used in the first condition is the operating voltage, the operating parameter used in the second condition should also be the operating voltage, and there should be no overlap between the first and second conditions. For instance, if the first condition is that the chip's operating voltage is less than a low-voltage threshold, the second condition can be that the chip's operating voltage is greater than or equal to the low-voltage threshold.

[0125] Furthermore, in some embodiments, to avoid ping-pong issues in controlling the chip request processing speed, the threshold values ​​for the operating parameters used in the first and second conditions can be different. Taking the first condition being that the chip's operating voltage is less than a low-voltage threshold as an example, the second condition could be that the chip's operating voltage is greater than a high-voltage threshold, which is greater than the low-voltage threshold.

[0126] For example, the first operating condition is an operating voltage of less than 1V, and the second operating condition can be an operating voltage of greater than 1.3V. This is to avoid repeatedly starting or stopping the generation of the target reverse voltage signal when the chip's operating voltage fluctuates around 1V.

[0127] In some embodiments, the initial value of the count is a prime number.

[0128] Since prime numbers are only divisible by 1 and themselves, when the scrambling period of the reference backpressure signal is a prime number, it ensures that the least common multiple of the output period of the target backpressure signal and the requested transmission period is large. This makes it less likely for the output period of the target backpressure signal and the requested transmission period to coincide. This increases the randomness of the target backpressure signal, further reducing the probability of livelock, thus avoiding the waste of significant computational resources caused by livelock and improving the chip's resource utilization and stability.

[0129] In some embodiments, to further reduce the probability of the output period of the target backpressure signal and the request transmission period of the buffer coinciding, the initial value of the count can be a large prime number, such as a prime number greater than the target value. This target value can be determined based on actual usage requirements. For example, the target value can be 150, meaning the initial value of the count is a prime number greater than 150, such as 151, 157, 163, etc., to ensure that the common multiple period between the output period of the target backpressure signal and the request transmission period of the buffer is sufficiently large, further reducing the probability of livelock.

[0130] This application provides a chip control method that, in the event of an abnormal chip operating state, generates a target reverse pressure signal and sends it to a buffer used for sending requests, causing the buffer to stop sending requests to the processing unit. By directly suppressing request transmission in the buffer, rapid control of the chip's request processing speed can be achieved. This adjustment of the chip's operating state can be realized without the intervention of the chip power management module, thereby reducing chip latency and improving control efficiency.

[0131] Furthermore, to avoid the target backpressure signal's request suppression period coinciding with the buffer's request transmission period, which could prevent the buffer from continuously sending requests to the chip's processing unit, a reference backpressure signal is obtained by setting random bits in the initial backpressure signal to high levels when generating the target backpressure signal. The target backpressure signal is then output by cyclically shifting the reference backpressure signal left. In this way, since the high-level positions in the reference backpressure signal are randomly determined, a random backpressure effect can be achieved when applying backpressure to the buffer, reducing the probability of period overlap and preventing lockout.

[0132] Furthermore, considering that even if the target reverse voltage signal is generated by randomly setting bits to high level, the reference reverse voltage signal still has a limited number of bits, and periodic overlap may still occur during the cyclic left shift. Therefore, a counter can be used to periodically shuffle the reference reverse voltage signal to further improve the randomness of the target reverse voltage signal, reduce the probability of periodic overlap, and avoid lockout.

[0133] The above text combines Figure 3 and Figure 4The chip control method provided in this embodiment has been described in detail. The various devices corresponding to the chip control method provided in this embodiment will be described below.

[0134] This application provides a chip control device, which can be the chip control device 22 described above. The chip control device includes a control circuit, which is used to implement all or part of the steps of the method provided in the above method embodiments.

[0135] Figure 5 A schematic architecture diagram of a chip control device 50 is shown, such as... Figure 5 As shown, the chip control device 50 includes a signal generation circuit 51 and a processing circuit 52.

[0136] The signal generation circuit 51 is used to generate a target reverse voltage signal when the chip's operating parameters meet a first condition. The first condition is used to indicate that the chip's operating state is abnormal.

[0137] The processing circuit 52 is used to control the chip's request processing speed based on the target reverse pressure signal. The request processing speed is used to indicate the processing speed of the chip when processing tasks.

[0138] Optional, combined Figure 2 , Figure 5 The signal generation circuit 51 shown can be Figure 2 The control module 221 in the middle.

[0139] Optional, such as Figure 5 As shown, the processing circuit 52 includes a buffer 521 for sending requests and a processing unit 522 for processing requests. Specifically, the processing circuit 52 is used to send a target backpressure signal to the buffer 521, so that the buffer 521 stops sending requests to the processing unit 522.

[0140] Optional, combined Figure 2 , Figure 5 The buffer 521 shown can be Figure 2 The buffer 222 and the processing unit 522 can be Figure 2 Processing unit 223.

[0141] Optionally, the operating parameters include the operating voltage, and the first condition includes that the chip's operating voltage is less than a low voltage threshold.

[0142] Optional, such as Figure 5As shown, the signal generation circuit 51 includes a first signal generation circuit 511 and a second signal generation circuit 522. The first signal generation circuit 511 is used to set random bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal, wherein the initial reverse voltage signal is a multi-bit low-level signal. The second signal generation circuit 512 is used to generate a target reverse voltage signal based on the reference reverse voltage signal.

[0143] Optionally, the first signal generation circuit 511 is specifically used to: determine the target quantity based on the operating parameters, the target quantity being used to indicate the number of bits in the initial reverse voltage signal that need to be set to a high level; and randomly set the target quantity of bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal.

[0144] Optionally, the second signal generation circuit 512 is specifically used to: cyclically shift the reference reverse pressure signal to the left, and use the shifted-out reference reverse pressure signal as the target reverse pressure signal.

[0145] Optionally, the chip also includes a counter whose count value is cyclically decremented, with an initial value of a positive integer. The second signal generation circuit 512 is specifically used to: obtain the current count value of the counter. If the current count value is not equal to 0, the reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition. The second condition is used to indicate that the chip's operating state is normal. If the current count value is equal to 0, the reference reverse voltage signal is scrambled, the scrambled reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the shifted-out bit value is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter, until the chip's operating parameters meet the second condition.

[0146] Optionally, in conjunction with the relevant description of the above method embodiments, the counter can also be integrated into the signal generation circuit 51, such as into the second signal generation circuit 512 included in the signal generation circuit 51.

[0147] Optionally, the count value can be initialized as a prime number.

[0148] Optionally, the signal generation circuit and processing circuit in the chip control device provided in this application embodiment can be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0149] This application provides a chip control device that, in the event of an abnormal chip operating state, generates a target reverse pressure signal and sends it to a buffer used for sending requests, causing the buffer to stop sending requests to the processing unit. By directly suppressing request transmission in the buffer, rapid control of the chip's request processing speed can be achieved. This adjustment of the chip's operating state can be realized without the intervention of the chip power management module, thereby reducing chip latency and improving control efficiency.

[0150] Furthermore, to avoid the target backpressure signal's request suppression period coinciding with the buffer's request transmission period, which could prevent the buffer from continuously sending requests to the chip's processing unit, a reference backpressure signal is obtained by setting random bits in the initial backpressure signal to high levels when generating the target backpressure signal. The target backpressure signal is then output by cyclically shifting the reference backpressure signal left. In this way, since the high-level positions in the reference backpressure signal are randomly determined, a random backpressure effect can be achieved when applying backpressure to the buffer, reducing the probability of period overlap and preventing lockout.

[0151] Furthermore, considering that even if the target reverse voltage signal is generated by randomly setting bits to high level, the reference reverse voltage signal still has a limited number of bits, and periodic overlap may still occur during the cyclic left shift. Therefore, a counter can be used to periodically shuffle the reference reverse voltage signal to further improve the randomness of the target reverse voltage signal, reduce the probability of periodic overlap, and avoid lockout.

[0152] Based on the same inventive concept, this application also provides a chip, which includes the chip control device 50 described above.

[0153] It should be noted that the chips can include various possible chips such as ASIC chips, FPGA chips, NP chips, GAL chips, encryption chips, and decryption chips.

Claims

1. A chip control method, characterized in that, include: When the chip's operating parameters meet the first condition, a target reverse voltage signal is generated, where the first condition is used to indicate that the chip's operating state is abnormal. Based on the target back pressure signal, the request processing speed of the chip is controlled, and the request processing speed is used to indicate the processing speed of the chip when processing tasks.

2. The method according to claim 1, characterized in that, The chip includes a buffer for sending requests and a processing unit for processing requests. Controlling the request processing speed of the chip based on the target backpressure signal includes: The target backpressure signal is sent to the buffer so that the buffer stops sending requests to the processing unit.

3. The method according to claim 1, characterized in that, The operating parameters include the operating voltage, and the first condition includes the chip's operating voltage being less than a low-voltage threshold.

4. The method according to any one of claims 1 to 3, characterized in that, The generation of the target back pressure signal includes: The reference reverse voltage signal is obtained by setting random bits in the initial reverse voltage signal to high level, wherein the initial reverse voltage signal is a multi-bit low-level signal; The target back pressure signal is generated based on the reference back pressure signal.

5. The method according to claim 4, characterized in that, The step of setting random bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal includes: Based on the operating parameters, a target quantity is determined, which indicates the number of bits in the initial reverse voltage signal that need to be set to a high level. The target number of bits in the initial reverse voltage signal are randomly set to high level to obtain the reference reverse voltage signal.

6. The method according to claim 4, characterized in that, The step of generating the target back pressure signal based on the reference back pressure signal includes: The reference back pressure signal is cyclically shifted to the left, and the shifted-out reference back pressure signal is used as the target back pressure signal.

7. The method according to claim 4, characterized in that, The chip also includes a counter, the counter's count value of which is cyclically decremented, the initial value of which is a positive integer, and the cyclic left shift of the reference reverse voltage signal, using the shifted-out reference reverse voltage signal as the target reverse voltage signal, including: Obtain the current count value of the counter; If the current count value is not equal to 0, the reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the value of the shifted-out bit is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter until the chip's operating parameters meet the second condition, which is used to indicate that the chip's operating state is normal. If the current count value is equal to 0, the reference reverse voltage signal is scrambled, the scrambled reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the value of the shifted-out bit is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter until the operating parameters of the chip meet the second condition.

8. The method according to claim 7, characterized in that, The initial value of the count is a prime number.

9. A chip control device, characterized in that, The chip control device includes a signal generation circuit and a processing circuit; The signal generation circuit is used to generate a target reverse voltage signal when the chip's operating parameters meet a first condition, wherein the first condition is used to indicate that the chip's operating state is abnormal. The processing circuit is used to control the request processing speed of the chip based on the target reverse pressure signal, wherein the request processing speed is used to indicate the processing speed of the chip when processing tasks.

10. The apparatus according to claim 9, characterized in that, The processing circuit includes a buffer for sending requests and a processing unit for processing requests. Specifically, the processing circuit is used to send the target backpressure signal to the buffer so that the buffer stops sending requests to the processing unit.

11. The apparatus according to claim 9 or 10, characterized in that, The signal generation circuit includes a first signal generation circuit and a second signal generation circuit: The first signal generation circuit is used to set random bits in the initial reverse voltage signal to a high level to obtain a reference reverse voltage signal, wherein the initial reverse voltage signal is a multi-bit low-level signal; The second signal generation circuit is used to generate the target reverse pressure signal based on the reference reverse pressure signal.

12. The apparatus according to claim 11, characterized in that, The first signal generation circuit is specifically used for: Based on the operating parameters, a target quantity is determined, which indicates the number of bits in the initial reverse voltage signal that need to be set to a high level. The target number of bits in the initial reverse voltage signal are randomly set to high level to obtain the reference reverse voltage signal.

13. The apparatus according to claim 11, characterized in that, The second signal generation circuit is specifically used to: cyclically shift the reference back pressure signal to the left, and use the shifted-out reference back pressure signal as the target back pressure signal.

14. The apparatus according to claim 11, characterized in that, The chip also includes a counter, the counter's count value being cyclically decremented, the initial value of the count value being a positive integer; the second signal generation circuit is specifically used for: Obtain the current count value of the counter; If the current count value is not equal to 0, the reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the value of the shifted-out bit is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter until the chip's operating parameters meet the second condition, which is used to indicate that the chip's operating state is normal. If the current count value is equal to 0, the reference reverse voltage signal is scrambled, the scrambled reference reverse voltage signal is shifted left by one bit, the value of the shifted-out bit is used as the target reverse voltage signal, and the value of the shifted-out bit is inserted into the last bit of the reference reverse voltage signal. The process returns to the step of obtaining the current count value of the counter until the operating parameters of the chip meet the second condition.

15. A chip, characterized in that, The chip includes a chip control device as described in any one of claims 9-14.

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