Compiling method, compiling device, readable medium, electronic equipment and program product

Abstract

The invention relates to the technical field of computers, and discloses a compiling method, a compiling device, a readable medium, electronic equipment and a program product. According to the compiling method provided by the embodiment of the invention, the first instruction meeting the first processing condition can be determined through the defined access identifier and / or the defined access identifier, and the first instruction is merged and / or deleted. According to the compiling method, the number of memory access instructions is reduced, meanwhile, the risk of wrong combination and / or wrong deletion of the instructions is reduced, and then the risk of program running errors is reduced.

Description

[0001] This application claims priority to Chinese Patent Application No. 202411345298.X, filed on September 24, 2024, entitled “Compilation Method, Compilation Apparatus, Readable Medium, Electronic Device and Program Product”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a compilation method, compilation apparatus, readable medium, electronic device, and program product. Background Technology

[0003] Electronic devices, such as computer processors, typically need to read data from memory and / or write data to memory while running applications (APPs).

[0004] However, since the processor processes data much faster than the memory can read and write data, the processor needs to spend a lot of time waiting for the required data to be read from memory and / or written to memory while running applications, which affects the processor's efficiency in running applications. Summary of the Invention

[0005] The purpose of this application is to provide a compilation method, a compilation apparatus, a readable medium, an electronic device, and a program product.

[0006] The first aspect of this application provides a compilation method, comprising: obtaining a first source program, wherein the first source program includes variable dependency information and a first access identifier, the dependency information including at least one parameter, the at least one parameter being used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially, and the storage space corresponding to a target variable modified by the first access identifier does not overlap with the storage spaces corresponding to variables other than the target variable; determining a first target code file based on the first source program, and the dependency information and / or the first access identifier in the first source program, wherein the number of memory access instructions in the first target code file is less than the number of memory access instructions in a second target code file, and the second target code file is a target code file not determined based on the dependency information and / or the first access identifier in the first source program.

[0007] It is understandable that if the same type of memory access instructions are processed directly to obtain the target code file without considering whether there is overlap in the memory space between the memory access instructions, although the number of memory access instructions in the target code file can be reduced, it may lead to problems of incorrect merging and / or incorrect deletion, thereby affecting the operation of the application.

[0008] In this embodiment, before the source program is compiled, the developer can further perform correlation information identification and access identification on the member data of variables of various composite data types (e.g., structure variables) in the source program. The correlation information includes at least one parameter indicating whether the memory spaces corresponding to at least two variables do not overlap at least partially. The memory space corresponding to the target variable modified by the first access identifier does not overlap with the memory spaces corresponding to variables other than the target variable.

[0009] Therefore, during the compilation phase, based on dependency information and / or the first access identifier, a first object code file with a reduced number of memory access instructions is determined, thereby improving the execution efficiency of the first source program. Furthermore, it can reduce the probability of erroneous merging and / or incorrect deletion, thus lowering the risk of program runtime errors.

[0010] In one possible implementation of the first aspect above, at least one parameter includes a first parameter and a second parameter, wherein the first parameter is used to indicate whether there are at least two variables whose storage spaces do not overlap, and the second parameter is used to indicate whether the storage spaces corresponding to at least two overlapping variables are partially non-overlapping.

[0011] In one possible implementation of the first aspect described above, the storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and the same second parameter partially do not overlap; or, the storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters and the same second parameter partially do not overlap; or, the storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and different second parameters partially do not overlap; or, the storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters and different second parameters partially do not overlap.

[0012] In one possible implementation of the first aspect above, at least one parameter includes a third parameter, wherein the third parameter is used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially.

[0013] In one possible implementation of the first aspect above, the storage spaces corresponding to variables with different third parameters do not overlap at least partially; or, the storage spaces corresponding to variables with the same third parameter do not overlap at least partially.

[0014] In one possible implementation of the first aspect above, the first access identifier is used to indicate that the storage space corresponding to the target variable is accessed only through the target variable.

[0015] In one possible implementation of the first aspect above, determining the first target code file based on the first source program, and the related information and / or the first access identifier in the first source program, includes: determining at least two first instructions that satisfy the first processing condition from a plurality of memory access instructions corresponding to the first source program based on the related information and the first access identifier in the first source program; performing first processing on the at least two first instructions to obtain the first target code file; wherein the first processing condition includes: at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially, the first variable is modified by the first access identifier, and the at least two first instructions are of the same type.

[0016] In this embodiment of the application, during the compilation stage, the correlation information and access identifier can be combined to determine whether the memory access instructions corresponding to variables whose memory spaces do not overlap at least partially can be merged, so as to reduce the number of memory access instructions.

[0017] Furthermore, the memory space corresponding to the memory access instruction that undergoes the first processing does not overlap with the memory space corresponding to the memory access instruction that does not undergo the first processing. This compilation method reduces the number of memory access instructions while reducing the risk of instruction merging errors and / or deletion errors, thereby reducing the risk of program runtime errors.

[0018] In one possible implementation of the first aspect above, determining the first target code file based on the first source program, and the related information and / or the first access identifier in the first source program, further includes: determining at least two third instructions that satisfy the second processing condition from a plurality of memory access instructions corresponding to the first source program based on the first access identifier in the first source program; performing first processing on the at least two third instructions to obtain the first target code file; wherein the second processing condition includes: at least two third instructions correspond to third variables, the third variables are modified by the first access identifier, and at least two third instructions are of the same type.

[0019] In this embodiment, during the compilation stage, memory access instructions that meet the conditions can be processed based on a first access identifier to reduce the number of memory access instructions. Furthermore, the memory space corresponding to the memory access instructions that undergo the first processing does not overlap with the memory space corresponding to the memory access instructions that do not undergo the first processing. This compilation method reduces the number of memory access instructions while also reducing the risk of instruction merging errors and / or incorrect deletion, thereby reducing the risk of program runtime errors.

[0020] In one possible implementation of the first aspect above, determining the first target code file based on the first source program, and the related information and / or the first access identifier in the first source program, further includes: determining at least two fifth instructions that satisfy the third processing condition from a plurality of memory access instructions corresponding to the first source program based on the related information in the first source program; performing first processing on the at least two fifth instructions to obtain the first target code file; wherein the third processing condition includes: at least two fifth instructions correspond to fifth variables, there is at least one sixth instruction corresponding to a sixth variable among the at least two fifth instructions, the storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable, and the at least two fifth instructions are of the same type.

[0021] In this embodiment, during the compilation stage, memory access instructions that meet the conditions can undergo first processing based on relevance information to reduce the number of memory access instructions. Furthermore, the memory space corresponding to the memory access instructions that undergo first processing does not overlap with the memory space corresponding to the memory access instructions that do not undergo first processing. This compilation method reduces the number of memory access instructions while also mitigating the risk of instruction merging errors and / or incorrect deletion, thereby reducing the risk of program runtime errors.

[0022] In one possible implementation of the first aspect above, corresponding to the type of the first instruction being a read operation instruction, the first processing condition further includes at least one of the following: the first instruction is a read operation instruction and the second instruction is a write operation instruction; the first instruction is a write operation instruction and the second instruction is a read operation instruction.

[0023] In one possible implementation of the first aspect above, the first process includes at least one of the following: merging process, deletion process.

[0024] In one possible implementation of the first aspect above, the first processing includes merging processing, and the first processing condition further includes: the storage space accessed by each first instruction is a contiguous storage space, or the data stored in the storage space accessed by each first instruction corresponds to the same variable.

[0025] In one possible implementation of the first aspect above, multiple memory access instructions corresponding to the first source program are determined by the following method: generating a first intermediate representation based on the first source program, wherein the first intermediate representation includes multiple instructions; and determining multiple memory access instructions from the multiple instructions in the first intermediate representation.

[0026] In one possible implementation of the first aspect above, obtaining the first target code file includes: performing a first processing on at least two first instructions to obtain a second intermediate representation, wherein the number of first instructions in the second intermediate representation is less than the number of first instructions in the first intermediate representation; and generating the first target code file based on the second intermediate representation.

[0027] A second aspect of this application provides a compilation method, comprising: obtaining a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, the first access identifier being used to indicate that the first member data is accessed only through a first access mode; determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes: the first instructions are instructions that access the first member data through the first access mode, and the at least two first instructions are of the same type; performing a first processing on the at least two first instructions, and obtaining a first object code file.

[0028] It is understandable that directly merging and / or deleting memory access instructions of the same type without considering whether there is any overlap in the memory spaces between the memory access instructions can reduce the number of memory access instructions, but it may lead to erroneous merging or deletion, thereby affecting the operation of the application.

[0029] In this embodiment, before the source program is compiled, for example during the program design phase (or coding phase), the program developer configures access identifiers for the member data of each composite type data in the source program. These access identifiers indicate the access method for the member data. For example, the composite type data includes first member data, which includes a first access modifier (e.g., _unique_). The first access modifier indicates that the first member data is accessed only through a first access method. During the compilation phase, at least two memory access instructions of the first type (first instructions) that satisfy the first processing condition among multiple memory access instructions corresponding to the first source program are determined. Then, the multiple first instructions undergo first processing, resulting in an executable file (first object code file).

[0030] It is understood that the compilation method provided in this application can determine the first instruction that meets the first processing condition through the defined access identifier, and merge and / or delete the first instruction. This compilation method reduces the number of memory access instructions while lowering the risk of incorrect instruction merging and / or incorrect deletion, thereby reducing the risk of program runtime errors.

[0031] In one possible implementation of the second aspect above, the multiple memory access instructions corresponding to the first source program are determined by the following method: generating a first intermediate representation based on the first source program, wherein the first intermediate representation includes multiple instructions; and determining multiple memory access instructions from the multiple instructions in the first intermediate representation.

[0032] In one possible implementation of the second aspect above, accessing the first member data through a first access method includes: accessing the first member data through a first variable, or accessing the first member data through a variable of a first type.

[0033] In one possible implementation of the second aspect above, the first processing condition further includes: at least two first instructions are consecutive memory access instructions.

[0034] In one possible implementation of the second aspect above, the composite type data further includes second member data, and the second member data does not include the first access identifier. There is at least one second instruction between at least two first instructions, and the first processing condition further includes: the second instruction is a memory access instruction that does not access the second member data through the first access method.

[0035] In one possible implementation of the second aspect above, the composite type data further includes second member data, and the second member data includes a second access identifier. At least one second instruction exists between at least two first instructions, wherein the second access identifier is used to indicate that the second member data is accessed through an access method other than the first access method. Furthermore, the first processing condition further includes: the second instruction is a memory access instruction for accessing the second member data through a second access method, wherein the second access method is an access method other than the first access method.

[0036] In one possible implementation of the second aspect above, corresponding to the type of the first instruction being a read operation instruction, the first processing condition further includes at least one of the following: the first instruction is a read operation instruction and the second instruction is a write operation instruction; the first instruction is a write operation instruction and the second instruction is a read operation instruction.

[0037] In the embodiments of this application, the first instruction and the second instruction are memory access instructions of different types.

[0038] In one possible implementation of the second aspect described above, the first source program further includes a correlation identifier for the variable, which indicates whether there is another variable whose storage space intersects with that of the variable; and the method further includes: based on the correlation identifier in the first source program, determining at least two third instructions among a plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition but satisfy the second processing condition, wherein the second processing condition includes: at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable among the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable; performing first processing on the plurality of third instructions to obtain a first object code file.

[0039] In this embodiment of the application, before the source program is compiled, the program developer can also configure a correlation identifier for each variable in the source program. The correlation identifier is used to indicate whether the memory space (storage space) corresponding to the variable overlaps, so that the compilation device can further determine whether the memory access instruction meets the second processing condition based on the correlation identifier during the compilation stage, so as to further reduce the number of memory access instructions.

[0040] It is understood that the compilation method provided in this application can configure the correlation identifiers for each variable in the source program through defined correlation identifiers. The correlation identifiers are used to indicate whether the memory spaces (storage spaces) corresponding to the variables overlap. During the compilation stage, based on the correlation identifiers of each variable in the source program, at least two third instructions that satisfy the second processing condition are determined among the multiple memory access instructions corresponding to the first source program. Then, the at least two third instructions undergo first processing, and an executable file (first object code file) is obtained. In this way, the number of memory access instructions can be further reduced, thereby improving the running efficiency of the application program corresponding to the source program.

[0041] In one possible implementation of the second aspect above, the correlation identifier is used to indicate whether there is another variable whose storage space intersects with that of the variable, including: the storage spaces corresponding to variables with the same correlation identifier do not intersect.

[0042] In one possible implementation of the second aspect above, the storage space corresponding to the fourth variable does not overlap with the storage space corresponding to the third variable, including: the correlation identifier of the fourth variable corresponding to the fourth instruction is the same as the correlation identifier of the third variable corresponding to the third instruction.

[0043] In one possible implementation of the second aspect above, the number of memory access instructions in the first object code file is less than the number of memory access instructions in the second object code file, and the second object code file is an object code file obtained without performing the first processing on the memory access instructions.

[0044] In one possible implementation of the second aspect above, the first process includes at least one of the following: merging process, deletion process.

[0045] In one possible implementation of the second aspect above, the first processing includes merging processing, and the first processing condition further includes: the storage space accessed by each first instruction is a contiguous storage space, or the data stored in the storage space accessed by each first instruction corresponds to the same variable.

[0046] In one possible implementation of the second aspect above, the merging process includes: merging multiple first instructions that satisfy the first processing condition into a single fifth instruction, wherein the storage space accessed by the fifth instruction includes the storage space accessed by the multiple first instructions.

[0047] In one possible implementation of the second aspect above, the merging process further includes: merging multiple first instructions that meet the processing conditions into multiple sixth instructions, wherein the storage space accessed by the sixth instructions includes the storage space accessed by the multiple first instructions, and the number of sixth instructions is less than the number of first instructions.

[0048] In one possible implementation of the second aspect above, the deletion process includes: if there are M seventh instructions of the same type that access the first storage space in the first intermediate representation, and the storage space accessed by other instructions among the M seventh instructions does not intersect with the storage space accessed by the seventh instructions, then delete N seventh instructions, where M is an integer greater than 1 and N is a positive integer less than M.

[0049] In one possible implementation of the second aspect above, the seventh instruction is a read operation instruction. Among the N seventh instructions, there is an eighth instruction that reads data from the first storage space into the second storage space. The second storage space is different from the storage space read by the MN seventh instructions (excluding the N seventh instructions) from the first storage space. The address information of the second storage space in the ninth instruction that reads data from the second storage space is replaced with the address information of the storage space read by any one of the MN seventh instructions from the first storage space. The ninth instruction is the instruction in the first intermediate representation that is after the eighth instruction and before the next instruction that writes data to the second storage space. The address information of the storage space includes the register name.

[0050] In this embodiment, instruction m is a read operation instruction that reads data from storage space P (first storage space) into register R0, and instruction n is a read operation instruction that reads data from storage space P into register R1 (second storage space). If instruction n is deleted, then in the first intermediate representation, register R1 in each instruction after instruction n and before the next instruction that writes data to register R1 needs to be replaced with register R0 so that the semantics in the first intermediate representation are correct.

[0051] In one possible implementation of the second aspect above, if the first instruction is a write operation instruction, the deletion process includes: deleting N seventh instructions from the first M-1 seventh instructions out of M seventh instructions.

[0052] In this embodiment of the application, the deletion process includes: retaining the last executed seventh instruction among a plurality of seventh instructions, and deleting at least one seventh instruction other than the last executed seventh instruction among a plurality of seventh instructions.

[0053] In one possible implementation of the second aspect above, obtaining the first target code file includes: performing a first processing on at least two first instructions to obtain a second intermediate representation, wherein the number of first instructions in the second intermediate representation is less than the number of first instructions in the first intermediate representation; and generating the first target code file based on the second intermediate representation.

[0054] It is understood that the compilation method provided in the first aspect of this application can determine the memory access instructions that meet the first and second processing conditions through the defined access identifier and related identifier, and perform merging and / or deletion processing on the memory access instructions that meet the conditions, which can reduce the number of memory access instructions, thereby improving the running efficiency of the application program corresponding to the source program, and reducing the risk of incorrect merging and / or incorrect deletion, thereby reducing the risk of program running errors.

[0055] A third aspect of this application provides a compilation method, comprising: obtaining a first source program, wherein the first source program includes variable correlation identifiers, and the storage spaces corresponding to variables with the same correlation identifier do not overlap; based on the correlation identifiers in the first source program, determining at least two first instructions from a plurality of memory access instructions corresponding to the first source program that satisfy a first processing condition, wherein the first processing condition includes: at least two first instructions correspond to first variables, there is at least one second instruction corresponding to a second variable among the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; performing a first processing on the at least two first instructions, and obtaining a first object code file.

[0056] It is understandable that directly merging memory access instructions of the same type that access contiguous memory addresses, without considering whether the memory space accessed by other types of memory access instructions overlaps with the memory space accessed by the merged memory access instructions, may reduce the number of memory access instructions, but may lead to erroneous merging problems, thereby affecting the operation of the application.

[0057] In this embodiment, before the source program is compiled, for example during the program design phase (or coding phase), the program developers configure correlation identifiers for each variable in the source program. These correlation identifiers indicate whether the memory spaces (storage spaces) corresponding to the variables overlap. During the compilation phase, the instructions in the source program are converted into an intermediate representation. Based on the correlation identifiers of each variable in the source program, multiple memory access instructions (first instructions) of the first type that satisfy processing conditions (e.g., merging conditions) are determined in the intermediate representation. Then, the multiple first instructions are merged, and based on the merged intermediate representation, an executable file (first object code file) is obtained.

[0058] It is understood that the compilation method provided in this application can determine the overlapping relationship of memory spaces corresponding to variables through defined dependency identifiers, thereby identifying the first instruction that meets the merging conditions and merging the first instruction, reducing the risk of erroneous merging and thus reducing the risk of program execution errors. Furthermore, even when the dependency identifier of a variable does not indicate that the memory spaces corresponding to the variable definitely do not overlap, the first instruction that meets the merging conditions can be further identified based on the access identifiers of member data in variables of various composite data types in the source program, and the first instruction can be merged, further reducing the number of memory access instructions and thus improving the running efficiency of the application program corresponding to the source program.

[0059] A fourth aspect of this application provides a compilation apparatus, comprising: an acquisition module for acquiring a first source program, wherein the first source program includes variable dependency information and a first access identifier, the dependency information including at least one parameter, the at least one parameter being used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially, and the storage space corresponding to a target variable modified by the first access identifier does not overlap with the storage spaces corresponding to variables other than the target variable; and an optimization module for determining a first target code file based on the first source program, the dependency information in the first source program, and / or the first access identifier in the first source program, wherein the number of memory access instructions in the first target code file is less than the number of memory access instructions in a second target code file, and the second target code file is a target code file not determined based on the dependency information in the first source program and / or the first access identifier.

[0060] In one possible implementation of the fourth aspect above, the optimization module includes a processing module and a code generation module; and the processing module is used to determine at least two first instructions that satisfy a first processing condition from multiple memory access instructions corresponding to the first source program based on the correlation information and the first access identifier in the first source program. The first processing condition includes: at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially, the first variable is modified by the first access identifier, and the at least two first instructions are of the same type; the processing module is also used to perform a first processing on the at least two first instructions; and the code generation module is used to obtain a first target code file.

[0061] In one possible implementation of the fourth aspect above, the optimization module includes a processing module and a code generation module; and the processing module is used to determine at least two third instructions that satisfy a second processing condition from multiple memory access instructions corresponding to the first source program based on a first access identifier in the first source program, wherein the second processing condition includes: at least two third instructions correspond to third variables, the third variables are modified by the first access identifier, and at least two third instructions are of the same type; the processing module is also used to perform a first processing on the at least two third instructions; and the code generation module is used to obtain a first target code file.

[0062] In one possible implementation of the fourth aspect above, the optimization module includes a processing module and a code generation module; and the processing module is used to determine at least two fifth instructions that satisfy a third processing condition from multiple memory access instructions corresponding to the first source program based on the correlation information in the first source program, wherein the third processing condition includes: at least two fifth instructions correspond to fifth variables, there is at least one sixth instruction corresponding to a sixth variable among the at least two fifth instructions, the storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable, and the at least two fifth instructions are of the same type; the processing module is also used to perform a first processing on the at least two fifth instructions; the code generation module is used to obtain a first target code file.

[0063] A fifth aspect of this application provides a compilation apparatus, comprising: an acquisition module for acquiring a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, the first access identifier being used to indicate that the first member data is accessed only through a first access method; an optimization module for determining at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes: the first instructions are instructions that access the first member data through the first access method, and the at least two first instructions are of the same type; the optimization module is further configured to perform a first processing on the at least two first instructions; and a code generation module for obtaining a first object code file.

[0064] In one possible implementation of the fifth aspect above, the acquisition module is further configured to acquire a first source program, wherein the first source program includes a correlation identifier for variables, the correlation identifier indicating whether there is another variable whose storage space intersects with the variable's corresponding variable; the optimization module is further configured to, based on the correlation identifier in the first source program, determine at least two third instructions among the multiple memory access instructions corresponding to the first source program that do not satisfy the first processing condition but satisfy the second processing condition, wherein the second processing condition includes: at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable among the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable; the optimization module is further configured to perform first processing on the at least two third instructions; and the code generation module is further configured to obtain a first target code file.

[0065] A sixth aspect of this application provides a compilation apparatus, comprising: an acquisition module for acquiring a first source program, wherein the first source program includes variable correlation identifiers, and the storage spaces corresponding to variables with the same correlation identifier do not overlap; an optimization module for determining, based on the correlation identifiers in the first source program, at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes: at least two first instructions corresponding to first variables, at least one second instruction corresponding to a second variable existing between the at least two first instructions, and the correlation identifier of the second variable being the same as the correlation identifier of the first variable; the optimization module further comprising performing a first processing on the at least two first instructions; and a code generation module for obtaining a first object code file.

[0066] A seventh aspect of this application provides a readable medium storing instructions that, when executed on an electronic device, cause the electronic device to perform any one of the methods described in the first, second, and third aspects above.

[0067] The eighth aspect of this application provides an electronic device, including a memory for storing instructions executable by one or more processors of the electronic device, and a processor, one of the processors of the electronic device, for performing any one of the methods of the first, second and third aspects described above.

[0068] The ninth aspect of this application provides a program product including instructions that, when executed on an electronic device, cause the electronic device to implement any one of the methods of the first, second, and third aspects described above. Attached Figure Description

[0069] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0070] Figure 1 An embodiment of this application illustrates a conversion process from program source code to an executable file;

[0071] Figure 2 A schematic diagram of a memory access process is shown according to an embodiment of this application;

[0072] Figure 3A An embodiment of this application illustrates a schematic diagram of data interaction between a processor and memory;

[0073] Figure 3B An example of an access process comparison diagram is shown according to an embodiment of this application;

[0074] Figure 3C A schematic diagram of an access process is shown according to an embodiment of this application;

[0075] Figures 4A to 4D An illustration of an error merging scenario is shown according to an embodiment of this application;

[0076] Figure 5 A flowchart of a compilation method is shown according to an embodiment of this application;

[0077] Figure 6 A flowchart illustrating a compilation method based on access identifiers is shown according to an embodiment of this application;

[0078] Figure 7 A flowchart illustrating a compilation method based on access identifiers and relevance identifiers is shown according to an embodiment of this application.

[0079] Figure 8 A flowchart illustrating a compilation method based on variable relevance identification is shown according to an embodiment of this application;

[0080] Figure 9 A flowchart illustrating a compilation method based on relevance identifiers and access identifiers is shown according to an embodiment of this application;

[0081] Figure 10 A flowchart illustrating a compilation method based on relevance information and / or a first access identifier is shown according to an embodiment of this application.

[0082] Figure 11 A schematic diagram of the structure of a compiler apparatus is shown according to an embodiment of this application;

[0083] Figure 12 A schematic diagram of another compilation apparatus is shown according to an embodiment of this application;

[0084] Figure 13 A schematic diagram of the hardware structure of a compilation device is shown according to an embodiment of this application. Detailed Implementation

[0085] The illustrative embodiments of this application include, but are not limited to, a compilation method, a compilation apparatus, a readable medium, an electronic device, and a program product.

[0086] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described clearly and in detail below with reference to the accompanying drawings.

[0087] Before introducing the technical solutions involved in the embodiments of this application, some of the terms included in the embodiments of this application will be explained.

[0088] (1) Variables

[0089] In computer programming, variables are identifiers used to store data. For example, a variable name can represent the starting address of the memory space where the data is stored. Each variable has an associated data type, which includes, but is not limited to, basic data types such as integers (int), floating-point numbers (float), characters (char), strings (string), and booleans, as well as composite data types such as arrays (array), structures (struct), and classes (class).

[0090] The definition of a variable based on a basic data type is as follows: data type variable name. For example, `int a` means that the data corresponding to the variable named `a` is integer data.

[0091] The definition of a variable of a composite data type (or composite type data) is as follows: Composite data type composite data name {member list} composite data variable name. For example, struct Student{char name; int age; floatscore;} student1 represents the definition of a structure variable student1 with the structure name Student. The structure variable includes multiple member data: the character member data name, the integer member data age, and the floating-point member data score.

[0092] (2) Pointer variables

[0093] A variable that stores an address is called a pointer variable, and a pointer variable is a special type of variable.

[0094] The form for defining a pointer variable is as follows: data type * variable name. For example, `int *p` represents a pointer variable with the variable name `p`, and the data in the memory space (hereinafter referred to as the memory space) corresponding to the address where the pointer variable `p` is stored is integer data. Pointer variables can be used to access the memory space corresponding to variables of basic data types or variables of composite data types.

[0095] For example, accessing elements in an array via a pointer: assuming the character array is `char array`, you can define a pointer variable `char*ptr`. For example, `*(ptr)` accesses the first element of the array `array`, `*(ptr+1)` accesses the second element of the array `array`, and so on.

[0096] For example, accessing member data in a structure via a pointer: For the structure variable `struct Student{char name; int age; float score;} student1`, a pointer variable `struct Student* pStudent` can be defined, and `pStudent = &student1` represents accessing the structure variable `student1`. For example, the member data `age` of the structure variable `student1` can be accessed through any of the following forms: `student1.age`, `(*pStudent).age`, and `pStudent->age`.

[0097] (3) Formal parameters: When defining a function, the variables enclosed in parentheses after the function name are called formal parameters, or simply formal parameters. Formal parameters are variables used during function definition. A formal parameter is a virtual variable without a specific value; it is used to receive the values ​​passed from the actual parameters during function calls and to perform calculations based on those values. Formal parameters are only instantiated (memory space allocated) during function calls and are automatically destroyed after the function call is complete. That is, formal parameters are only valid during function execution.

[0098] (4) Actual Parameters: When calling a function, the parameters in parentheses after the function name are called actual parameters, or simply arguments. Actual parameters are variables used during function calls, possessing definite values, and are used to pass these values ​​to the formal parameters of the called function. Actual parameters can take various forms, including but not limited to: constants, variables, expressions, and functions. Regardless of their form, actual parameters must have definite values ​​during function calls so that these values ​​can be passed to the formal parameters. For example, if an actual parameter is an expression, each variable in the expression must have definite values ​​to derive the expression's value. Or, for example, if an actual parameter is a function, each parameter of the function must have definite values ​​to derive the function's value.

[0099] For example, refer to the following code:

[0100]

[0101] The `add` function calculates the sum of the values ​​of parameters `x` and `y`. Parameters `x` and `y` are formal parameters, while parameters `a` and `b` are actual parameters.

[0102] (5) Compilation: Compilation is the process of converting source code (or source program, program source code) written in one programming language (hereinafter referred to as the original language) into target code in another programming language (hereinafter referred to as the target language), such as a binary executable file. The original language is more complex than the target language. For example, the original language can be a high-level language, such as Pascal, C, C++, C#, Java, etc.; the target language can be assembly language or machine language. Machine language code can be the object code of the target machine (e.g., a device that runs machine language code), also known as machine code.

[0103] To facilitate understanding, the following example uses a high-level language as the source language and a machine language as the target language to illustrate the process of converting a source program into an executable file that can be executed by a processor (i.e., the program compilation process).

[0104] Figure 1 A schematic diagram illustrating a conversion process from source code to an executable file is shown according to an embodiment of this application. Figure 1 As shown, the conversion process from source code to executable file includes the following stages:

[0105] 1. Compilation Phase: The compiler in the compilation device obtains the source program, performs lexical analysis, syntax analysis, and semantic analysis, generates an intermediate representation (IR, or intermediate code), and optimizes the intermediate representation (e.g., instruction merging) to obtain the assembly code file. The forms of the intermediate representation include, but are not limited to, suffix representation, graph representation, three-address code, and low-level virtual machine (LLVM) intermediate representation.

[0106] For example, let's take C as the source language and machine language as the target language. Assume the source program is:

[0107]

[0108] The memory access instructions in the intermediate representation corresponding to the swap function can be referenced in the following form:

[0109] Load1B@addr1; / / Read one byte of data from the memory space starting at address addr1 pointed to by pointer variable p.

[0110] Load1B@addr2; / / Read one byte of data from the memory space starting at address addr2 pointed to by pointer variable q.

[0111] Store1B@addr1; / / Writes one byte of data to the memory space pointed to by pointer variable q, starting at address addr1.

[0112] Store1B@addr2; / / Writes one byte of data to the memory space pointed to by pointer variable q, starting at address addr2.

[0113] Here, addr1 and addr2 are virtual addresses (VA). When the executable file is run, the processor of the running device translates the virtual address into a physical address (PA), that is, it allocates available physical memory space and sends the physical address to the processor core in the processor. The processor core controls the data bus to read / write data to the memory space corresponding to the physical address (memory access).

[0114] It can be understood that pointer variables p and q are formal parameters of the swap function. The lifetime of pointer variables p and q is only during the execution of the swap function; that is, pointer variables p and q are local variables, and the processor determines the memory space they point to when it executes the machine instructions corresponding to the swap function. In other words, the address information of the memory space corresponding to pointer variables p and q cannot be determined during the compilation phase; it needs to be determined during the processor's execution phase.

[0115] 2. Assembly stage: The assembler of the compilation device obtains the assembly code file generated by the compiler, converts the assembly instructions in the assembly code file into machine instructions (e.g., 01 sequences), and generates the object file.

[0116] 3. Linking stage: Since there may be cases where object files call functions from library files or other files, the linker of the compilation device needs to link the relevant object files generated by the assembler, as well as link them with the library files, to generate an executable file so that the processor of the running device can run the generated executable file.

[0117] It is understandable that the compilation device and the runtime device can be the same device or different devices.

[0118] The compilation method provided in this application can be applied to a compiler or a device with program compilation capabilities.

[0119] The compilers in this application embodiment include, but are not limited to, the GNU compiler collection (GCC) and the low-level virtual machine (LLVM).

[0120] The devices in this application embodiment can be terminal devices, such as mobile phones, smart TVs, wearable devices, tablets, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in autonomous driving, wireless terminals in remote surgery, wireless terminals in smart grids, and wireless terminals in smart homes. The devices can also be physical servers or cloud devices, or virtual machines (VMs) implemented based on general-purpose physical servers combined with network functions virtualization (NFV) technology. A virtual machine refers to a complete computer system simulated by software, possessing full hardware system functionality and running in a completely isolated environment. Electronic devices can also be server clusters composed of multiple servers, or a cloud computing service center.

[0121] This application does not impose any restrictions on the specific types of compilers and devices.

[0122] For ease of description, the embodiments of this application will be described in detail below using the source language as a high-level language and the target language as machine language as an example.

[0123] As mentioned earlier, since the processor of a running device processes data much faster than the memory read and write speed, the processor needs to spend a lot of time waiting for the required data to be read from memory and / or written to memory during the process of running the executable file corresponding to the application, thus affecting the efficiency of the processor in running the application.

[0124] Therefore, in order to improve the efficiency of the processor in running applications, memory access instructions (such as read or write instructions) of the same type that access contiguous memory spaces in the intermediate representation can usually be merged during the compilation stage of the source program corresponding to the application, and an executable file can be obtained based on the merged intermediate representation.

[0125] It's understandable that since the executable file is based on the merged intermediate representation, the memory access instructions in the executable file are also merged memory access instructions. Compared to the executable file without merging, the merged executable file has fewer memory access instructions, that is, fewer memory access requests sent by the processor to memory, thereby improving access efficiency, reducing processor waiting time, and thus improving the processor's efficiency in running applications.

[0126] For example, suppose the fun function is:

[0127] int fun(int A[3],int B[3]){

[0128] …

[0129] B[1] = A[0];

[0130] B[2] = A[1] + A[2];

[0131] …

[0132] }

[0133] Here, array A and array B are two formal parameters of the fun function.

[0134] Taking the instructions B[1] = A[0] and B[2] = A[1] + A[2] in the fun function as an example, refer to Figure 2 The diagram shown illustrates the memory access process. The middle section represents five memory access instructions, which are ordered in the following order of execution:

[0135] ① The read operation instruction Load1B@VA0 is used to read the first element A[0] in array A;

[0136] ② The write operation instruction Store1B@VB1 to write data to the second element of array B;

[0137] ③ The instruction Load1B@VA1 is used to read the data in the second element A[1] of array A;

[0138] ④ The instruction Load1B@VA2 is used to read data from the third element of array A;

[0139] ⑤ Write operation instruction Store1B@VB2 to write data to the third element of array B.

[0140] Wherein, VA0 is the virtual address corresponding to A[0], VA1 is the virtual address corresponding to A[1], VA2 is the virtual address corresponding to A[2], VB1 is the virtual address corresponding to B[1], and VB2 is the virtual address corresponding to B[2].

[0141] It is understandable that the memory addresses corresponding to the elements in array A are contiguous, and the memory addresses corresponding to the elements in array B are also contiguous.

[0142] Continue to refer to Figure 2The memory access process diagram shown shows that since the instructions Load1B@VA0, Load1B@VA1 and Load1B@VA2 are all read operation instructions and the addresses of the memory spaces they access are contiguous, the instructions Load1B@VA0, Load1B@VA1 and Load1B@VA2 can be merged into a new read operation instruction Load3B@VA0. This new read operation instruction Load3B@VA0 is used to read the first element A[0], the second element A[1] and the third element A[2] in array A.

[0143] It is understandable that since both Store1B@VB1 and Store1B@VB2 are write operation instructions and the addresses of the memory spaces they access are contiguous, Store1B@VB1 and Store1B@VB2 can be merged into a new write operation instruction Store2B@VB1. This new write operation instruction is used to write data into the memory spaces corresponding to the second element B[1] and the third element B[2] in array B.

[0144] Because the processor and memory interact via a bus, when the processor reads data from memory or writes data to memory, it first needs to translate the virtual address into the corresponding physical address in memory, then send the physical address and control signals to memory. Memory then locates the corresponding physical address and sends the data from the memory space corresponding to that physical address to the processor, or vice versa. For example, see [reference]. Figure 3A The diagram shows the data interaction between the processor and memory.

[0145] like Figure 3A As shown, the processor and memory are connected via a bus, which includes a control bus, an address bus, and a data bus. The process of the processor executing a memory access instruction involves: the processor's physical core sending a virtual address to the memory management unit (MMU); the MMU converting the virtual address to a physical address and sending the physical address to memory; and if the memory access instruction is a read operation, the processor's physical core sends a control signal indicating data read to memory via the control bus; upon receiving the physical address and the control signal, memory sends the data from the memory space corresponding to the physical address to the processor's cache via the data bus. If the memory access instruction is a write operation, the processor's physical core sends a control signal indicating data write to memory via the control bus and sends the data to be written to memory via the data bus; upon receiving the physical address, the data to be written, and the control signal, memory stores the data to be written in the memory space corresponding to the physical address.

[0146] It is understandable that after the merger, the processor only needs to implement the functions of the above three read operation instructions through a new read operation instruction Load3B@VA0, thereby reducing the number of times the processor accesses memory, reducing the processor's waiting time, and thus improving the processor's efficiency in running executable files.

[0147] For example, combining Figure 2 The memory access instructions shown are referenced. Figure 3B The diagram illustrates a comparison of the access process. (See attached diagram.) Figure 3B As shown, the execution process of memory access instructions before instruction merging includes:

[0148] 1. The processor sends the physical address corresponding to VA0 and control signals for reading data to the memory.

[0149] 2. The memory sends the data from the memory cell corresponding to the physical address of VA0 to the processor.

[0150] 3. The processor sends the physical address corresponding to VB1, the control signal for writing data, and the data to be written to the memory.

[0151] 4. The processor sends the physical address corresponding to VA1 and control signals for reading data to the memory.

[0152] 5. The memory sends the data from the memory cell corresponding to the physical address of VA1 to the processor.

[0153] 6. The processor sends the physical address corresponding to VA2 and control signals for reading data to the memory.

[0154] 7. The memory sends the data from the memory cell corresponding to the physical address of VA2 to the processor.

[0155] 8. The processor sends the physical address of VB2, the control signal for writing data, and the data to be written to the memory.

[0156] The execution process of the memory access instruction after instruction merging includes:

[0157] 1'. The processor sends control signals to the memory corresponding to the physical address of VA0 and to read data from the three memory units.

[0158] 2'. The memory sends data from the memory space starting at the physical address corresponding to VA0 to the processor.

[0159] 3'. The processor sends the physical address corresponding to VB1, the control signal for writing data, and the data to be written to the memory.

[0160] It is understandable that after instruction merging, the processor only needs to send the physical address and control signals corresponding to the data to be read to the memory once, and send the physical address and control signals corresponding to the data to be written to the memory once, reducing the number of times physical addresses and control signals are sent to the memory, thereby shortening the time for reading and writing data.

[0161] However, since memory space is allocated when the processor runs the executable file, the compilation device cannot obtain information about the specific memory space corresponding to the formal parameter arrays A and B of the fun function during the compilation phase.

[0162] In some cases, refer to Figure 3C The diagram illustrates the access process. The formal parameter arrays A and B of the `fun` function may correspond to the same actual parameter array N; that is, arrays A and B occupy the same memory space. For example, ... Figure 3C As shown, the virtual address VA0 corresponding to A[0] corresponds to the physical address PA0. The virtual address VA1 corresponding to A[1] and the virtual address VB1 corresponding to B[1] correspond to the same physical address PA1. The virtual address VA2 corresponding to A[2] and the virtual address VB2 corresponding to B[2] correspond to the same physical address PA2. The memory spaces accessed by the above read operation instruction Load1B@VA1 and the write operation instruction Store1B@VB1 overlap, for example, both are memory space 1. The above read operation instruction Load1B@VA1 is executed after the write operation instruction Store1B@VB1, that is, read after write. The memory spaces accessed by the above read operation instruction Load1B@VA2 and the write operation instruction Store1B@VB2 overlap, for example, both are memory space 2. The above write operation instruction Store1B@VB2 is executed after the read operation instruction Load1B@VA2, that is, write after read.

[0163] In some cases, if the data read by the read instruction Load1B@VA1 from memory space 1 is the same data that the processor wrote to memory space 1 via the write instruction Store1B@VB1, the execution order of the instructions may change after the above instruction merging. For example, if the new read instruction Load3B@VA0 is executed first, followed by the write instruction Store2B@VB1, the data read by the processor from memory space 1 may not be the expected data. That is, the processor may write the data to memory space 1 via the write instruction Store2B@VB1, leading to program errors, or even application malfunctions or crashes.

[0164] In other cases, if there is another write operation instruction Store1B@VC1 (not shown in the diagram) between the aforementioned write operation instructions Store1B@VB1 and Store1B@VB2, and the write operation instruction Store1B@VB2 is executed after the write operation instruction Store1B@VC1 (i.e., write-after-write), and if the memory space accessed by the write operation instruction Store1B@VC1 overlaps with that of the write operation instructions Store1B@VB1 and / or Store1B@VB2, merging the write operation instructions Store1B@VB1 and Store1B@VB2 may change the execution order of the instructions, leading to program errors, or even application malfunctions or crashes.

[0165] For example, refer to Figures 4A to 4D The diagram illustrates a scenario of incorrect merging. (See attached image.) Figure 4A As shown, mobile phone 10 is running a video application and displaying the video application's user interface 10a. If a video switching operation is detected, for example... Figure 4A The swipe-up operation shown requires the phone's processor to run a video switching process for a video application, such as retrieving video data from another video or rendering the image. If the memory access instructions in the program corresponding to the video switching process of the video application running on the phone are incorrectly merged—for example, if the memory space accessed by write operations between merged read operations is not considered to overlap with the memory space accessed by the merged read operations—it may cause the video application to malfunction. For example, display... Figure 4B The user interface 10b shows a "Loading failed" message. For example, it displays something like... Figure 4C The abnormal white screen interface shown is 10c. For example, it displays something like... Figure 4D The desktop 10d of the phone 10 shown indicates that the video application has ended running, etc.

[0166] It is understandable that if memory access instructions of the same type that access contiguous memory spaces are merged in the above manner, without considering whether the memory spaces accessed by other types of memory access instructions overlap with the memory spaces accessed by the merged memory access instructions, although the number of memory access instructions can be reduced, it may lead to the aforementioned problem of incorrect merging, thereby affecting the operation of the application.

[0167] However, since memory space is allocated when the processor runs the executable file, the compiler does not allocate memory space for each variable in the source program during the compilation phase. Therefore, the compiler cannot obtain information about the memory space accessed by each memory access instruction, nor can it determine whether there is any overlap in the memory spaces accessed by multiple memory access instructions.

[0168] Therefore, this application provides a compilation method in which:

[0169] Before the source program is compiled, such as during the program design phase (or coding phase), the program developers configure correlation identifiers for each variable in the source program. These correlation identifiers are used to indicate whether there is an overlap between the memory spaces corresponding to the variables.

[0170] In some embodiments, variables whose corresponding memory spaces definitely do not overlap can be marked with the same first type of correlation identifier, or variables whose corresponding memory spaces may overlap can be marked with different first type of correlation identifiers, so that the compilation stage can determine whether the memory spaces corresponding to the memory access instructions have an overlap based on the first type of correlation identifiers of each variable.

[0171] For example, for the `fun` function mentioned above, if the developer knows that array A and array B are definitely not the same array, then array A and array B can be marked with the same Type I alias, for example, `no_alias`. <0> If developers cannot determine whether array A and array B are necessarily not the same array, they can assign different Type I aliases to array A and array B, for example, using `no_alias`. <1> Identify data A using no_alias. <2> Label array B.

[0172] In other embodiments, variables whose corresponding memory spaces may overlap may be marked with the same second type of correlation identifier, or variables whose corresponding memory spaces definitely do not overlap may be marked with different second type of correlation identifiers, so that the compilation stage can determine whether the memory spaces corresponding to the memory access instructions overlap based on the second type of correlation identifiers of each variable.

[0173] For example, regarding the `fun` function mentioned above, if the developer knows that array A and array B are definitely not the same array, they can assign different Type II relevance labels to array A and array B, for example, using an alias. <0> Identify data A using an alias. <1> Identify array B. If developers cannot determine whether array A and array B are necessarily not the same array, they can assign the same Type II related identifier to array A and array B, for example, using an alias. <2> Label data A and array B.

[0174] During the compilation phase, the compiler converts the instructions in the source program into an intermediate representation. Based on the correlation identifiers of various variables in the source program, it identifies multiple memory access instructions of type 1 (hereinafter referred to as first instructions) in the intermediate representation that meet the merging conditions, and treats them as multiple instructions to be merged. Then, the instructions to be merged are merged, and based on the merged intermediate representation, the executable file is obtained.

[0175] In some embodiments, multiple first instructions may correspond to multiple variables of different basic data types.

[0176] Merging conditions can be: multiple first instructions have the same type, multiple first instructions access memory space addresses consecutively, multiple first instructions are consecutive memory access instructions, and the correlation indicators of multiple variables corresponding to multiple first instructions indicate that the memory spaces corresponding to multiple variables do not overlap.

[0177] The merging conditions can also be: multiple first instructions are of the same type, the memory space addresses accessed by multiple first instructions are consecutive, the correlation indicators of multiple variables corresponding to multiple first instructions indicate that the memory spaces corresponding to multiple variables do not overlap, there is at least one second instruction among multiple first instructions, and the correlation indicators of the variables corresponding to the second instruction indicate that the memory space corresponding to the variables of the second instruction does not overlap with the memory spaces corresponding to the variables of the first instruction.

[0178] If the first instruction is a read operation instruction, the merging conditions can also be: multiple first instructions are of the same type, the memory space addresses accessed by multiple first instructions are consecutive, the correlation indicators of multiple variables corresponding to multiple first instructions indicate that the memory spaces corresponding to multiple variables do not overlap, there is at least one second instruction among multiple first instructions, the type of the second instruction is different from the type of the first instruction, and the correlation indicators of the variables corresponding to the second instruction indicate that the memory space corresponding to the variables of the second instruction does not overlap with the memory spaces corresponding to the variables of the first instruction.

[0179] In other embodiments, multiple first instructions may also correspond to variables of the same composite data type.

[0180] The merging conditions can be: multiple first instructions have the same type, multiple first instructions access memory space addresses consecutively, multiple first instructions correspond to variables that are first variables, multiple first instructions have at least one second instruction, and the correlation flag of the second variable corresponding to the second instruction indicates that the memory space corresponding to the second variable does not overlap with the memory space corresponding to the first variable.

[0181] If the first instruction is a read operation instruction, the merging conditions can also be: multiple first instructions are of the same type, the memory space addresses accessed by multiple first instructions are consecutive, the variables corresponding to multiple first instructions are first variables, there is at least one second instruction among multiple first instructions, the second instruction is of a different type from the first instruction, and the correlation flag of the second variable corresponding to the second instruction indicates that the memory space corresponding to the second variable does not overlap with the memory space corresponding to the first variable.

[0182] In some embodiments, when the correlation identifier of a variable is the aforementioned first type of correlation identifier, the compilation device can obtain the first type of correlation identifier of the variable in the source program.

[0183] If multiple variables in the source program have the same Type I dependency identifier, the compiler can determine that the memory spaces corresponding to these variables do not overlap. The compiler then identifies consecutive first instructions that access contiguous memory spaces and correspond to the variables with the same Type I dependency identifier as instructions to be merged; alternatively, it identifies the first instruction among the multiple first instructions that access contiguous memory spaces and correspond to variables with the same Type I dependency identifier as the variable corresponding to the second instruction between these multiple first instructions as instructions to be merged.

[0184] If the first type of correlation identifiers of the variables in the source program are different, the electronic device cannot determine whether there is an intersection between the memory spaces corresponding to multiple variables with different first type of correlation identifiers, and therefore cannot determine the instructions to be merged.

[0185] In other embodiments, when the correlation identifier of a variable is the aforementioned second type of correlation identifier, the compilation device can obtain the second type of correlation identifier of the variable in the source program.

[0186] If multiple variables in the source program have different Type II dependency identifiers, the compiler can determine that the memory spaces corresponding to these variables do not overlap. The compiler then identifies consecutive first instructions that access contiguous memory spaces and correspond to variables with different Type II dependency identifiers as instructions to be merged; alternatively, it identifies the first instruction whose dependency identifier differs from the second instruction between these first instructions and the variables corresponding to these second instructions as instructions to be merged.

[0187] If the second type of dependency identifiers of the variables in the source program are the same, the compiler cannot determine whether there is an intersection between the memory spaces corresponding to multiple variables with the same second type of dependency identifier, and therefore cannot determine the instructions to be merged.

[0188] For example, if the memory space I accessed by read operation instruction I is adjacent to the memory space II accessed by read operation instruction II, and there is a write operation instruction III between read operation instruction I and read operation instruction II, and the memory space III accessed by write operation instruction III has no intersection with memory space I and memory space II, then read operation instruction I and read operation instruction II can be merged into a new read operation instruction I', and the memory space accessed by read operation instruction I' is memory space I and memory space II.

[0189] For example, if the memory space III accessed by write operation instruction III is adjacent to the memory space IV accessed by write operation instruction IV, and there is a read operation instruction V between write operation instruction III and write operation instruction IV, and the memory space V accessed by read operation instruction V has no intersection with memory space III and memory space IV, then write operation instruction III and write operation instruction IV can be merged into a new write operation instruction III', and the memory space accessed by write operation instruction III' is memory space III and memory space IV.

[0190] It is understood that the compilation method provided in this application, by defining and using a dependency identifier, enables the compiler to determine whether instructions that access contiguous memory spaces can be merged through the dependency identifier in the source program, thereby reducing the risk of erroneous merging and thus reducing the risk of program runtime errors.

[0191] Specifically, the compilation phase may include:

[0192] First, the code in the source program is converted into an intermediate representation, where the source program includes the correlation identifiers of variables.

[0193] Secondly, multiple memory access instructions of the same type that access contiguous memory addresses in the intermediate representation are treated as multiple target instructions.

[0194] Then, the correlation identifiers of each variable in the source program are obtained, the overlap relationship of the memory space corresponding to each variable is determined based on the correlation identifiers of each variable, and the overlap relationship of the memory space is used to determine whether there are any instructions to be merged among the multiple target instructions that meet the merging conditions, and the instructions to be merged are merged.

[0195] It is understandable that if the variables corresponding to the first and second instructions to be merged are both the same variable (e.g., they correspond to the same composite data type variable), then the memory spaces accessed by the first and second instructions to be merged must not overlap (i.e., their addresses are unrelated). Furthermore, if the first and second instructions to be merged are consecutive memory access instructions, meaning there are no other memory access instructions between them, then the first and second instructions to be merged can be merged.

[0196] In some embodiments, taking a read operation instruction as an example, if the variable corresponding to the first instruction to be merged and the second instruction to be merged is the first variable, and there is a write operation instruction between the first instruction to be merged and the second instruction to be merged, and the first type of correlation identifier of the second variable corresponding to the write operation instruction is the same as the first type of correlation identifier of the first variable, then the first instruction to be merged and the second instruction to be merged can be merged.

[0197] For example, with Figure 2The five memory access instructions shown are: Load1B@VA0 (read operation), Store1B@VB1 (write operation), Load1B@VA1 (read operation), Load1B@VA2 (read operation), and Store1B@VB2 (write operation). Taking these five instructions as an example, VA0 is the virtual address corresponding to A[0], VA1 is the virtual address corresponding to A[1], VA2 is the virtual address corresponding to A[2], VB1 is the virtual address corresponding to B[1], and VB2 is the virtual address corresponding to B[2].

[0198] In some embodiments, it is assumed that the relevance identifier of array A is the first type of relevance identifier no_alias. <0> The correlation identifier for array B is also the first type of correlation identifier, no_alias. <0> .

[0199] Since the memory addresses corresponding to the first element A[0], the second element A[1], and the third element A[2] of array A are contiguous, VA0, VA1, and VA2 are also contiguous addresses. Therefore, the read operation instructions Load1B@VA0, Load1B@VA1, and Load1B@VA2 can be used as instructions to be merged. Then, based on the correlation identifiers of the variables corresponding to the instructions to be merged, it can be determined whether there are any instructions that can be merged.

[0200] There is a write operation instruction Store1B@VB1 between the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1. Furthermore, the variable array A corresponding to the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 has the same first-type correlation identifier as the variable array B corresponding to the write operation instruction Store1B@VB1. The memory spaces corresponding to array A and array B do not overlap. That is, the memory spaces accessed by the read operation instruction Load1B@VA0, the read operation instruction Load1B@VA1, and the write operation instruction Store1B@VB1 do not overlap. Therefore, the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1 can be merged.

[0201] If there is no write operation instruction between the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2, that is, if the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 are consecutive memory access instructions, then the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be combined.

[0202] Therefore, the read operation instructions Load1B@VA0, Load1B@VA1, and Load1B@VA2 can be combined into a single read operation instruction Load3B@VA0.

[0203] Since the memory addresses corresponding to the second element B[1] and the third element B[2] of array B are contiguous, VB1 and VB2 are also contiguous addresses. Therefore, the write operation instructions Store1B@VB1 and Store1B@VB2 can be used as instructions to be merged. Then, based on the correlation identifier of the variables corresponding to the instructions to be merged, it can be determined whether there are any instructions that can be merged.

[0204] There are read operations Load1B@VA1 and Load1B@VA2 between the write operation instructions Store1B@VB1 and Store1B@VB2. Furthermore, the variable array B corresponding to the write operation instructions Store1B@VB1 and Store1B@VB2 has the same first-type correlation identifier as the variable array A corresponding to the read operation instructions Load1B@VA1 and Load1B@VA2. The memory spaces corresponding to array A and array B do not overlap. That is, the memory spaces accessed by the write operation instructions Store1B@VB1 and Store1B@VB2 do not overlap with the memory spaces accessed by the read operation instructions Load1B@VA1 and Load1B@VA2. Therefore, the write operation instructions Store1B@VB1 and Store1B@VB2 can be merged into a single write operation instruction Store2B@VB1.

[0205] In other embodiments, it is assumed that the relevance identifier of array A is the first type of relevance identifier no_alias. <0> The relevance identifier for array B is the first-class relevance identifier no_alias. <1> .

[0206] Since the memory addresses corresponding to the first element A[0], the second element A[1], and the third element A[2] of array A are contiguous, VA0, VA1, and VA2 are also contiguous addresses. Therefore, the read operation instructions Load1B@VA0, Load1B@VA1, and Load1B@VA2 can be used as instructions to be merged. Then, based on the correlation identifiers of the variables corresponding to the instructions to be merged, it can be determined whether there are any instructions that can be merged.

[0207] There is a write operation instruction Store1B@VB1 between the read operation instruction Load1B@VA0 and the read operation instruction Load1B@VA1. Furthermore, the first-type dependency identifier of the variable array A corresponding to the read operation instructions Load1B@VA0 and Load1B@VA1 is different from the first-type dependency identifier of the variable array B corresponding to the write operation instruction Store1B@VB1. The memory spaces corresponding to array A and array B may overlap; that is, the memory space accessed by the write operation instruction Store1B@VB1 may overlap with the memory spaces accessed by the read operation instructions Load1B@VA0 and / or Load1B@VA1. Therefore, the read operation instructions Load1B@VA0 and Load1B@VA1 cannot be merged.

[0208] There is no write operation instruction between the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2. That is, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 are consecutive memory access instructions, so the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be combined.

[0209] Therefore, the read operation instruction Load1B@VA1 and the read operation instruction Load1B@VA2 can be combined into a single read operation instruction Load2B@VA1.

[0210] Since the memory addresses corresponding to the second element B[1] and the third element B[2] of array B are contiguous, VB1 and VB2 are also contiguous addresses. Therefore, the write operation instructions Store1B@VB1 and Store1B@VB2 can be used as instructions to be merged. Then, based on the correlation identifier of the variables corresponding to the instructions to be merged, it can be determined whether there are any instructions that can be merged.

[0211] There are read operations Load1B@VA1 and Load1B@VA2 between the write operation instructions Store1B@VB1 and Store1B@VB2. Furthermore, the variable array B corresponding to the write operation instructions Store1B@VB1 and Store1B@VB2 has a different first-type correlation identifier than the variable array A corresponding to the read operation instructions Load1B@VA1 and Load1B@VA2. The memory space corresponding to array A and the memory space corresponding to array B may overlap. That is, the memory space accessed by the write operation instructions Store1B@VB1 and / or the write operation instructions Store1B@VB2 may overlap with the memory space accessed by the read operation instructions Load1B@VA1 and / or the read operation instructions Load1B@VA2. Therefore, the write operation instructions Store1B@VB1 and Store1B@VB2 cannot be merged.

[0212] It is understood that the compilation method provided in this application can determine the overlapping relationship of memory spaces corresponding to variables through defined correlation identifiers, thereby identifying the instructions to be merged and merging them. This compilation method reduces the number of memory access instructions while lowering the risk of instruction error merging, thereby reducing the risk of program runtime errors.

[0213] In some embodiments, before the source program is compiled, the program developer can also mark the member data of each composite data type variable (e.g., structure variable) in the source program, so that the compilation device can further determine whether the memory access instructions corresponding to variables whose memory spaces do not have an intersection as indicated by the correlation mark can be merged, thereby further reducing the number of memory access instructions.

[0214] The access identifier includes a first access identifier. Member data identified by the first access identifier (or first access modifier) ​​can only be accessed through the variable of the corresponding composite data type. It can be understood that the storage space corresponding to the target variable identified by the first access identifier does not overlap with the storage space corresponding to other variables.

[0215] In some embodiments, the access identifier may further include a second access identifier (or second access modifier) ​​indicating that the member data can be accessed through a variable of the composite data type corresponding to the member data, or through a variable of a data type other than the variable of the composite data type corresponding to the member data, such as through a pointer variable of the data type corresponding to the member data.

[0216] For example, consider a structure variable `s1` defined as `struct S{_unique_int a; _unique_int b; _shared_int c;}s1`, where `_unique_` is the first access modifier and `_shared_` is the second access modifier. Then, member data `a` and member data `b` can only be accessed through variables of type `S`. For instance, defining a pointer variable of type `S` as `struct S*ptr`, and then accessing member data `a` and member data `b` of the structure variable `s1` by `ptr = &s1`. For example, member data `a` of the structure variable `s1` can be accessed through any of the following forms: `s1.a`, `(*ptr).a`, or `ptr->a`.

[0217] In some embodiments, when the first type of correlation identifier of the second variable corresponding to the second instruction among the plurality of first instructions is different from the first type of correlation identifier of the first variable corresponding to the plurality of first instructions:

[0218] If the first variable is used to access the member data of the first composite data type variable, that is, the data stored in the memory space corresponding to the first variable is the member data of the first composite data type variable.

[0219] The access identifier corresponding to the member data accessed by the first variable is the first access modifier; and if the first variable is a variable of the first composite data type, while the second variable corresponding to the second instruction is not a variable of the first composite data type, then it is determined that multiple first instructions can be merged.

[0220] For example, for the structure variable struct S{_unique_int a;_unique_int b;_shared_intc;}s1, define pointer variables struct S*ptr1 and int*ptr2.

[0221] If the source program contains the following instructions:

[0222] *(ptr2+1)=ptr1->a;

[0223] *(ptr2+2)=ptr1->b;

[0224] The corresponding intermediate representation can be referenced as follows:

[0225] Load1B@ptr1;

[0226] Store1B@ptr2+1;

[0227] Load1B@ptr1+1;

[0228] Store1B@ptr2+2;

[0229] The following section uses the read operation instructions Load1B@ptr1 and Load1B@ptr1+1 as examples to illustrate the process by which, during the compilation phase, the read operation instructions Load1B@ptr1 and Load1B@ptr1+1 can be merged based on the data types of pointer variables ptr1 and ptr2, as well as the access identifiers of the member data accessed by the corresponding pointer variables ptr1 and ptr2.

[0230] For example, the read operation instructions Load1B@ptr1 and Load1B@ptr1+1 access the member data a and member data b of the structure s1. The access identifiers of member data a and member data b are the first access modifier (_unique_). Furthermore, the data type of pointer variable ptr1 is the data type (S) corresponding to the structure s1, and the data type of pointer variable ptr2 is integer (int).

[0231] It's understandable that since member data 'a' and member data 'b' are accessed using the first access modifier (_unique_), they can only be accessed through variables of the data type corresponding to structure 's1'. However, the write operation instruction Store1B@ptr2+1 accesses the data through the integer pointer variable ptr2. Therefore, pointer variable ptr2 cannot access member data 'a' and member data 'b'. In other words, the write operation instruction Store1B@ptr2+1 is definitely not an operation that writes data to the memory space storing member data 'a' and / or member data 'b'. The memory space corresponding to pointer variable ptr2 and pointer variable ptr1 definitely do not overlap. Therefore, the read operation instructions Load1B@ptr1 and Load1B@ptr1+1 corresponding to pointer variable ptr1 can be merged.

[0232] It is understandable that by defining access identifiers, it can be determined whether memory access instructions for multiple member data in a variable of a composite data type can be merged, thereby reducing the number of times the processor accesses memory and thus improving the efficiency of the processor in running executable files.

[0233] It is understood that the above explanation only uses two memory access instructions of the first type that access adjacent memory addresses as an example to illustrate whether the first instructions can be merged. In other embodiments, the first instruction can be multiple memory access instructions of the first type that access consecutive memory addresses. If there is no second instruction between any two adjacent first instructions among the multiple first instructions, the multiple first instructions can be merged. It is understood that it is also possible to determine each pair of adjacent first instructions among the multiple first instructions separately, add the first instructions that can be merged to the set of instructions to be merged, and then merge the first instructions in the set of instructions to be merged. This application does not limit the specific process of determining whether the first instructions can be merged.

[0234] For example, Figure 5 A flowchart of a compilation method is shown according to an embodiment of this application. It can be understood that... Figure 5 The execution entity of the illustrated process is electronic device 100. Electronic device 100 can be a compilation device, a device including a compiler, or a device including a compilation unit. For simplicity, the following description... Figure 5 The execution entity will not be described again when the process is shown.

[0235] like Figure 5 As shown, this process includes, but is not limited to:

[0236] S501: Obtain the first source program.

[0237] In some embodiments, the first source program includes access identifiers for composite data and member data of the composite data, the access identifiers being used to indicate the access method of the member data.

[0238] For example, composite data types include first member data, which includes a first access modifier (e.g., _unique_). The first access modifier indicates that the first member data can only be accessed through a first access method. For example, member data identified by the first access modifier can only be accessed through a variable of the composite data type corresponding to that member data (a first variable or a variable of the first type).

[0239] For example, composite data types may also include a second member data that does not include the first access modifier but includes a second access modifier (e.g., _shared_). The second access modifier indicates that the second member data is not accessed through the first access method. For instance, member data identified by the second access modifier can be accessed through a variable of the composite data type corresponding to that member data, or through a variable of a different type than the variable of the composite data type corresponding to that member data, such as through a pointer variable of the data type corresponding to that member data.

[0240] It is understood that the above description of the access identifier is based only on the first access modifier and the second access modifier. In other embodiments, the access identifier may be in other forms, and this application does not limit this.

[0241] In other embodiments, the first source program includes a correlation identifier for variables, and the storage spaces corresponding to variables with the same correlation identifier do not overlap.

[0242] It can be understood that the correlation identifier of a variable is used to indicate whether there is another variable whose memory space intersects with the memory space corresponding to the identified variable. In other words, the correlation identifier of a variable is used to indicate whether there is an intersection between the memory spaces corresponding to multiple variables. The intersection between the memory spaces corresponding to multiple variables includes, but is not limited to: the memory spaces corresponding to multiple variables completely overlapping; the memory spaces corresponding to multiple variables partially overlapping; and the memory spaces corresponding to multiple variables having an inclusion relationship, i.e., the memory space corresponding to one variable contains the memory space corresponding to another variable, etc. This application does not impose specific limitations in this regard.

[0243] It can be understood that if the marked variable is a pointer variable, then the memory space corresponding to the variable is the memory space pointed to by the pointer variable. That is, the overlap of the memory spaces pointed to by the pointer variables can be determined by the correlation identifier of the pointer variables. If the marked variable is a non-pointer variable, then the memory space corresponding to the non-pointer variable is the memory space storing the non-pointer variable. That is, the overlap of the memory spaces storing the non-pointer variable can be determined by the correlation identifier of the non-pointer variable.

[0244] S502: Determine at least two first instructions that satisfy the first processing condition from among the multiple memory access instructions corresponding to the first source program.

[0245] In some embodiments, the electronic device 100 generates a first intermediate representation based on a first source program, wherein the first intermediate representation includes a plurality of instructions; determines a plurality of memory access instructions from the plurality of instructions in the first intermediate representation, and determines at least two first instructions that satisfy a first processing condition from the plurality of memory access instructions.

[0246] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0247] In some embodiments, the first processing condition may be: the first instruction is an instruction to access the first member data through a first access method, and at least two first instructions are of the same type.

[0248] In some embodiments, the first processing condition further includes: at least two first instructions are consecutive memory access instructions, or at least two first instructions have at least one second instruction between them.

[0249] In other words, the first processing condition can be: the first instruction is an instruction that accesses the first member data through the first access method, and at least two first instructions are of the same type and at least two first instructions are consecutive memory access instructions; or, the first instruction is an instruction that accesses the first member data through the first access method, and at least two first instructions are of the same type and at least two first instructions exist between them.

[0250] In other embodiments, if the composite data also includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between at least two first instructions, then the first processing condition may also be: the first instruction is an instruction that accesses the first member data through the first access method, and at least two first instructions are of the same type, and the second instruction is a memory access instruction that does not access the second member data through the first access method.

[0251] In some embodiments, if the first instruction is a read operation instruction, the first processing condition further includes that the first instruction and the second instruction are of different types. That is, the first instruction is a read operation instruction and the second instruction is a write operation instruction; or, the first instruction is a write operation instruction and the second instruction is a read operation instruction.

[0252] S503: Perform first processing on at least two first instructions and obtain the first object code file.

[0253] In some embodiments, the electronic device 100 can directly generate a first target code file based on a first intermediate representation.

[0254] In other embodiments, the electronic device 100 may also perform a first processing on a plurality of first instructions to obtain a second intermediate representation, and convert the second intermediate representation into target code to obtain a first target code file.

[0255] It is understood that the first processing includes, but is not limited to, merging and deleting processes. The processing methods of the first processing will be described in detail below, and will not be repeated here.

[0256] It is understandable that the number of memory access instructions in the first object code file is less than the number of memory access instructions in the second object code file, which is the object code file obtained without performing the first processing on the memory access instructions.

[0257] It is understood that in some embodiments, if the first processing condition is to determine the first instruction from multiple memory access instructions corresponding to the first source program based on the access identifier, the electronic device 100 can also determine, based on the correlation identifier, at least two third instructions from the multiple memory access instructions corresponding to the first source program that do not meet the first processing condition but meet the second processing condition, perform the first processing on the at least two third instructions, and obtain the first target code file. The second processing condition may be: at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable between the at least two third instructions, and the storage space corresponding to the fourth variable does not overlap with the storage space corresponding to the third variable.

[0258] It is understood that in some embodiments, if the first processing condition is to determine the first instruction from multiple memory access instructions corresponding to the first source program based on the correlation identifier, the electronic device 100 can also determine, based on the access identifier, at least two third instructions from the multiple memory access instructions corresponding to the first source program that do not meet the first processing condition but meet the second processing condition, perform the first processing on the at least two third instructions, and obtain the first object code file. The second processing condition may be: the third instruction is an instruction that accesses the first member data through the first access method, and at least two third instructions are of the same type.

[0259] It is understood that the compilation method provided in this application can determine the first instruction that meets the first processing condition through the defined access identifier and / or access flag, and perform merging and / or deletion processing on the first instruction. This compilation method reduces the number of memory access instructions while lowering the risk of incorrect instruction merging and / or incorrect deletion, thereby reducing the risk of program runtime errors.

[0260] To better understand the technical solutions of the embodiments of this application, some technical solutions of this application will be described in detail below with reference to the accompanying drawings.

[0261] Example 1

[0262] This application also provides a compilation method that, based on the access identifiers of member data in variables of various composite data types in the source program, determines memory access instructions that meet the processing conditions, and merges and / or deletes the memory access instructions that meet the conditions to reduce the number of memory access instructions.

[0263] For example, Figure 6 A flowchart illustrating a compilation method based on access identifiers is shown according to an embodiment of this application. It can be understood that... Figure 6 The execution entity of the illustrated process is electronic device 100. Electronic device 100 can be a compilation device, a device including a compiler, or a device including a compilation unit. For simplicity, the following description... Figure 6 The execution entity will not be described again when the process is shown.

[0264] like Figure 6 As shown, this process includes, but is not limited to:

[0265] S601: Obtain the first source program, wherein the first source program includes access identifiers for member data of composite data types, and the access identifiers are used to indicate the access method of the member data.

[0266] Among them, the access identifier of the member data of composite data is used to indicate the access method of the member data.

[0267] In some embodiments, the access identifier may be a first access modifier. Member data identified by a first access modifier (e.g., _unique_) can only be accessed through a first access method. For example, member data identified by a first access modifier can only be accessed through a variable of the composite data type corresponding to that member data. Or, for example, member data identified by a first access modifier can only be accessed through the variable corresponding to that member data.

[0268] In other embodiments, the access identifier can be a first access modifier (e.g., _unique_) and a second access modifier (e.g., _shared_). Member data identified by the second access modifier can be accessed through a variable of the composite data type corresponding to the member data, or through a variable of a different type than the variable of the composite data type corresponding to the member data, such as through a pointer variable of the data type corresponding to the member data.

[0269] For example, a composite data type includes a first member data, which includes a first access modifier. The composite data type also includes a second member data, which does not include the first access modifier, but may include a second access modifier.

[0270] For example, suppose the source program includes the definition of the composite data type s_type:

[0271] typedef struct{

[0272] _unique_UINT32 a;

[0273] _unique_UINT32 b;

[0274] _shared_UINT32 c

[32] ;

[0275] }s_type;

[0276] The structure variable of type s_type includes three member data types: 32-bit integer data type 'a', 32-bit integer data type 'b', and a 32-bit integer data type array 'c', where array 'c' contains 32 elements. Member data types 'a' and 'b' can only be accessed through pointer variables of type s_type, while the member data array 'c' can be accessed through pointer variables of type 32-bit integer data type.

[0277] It is understood that the above description of the access identifier is based only on the first access modifier and the second access modifier. In other embodiments, the access identifier may be in other forms, and this application does not limit this.

[0278] It is understood that the above description only uses the example of accessing the first member data through a variable of the composite data type identified by the first access modifier, i.e., accessing the first member data through a variable of the first type, to illustrate the technical solution in the embodiments of this application. It is understood that the first access method can also be accessing the first member data through a variable identified by the first access modifier, i.e., accessing the first member data through a first variable. For example, in some embodiments, if the access modifier corresponding to the above-mentioned 32-bit integer data type member data array c is the first access modifier, then the member data c or the elements in the member data c can only be accessed through s_type.c, or through the same pointer variable (e.g., ptrC). This application does not impose any restrictions on this.

[0279] S602: Convert the first source program into a first intermediate representation, wherein the first intermediate representation includes multiple instructions, and each instruction has a corresponding variable.

[0280] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0281] For example, suppose the source program includes the definition of the function foo:

[0282] UINT32 foo(s_type*ptrA,UINT32*ptrB){

[0283] ptrB[0] = ptrA->a;

[0284] ptrB[1] = ptrA->b;

[0285] …

[0286] }

[0287] The foo function includes two formal parameters: a pointer variable ptrA of type s_type and a pointer variable ptrB of type 32-bit integer data.

[0288] The intermediate representations of ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function can be found in the following form:

[0289] Load4B@ptrA;

[0290] Store4B@ptrB;

[0291] Load4B@ptrA+1;

[0292] Store4B@ptrB+1;

[0293] S603: Based on the access identifier of the member data of the composite data type in the first source program, determine the multiple first instructions that satisfy the first processing condition among the multiple memory access instructions of the first intermediate representation.

[0294] In some embodiments, the first processing condition may be: multiple first instructions are of the same type, the multiple first instructions are instructions that access first member data through a first access method, and the multiple first instructions are consecutive memory access instructions.

[0295] In some embodiments, if the composite data further includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between at least two first instructions, then the first processing condition may also be: the multiple first instructions are of the same type, the first instruction is a memory access instruction that accesses the first member data through the first access method, and the second instruction is a memory access instruction that does not access the second member data through the first access method.

[0296] In other embodiments, corresponding to the first instruction being a read operation instruction, the first processing condition may also be: the multiple first instructions are of the same type, the multiple first instructions are instructions that access the first member data through the first access method, the multiple first instructions are consecutive memory access instructions, and the types of the first instruction and the second instruction are different; or, the multiple first instructions are of the same type, the first instruction is a memory access instruction that accesses the first member data through the first access method, the second instruction is a memory access instruction that does not access the second member data through the first access method, and the types of the first instruction and the second instruction are different.

[0297] For example, if the first variable corresponding to the first instruction is used to access the first member data of the first composite data, the data type of the second variable corresponding to the second instruction among multiple first instructions is a different data type from the first composite data type, and the access identifier of the first member data accessed by the first instruction is a first access modifier, then the electronic device 100 can determine that multiple first instructions can be merged.

[0298] For example, taking the intermediate representation corresponding to the above-mentioned foo function as an example, the pointer variable ptrA corresponding to the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is used to access member data a and member data b in the s_type structure. The access identifiers of member data a and member data b are both the first access modifier. Furthermore, the data type of the pointer variable ptrA corresponding to the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is s_type. The data type of the pointer variable ptrB corresponding to the write operation instruction Store4B@ptrB between the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is 32-bit integer. Therefore, it can be determined that the memory space accessed by the write operation instruction Store4B@ptrB and the memory space accessed by the read operation instructions Load4B@ptrA and / or Load4B@ptrA+1 definitely do not overlap. Electronic device 100 can determine that the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1 can be merged, for example, the merged read operation instruction Load8B@ptrA can be obtained.

[0299] S604: Perform first processing on multiple first instructions and obtain the first object code file.

[0300] It is understood that the first processing includes, but is not limited to, merging and deleting processes. The processing methods of the first processing will be described in detail below, and will not be repeated here.

[0301] For details, please refer to the relevant description in S503 above, which will not be repeated here.

[0302] It is understood that the compilation method provided in this application can determine the first instruction that meets the first processing condition through the defined access identifier, and merge and / or delete the first instruction. This compilation method reduces the number of memory access instructions while lowering the risk of incorrect instruction merging and / or incorrect deletion, thereby reducing the risk of program runtime errors.

[0303] Example 2

[0304] This application also provides a compilation method that, based on the access identifiers of member data of various composite data types in the source program and the correlation identifiers of variables, determines the memory access instructions that meet the processing conditions, and merges and / or deletes the memory access instructions that meet the processing conditions, so as to further reduce the number of memory access instructions.

[0305] For example, Figure 7 A flowchart illustrating a compilation method based on access identifiers and relevance identifiers is shown according to an embodiment of this application. It can be understood that... Figure 7 The execution subject of the process shown is electronic device 100. For simplicity, the following description... Figure 7 The execution entity will not be described again when the process is shown.

[0306] like Figure 7 As shown, this process includes, but is not limited to:

[0307] S701: Obtain the first source program, wherein the first source program includes the correlation identifier of variables and the access identifier of member data of composite type data.

[0308] The correlation flag of a variable is used to indicate whether there exists another variable whose memory space intersects with that of the identified variable. In other words, the correlation flag of a variable is used to indicate whether there is any intersection between the memory spaces corresponding to multiple variables.

[0309] The overlap between the memory spaces corresponding to multiple variables includes, but is not limited to: the memory spaces corresponding to multiple variables completely overlapping; the memory spaces corresponding to multiple variables partially overlapping; and the memory spaces corresponding to multiple variables having an inclusion relationship, that is, the memory space corresponding to one variable contains the memory space corresponding to another variable. This application does not impose specific limitations in this regard.

[0310] In some embodiments, the correlation identifier can be the aforementioned first type of correlation identifier. Variables with the same first type of correlation identifier do not have an overlap in their memory spaces. The overlap relationship between the memory spaces corresponding to variables with different first type of correlation identifiers is unknown. That is, they may or may not have an overlap.

[0311] In other embodiments, the correlation identifier may also be the aforementioned second type of correlation identifier. The memory spaces corresponding to variables with the same second type of correlation identifier have unknown overlap relationships. That is, there may be an intersection or there may be no intersection. The memory spaces corresponding to variables with different second type of correlation identifiers do not have an intersection.

[0312] It can be understood that if the marked variable is a pointer variable, then the memory space corresponding to the variable is the memory space pointed to by the pointer variable. That is, the overlap of the memory spaces pointed to by the pointer variables can be determined by the correlation identifier of the pointer variables. If the marked variable is a non-pointer variable, then the memory space corresponding to the non-pointer variable is the memory space storing the non-pointer variable. That is, the overlap of the memory spaces storing the non-pointer variable can be determined by the correlation identifier of the non-pointer variable.

[0313] It is understood that the above description of the correlation identifier is based only on the first type of correlation identifier and the second type of correlation identifier. In other embodiments, the correlation identifier may be in other forms, and this application does not limit this.

[0314] In some embodiments, the access identifier for member data of composite data types is used to indicate the access method for the member data. The access identifier can be referenced as described above. Figure 5 The relevant descriptions in the document are not repeated here.

[0315] For example, suppose the source program includes the definition of the composite data type s_type:

[0316] typedef struct{

[0317] UINT32 a;

[0318] UINT32 b;

[0319] UINT32 c

[32] ;

[0320] }s_type;

[0321] The s_type structure variable includes a 32-bit integer data member a, a 32-bit integer data member b, and a 32-bit integer data member array c, which contains 32 elements.

[0322] Assume the source program includes the definition of function foo:

[0323] UINT32 foo(s_type*no_alias <0> ptrA,UINT32*no_alias <0> ptrB){

[0324] ptrB[0] = ptrA->a;

[0325] ptrB[1] = ptrA->b;

[0326] …

[0327] }

[0328] The `foo` function includes two formal parameters: a pointer variable `ptrA` of type `s_type` and a pointer variable `ptrB` of type 32-bit integer. The alias flag for pointer variable `ptrA` is the first-class alias flag `no_alias`. <0> The alias flag for the pointer variable ptrB is the first type of alias flag, no_alias. <0> .

[0329] S702: Convert the first source program into a first intermediate representation, wherein the first intermediate representation includes multiple instructions, and each instruction has a corresponding variable.

[0330] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0331] For example, taking the foo function in S701 above as an example, the intermediate representations of ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function can be referred to as follows:

[0332] Load4B@ptrA;

[0333] Store4B@ptrB;

[0334] Load4B@ptrA+1;

[0335] Store4B@ptrB+1.

[0336] S703: Based on the access identifier of the member data of the composite type data in the first source program, determine a plurality of first instructions that satisfy the first processing condition, and based on the correlation identifier of the variables in the first source program, determine a plurality of third instructions that satisfy the second processing condition.

[0337] In some embodiments, the electronic device 100 determines, based on the access identifier of the member data of the composite type data in the first source program, a plurality of first instructions among the plurality of instructions in the first intermediate representation that satisfy the first processing condition. The methods for determining the first processing condition and the first instructions can be specifically referred to the above. Figure 5 The relevant descriptions in the document are not repeated here.

[0338] In some embodiments, the electronic device 100 determines, based on the correlation identifier of variables in the first source program, a plurality of (at least two) third instructions among a plurality of instructions in the first intermediate representation that do not satisfy the first processing condition but satisfy the second processing condition.

[0339] In some embodiments, the second processing condition may be: multiple third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable among the multiple third instructions, and the storage space corresponding to the fourth variable does not overlap with the storage space corresponding to the third variable.

[0340] In other embodiments, the second processing condition may also be: the multiple third instructions are of the same type, the variables corresponding to the multiple third instructions are third variables, there is at least one fourth instruction among the multiple third instructions, and the memory space of the fourth variable corresponding to the fourth instruction does not overlap with the memory space of the third variables corresponding to the multiple third instructions.

[0341] In other embodiments, corresponding to the third instruction being a read operation instruction, the second processing condition may also be: multiple third instructions are of the same type, the variables corresponding to the multiple third instructions are third variables, there is at least one fourth instruction among the multiple third instructions, the type of the fourth instruction is different from the type of the third instruction, and the memory space of the fourth variable corresponding to the fourth instruction does not overlap with the memory space of the third variables corresponding to the multiple third instructions.

[0342] It is understandable that whether there is an intersection in the memory spaces of variables can be determined based on the correlation identifier of the variables. The correlation identifier can be a first-type correlation identifier or a second-type correlation identifier, which will not be elaborated here.

[0343] For example, taking the intermediate representation corresponding to the above-mentioned foo function as an example, there is a write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1. The member data 'a' accessed by the read operation instruction Load4B@ptrA and the member data 'b' accessed by the read operation instruction Load4B@ptrA+1 do not contain access modifiers. Therefore, the electronic device 100 cannot determine whether the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged based on the access identifiers of the member data of the composite data type.

[0344] In other embodiments, in cases where the first instruction that can be merged cannot be determined based on the access identifier of the member data of the composite type data, the electronic device 100 can further determine the third instruction that can be merged based on the correlation identifier of the variable.

[0345] Taking the intermediate representation corresponding to the foo function above as an example, the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA is the first type of correlation identifier no_alias. <0> The correlation identifier for the variable ptrA corresponding to the read operation instruction Load4B@ptrA+1 is the first type correlation identifier no_alias. <0> That is, the variable corresponding to the read operation instruction Load4B@ptrA and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first-type correlation identifier, and the memory space accessed by the read operation instruction Load4B@ptrA and the memory space accessed by the read operation instruction Load4B@ptrA+1 do not overlap.

[0346] There is a write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1. The dependency flag for the variable ptrB corresponding to the write operation instruction Store4B@ptrB is the first type dependency flag no_alias. <0> That is, the variable corresponding to the write operation instruction Store4B@ptrB, the variable corresponding to the read operation instruction Load4B@ptrA, and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first-type correlation identifier. If the memory space accessed by the write operation instruction Store4B@ptrB does not overlap with the memory space accessed by the read operation instruction Load4B@ptrA and / or the memory space accessed by the read operation instruction Load4B@ptrA+1, then the electronic device 100 can determine that the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged.

[0347] S704: Perform first processing on multiple first instructions and multiple third instructions respectively, and obtain the first object code file.

[0348] In some embodiments, the electronic device 100 may perform first processing on a plurality of first instructions and a plurality of third instructions respectively, and directly generate a first object code file.

[0349] In other embodiments, the electronic device 100 may also perform first processing on a plurality of first instructions and a plurality of third instructions respectively to obtain a second intermediate representation, and convert the second intermediate representation into target code to obtain a first target code file.

[0350] For example, if the source program corresponds to a high-level language and the target language file is machine language, the electronic device 100 generates an assembly instruction file based on the intermediate representation after the first processing, and then performs assembly, linking and other processes on the assembly instruction file to obtain an executable file, that is, an object code file.

[0351] For example, if the source language of the source program is assembly language and the target language file is machine language, then the electronic device 100 generates an executable file, i.e., an object code file, based on the intermediate representation after the first processing.

[0352] For example, if the source language of the source program is a high-level language and the target language is assembly language, then the electronic device 100 generates an assembly instruction file, i.e., a target code file, based on the intermediate representation after the first processing.

[0353] It is understandable that the first processing includes, but is not limited to, merging and deleting processes.

[0354] The following example, taking the memory access instruction that performs the first processing as a first instruction that meets the first processing conditions, will further explain the method and conditions of the first processing.

[0355] In some embodiments, corresponding to the first process being a merging process, the first processing condition further includes that the memory space accessed by the first instruction is a contiguous memory space. That is, the merging condition may be: the memory spaces accessed by multiple first instructions are contiguous, the multiple first instructions are of the same type, the memory space addresses accessed by the multiple first instructions are contiguous, and the multiple first instructions are instructions that access first member data through a first access method.

[0356] For example, assuming the virtual address corresponding to the first element A[0] of array A is VA0 and the virtual address corresponding to the second element A[1] of array A is VA1, then the read operation instructions Load1B@VA0 and Load1B@VA1 access contiguous memory space. The compiler can then merge the read operation instructions Load1B@VA0 and Load1B@VA1 into a new read operation instruction Load2B@VA0.

[0357] In other embodiments, if the composite data type also includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between at least two first instructions, corresponding to a merging process for the first processing, then the first processing condition further includes that the memory space accessed by the multiple first instructions corresponds to the same variable for the data stored therein. That is, the merging condition can be: the multiple first instructions are of the same type, the memory space accessed by the multiple first instructions corresponds to the same variable for the data stored therein, the first instruction is a memory access instruction that accesses the first member data through a first access method, and the second instruction is a memory access instruction that does not access the second member data through a first access method.

[0358] For example, assuming the virtual address corresponding to the first element A[0] of array A is VA0 and the virtual address corresponding to the third element A[2] of array A is VA2, then the data stored in the memory space accessed by the read operation instructions Load1B@VA0 and Load1B@VA2 corresponds to the same variable, namely, array A. The compiler can then merge the read operation instructions Load1B@VA0 and Load1B@VA2 into a new read operation instruction Load3B@VA0.

[0359] It is understood that, in the embodiments of this application, in addition to merging memory access instructions that access contiguous memory spaces, memory access instructions that access non-contiguous memory spaces but whose data corresponds to the same variable can also be merged, so that the number of memory access instructions can be further reduced, thereby improving the running efficiency of the application corresponding to the source program.

[0360] The merging process can be as follows: multiple first instructions that meet the first processing conditions are merged into a single fifth instruction, where the memory space accessed by the fifth instruction includes the memory spaces accessed by the multiple first instructions. For example, the memory space accessed by the fifth instruction is a set of memory spaces accessed by the multiple first instructions.

[0361] Alternatively, the merging process can be as follows: multiple first instructions that meet the processing conditions are merged into multiple sixth instructions, the memory space accessed by the sixth instructions includes the memory space accessed by multiple first instructions, and the number of sixth instructions is less than the number of first instructions.

[0362] In some embodiments, the first process corresponds to the deletion process. The first process may be: if there are M seventh instructions of the same type that access the first storage space in the first intermediate representation, and the storage space accessed by other instructions among the M seventh instructions does not intersect with the storage space accessed by the seventh instructions, delete N seventh instructions, where M is an integer greater than 1 and N is a positive integer less than M.

[0363] In other embodiments, if the type of the seventh instruction is a read operation instruction, and among the N seventh instructions there is an eighth instruction that reads data from the first storage space into the second storage space, and the second storage space is different from the storage space read by the MN seventh instructions (excluding the N seventh instructions) from the first storage space, then the address information of the second storage space in the ninth instruction that reads data from the second storage space can be replaced with the address information of the storage space read by any one of the MN seventh instructions from the first storage space. Here, the ninth instruction is the instruction in the first intermediate representation that follows the eighth instruction and precedes the next instruction that writes data to the second storage space, and the address information of the storage space includes the register name. Alternatively, the data read in the tenth instruction that reads data from the second storage space can be replaced with the data from the first storage space. Here, the tenth instruction is the instruction in the first intermediate representation that follows the eighth instruction and precedes the next instruction that writes data to the second storage space.

[0364] For example, instruction m is a read operation instruction that reads data from memory space P (first storage space) into register R0, and instruction n is a read operation instruction that reads data from memory space P into register R1 (second storage space). If instruction n is deleted, then in the first intermediate representation, register R1 in each instruction after instruction n and before the next instruction that writes data to register R1 needs to be replaced with register R0 to make the semantics in the first intermediate representation correct.

[0365] In other embodiments, if the first instruction is a write operation instruction, the deletion process may be: deleting N seventh instructions from the first M-1 seventh instructions out of M seventh instructions. That is, retaining the last executed seventh instruction among the multiple seventh instructions, and deleting at least one seventh instruction other than the last executed seventh instruction among the multiple seventh instructions.

[0366] In summary, the compilation method provided in this application can determine the first instruction that meets the merging condition based on the access identifiers of member data in variables of various composite data types in the source program, and determine the overlap relationship of the memory spaces corresponding to the variables through the correlation identifier, thereby determining the third instruction that meets the merging condition. Furthermore, by performing first processing on the first and third instructions, the number of memory access instructions is reduced.

[0367] Example 3

[0368] This application also provides a compilation method that, based on the correlation identifiers of variables in the source program, determines memory access instructions that meet the processing conditions, and merges and / or deletes the memory access instructions that meet the conditions to reduce the number of memory access instructions.

[0369] For example, Figure 8 A flowchart illustrating a compilation method based on variable relevance identification is shown according to an embodiment of this application. It can be understood that... Figure 8 The execution entity of the illustrated process is electronic device 100. Electronic device 100 can be a compilation device, a device including a compiler, or a device including a compilation unit. For simplicity, the following description... Figure 8 The execution entity will not be described again when the process is shown.

[0370] like Figure 8 As shown, this process includes, but is not limited to:

[0371] S801: Obtain the first source program, which includes the correlation identifiers of variables.

[0372] The dependency flag of a variable indicates whether there exists another variable whose memory space intersects with that of the variable being flagged. In other words, the dependency flag indicates whether there is any overlap between the memory spaces corresponding to multiple variables. The original language corresponding to the first source program includes, but is not limited to, high-level languages ​​and assembly languages.

[0373] In some embodiments, the correlation identifier can be the aforementioned first type of correlation identifier. Variables with the same first type of correlation identifier do not have an overlap in their memory spaces. The overlap relationship between the memory spaces corresponding to variables with different first type of correlation identifiers is unknown. That is, they may or may not have an overlap.

[0374] In other embodiments, the correlation identifier may also be the aforementioned second type of correlation identifier. The memory spaces corresponding to variables with the same second type of correlation identifier have unknown overlap relationships. That is, there may be an intersection or there may be no intersection. The memory spaces corresponding to variables with different second type of correlation identifiers do not have an intersection.

[0375] It is understood that the above description of the correlation identifier is based only on the first type of correlation identifier and the second type of correlation identifier. In other embodiments, the correlation identifier may be in other forms, and this application does not limit this.

[0376] S802: Convert the first source program into a first intermediate representation, wherein the first intermediate representation includes multiple instructions, and each instruction has a corresponding variable.

[0377] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0378] S803: Based on the correlation identifier of variables in the first source program, determine the first instructions that satisfy the first processing condition among the multiple instructions in the first intermediate representation.

[0379] In some embodiments, the first processing condition may be: multiple first instructions are of the same type, the variables corresponding to the multiple first instructions are first variables, and the multiple first instructions are consecutive memory access instructions.

[0380] In other embodiments, the first processing condition may also be: multiple first instructions are of the same type, the variables corresponding to the multiple first instructions are first variables, there is at least one second instruction among the multiple first instructions, and the memory space of the second variable corresponding to the second instruction does not overlap with the memory space of the first variable corresponding to the multiple first instructions.

[0381] In other embodiments, corresponding to the first instruction being a read operation instruction, the first processing condition may also be: multiple first instructions are of the same type, the variables corresponding to the multiple first instructions are first variables, there is at least one second instruction among the multiple first instructions, the type of the second instruction is different from the type of the first instruction, and the memory space of the second variable corresponding to the second instruction does not overlap with the memory space of the first variables corresponding to the multiple first instructions.

[0382] It is understandable that whether there is an intersection in the memory spaces of variables can be determined based on the correlation identifier of the variables. The correlation identifier can be a first-type correlation identifier or a second-type correlation identifier, which will not be elaborated here.

[0383] S804: Performs first processing on multiple first instructions to obtain the first object code file.

[0384] In some embodiments, the electronic device 100 can directly generate a first object code file based on an intermediate representation.

[0385] In other embodiments, the electronic device 100 may also perform a first processing on multiple first instructions to obtain a second intermediate representation, and convert the second intermediate representation into target code to obtain a first target code file.

[0386] It is understandable that the first processing includes, but is not limited to, merging and deleting processes.

[0387] In some embodiments, corresponding to the first processing being a merging process, the first processing condition further includes that the memory space accessed by the first instruction is a contiguous memory space. That is, the merging condition may be: multiple first instructions are of the same type, the memory spaces accessed by the multiple first instructions are contiguous, there is at least one second instruction among the multiple first instructions, the type of the second instruction is different from that of the first instruction, and the memory space of the second variable corresponding to the second instruction does not overlap with the memory spaces of the first variables corresponding to the multiple first instructions.

[0388] In other embodiments, corresponding to the first process being a merging process, the first processing condition further includes that the data stored in the memory space accessed by multiple first instructions corresponds to the same variable. That is, the merging condition can be: multiple first instructions are of the same type, the data stored in the memory space accessed by multiple first instructions corresponds to the same variable, there is at least one second instruction among the multiple first instructions, the type of the second instruction is different from that of the first instruction, and the memory space of the second variable corresponding to the second instruction does not overlap with the memory space of the first variables corresponding to the multiple first instructions.

[0389] The merging process can be as follows: multiple first instructions that meet the processing conditions are merged into a single third instruction, where the memory space accessed by the third instruction includes the memory spaces accessed by the multiple first instructions. For example, the memory space accessed by the third instruction is a set of memory spaces accessed by the multiple first instructions.

[0390] Alternatively, the merging process can be as follows: multiple first instructions that meet the processing conditions are merged into multiple fourth instructions, the memory space accessed by the fourth instructions includes the memory space accessed by multiple first instructions, and the number of fourth instructions is less than the number of first instructions.

[0391] In other embodiments, corresponding to the first process being a deletion process, the processing condition further includes that the memory spaces accessed by the first instructions are the same memory spaces. That is, the merging condition can be: M first instructions are of the same type, the M first instructions access the same memory spaces, there is at least one second instruction among the M first instructions, the type of the second instruction is different from the first instruction, and the memory space of the second variable corresponding to the second instruction does not overlap with the memory spaces of the first variables corresponding to the multiple first instructions. Here, M is an integer greater than 1.

[0392] The deletion process can be: deleting N first instructions, where N is a positive integer less than M.

[0393] In some embodiments, if the first instruction is a read operation instruction and the second instruction is a write operation instruction, the deletion process may be as follows: among the N first instructions, there is a fifth instruction that reads data from the first storage space into the second storage space, and the second storage space is different from the storage space read by the data from the first storage space by the MN first instructions other than the N first instructions; the address information of the second storage space in the sixth instruction that reads data from the second storage space is replaced with the address information of the storage space read by any one of the MN first instructions, wherein the sixth instruction is the instruction in the first intermediate representation that is after the fifth instruction and before the next instruction that writes data to the second storage space, and the address information of the storage space includes the register name.

[0394] In some embodiments, if the first instruction is a write operation instruction and the second instruction is a read operation instruction, the deletion process can be: deleting N first instructions from the first M-1 first instructions out of M first instructions. That is, retaining the last executed first instruction among the multiple first instructions, and deleting at least one first instruction other than the last executed first instruction among the multiple first instructions.

[0395] It is understood that the number of memory access instructions (e.g., the first instruction) in the first object code file is less than the number of memory access instructions (e.g., the first instruction) in the second object code file, and the second object code file has not undergone the first processing.

[0396] It is understood that the compilation method provided in this application can determine the overlapping relationship of memory spaces corresponding to variables through defined correlation identifiers, thereby identifying the first instruction that meets the merging conditions, and merging and / or deleting the first instruction. This compilation method reduces the number of memory access instructions while reducing the risk of instruction error merging, thereby reducing the risk of program runtime errors.

[0397] Example 4

[0398] This application also provides a compilation method. In the case that the correlation identifier of the variable in the aforementioned embodiment 3 does not indicate that the memory space corresponding to the variable must not overlap, the first instruction that meets the merging condition is determined based on the access identifier of the member data in the variables of various composite data types in the source program, and the first instruction is merged to further reduce the number of memory access instructions.

[0399] For example, Figure 9 A flowchart illustrating a compilation method based on relevance identifiers and access identifiers is shown according to an embodiment of this application. It can be understood that... Figure 9 The process shown is executed by electronic device 100. For simplicity, the following description... Figure 9 The execution entity will not be described again when the process is shown.

[0400] like Figure 9 As shown, the process includes, but is not limited to, the following steps:

[0401] S901: Obtain the first source program, wherein the first source program includes the correlation identifier of variables and the access identifier of member data of composite type data.

[0402] Specifically, the correlation identifiers for variables and the access identifiers for member data of composite data types can be referenced above. Figure 5 The relevant descriptions in S501 are not repeated here.

[0403] S902: Convert the first source program into a first intermediate representation, wherein the first intermediate representation includes multiple instructions, and each instruction has a corresponding variable.

[0404] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0405] For example, suppose the source program includes the definition of the function foo:

[0406] UINT32 foo(s_type*no_alias <0> ptrA,UINT32*no_alias <1> ptrB){

[0407] ptrB[0] = ptrA->a;

[0408] ptrB[1] = ptrA->b;

[0409] …

[0410] }

[0411] The `foo` function includes two formal parameters: a pointer variable `ptrA` of type `s_type` and a pointer variable `ptrB` of type 32-bit integer. The alias flag for pointer variable `ptrA` is the first-class alias flag `no_alias`. <0> The alias flag for the pointer variable ptrB is the first type of alias flag, no_alias. <1> .

[0412] The intermediate representations of ptrB[0] = ptrA->a and ptrB[1] = ptrA->b in the foo function can be found in the following form:

[0413] Load4B@ptrA;

[0414] Store4B@ptrB;

[0415] Load4B@ptrA+1;

[0416] Store4B@ptrB+1;

[0417] S903: Based on the correlation identifier of variables in the first source program, determine a plurality of first instructions that satisfy the first processing condition, and based on the access identifier of member data of composite type data in the first source program, determine a plurality of third instructions that satisfy the second processing condition.

[0418] In some embodiments, the electronic device 100 determines, based on the correlation identifiers of variables in the first source program, a plurality of first instructions among the plurality of instructions in the first intermediate representation that satisfy the first processing condition. The methods for determining the first processing condition and the first instructions can be specifically referred to the above. Figure 8 The relevant descriptions in the document are not repeated here.

[0419] In some embodiments, the electronic device 100 determines, based on the access identifier of the member data of the composite type data in the first source program, a plurality of (at least two) third instructions among the plurality of instructions of the first intermediate representation that do not satisfy the first processing condition but satisfy the second processing condition.

[0420] In some embodiments, the second processing condition may be: multiple third instructions are of the same type, the multiple third instructions are instructions that access the first member data through the first access method, and the multiple third instructions are consecutive memory access instructions.

[0421] In other embodiments, if the composite data also includes second member data, and the second member data does not include the first access identifier, and there is at least one second instruction between at least two first instructions, then the second processing condition may be: the first instruction is an instruction that accesses the first member data through the first access method, and at least two first instructions are of the same type, and the second instruction is a memory access instruction that does not access the second member data through the first access method.

[0422] For example, in some embodiments, the electronic device 100 determines, based on the correlation identifier of the variable, whether there is a first instruction that can be merged among the multiple instructions of the first intermediate representation.

[0423] For example, taking the intermediate representation corresponding to the above foo function as an example, the correlation identifier of the variable ptrA corresponding to the read operation instruction Load4B@ptrA is the first type of correlation identifier no_alias. <0> The correlation identifier for the variable ptrA corresponding to the read operation instruction Load4B@ptrA+1 is the first type correlation identifier no_alias. <0> That is, the variable corresponding to the read operation instruction Load4B@ptrA and the variable corresponding to the read operation instruction Load4B@ptrA+1 have the same first-type correlation identifier, and the memory space accessed by the read operation instruction Load4B@ptrA and the memory space accessed by the read operation instruction Load4B@ptrA+1 do not overlap.

[0424] There is a write operation instruction Store4B@ptrB between the read operation instruction Load4B@ptrA and the read operation instruction Load4B@ptrA+1. The dependency flag for the variable ptrB corresponding to the write operation instruction Store4B@ptrB is the first type dependency flag no_alias. <1> That is, the variable corresponding to the write operation instruction Store4B@ptrB, the variable corresponding to the read operation instruction Load4B@ptrA, and the variable corresponding to the read operation instruction Load4B@ptrA+1 have different first-type correlation identifiers. The memory space accessed by the write operation instruction Store4B@ptrB may overlap with the memory space accessed by the read operation instruction Load4B@ptrA and / or the memory space accessed by the read operation instruction Load4B@ptrA+1. Therefore, the electronic device 100 cannot determine whether the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged based on the correlation identifiers of the variables.

[0425] It is understandable that if the correlation identifier of the variable ptrB corresponding to the write operation instruction Store4B@ptrB is also the first type of correlation identifier no_alias... <0> This indicates that the memory space accessed by the write operation instruction Store4B@ptrB, the memory space accessed by the read operation instruction Load4B@ptrA, and the memory space accessed by the read operation instruction Load4B@ptrA+1 do not overlap. Therefore, it can be determined that the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged.

[0426] In other embodiments, in cases where the first instruction that can be merged cannot be determined based on the correlation identifier of the variables, the electronic device 100 can further determine the third instruction that can be merged based on the access identifier of the member data of the composite type data.

[0427] For example, in some embodiments, if the third variable corresponding to the third instruction is used to access the member data of the variable of the first composite data type, the data type of the fourth variable corresponding to the fourth instruction among multiple third instructions is a different data type from the first composite data type, and the access identifier of the first member data accessed by the third instruction is a first access modifier, then the electronic device 100 can determine that multiple third instructions can be merged.

[0428] For example, still using the intermediate representation corresponding to the above-mentioned foo function as an example, electronic device 100 cannot determine whether the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged based on the variable correlation identifier. The pointer variable ptrA corresponding to the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is used to access member data a and member data b in a structure of type s_type. The access identifiers for member data a and member data b are both the first access modifier. Furthermore, the data type of the pointer variable ptrA corresponding to the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is of type s_type. The data type of the pointer variable ptrB corresponding to the write operation instruction Store4B@ptrB between the read operation instructions Load4B@ptrA and Load4B@ptrA+1 is a 32-bit integer. Therefore, it can be determined that the memory space accessed by the write operation instruction Store4B@ptrB does not overlap with the memory space accessed by the read operation instruction Load4B@ptrA and / or the read operation instruction Load4B@ptrA+1. Electronic device 100 can determine that the read operation instructions Load4B@ptrA and Load4B@ptrA+1 can be merged; for example, a merged read operation instruction Load8B@ptrA can be obtained.

[0429] It is understood that the above description only uses the first type of correlation identifier for variables as an example. In other embodiments, the correlation identifier for variables may also be a second type of correlation identifier or other forms of correlation identifier. This application does not impose specific limitations on this.

[0430] S904: Perform first processing on multiple first instructions and multiple third instructions respectively, and obtain the first target code file.

[0431] In some embodiments, the electronic device 100 can directly generate a first object code file based on an intermediate representation.

[0432] In other embodiments, the electronic device 100 may also merge multiple first instructions to obtain a second intermediate representation, and convert the second intermediate representation into target code to obtain a first target code file.

[0433] It is understood that the above description only uses the merging of memory access instructions that meet the merging conditions as an example to illustrate the compilation method provided in this application. In other embodiments, the compilation method provided in this application can also delete memory access instructions that meet the deletion conditions. The deletion conditions may be: multiple first instructions of the same type, multiple first instructions accessing the same memory space, multiple third instructions accessing first member data through a first access method, and multiple third instructions being consecutive memory access instructions; or, multiple first instructions of the same type, multiple first instructions accessing the same memory space, first instructions accessing first member data through a first access method, at least two first instructions of the same type, and the second instruction accessing second member data without using the first access method. The specific method for performing the deletion process can be referred to the above. Figure 7 The relevant descriptions regarding deletion processing are not repeated here. In other embodiments, the compilation method provided in this application can also perform first processing on other first instructions that satisfy the first condition, and this application does not impose any limitations on this.

[0434] In summary, the compilation method provided in this application can determine the overlapping relationship of memory spaces corresponding to variables through defined dependency identifiers, thereby identifying the first instruction that meets the merging conditions and merging the first instruction, reducing the risk of erroneous merging and thus reducing the risk of program execution errors. Furthermore, even when the dependency identifier of a variable does not indicate that the memory spaces corresponding to the variable definitely do not overlap, the first instruction that meets the merging conditions is determined based on the access identifiers of member data in variables of various composite data types in the source program, and the first instruction is merged to further reduce the number of memory access instructions.

[0435] It is understood that the multiple instructions in the above embodiments can be multiple memory access instructions; the number of multiple first instructions is an integer greater than 1, that is, at least two first instructions; the number of multiple third instructions is an integer greater than 1, that is, at least two third instructions, which will not be elaborated in this application.

[0436] It is understood that in the above embodiments, the correlation identifier is used to indicate the overlapping relationship of the addresses corresponding to the variables (that is, the correlation identifier is used to indicate whether the memory spaces corresponding to the variables overlap), and the first access identifier is used to indicate the overlapping relationship between the memory space corresponding to the target variable modified by the first access identifier and the memory space corresponding to the variables other than the target variable.

[0437] In other embodiments, before the source program is compiled, the developer may also mark the member data of variables of various composite data types (e.g., structure variables) and / or pointer variables pointing to memory spaces used to store member data of variables of composite data types (e.g., structure variables) in the source program with dependency information and / or access marking. The dependency information includes at least one parameter indicating whether the memory spaces corresponding to at least two variables do not overlap at least partially. The memory space corresponding to the target variable modified by the first access marker does not overlap with the memory spaces corresponding to variables other than the target variable.

[0438] Therefore, during the compilation phase, the compiler can merge memory access instructions corresponding to variables whose memory spaces do not overlap, based on dependency information or the first access identifier, to reduce the number of memory access instructions. Alternatively, during the compilation phase, the compiler can combine dependency information and the access identifier to determine whether memory access instructions corresponding to variables whose memory spaces do not overlap at least partially, as indicated by the dependency information, can be merged, thereby reducing the number of memory access instructions.

[0439] In some embodiments, at least one parameter of the correlation information includes a first parameter and a second parameter, wherein the first parameter is used to indicate whether there are at least two variables whose storage spaces do not overlap, and the second parameter is used to indicate whether the storage spaces corresponding to at least two overlapping variables are partially non-overlapping.

[0440] For example, variables whose corresponding memory spaces definitely do not overlap can be labeled with the same first parameter, or variables whose corresponding memory spaces may overlap can be labeled with different first parameters.

[0441] Furthermore, variables whose memory spaces may overlap are labeled with a second parameter. For example, variables whose corresponding memory spaces partially do not overlap are labeled with the same second parameter, or variables whose corresponding memory spaces partially do not overlap are labeled with different second parameters.

[0442] That is, the storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and the same second parameter partially do not overlap; or, the storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters and the same second parameter partially do not overlap; or, the storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and different second parameters partially do not overlap; or, the storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters and different second parameters partially do not overlap.

[0443] It is understandable that the semantics and function of the first parameter of the relevance information are consistent with the semantics and function of the aforementioned relevance identifier. If the marked variable is a pointer variable, then the memory space corresponding to the variable is the memory space pointed to by the pointer variable; that is, the overlapping relationship of the memory spaces pointed to by the pointer variable can be determined through the relevance information of the pointer variable. If the marked variable is a non-pointer variable, then the memory space corresponding to the non-pointer variable is the memory space storing the non-pointer variable; that is, the overlapping relationship of the memory spaces storing the non-pointer variable can be determined through the relevance information of the non-pointer variable.

[0444] For example, if the memory space corresponding to pointer variable ptra does not partially overlap with the memory space corresponding to pointer variable ptrb, the memory space corresponding to pointer variable ptrc does not overlap with the memory space corresponding to pointer variable ptra, pointer variable ptrb, and pointer variable ptrd, but the memory space corresponding to pointer variable ptrd may overlap with the memory spaces corresponding to pointer variables ptra and ptrb.

[0445] Pointer variables ptra, ptrb, ptrc, and ptrd can be defined in the following ways:

[0446] stra*_alias_group_<0,0>ptra,

[0447] strb*_alias_group_<0,0>ptrb,

[0448] strc*_alias_group_ <1> ptrc,

[0449] strd*_alias_group_<0,1>ptrd.

[0450] Among them, the first parameter of the correlation information of pointer variable ptra is 0, and the second parameter is also 0; the first parameter of the correlation information of pointer variable ptrb is 0, and the second parameter is also 0; the first parameter of the correlation information of pointer variable ptrc is 1; and the first parameter of the correlation information of pointer variable ptrd is 0, and the second parameter is 1.

[0451] It is understandable that the first parameter of pointer variables ptra, ptrb, and ptrd is 0 (they have the same first parameter), and the first parameter of pointer variable ptrc is 1. Therefore, the memory spaces corresponding to pointer variables ptra, ptrb, and ptrd may overlap, while the memory spaces corresponding to pointer variables ptrc do not overlap with the memory spaces corresponding to pointer variables ptra, ptrb, and ptrd.

[0452] Furthermore, the second parameter of both pointer variables ptra and ptrb is 0 (they have the same second parameter), while the second parameter of pointer variable ptrd is 1. Therefore, the memory space corresponding to pointer variable ptra and pointer variable ptrb do not overlap in some aspects.

[0453] It is understood that the above description only uses the example of the correlation information including two parameters, the first parameter and the second parameter. In other embodiments, the correlation information may include more or fewer parameters, as long as the correlation information satisfies the function of indicating whether the memory spaces corresponding to at least two variables do not overlap at least partially. This application does not impose a specific limit on the number of parameters of the correlation information.

[0454] For example, in some other embodiments, at least one parameter of the correlation information includes a third parameter, wherein the third parameter is used to indicate whether the memory spaces corresponding to at least two variables do not overlap at least partially.

[0455] For example, variables whose corresponding memory spaces have at least partial non-overlapping (non-overlapping or partially non-overlapping) can be labeled with the same third parameter, or variables whose corresponding memory spaces have at least partial non-overlapping can be labeled with different third parameters.

[0456] That is, the storage spaces corresponding to variables with different third parameters do not overlap at least partially; or, the storage spaces corresponding to variables with the same third parameter do not overlap at least partially.

[0457] For example, if the memory space corresponding to the pointer variable ptrf does not overlap with the memory space corresponding to the pointer variable ptrf at least partially, the memory space corresponding to the pointer variable ptrg may overlap with the memory space corresponding to the pointer variable ptrf, and the memory space corresponding to the pointer variable ptrg does not overlap with the memory space corresponding to the pointer variable ptrf at least partially.

[0458] Pointer variables ptrf, ptrg, and ptrg can be defined in the following ways:

[0459] stre*_alias_group_ <0> ptre,

[0460] strf*_alias_group_ <1> ptrf,

[0461] strg*_alias_group_ <0> ptrg.

[0462] It can be understood that the third parameter of pointer variable ptrf is 1, the third parameter of pointer variable ptrg is 0, and pointer variables ptrf and ptrf have different third parameters. Therefore, the memory space corresponding to pointer variable ptrf and pointer variable ptrf do not overlap at least partially.

[0463] It is understood that the above is only an example illustrative description using the first, second, and third parameters being 0 or 1. In other embodiments, the values ​​of the first, second, and third parameters can also be other values, as long as the existence of memory spaces corresponding to the indicator variables is satisfied as long as they do not overlap to some extent. This application does not limit the specific values ​​of the first, second, and third parameters.

[0464] For example, if the memory space corresponding to the pointer variable ptrh does not overlap with the memory spaces corresponding to the pointer variables ptra, ptrb, ptrc, and ptrd mentioned above.

[0465] The pointer variable ptrh can then be defined in the following way:

[0466] strh*_alias_group_ <2> ptrh.

[0467] It can be understood that the first parameter of pointer variables ptra, ptrb, and ptrd is 0 (they have the same first parameter), the first parameter of pointer variable ptrc is 1, and the first parameter of pointer variable ptrh is 2. That is, the first parameter of pointer variable ptrh is different from the first parameters of pointer variables ptra, ptrb, ptrc, and ptrd, and the memory space corresponding to pointer variable ptrh does not overlap with the memory spaces corresponding to pointer variables ptra, ptrb, ptrc, and ptrd.

[0468] It is understood that, since the second parameter is used to indicate whether the storage spaces corresponding to at least two overlapping variables partially do not overlap, in the above example, the correlation information of variables without the same first parameter only shows one parameter (i.e., the first parameter). In practical applications, the second parameter can also be null or other values, and this application does not impose any restrictions on this. It should be understood that, since the first parameter is used to indicate whether there are at least two variables whose memory spaces do not overlap, and the second parameter is used to indicate whether the memory spaces corresponding to at least two overlapping variables partially do not overlap, the second parameter of the at least two variables is an invalid parameter if the first parameter has already indicated that the memory spaces of at least two variables do not overlap.

[0469] As mentioned earlier, memory access instructions that meet the conditions can undergo a first processing step (merging or deletion). This step involves either no other memory access instructions among those that meet the conditions, or the memory spaces corresponding to other memory access instructions among those that meet the conditions do not overlap with the memory spaces corresponding to those instructions. This reduces the number of memory access instructions and lowers the risk of incorrect instruction merging.

[0470] Therefore, embodiments of this application also provide a compilation method, which includes: obtaining a first source program, wherein the first source program includes variable correlation information and a first access identifier; determining a first target code file based on the first source program, and the correlation information and / or the first access identifier in the first source program, wherein the number of memory access instructions in the first target code file is less than the number of memory access instructions in a second target code file, and the second target code file is a target code file not determined based on the correlation information and / or the first access identifier in the first source program.

[0471] This reduces the number of memory access instructions in the target code file, thus improving the execution efficiency of the target code file.

[0472] The following is a detailed description of the compilation method for determining the first object code file based on the correlation information and / or the first access identifier in the first source program, as provided in the embodiments of this application.

[0473] For example, Figure 10 A flowchart illustrating a compilation method based on access identifiers is shown according to an embodiment of this application. It can be understood that... Figure 10 The execution entity of the illustrated process is electronic device 100. Electronic device 100 can be a compilation device, a device including a compiler, or a device including a compilation unit. For simplicity, the following description... Figure 10 The execution entity will not be described again when the process is shown.

[0474] like Figure 10As shown, this process includes, but is not limited to:

[0475] S1001: Obtain the first source program, wherein the first source program includes variable correlation information and a first access identifier.

[0476] The correlation information includes at least one parameter, which indicates whether the memory spaces corresponding to at least two variables do not overlap at least partially. For example, the correlation information can be in the form _alias_group_<first parameter, second parameter>, which includes the first and second parameters, or it can be in the form _alias_group_<third parameter>, which includes the third parameter.

[0477] The first access identifier can be one of the aforementioned first access modifiers (e.g., _unique_). The memory space corresponding to the target variable modified by the first access identifier does not overlap with the memory space corresponding to variables other than the target variable.

[0478] In some embodiments, a variable modified by a first access modifier can only be accessed through a first access method. For example, a target variable modified by a first access modifier can only access the storage space corresponding to the target variable through the target variable itself.

[0479] Specifically, the meaning and function of the relevance information and the first access identifier can be referred to the above description of the relevance information and the first access identifier, and will not be repeated here.

[0480] For example, suppose the first source program includes the definition of the composite data type stra:

[0481] typedef struct{

[0482] _unique_UINT32 name;

[0483] _unique_UINT32 id;

[0484] strb list

[32] ;

[0485] }stra;

[0486] The `stra` type structure variable includes a 32-bit integer member data `name`, a 32-bit integer member data `id`, and a `strb` type member data array `list`, which contains 32 elements. The member data `name` and `id` are modified with `_unique_`.

[0487] Assume the first source code also includes the definition of the function saveinfo:

[0488] UINT32 saveinfo(stra*_alias group<0,0>ptra,

[0489] strb*_alias group<0,0>ptrb,

[0490] strc*_alias group <1> ptrc,

[0491] strd*_alias group<0,1>ptrd){

[0492] UINT32 name = ptra->name;

[0493] ptrb[name]->a = 0xffff;

[0494] / *Do something with name* /

[0495] UINT32 id = ptra->id;

[0496] }

[0497] The saveinfo function includes four formal parameters: a pointer variable ptra of type stra, a pointer variable ptrb of type strb, a pointer variable ptrc of type strc, and a pointer variable ptrd of type strd.

[0498] It is understandable that pointer variables `ptra` and `ptrb` share the same first and second parameters, and the memory spaces corresponding to pointer variables `a` and `b` at least partially overlap. However, variables `name` and `id` are modified with `_unique_`, meaning their memory spaces do not overlap with the memory spaces of other variables (such as the array `list`). Furthermore, the memory spaces corresponding to variables `name` and `id` are accessed only through a pointer variable of type `stra` (pointer variable `ptra`), meaning the memory space accessed through pointer variable `ptra` does not overlap with the memory space accessed through other pointer variables.

[0499] S1002: Based on the first source program, and the related information in the first source program and / or the first access identifier in the first source program, determine the first object code file.

[0500] The number of memory access instructions in the first object code file is less than the number of memory access instructions in the second object code file, and the second object code file is an object code file that was not determined based on the correlation information and / or the first access identifier in the first source program.

[0501] In some embodiments, the electronic device 100 generates a first intermediate representation based on a first source program, wherein the first intermediate representation includes a plurality of instructions, and a plurality of memory access instructions are determined from the plurality of instructions in the first intermediate representation.

[0502] The forms of the first intermediate representation include, but are not limited to: suffix representation, graph representation, three-address code, underlying virtual machine intermediate representation, assembly code representation, etc.

[0503] For example, taking the saveinfo function in S1001 above as an example, the intermediate representation of UINT32 name = ptra->name and UINT32 id = ptra->id in the saveinfo function can be referred to as follows:

[0504] Load4B@ptra+0;

[0505] Store4B@ptrb+name+offset_a;

[0506] Load4B@ptra+4.

[0507] In some embodiments, the electronic device 100 determines at least two first instructions that satisfy the first processing condition from a plurality of memory access instructions corresponding to the first source program based on the correlation information in the first source program and the first access identifier in the first source program; performs first processing on the at least two first instructions, and obtains a first object code file.

[0508] The first processing condition includes: at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable between the at least two first instructions, the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially, the first variable is modified by a first access identifier, and the at least two first instructions are of the same type.

[0509] It can be understood that if the first variable is a pointer variable, then the first variable is modified by the first access identifier, which marks the member data of the composite type data corresponding to the first variable. That is, the member data of the composite type data corresponding to the first variable includes the first access identifier. For example, taking the saveinfo function mentioned above, assuming the first variable is the pointer variable ptra, then the member data name of the composite type data corresponding to the first variable includes the first access identifier _unique_.

[0510] If the first variable is a non-pointer variable, then the first variable is modified by the first access identifier as follows: the first variable is marked by the first access identifier, where the first variable is a member data of a composite type. For example, taking the saveinfo function above as an example, assuming the first variable is the member data id of a composite type, then the member data id of the composite type corresponding to the first variable includes the first access identifier _unique_.

[0511] For example, taking the intermediate representation corresponding to the saveinfo function mentioned above as an example, since the memory space corresponding to the pointer variable ptra and the memory space corresponding to the pointer variable ptrb have some non-overlapping areas, that is, the memory space corresponding to the pointer variable ptra and the memory space corresponding to the pointer variable ptrb have some overlapping areas.

[0512] There may be instructions that access memory space through pointer variable ptra, such as Load4B@ptra+0 and Load4B@ptra+4, which may modify data in the overlapping area (e.g., the instruction Store4B@ptrb+name+offset_a mentioned above). If multiple instructions that access memory space through pointer variable ptra are merged, erroneous merging may occur.

[0513] The pointer variable `ptra` corresponding to the read operation instructions `Load4B@ptra+0` and `Load4B@ptra+4` is used to access the member data `name` and member data `id` in a structure of type `s_type`. Both member data `name` and member data `id` are modified by a first access identifier. That is, the memory space accessed by the pointer variable `ptra` cannot be accessed based on any other variable besides `ptra`. Therefore, there will be no situation where data in the memory space accessed by the pointer variable `ptra` is modified through other variables (such as the pointer variable `ptrb`). Thus, the electronic device 100 can determine that the read operation instructions `Load4B@ptra+0` and `Load4B@ptra+4` can be merged; for example, the merged read operation instruction `Load8B@ptra+0` can be obtained.

[0514] In some embodiments, the type corresponding to the first instruction is a read operation instruction, and the first processing condition further includes at least one of the following: the first instruction is a read operation instruction and the second instruction is a write operation instruction; the first instruction is a write operation instruction and the second instruction is a read operation instruction.

[0515] In some embodiments, the electronic device 100 performs a first processing on at least two first instructions to obtain a second intermediate representation, wherein the number of first instructions in the second intermediate representation is less than the number of first instructions in the first intermediate representation; and generates a first object code file based on the second intermediate representation.

[0516] It is understood that the first process includes at least one of the following: merging process and deletion process.

[0517] In some embodiments, the first processing includes a merging process, and the first processing condition further includes: the storage space accessed by each first instruction is a contiguous storage space, or the data stored in the storage space accessed by each first instruction corresponds to the same variable.

[0518] Specifically, please refer to the aforementioned description of the first process; this application will not repeat it here.

[0519] In other embodiments, the electronic device 100 determines at least two third instructions that satisfy the second processing condition from a plurality of memory access instructions corresponding to the first source program based on the first access identifier in the first source program; performs first processing on the at least two third instructions to obtain a first target code file; wherein the second processing condition includes: at least two third instructions correspond to third variables, the third variables are modified by the first access identifier, and at least two third instructions are of the same type.

[0520] Specifically, please refer to the above. Figure 6 The relevant descriptions in the illustrated process, and the corresponding second processing conditions Figure 6 The first condition and the third instruction in the illustrated process can correspond to Figure 6 The first instruction in the process shown is not described in detail here.

[0521] In other embodiments, the electronic device 100 determines at least two fifth instructions that satisfy a third processing condition from a plurality of memory access instructions corresponding to the first source program based on the correlation information in the first source program; performs first processing on the at least two fifth instructions to obtain a first target code file; wherein, the third processing condition includes: at least two fifth instructions correspond to fifth variables, there is at least one sixth instruction corresponding to a sixth variable between the at least two fifth instructions, the storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable, and the at least two fifth instructions are of the same type.

[0522] For example, suppose the first source program also includes the definition of the function instr:

[0523]

[0524] The instr function includes three formal parameters: aa (a type of sa), bb (sb type of bb), and cc (sc type of cc).

[0525] It is understandable that pointer variables aa and bb have different first parameters, pointer variables bb and cc have different first parameters, and the memory space corresponding to pointer variable bb does not overlap with the memory space corresponding to pointer variables aa and cc.

[0526] In the `instr` function, the intermediate representations of `char len = bb->length`, `aa->a = 0xff`, `aa->b = 0`, and `bb->c += 1` can be referenced as follows:

[0527] Load1B@bb;

[0528] Store1B@aa;

[0529] Store1B@aa+1;

[0530] Load1B@bb+1;

[0531] Store1B@bb+1.

[0532] It is understandable that there are write operations Store1B@aa and Store1B@aa+1 between the read operation instruction Load1B@bb ​​and the read operation instruction Load1B@bb+1. Since the memory space corresponding to the pointer variable bb does not overlap with the memory space corresponding to the pointer variable aa, the write operation instruction between the read operation instructions Load1B@bb ​​and Load1B@bb+1 will not access the memory space accessed by the read operation instructions Load1B@bb ​​and Load1B@bb+1. Therefore, merging the read operation instructions Load1B@bb ​​and Load1B@bb+1 will not result in a merging error. The electronic device 100 can determine that the read operation instructions Load1B@bb ​​and Load1B@bb+1 can be merged; for example, the merged read operation instruction Load2B@bb can be obtained.

[0533] It is understandable that the method and conditions for determining memory access instructions that meet the processing conditions based solely on the first parameter of the correlation information are consistent with the aforementioned method and conditions for determining memory access instructions that meet the processing conditions based solely on the correlation identifier.

[0534] It is understood that the above description only uses the example of correlation information including a first parameter and a second parameter, where the storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and the same second parameter partially do not overlap. The correlation information provided in the embodiments of this application is not limited to this. For example, in some other embodiments, the correlation information includes a third parameter, which is used to indicate whether there is partial non-overlapping of the memory spaces corresponding to different variables. This application does not impose any restrictions on this.

[0535] This application also provides a compilation apparatus. Exemplarily, Figure 11 A schematic diagram of the structure of a compiler apparatus 1000 is shown according to an embodiment of this application. For example... Figure 11 As shown, the device 1000 includes:

[0536] The acquisition module 1001 is used to acquire the source program, wherein the source program includes access identifiers (or access modifiers) of member data of composite data types. In some embodiments, the source program also includes variable dependency identifiers. The optimization module 1002 is used to acquire the source program from the acquisition module 1001, convert the source program into a first intermediate representation, and determine whether the memory access instructions in the first intermediate representation can be processed based on the variable dependency identifiers and / or the access identifiers of member data of composite data types in the source program, and perform first processing on the memory access instructions that can be processed. The first processing includes, but is not limited to, merging processing, deletion processing, etc.

[0537] In some embodiments, the optimization module 1002 can obtain the relevant semantic information of the access identifier and the correlation identifier through the interface, and determine whether the memory access instruction in the first intermediate representation can be processed first, i.e. whether the first processing condition and / or the second processing condition are met, based on the correlation identifier of the variable in the source program and / or the access identifier of the member data of the composite type data, as well as the relevant semantic information of the access identifier and the correlation identifier.

[0538] In some embodiments, access identifiers are used to indicate how member data is accessed. For example, member data identified by a first access modifier (e.g., _unique_) can only be accessed through a variable of the corresponding composite data type (a first variable or a variable of a first type). Or, for example, member data identified by a second access modifier (e.g., _shared_) can be accessed through a variable of the corresponding composite data type, or through a variable of a different type than the variable of the corresponding composite data type, such as through a pointer variable of the corresponding data type.

[0539] It is understandable that if, between two memory access instructions of the same type accessing the first member data through a variable of a composite data type, there is one memory access instruction accessing the second member data through a variable of a non-composite data type, and the first member data includes a first access modifier while the second member data does not include the first access modifier (e.g., includes a second access modifier), then the optimization module 1002 can determine that the first member data and the second member data are different member data, that is, the memory spaces corresponding to the first member data and the second member data do not overlap. Furthermore, the optimization module 1002 can determine that the two memory access instructions of the same type accessing the first member data through a variable of a composite data type satisfy the first processing condition (or the second processing condition).

[0540] In other embodiments, the correlation identifier of a variable is used to indicate whether there is another variable whose memory space intersects with the memory space corresponding to the identified variable. That is, the correlation identifier of a variable is used to indicate whether there is an intersection between the memory spaces corresponding to multiple variables. The intersection between the memory spaces corresponding to multiple variables includes, but is not limited to: the memory spaces corresponding to multiple variables completely overlapping; the memory spaces corresponding to multiple variables partially overlapping; and the memory spaces corresponding to multiple variables having an inclusion relationship, i.e., the memory space corresponding to one variable contains the memory space corresponding to another variable. This application does not impose specific limitations in this regard.

[0541] It is understood that if there is a memory access instruction corresponding to a second variable (e.g., an instruction to access the first variable, or an instruction to access data through the first variable) between two memory access instructions of the same type corresponding to the first variable, and the correlation identifier of the first variable and the correlation identifier of the second variable indicate that there is no intersection between the memory space corresponding to the first variable and the memory space corresponding to the second variable, then the optimization module 1002 can determine that the two memory access instructions of the same type corresponding to the first variable satisfy the first processing condition (or the second processing condition).

[0542] It is understandable that performing first processing (e.g., merging and / or deleting) on ​​memory access instructions that meet the first and / or second processing conditions can effectively reduce the number of memory access instructions, thereby improving the running efficiency of the application program corresponding to the source program. Simultaneously, determining whether there are memory access instructions in the source program that meet the first and / or second processing conditions based on memory access flags and / or correlation flags can reduce the risk of erroneous merging and / or erroneous deletion, thus reducing the risk of program errors.

[0543] The code generation module 1003 is used to obtain a first intermediate representation after the first processing by the optimization module 1002, and generate a target code file (as a first target code file) based on the first intermediate representation, such as an executable file. For example, in some embodiments, the acquisition module 1001 is used to obtain a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access method. The optimization module 1002 is used to determine at least two first instructions that satisfy a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes: the first instruction is an instruction that accesses the first member data through a first access method, and the at least two first instructions are of the same type; it is also used to perform a first processing on the at least two first instructions. The code generation module 1003 is used to obtain the first target code file.

[0544] In some embodiments, the acquisition module 1001 is further configured to acquire a first source program, wherein the first source program includes a correlation identifier for variables, the correlation identifier indicating whether there is another variable whose storage space intersects with the variable's corresponding variable. The optimization module 1002 is further configured to, based on the correlation identifier in the first source program, determine at least two third instructions among the plurality of memory access instructions corresponding to the first source program that do not satisfy the first processing condition but satisfy the second processing condition, wherein the second processing condition includes: at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable among the at least two third instructions, and the storage space corresponding to the fourth variable does not intersect with the storage space corresponding to the third variable; and is further configured to perform first processing on the plurality of third instructions.

[0545] For example, in some embodiments, the acquisition module 1001 is used to acquire a first source program, wherein the first source program includes correlation identifiers of variables, and the storage spaces corresponding to variables with the same correlation identifier do not overlap. The optimization module 1002 is used to determine, based on the correlation identifiers in the first source program, at least two first instructions satisfying a first processing condition from multiple memory access instructions corresponding to the first source program, wherein the first processing condition includes: at least two first instructions correspond to first variables, there is at least one second instruction corresponding to a second variable between the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; it is also used to perform a first processing on the at least two first instructions. The code generation module 1003 is used to obtain a first target code file.

[0546] In other embodiments, the acquisition module 1001 is further configured to acquire a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, the first access identifier is used to indicate that the first member data is accessed only through a first access method. The optimization module 1002 is further configured to determine from a plurality of memory access instructions corresponding to the first source program at least two third instructions that do not meet the first processing condition but meet the second processing condition, wherein the second processing condition includes: the third instructions are instructions that access the first member data through the first access method, and at least two third instructions are of the same type; and is further configured to perform a first processing on the plurality of third instructions.

[0547] It should be understood that the compilation device 1000 here is embodied in the form of functional modules. The term "unit" here can refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, dedicated processors, or group processors) and memory for executing one or more software or firmware programs, merging logic circuits, and / or other suitable components supporting the described functions. For example, if the compilation device 1000 is a compiler, then the acquisition module 1001 could be a compiler frontend, the optimization module 1002 could be a compiler optimizer, and the code generation module 1003 could be a compiler backend.

[0548] In some embodiments, the compilation device 1000 can be used to perform the above-described... Figure 5 The method embodiment shown Figure 6 The method embodiment shown Figure 7 The method embodiment shown Figure 8 The method embodiment shown or Figure 9 To avoid repetition, the various processes corresponding to the method embodiments shown will not be described again here.

[0549] For example, Figure 12 A schematic diagram of another compiler apparatus 2000 is shown according to an embodiment of this application. Figure 12 As shown, the device 2000 includes:

[0550] Acquisition module 2001 is used to acquire a first source program, wherein the first source program includes variable correlation information and a first access identifier. The correlation information includes at least one parameter, which indicates whether the storage spaces corresponding to at least two variables do not overlap at least partially. The storage space corresponding to the target variable modified by the first access identifier does not overlap with the storage spaces corresponding to variables other than the target variable. Optimization module 2002 is used to determine a first target code file based on the first source program, the correlation information in the first source program, and / or the first access identifier in the first source program. The number of memory access instructions in the first target code file is less than the number of memory access instructions in a second target code file. The second target code file is a target code file not determined based on the correlation information and / or the first access identifier in the first source program.

[0551] In some embodiments, the optimization module 2002 can obtain the relevant semantic information of the access identifier and the correlation identifier through the interface, and determine whether the memory access instruction in the first intermediate representation can be processed based on the correlation information of the variables in the first source program and / or the first access identifier, as well as the relevant semantic information of the first access identifier and the correlation information.

[0552] In some embodiments, the correlation information includes at least one parameter indicating whether the memory spaces corresponding to at least two variables do not overlap at least partially. The memory space corresponding to the target variable modified by the first access identifier does not overlap with the memory spaces corresponding to variables other than the target variable.

[0553] In some embodiments, the optimization module 2002 includes a processing module 2003 and a code generation module 2004.

[0554] In some embodiments, processing module 2003 is configured to determine at least two first instructions satisfying a first processing condition from a plurality of memory access instructions corresponding to the first source program, based on correlation information and a first access identifier in the first source program. The first processing condition includes: at least two first instructions correspond to a first variable; there is at least one second instruction corresponding to a second variable between the at least two first instructions; the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially; the first variable is modified by a first access identifier; and the at least two first instructions are of the same type. Processing module 2003 is further configured to perform a first processing on the at least two first instructions. Code generation module 2004 is configured to obtain a first object code file.

[0555] In other embodiments, processing module 2003 is configured to determine at least two third instructions satisfying a second processing condition from a plurality of memory access instructions corresponding to the first source program based on a first access identifier in the first source program. The second processing condition includes: at least two third instructions correspond to third variables, the third variables are modified by the first access identifier, and the at least two third instructions are of the same type. Processing module 2003 is further configured to perform a first processing on the at least two third instructions. Code generation module 2004 is configured to obtain a first object code file.

[0556] In other embodiments, processing module 2003 is configured to determine at least two fifth instructions that satisfy a third processing condition from multiple memory access instructions corresponding to the first source program based on correlation information in the first source program. The third processing condition includes: at least two fifth instructions correspond to fifth variables; there is at least one sixth instruction corresponding to a sixth variable among the at least two fifth instructions; the storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable; and the at least two fifth instructions are of the same type. Processing module 2003 is further configured to perform a first processing on the at least two fifth instructions. Code generation module 2004 is configured to obtain a first target code file.

[0557] It is understandable that performing initial processing (such as merging and / or deleting) on ​​memory access instructions that meet the processing conditions can effectively reduce the number of memory access instructions, thereby improving the running efficiency of the application program corresponding to the source program. Simultaneously, determining whether there are memory access instructions that meet the corresponding processing conditions among the memory access instructions corresponding to the first source program based on the first access identifier and / or correlation information can reduce the risk of erroneous merging and / or erroneous deletion, thereby reducing the risk of program errors.

[0558] In some embodiments, the compilation apparatus 2000 can be used to perform the above-described... Figure 10 To avoid repetition, the various processes corresponding to the method embodiments shown will not be described again here.

[0559] Understandable. Figure 11 and Figure 12 The compiler apparatus shown is merely illustrative; in other embodiments, the compiler apparatus may further include... Figure 11 and Figure 12 The compilation apparatus shown may have fewer or more modules, but this application does not limit this to such cases.

[0560] For example, Figure 13 A schematic diagram of the hardware structure of a compiler device 1000 is shown according to an embodiment of this application.

[0561] like Figure 13As shown, the compilation device 1000 includes one or more (only one is shown in the figure) processors 110, memory 120, communication interface 130, and bus 140. The processors 110, memory 120, and communication interface 130 are interconnected via the bus 140.

[0562] The processor 110 may include one or more processing units, such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU), an application-specific integrated circuit, etc., for executing related programs to implement the functions required by the modules in the compilation apparatus of this application embodiment, or to execute the compilation method of this application method embodiment.

[0563] Memory 120 may include one or more memories for storing data or one or more applications. The memory may be read-only memory (ROM), static storage, dynamic storage, or random access memory (RAM). For example, in some embodiments, memory 120 may store source code, including variable dependency identifiers and access identifiers for member data of composite data types.

[0564] In some embodiments, if the processor is a CPU, the corresponding memory 120 is main memory. In some embodiments, if the processor 110 is a GPU, the corresponding memory 120 can be video memory.

[0565] The processor 110 can also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the compilation method of this application can be completed through software instructions in the processor 110. The aforementioned processor 110 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory 120. The processor 110 reads the information in the memory 120 and, in conjunction with its hardware, performs the functions required by the units included in the compilation apparatus of this application embodiment, or executes the compilation method of this application method embodiment.

[0566] The communication interface 130 is used to enable communication between the compiler device 1000 and other devices or communication networks. The communication interface 130 may include a wired or wireless communication interface, so that the electronic device 100 can access the Internet via wired or wireless means, and obtain data from or send data to other devices based on the Internet.

[0567] Bus 140 is used to connect processor 110, memory 120, communication interface 130 and other possible modules or circuits.

[0568] It should be understood that Figure 13 The structure of the compiler 1000 shown is only an example. In other embodiments, the compiler 1000 may include more or fewer modules, which is not limited here.

[0569] In some embodiments, the hardware structure of the compiler 2000 may refer to the hardware structure of the compiler 1000, which will not be described in detail here.

[0570] This application also provides an electronic device, which includes a memory for storing instructions to be executed by one or more processors of the electronic device, and a processor, which is one of the processors of the electronic device, for executing the above-mentioned instructions. Figure 5 The method embodiment shown Figure 6The method embodiment shown Figure 7 The method embodiment shown Figure 8 The method embodiment shown Figure 9 The method embodiment shown or Figure 10 The compilation method corresponding to the method embodiment shown.

[0571] This application also provides a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, which is loaded and executed by a processor to implement the methods provided in the above-described method embodiments.

[0572] This application also provides a program product that includes instructions that, when executed by a device, enable the device to implement the method provided in this application.

[0573] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, optical discs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0574] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0575] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0576] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0577] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A compilation method, characterized in that, include: Obtain a first source program, wherein the first source program includes variable correlation information and a first access identifier, the correlation information includes at least one parameter, the at least one parameter is used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially, and the storage space corresponding to the target variable modified by the first access identifier does not overlap with the storage space corresponding to variables other than the target variable; Based on the first source program, and the correlation information in the first source program and / or the first access identifier in the first source program, a first target code file is determined, wherein the number of memory access instructions in the first target code file is less than the number of memory access instructions in the second target code file, and the second target code file is a target code file not determined based on the correlation information in the first source program and / or the first access identifier.

2. The method according to claim 1, characterized in that, The at least one parameter includes a first parameter and a second parameter, wherein, The first parameter is used to indicate whether there are at least two variables whose storage spaces do not overlap, and the second parameter is used to indicate whether the storage spaces corresponding to at least two overlapping variables are partially non-overlapping.

3. The method according to claim 2, characterized in that, The storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter and the same second parameter do not partially overlap. or, The storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters but the same second parameter do not partially overlap. or, The storage spaces corresponding to variables with different first parameters do not overlap, and the storage spaces corresponding to variables with the same first parameter but different second parameters do not overlap. or, The storage spaces corresponding to variables with the same first parameter do not overlap, and the storage spaces corresponding to variables with different first parameters and different second parameters do not overlap.

4. The method according to claim 1, characterized in that, The at least one parameter includes a third parameter, wherein, The third parameter is used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially.

5. The method according to claim 4, characterized in that, The storage spaces corresponding to variables with different third parameters do not overlap at least partially; or, The storage spaces corresponding to variables having the same third parameter are at least partially non-overlapping.

6. The method according to any one of claims 1 to 5, characterized in that, The first access identifier is used to indicate that the storage space corresponding to the target variable is accessed only through the target variable.

7. The method according to any one of claims 1 to 6, characterized in that, The step of determining the first target code file based on the first source program, and the relevant information in the first source program and / or the first access identifier in the first source program, includes: Based on the correlation information in the first source program and the first access identifier in the first source program, at least two first instructions that satisfy the first processing condition are determined from the multiple memory access instructions corresponding to the first source program. The at least two first instructions are processed in a first manner to obtain a first object code file; wherein, The first processing conditions include: The at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable among the at least two first instructions, the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially, the first variable is modified by the first access identifier, and the at least two first instructions are of the same type.

8. The method according to any one of claims 1 to 6, characterized in that, The step of determining the first target code file based on the first source program, the relevant information in the first source program, and / or the first access identifier in the first source program further includes: Based on the first access identifier in the first source program, at least two third instructions that satisfy the second processing condition are determined from the multiple memory access instructions corresponding to the first source program. The at least two third instructions are processed in a first manner to obtain a first object code file; wherein, The second processing conditions include: The at least two third instructions correspond to third variables, the third variables are modified by the first access identifier, and the at least two third instructions are of the same type.

9. The method according to any one of claims 1 to 7, characterized in that, The step of determining the first target code file based on the first source program, the relevant information in the first source program, and / or the first access identifier in the first source program further includes: Based on the correlation information in the first source program, at least two fifth instructions that satisfy the third processing condition are determined from the multiple memory access instructions corresponding to the first source program. The at least two fifth instructions are subjected to first processing to obtain the first target code file; wherein, The third processing condition includes: The at least two fifth instructions correspond to fifth variables, and there is at least one sixth instruction corresponding to a sixth variable among the at least two fifth instructions. The storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable, and the at least two fifth instructions are of the same type.

10. The method according to claim 7, characterized in that, Corresponding to the first instruction being a read operation instruction, the first processing condition further includes at least one of the following: The first instruction is a read operation instruction, and the second instruction is a write operation instruction; The first instruction is a write operation instruction, and the second instruction is a read operation instruction.

11. The method according to claim 7 or 10, characterized in that, The first process includes at least one of the following: merging process, deletion process.

12. The method according to claim 11, characterized in that, Corresponding to the first processing including merging processing, the first processing conditions further include: The memory space accessed by each of the first instructions is a contiguous memory space, or... The data stored in the memory space accessed by each of the first instructions corresponds to the same variable.

13. The method according to claim 7, characterized in that, The multiple memory access instructions corresponding to the first source program are determined using the following method: Based on the first source program, a first intermediate representation is generated, wherein the first intermediate representation includes multiple instructions; Multiple memory access instructions are determined from multiple instructions in the first intermediate representation.

14. The method according to claim 13, characterized in that, The process of obtaining the first target code file includes: The at least two first instructions are processed to obtain a second intermediate representation, wherein the number of first instructions in the second intermediate representation is less than the number of first instructions in the first intermediate representation; The first target code file is generated based on the second intermediate representation.

15. A compilation method, characterized in that, include: Obtain a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access method; From the multiple memory access instructions corresponding to the first source program, at least two first instructions that satisfy the first processing condition are determined, wherein the first processing condition includes: the first instruction is an instruction that accesses the first member data through the first access method, and the at least two first instructions are of the same type; The at least two first instructions are processed first to obtain a first target code file.

16. The method according to claim 15, characterized in that, The multiple memory access instructions corresponding to the first source program are determined using the following method: Based on the first source program, a first intermediate representation is generated, wherein the first intermediate representation includes multiple instructions; Multiple memory access instructions are determined from multiple instructions in the first intermediate representation.

17. The method according to claim 15, characterized in that, Accessing the first member data via the first access method includes: Access the first member data through the first variable, or... Access the first member data through a variable of the first type.

18. The method according to claim 15, characterized in that, The first processing condition also includes: The at least two first instructions are consecutive memory access instructions.

19. The method according to claim 15, characterized in that, The composite data type further includes second member data, and the second member data does not include the first access identifier; there is at least one second instruction between the at least two first instructions; and... The first processing condition also includes: The second instruction is a memory access instruction for accessing the second member data without using the first access method.

20. The method according to claim 19, characterized in that, Corresponding to the first instruction being a read operation instruction, the first processing condition further includes at least one of the following: The first instruction is a read operation instruction, and the second instruction is a write operation instruction; The first instruction is a write operation instruction, and the second instruction is a read operation instruction.

21. The method according to claim 15, characterized in that, The first source program also includes a correlation identifier for the variable, which indicates whether there exists another variable whose storage space intersects with that of the variable; and, The method further includes: Based on the correlation identifier in the first source program, at least two third instructions among the multiple memory access instructions corresponding to the first source program are identified that do not meet the first processing condition but meet the second processing condition, wherein the second processing condition includes: The at least two third instructions correspond to third variables, there is at least one fourth instruction corresponding to a fourth variable among the at least two third instructions, and the storage space corresponding to the fourth variable does not overlap with the storage space corresponding to the third variable; The first processing is performed on multiple third instructions to obtain the first target code file.

22. The method according to claim 21, characterized in that, The correlation identifier is used to indicate whether there is another variable whose storage space intersects with the variable corresponding to the variable, including: The storage spaces corresponding to variables with the same correlation identifier do not overlap.

23. The method according to claim 22, characterized in that, The storage space corresponding to the fourth variable does not overlap with the storage space corresponding to the third variable, including: The correlation identifier of the fourth variable corresponding to the fourth instruction is the same as the correlation identifier of the third variable corresponding to the third instruction.

24. The method according to claim 15, characterized in that, The number of memory access instructions in the first object code file is less than the number of memory access instructions in the second object code file, which is an object code file obtained without performing the first processing on the memory access instructions.

25. The method according to claim 15, characterized in that, The first process includes at least one of the following: merging process, deletion process.

26. The method according to claim 25, characterized in that, Corresponding to the first processing including merging processing, the first processing conditions further include: The memory space accessed by each of the first instructions is a contiguous memory space, or... The data stored in the memory space accessed by each of the first instructions corresponds to the same variable.

27. The method according to claim 16, characterized in that, The process of obtaining the first target code file includes: The at least two first instructions are processed to obtain a second intermediate representation, wherein the number of first instructions in the second intermediate representation is less than the number of first instructions in the first intermediate representation; The first target code file is generated based on the second intermediate representation.

28. A compilation method, characterized in that, include: Obtain a first source program, wherein the first source program includes correlation identifiers of variables, and the storage spaces corresponding to variables with the same correlation identifier do not overlap; Based on the correlation identifier in the first source program, at least two first instructions that satisfy the first processing condition are determined from the multiple memory access instructions corresponding to the first source program, wherein the first processing condition includes: The at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable among the at least two first instructions, and the correlation identifier of the second variable is the same as the correlation identifier of the first variable; The at least two first instructions are processed first to obtain a first target code file.

29. A compilation apparatus, characterized in that, include: An acquisition module is used to acquire a first source program, wherein the first source program includes variable correlation information and a first access identifier. The correlation information includes at least one parameter, which is used to indicate whether the storage spaces corresponding to at least two variables do not overlap at least partially, and the storage space corresponding to the target variable modified by the first access identifier does not overlap with the storage space corresponding to variables other than the target variable. An optimization module is configured to determine a first target code file based on the first source program, the correlation information in the first source program, and / or the first access identifier in the first source program, wherein the number of memory access instructions in the first target code file is less than the number of memory access instructions in the second target code file, and the second target code file is a target code file not determined based on the correlation information in the first source program and / or the first access identifier.

30. The apparatus according to claim 29, characterized in that, The optimization module includes a processing module and a code generation module; and... The processing module is configured to determine, based on the correlation information in the first source program and the first access identifier in the first source program, at least two first instructions that satisfy a first processing condition from a plurality of memory access instructions corresponding to the first source program. The first processing condition includes: the at least two first instructions correspond to a first variable, there is at least one second instruction corresponding to a second variable among the at least two first instructions, the storage space corresponding to the second variable and the storage space corresponding to the first variable do not overlap at least partially, the first variable is modified by the first access identifier, and the at least two first instructions are of the same type. The processing module is further configured to perform a first processing on the at least two first instructions; The code generation module is used to obtain the first target code file.

31. The apparatus according to claim 29, characterized in that, The optimization module includes a processing module and a code generation module; and... The processing module is configured to determine at least two third instructions that satisfy a second processing condition from a plurality of memory access instructions corresponding to the first source program based on the first access identifier in the first source program. The second processing condition includes: the at least two third instructions correspond to a third variable, the third variable is modified by the first access identifier, and the at least two third instructions are of the same type. The processing module is further configured to perform a first processing on the at least two third instructions; The code generation module is used to obtain the first target code file.

32. The apparatus according to claim 29, characterized in that, The optimization module includes a processing module and a code generation module; and... The processing module is configured to determine at least two fifth instructions that satisfy a third processing condition from multiple memory access instructions corresponding to the first source program based on the correlation information in the first source program. The third processing condition includes: the at least two fifth instructions correspond to a fifth variable, there is at least one sixth instruction corresponding to a sixth variable among the at least two fifth instructions, the storage space corresponding to the sixth variable does not overlap with the storage space corresponding to the fifth variable, and the at least two fifth instructions are of the same type. The processing module is also used to perform a first processing on the at least two fifth instructions; The code generation module is used to obtain the first target code file.

33. A compiler apparatus, characterized in that, include: The acquisition module is used to acquire a first source program, wherein the first source program includes composite type data, the composite type data includes first member data, the first member data includes a first access identifier, and the first access identifier is used to indicate that the first member data is accessed only through a first access method. An optimization module is configured to determine at least two first instructions that satisfy a first processing condition from a plurality of memory access instructions corresponding to the first source program, wherein the first processing condition includes: the first instruction is an instruction that accesses the first member data through the first access method, and the at least two first instructions are of the same type; The optimization module is further configured to perform a first processing on the at least two first instructions; The code generation module is used to obtain the first target code file.

34. A readable medium, characterized in that, The readable medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 28.

35. An electronic device, characterized in that, include: Memory, used to store instructions executed by one or more processors of an electronic device, and A processor is one of the processors in an electronic device, used to perform the method according to any one of claims 1 to 28.

36. A program product, characterized in that, The program product includes instructions that, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 28.

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