Replacement strategy circuit generation method and device based on reuse prediction
By using a replacement strategy based on reuse prediction, memory access sequence features are extracted and circuits are generated, solving the problem of dynamic adjustment of cache replacement strategies in automatic circuit design and improving processor performance and cache hit rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-01
- Publication Date
- 2026-03-27
AI Technical Summary
Existing cache replacement strategies have the problem of difficulty in achieving dynamic adjustment in automatic circuit design. Static replacement strategies are simple to design but have poor performance, while dynamic replacement strategies have good performance but complex circuit design and are difficult to automate deployment.
A replacement strategy based on reuse prediction is adopted. The feature extraction module extracts features from the memory access sequence, the cache simulation module labels the samples, the reuse prediction module learns the mapping relationship, and the existing circuit automatic design algorithm is used to generate the replacement strategy circuit to dynamically adjust the replacement priority of cache blocks.
It improves processor performance by predicting the reuse probability of cache blocks through a reuse prediction framework, reducing branch prediction penalties, increasing cache hit rate, and simplifying the automatic circuit design process.
Smart Images
Figure CN121743036A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of processor microarchitecture and automatic circuit design, and particularly to a method, apparatus, electronic device, computer-readable storage medium, and computer program product for generating circuits based on a replacement strategy using reuse prediction. Background Technology
[0002] Replacement strategy is a key mechanism in cache management in computer architecture. Its function is to determine which old data block to replace to free up space when new data needs to be loaded into the cache. The cache replacement problem is essentially about predicting the future memory access patterns of a program. By predicting future low-reusability cache blocks through historical access patterns, it prioritizes the replacement of these blocks, thereby preserving as much high-reusability data as possible. The accuracy of the prediction determines the cache hit rate.
[0003] Traditional cache replacement strategies rely on heuristic rules to statically predict future memory access patterns. However, due to the complexity and variability of memory access patterns in real-world programs, a single static prediction strategy can easily fail. Therefore, a learning-based cache replacement strategy is needed, which dynamically learns historical access patterns during program execution and adaptively adjusts the objects to be replaced. Furthermore, existing learning-based cache replacement strategies cannot be automatically implemented in the chip's hardware through circuit design; therefore, a novel cache replacement strategy that supports automated design needs to be developed. Summary of the Invention
[0004] The purpose of this invention is to solve the problems that static replacement is easy to automate circuit design but yields poor results, while dynamic replacement is effective but difficult to automate. This invention implements a replacement strategy that allows for dynamic replacement while facilitating automatic circuit design.
[0005] To address the shortcomings of existing technologies, such as Figure 2 As shown, this invention proposes a method for generating replacement strategy circuits based on reuse prediction, including:
[0006] The feature extraction step extracts subsequences from the memory access sequence for reuse prediction and encodes them as memory access features;
[0007] The cache simulation process records the characteristics of cache blocks and their corresponding memory access operations in the on-chip cache. If the current memory access operation hits, the previous access to the cache block will be marked as reused; if the current memory access operation misses, the previous access to the cache block will be marked as non-reuse.
[0008] The reuse prediction step receives the memory access feature, learns the mapping relationship between the memory access feature and cache block reuse, and adjusts the replacement priority of cache blocks according to the mapping relationship. If the current memory access operation is mapped to non-reuse, the replacement priority of the cache block it accesses is high.
[0009] The replacement strategy circuit generation method based on reuse prediction, wherein the feature extraction step includes:
[0010] The program's execution trace is collected, and the memory access sequence is extracted from the trace. The memory access characteristics of each memory access operation are obtained from the memory access sequence. These memory access characteristics include the memory access instruction and the memory block address.
[0011] The cache emulation process includes:
[0012] The state changes of the buffer after receiving the memory access sequence are simulated to determine whether each memory access operation is reused; the feature and reuse tag pairs are used as input-output pairs, and the circuit of the reuse prediction module is fitted by existing automatic circuit design methods.
[0013] The replacement strategy circuit generation method based on reuse prediction, wherein the memory access sequence in the feature extraction step includes multiple elements, each element being the address of the memory access instruction in memory and the memory address accessed by the memory access instruction; during processor execution, the element is recorded to obtain the memory access sequence.
[0014] like Figure 3 As shown, the present invention also proposes a replacement strategy circuit generation device B based on reuse prediction, which includes:
[0015] The feature extraction module extracts subsequences from the memory access sequence for reuse prediction and encodes them as memory access features.
[0016] The cache simulation module records the characteristics of cache blocks and their corresponding memory access operations in the cache on the chip; if the current memory access operation hits, the previous access to the cache block will be marked as reused; if the current memory access operation misses, the previous access to the cache block will be marked as not reused.
[0017] The reuse prediction module receives the memory access feature, learns the mapping relationship between the memory access feature and cache block reuse, and adjusts the replacement priority of cache blocks according to the mapping relationship. If the current memory access operation is mapped to non-reuse, the replacement priority of the cache block it accesses is high.
[0018] The replacement strategy circuit generation device based on reuse prediction, wherein the feature extraction module includes:
[0019] The program's execution trace is collected, and the memory access sequence is extracted from the trace. The memory access characteristics of each memory access operation are obtained from the memory access sequence. These memory access characteristics include the memory access instruction and the memory block address.
[0020] This cache simulation module includes:
[0021] The state changes of the buffer after receiving the memory access sequence are simulated to determine whether each memory access operation is reused; the feature and reuse tag pairs are used as input-output pairs, and the circuit of the reuse prediction module is fitted by existing automatic circuit design methods.
[0022] The replacement strategy circuit generation device based on reuse prediction, wherein the memory access sequence in the feature extraction module includes multiple elements, each element being the address of the memory access instruction in memory and the memory address accessed by the memory access instruction; during processor execution, the element is recorded to obtain the memory access sequence.
[0023] The present invention also proposes a client for any of the reuse prediction-based replacement strategy circuit generation devices.
[0024] The present invention also proposes an electronic device, including the aforementioned circuit generation device for a replacement strategy based on reuse prediction. The electronic device may be connected to an information display device, which is used to display the replacement priority of cache blocks using user-set display parameters, attributes, or through an artificial intelligence model.
[0025] The present invention also proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for generating replacement strategy circuits based on reuse prediction.
[0026] The present invention also proposes a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it implements the steps of the replacement strategy circuit generation method based on reuse prediction.
[0027] As can be seen from the above solutions, the advantages of the present invention are:
[0028] This replacement strategy uses a reuse prediction framework to predict the reuse probability of cache blocks. Based on instruction dependency confidence and branch prediction confidence, it improves processor performance from two aspects: data flow dependency and reducing branch prediction penalty.
[0029] The core module of this framework, the predictor, can automatically generate logic circuits from features to prediction results based on existing black-box circuit generation algorithms. Attached Figure Description
[0030] Figure 1 This is a system block diagram of the present invention;
[0031] Figure 2 This is a flowchart of the method of the present invention;
[0032] Figure 3 This is a block diagram of the device of the present invention;
[0033] Figure 4 This is a schematic diagram of the structure of the first electronic device of the present invention;
[0034] Figure 5 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;
[0035] Figure 6 This is a schematic diagram of the structure of the second electronic device of the present invention.
[0036] Figure label:
[0037] A - First electronic device;
[0038] B-Replacement strategy circuit generation device based on reuse prediction;
[0039] C-Data acquisition equipment;
[0040] D-Information display device;
[0041] 1000 - Second electronic device;
[0042] Ⅰ-Computational Unit;
[0043] II-ROM;
[0044] III-RAM;
[0045] N-bus;
[0046] V-Interface;
[0047] VI - Input Unit;
[0048] VII - Output Unit;
[0049] VIII - Storage medium;
[0050] IX - Communication Unit. Detailed Implementation
[0051] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0052] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0053] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).
[0054] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory and by calling data stored in memory.
[0055] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.
[0056] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.
[0057] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0058] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.
[0059] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.
[0060] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.
[0061] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0062] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0064] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0065] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0066] While researching cache replacement strategies, the inventors discovered that existing static replacement strategies, though simple in circuit design, were ineffective. Existing learning-based replacement strategies, while adaptable to program memory access patterns, suffered from complex circuit designs, making intelligent deployment difficult using existing automated circuit design methods. In their research on automated circuit design, the inventors found that existing automated circuit design algorithms could fit a circuit for a specific function with a certain degree of accuracy. By controlling relevant parameters, they achieved a trade-off between area and functional accuracy, automatically designing a black-box circuit to achieve an approximate function.
[0067] The inventors therefore designed a replacement strategy based on cache block reuse prediction. This strategy can be automatically designed using circuit automation methods and consists of three parts: a feature extraction module, a cache simulation module, and a reuse prediction module. The feature extraction module is responsible for extracting effective features from the memory access sequence, the reuse prediction module maps the features to the prediction results, and the cache simulation module labels the samples for training the prediction module. The prediction module needs to learn the mapping relationship, so machine learning models are often used. However, the complexity of machine learning models makes automatic circuit design difficult. The inventors use existing automatic circuit generation algorithms to directly fit the mapping from features to prediction results, thereby automatically generating the replacement strategy circuit.
[0068] In summary, to achieve the aforementioned technical effects, the present invention proposes the following key technical points:
[0069] Key Point 1: Replacement Strategy Based on Cache Block Reuse Prediction. Cache block reuse prediction refers to predicting whether a block accessed in the current memory access operation will be reused before being replaced, given the program's current memory access sequence, processor cache structure, and replacement strategy. Block reuse prediction learns the program's memory access patterns, identifies cache blocks that will be reused soon, and avoids prematurely replacing blocks with high reuse probability.
[0070] Key Point 2: Cache Block Reuse Prediction Framework. The prediction framework consists of three modules: a feature extraction module, a cache simulation module, and a reuse prediction module. The feature extraction module is responsible for extracting effective features from the memory access sequence, the reuse prediction module maps the features to the prediction results, and the cache simulation module labels the samples for training the prediction module.
[0071] Key point 3: Reuse the prediction module's automatic circuit design. Use existing automatic circuit design algorithms based on IO data, take different features as input data for training, and use the real reuse results as output data to train the black box circuit. Adjust the hyperparameters of the automatic circuit design algorithm to change the fitting accuracy, thereby balancing area and accuracy.
[0072] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.
[0073] 1. Cache block reuse prediction framework
[0074] like Figure 1As shown, the cache block reuse prediction framework consists of three parts: a feature extraction module, a cache simulation module, and a reuse prediction module. Specifically, the feature extraction module extracts a subsequence for reuse prediction from the complete memory access sequence (a pre-ordered subset of the entire memory access sequence, such as the most recent n accesses, or the memory access operations of the most recent n accesses to a specific data block), and encodes it as a feature. The cache simulation module records the features of the cache block and its corresponding memory access operation; this feature is extracted from the memory access subsequence. For example, considering the memory access subsequence as the most recent n memory access operations (including the memory access operation that needs to be predicted for block reuse), shifting and XORing the instruction PCs of the most recent n memory access operations compresses the subsequence into a feature, which is then marked as the feature of the currently predicted memory access operation. If the current memory access operation hits, the previous access to that block will be marked as "reused," and the feature of the current memory access will be recorded in the module; if the current memory access operation is missing, the previous access to that block will be marked as "not reused," and the current memory access feature will be written into the module. The reuse prediction module receives feature input and learns the mapping relationship between features and cached block reuse. The next time a cache miss occurs, blocks mapped as non-reusable are replaced first, as non-reusable blocks have higher replacement priority.
[0075] The memory access sequence originates from the following: Modern processors are instruction-driven, and some instructions access memory; these are called memory access instructions. The memory address of the memory access instruction (PC) and the memory address accessed by the instruction constitute an element of the memory access sequence. During processor execution, a hardware-implemented table can be used to record the memory access sequence by storing the memory access instruction's PC and the address of the access instruction.
[0076] The cache simulation module essentially adds access characteristic information to the metadata of cache blocks in the original cache structure. When a current memory access request accesses the cache, if the data block exists in the cache, it's a cache hit, indicating that the block was reused in the previous memory access operation. Since the characteristics of the previous memory access operation are recorded in the cache block metadata, this characteristic is read, mapped to reuse, and finally the metadata is updated with the characteristics of the current memory access operation. If the data block does not exist in the cache, it's a cache miss. In this case, the cache block replacement algorithm selects a block to evict, and the most recent memory access operation to the evicted block is marked as non-reusable. The characteristics of this memory access operation are read, mapped to non-reusable, and finally the metadata is updated with the characteristics of the current memory access operation.
[0077] 2. Automatic circuit design that reuses prediction modules
[0078] First, the program's execution trace is collected, and the memory access sequence is extracted from the trace. Features such as the current memory access instruction's program counter (PC), historical memory access instruction PCs, and memory block addresses are selected, and the trace is traversed to calculate the characteristics of each memory access operation. Based on this, a cache function simulator is implemented to simulate the cache state changes after receiving the memory access sequence, ultimately determining whether each memory access operation is reused. Using feature-reuse tag pairs as input-output pairs, existing automatic circuit design methods are used to fit the circuit of the reuse prediction module. The mapping relationship between features and cache block reuse is solidified into a hardware circuit; the input of this circuit is the feature corresponding to the data block, and the output is the reuse tag.
[0079] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.
[0080] like Figure 3 As shown, the present invention also proposes a replacement strategy circuit generation device B based on reuse prediction, which includes:
[0081] The feature extraction module extracts subsequences from the memory access sequence for reuse prediction and encodes them as memory access features.
[0082] The cache simulation module records the characteristics of cache blocks and their corresponding memory access operations in the cache on the chip; if the current memory access operation hits, the previous access to the cache block will be marked as reused; if the current memory access operation misses, the previous access to the cache block will be marked as not reused.
[0083] The reuse prediction module receives the memory access feature, learns the mapping relationship between the memory access feature and cache block reuse, and adjusts the replacement priority of cache blocks according to the mapping relationship. If the current memory access operation is mapped to non-reuse, the replacement priority of the cache block it accesses is high.
[0084] The replacement strategy circuit generation device based on reuse prediction, wherein the feature extraction module includes:
[0085] The program's execution trace is collected, and the memory access sequence is extracted from the trace. The memory access characteristics of each memory access operation are obtained from the memory access sequence. These memory access characteristics include the memory access instruction and the memory block address.
[0086] This cache simulation module includes:
[0087] The state changes of the buffer after receiving the memory access sequence are simulated to determine whether each memory access operation is reused; the feature and reuse tag pairs are used as input-output pairs, and the circuit of the reuse prediction module is fitted by existing automatic circuit design methods.
[0088] The replacement strategy circuit generation device based on reuse prediction, wherein the memory access sequence in the feature extraction module includes multiple elements, each element being the address of the memory access instruction in memory and the memory address accessed by the memory access instruction; during processor execution, the element is recorded to obtain the memory access sequence.
[0089] The present invention also proposes a client for any of the reuse prediction-based replacement strategy circuit generation devices.
[0090] like Figure 4 As shown, in another embodiment of the present invention, a first electronic device A is also provided, which includes the aforementioned replacement strategy circuit generation device B based on reuse prediction.
[0091] like Figure 5 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect memory access sequences, and the information display device D is used to display the replacement priority of the cache block obtained by the present invention.
[0092] The information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can present the user with the specified key information based on user-defined display parameters and / or attributes, such as the data range and font, color, and scrolling options. Users can access this information more quickly without needing to navigate to secondary pages or scroll through pages, saving them time and effort. Alternatively, the information display mechanism can be an artificial intelligence (AI) display model that learns the user's key information interests based on past usage habits, such as viewing time, click count, and edit count, and automatically presents rich and necessary key information.
[0093] The present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a readable storage medium, and when the computer program is executed by a processor, the computer is able to execute the replacement strategy circuit generation method based on reuse prediction provided by the above methods.
[0094] In another embodiment, the present invention also proposes a storage medium VIII for storing a computer program that executes the circuit generation method for the replacement strategy based on reuse prediction. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).
[0095] Figure 6 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.
[0096] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.
[0097] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0098] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S3. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).
[0099] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.
Claims
1. A method for generating replacement strategy circuits based on reuse prediction, characterized in that, include: The feature extraction step extracts subsequences from the memory access sequence for reuse prediction and encodes them as memory access features; The cache simulation process records the characteristics of cache blocks and their corresponding memory access operations in the on-chip cache. If the current memory access operation hits, the previous access to the cache block will be marked as reused; if the current memory access operation misses, the previous access to the cache block will be marked as non-reuse. The reuse prediction step receives the memory access feature, learns the mapping relationship between the memory access feature and cache block reuse, and adjusts the replacement priority of cache blocks according to the mapping relationship. If the current memory access operation is mapped to non-reuse, the replacement priority of the cache block it accesses is high.
2. The replacement strategy circuit generation method based on reuse prediction as described in claim 1, characterized in that, The feature extraction step includes: The program's execution trace is collected, and the memory access sequence is extracted from the trace. The memory access characteristics of each memory access operation are obtained from the memory access sequence. These memory access characteristics include the memory access instruction and the memory block address. The cache emulation process includes: The state changes of the cache after receiving the memory access sequence are simulated to determine whether each memory access operation is reused. The feature and reuse tag pair are used as input-output pairs. The circuit of the reuse prediction module is fitted by the existing circuit automatic design method to obtain the replacement strategy circuit, so as to solidify the mapping relationship between features and cache block reuse into hardware circuit. The input of the replacement strategy circuit is the memory access feature of the data block, and the output of the replacement strategy circuit is the tag of whether the data block is reused.
3. The replacement strategy circuit generation method based on reuse prediction as described in claim 1, characterized in that, In the feature extraction step, the memory access sequence includes multiple elements, each of which is the memory address of the memory access instruction and the memory address accessed by the memory access instruction; during processor execution, this element is recorded to obtain the memory access sequence.
4. A replacement strategy circuit generation apparatus based on reuse prediction, characterized in that, include: The feature extraction module extracts subsequences from the memory access sequence for reuse prediction and encodes them as memory access features. The cache simulation module records the characteristics of cache blocks and their corresponding memory access operations in the cache on the chip; if the current memory access operation hits, the previous access to the cache block will be marked as reused; if the current memory access operation misses, the previous access to the cache block will be marked as not reused. The reuse prediction module receives the memory access feature, learns the mapping relationship between the memory access feature and cache block reuse, and adjusts the replacement priority of cache blocks according to the mapping relationship. If the current memory access operation is mapped to non-reuse, the replacement priority of the cache block it accesses is high.
5. The replacement strategy circuit generation apparatus based on reuse prediction as described in claim 4, characterized in that, The feature extraction module includes: The program's execution trace is collected, and the memory access sequence is extracted from the trace. The memory access characteristics of each memory access operation are obtained from the memory access sequence. These memory access characteristics include the memory access instruction and the memory block address. This cache simulation module includes: The state changes of the cache after receiving the memory access sequence are simulated to determine whether each memory access operation is reused. The feature and reuse tag pair are used as input-output pairs. The circuit of the reuse prediction module is fitted by the existing circuit automatic design method to obtain the replacement strategy circuit, so as to solidify the mapping relationship between features and cache block reuse into hardware circuit. The input of the replacement strategy circuit is the memory access feature of the data block, and the output of the replacement strategy circuit is the tag of whether the data block is reused.
6. The replacement strategy circuit generation apparatus based on reuse prediction as described in claim 4, characterized in that, The memory access sequence in the feature extraction module includes multiple elements, each element being the memory address of the memory access instruction and the memory address accessed by the memory access instruction; during processor execution, this element is recorded to obtain the memory access sequence.
7. A client for any of the reuse prediction-based replacement strategy circuit generation apparatuses described in claims 4-6.
8. An electronic device, characterized in that, The invention includes a circuit generation apparatus for a replacement strategy based on reuse prediction as described in claims 5-7. The electronic device may be connected to an information display device, which is used to display the replacement priority of the cache block using user-set display parameters, attributes, or through an artificial intelligence model.
9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the replacement strategy circuit generation method based on reuse prediction as described in any one of claims 1-3.
10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the replacement strategy circuit generation method based on reuse prediction as described in any of claims 1-3.