A memory data exchange transmission processing method and transmission device

Abstract

The application discloses a memory data exchange transmission processing method and a transmission device, and belongs to the technical field of memory access management and data packet transmission.The processing method comprises the following steps: step 1, partitioning and segmenting a memory array, and storing segment information of the memory array into link table information of a data packet to be transmitted; step 2, inputting data into an IO port buffer module; step 3, starting to receive data and analyzing a packet header; step 4, starting to write data and performing corresponding function operations; and step 5, judging whether the link table information of the data packet contains a zone segment address of a next segment; if yes, returning to step 3; and if no, returning to step 2 to wait for new data input.The application realizes continuous transmission of data by identifying the zone segment address in the process of transmitting continuous data packets through partitioning and segmenting the memory, does not need to repeatedly generate and arbitrate an interrupt signal, improves the memory transmission efficiency, and reduces the load requirement.

Description

Technical Field

[0001] This invention belongs to the field of memory access management and data packet transmission technology, and relates to data storage technology, specifically to a memory data exchange and transmission processing method and transmission device. Background Technology

[0002] Data transmission is the communication process of transferring data from one place to another. A data transmission system typically consists of a transmission channel and data circuit termination equipment at both ends of the channel, as well as multiplexing equipment at both ends. The transmission channel can be a dedicated communication channel or provided by a data switching network, telephone switching network, or other types of switching networks. The input and output devices of a data transmission system are terminals or computers. The data information it sends is generally a combination of letters, numbers, and symbols. To transmit this information, each letter, number, or symbol must be represented by binary code. Data exchange via memory can take several forms:

[0003] 1. CPU / DSP Active Polling: Actively polling to check if there is data to be transmitted. If there is, data exchange is performed; otherwise, polling is performed again after a period of time.

[0004] 2. Interrupt handling: When data needs to be transferred, an interrupt signal will be sent to the CPU or DSP. After the interrupt is triggered, the data will be transferred.

[0005] 3. Direct Data Transfer (DMA): DMA design allows for the active exchange of data between two memories.

[0006] During data transmission, attention must be paid to issues such as the transmitting entity, transmission path, transmission method, efficiency, security, and synchronization. Summary of the Invention

[0007] To improve data transmission efficiency, reduce transmission steps, and increase transmission speed, this invention discloses a memory data exchange and transmission method.

[0008] Processing methods and transmission devices are provided to improve the efficiency of data transfer involving memory and reduce load requirements.

[0009] The memory data exchange and transmission processing method of the present invention includes the following steps:

[0010] Step 1. Based on the transmission purpose and characteristics of the transmitted data, partition and segment the memory array, and select the function modules to be called in the data processing module; and store the segmentation information of the memory array in the linked list information of the memory management module;

[0011] In the segmentation information of the memory array described in step 1, each segment address is marked as a default available segment address;

[0012] Step 2. Input data into the IO port buffer module. When data input begins, an interrupt arbitration message needs to be issued. In Step 2, while buffering each data packet, as long as there is subsequent data, the address of the available segment at the beginning of the linked list information in the memory management module is stored into the linked list information of the data packet. If there is no subsequent data, the above operation of storing the available segment address is not performed.

[0013] Step 3. Begin receiving data and parsing data packets, and set the subsequent data processing and storage methods based on the parsed information;

[0014] Step 4. Data storage and processing;

[0015] Step 41. Based on the data packet header information parsed in Step 3 and the linked list information of the memory management module, determine whether there is a function operation. If so, execute the corresponding function operation and store the new data obtained after execution in the corresponding storage area. If it is found that no function operation is required, store the data directly in the corresponding storage area.

[0016] Step 42. After the current data packet is stored, check whether the data packet's linked list information contains a segment address. If so, return to step 2 and continue to receive subsequent data packets. Execute steps 2 to 4 in sequence, and mark the obtained segment address as unavailable in the linked list information of the memory management module.

[0017] Step 5. After the data transmission is completed, continue to process the data that has not been processed during the data transmission and is stored in various storage areas; after all data has been processed, wait for the next data transmission.

[0018] Preferably, step 1 further includes setting the cache level of the IO port cache module; step 2, according to the cache level set in step 1, when the data volume reaches the cache level, data transmission from the IO port cache module begins.

[0019] Preferably, in step 3, the decision to start data reception is made based on the interrupt arbitration information only when the first data packet is input; subsequent data reception does not require an interrupt arbitration signal.

[0020] Preferably, in step 41, if the function operation occupies subsequent address segments, the occupied subsequent address segments are marked as unavailable in the linked list information of the memory management module.

[0021] Preferably, in step 41, no function operation is performed on data whose data volume increases after the function operation.

[0022] The present invention also discloses a memory data transmission device, including a memory management module, a memory array, and a data processing module, and including at least two I / O port buffer modules. The memory management module is used to partition and segment the memory array. The data processing module includes a function routing module and multiple function modules. The function routing module is used to plan the calling order of each function module. The memory data transmission device also includes a data transmission management module, which is used to execute the memory data exchange and transmission processing method.

[0023] Preferably, the memory management module further includes a memory protection module, a clock management module (CMU), and a reset management module (GMU).

[0024] Preferably, the memory data transfer device further includes a DMA interface.

[0025] The memory data exchange and transmission processing method and transmission device described in this invention partitions and segments the memory. During the continuous transmission of continuous data packets, continuous data transmission is achieved by identifying the segment address. This eliminates the need for repeated generation and arbitration of interrupt signals, thereby improving memory transmission efficiency. At the same time, it eliminates the need to call interrupt signal arbitration, reducing load requirements. Attached Figure Description

[0026] Figure 1 is a schematic diagram of a specific embodiment of the memory data exchange and transmission device of the present invention;

[0027] Figure 2 is a schematic diagram of a specific embodiment of partitioning and segmenting the memory in this invention;

[0028] Figure 3 is a schematic diagram of a specific embodiment of the data packet format described in this invention;

[0029] Figure 4 is a schematic diagram of a specific implementation of the memory data exchange and transmission processing method of the present invention. Detailed Implementation

[0030] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] The memory data transmission device of the present invention, as shown in Figure 1, includes a memory management module, a memory array, and a function module, and includes at least two I / O port buffer modules. The memory management module is used to partition and segment the memory array. The data processing module includes a function routing module and multiple function modules. The function routing module plans the calling order of each function module. The function modules include commonly used data processing functions such as a data reconstruction module, a Fourier operation module, and a filtering operation module.

[0032] The memory management module also includes conventional linked lists, memory tables, memory protection modules, clock management modules (CMU) and reset management modules (GMU), etc. The memory data transmission device also includes a DMA interface and a data transmission management module, which is used to execute the memory data exchange and transmission processing method of the present invention.

[0033] Before data transmission using the memory data exchange and transmission processing method described in this invention, it is necessary to first plan the functional address in the memory. Typically, the size of the planned address is 2 to 3 times the amount of data accessed in a single operation, which is used as a double buffering mechanism (ping-pong). At the same time, the required function modules are called in the data processing module.

[0034] Specific Implementation Example 1. Partition and segment the memory array.

[0035] The first storage area, 0x0001_0000 ~ 0x0001_ffff, is set to 512KB. Data in this first storage area may be rearranged. The rearrangement process is executed by the function routing module in the data processing module. Data transmitted in this range will be arranged in a certain way. The reason for the rearrangement is that when data is input from device 1 to device 2, the data formats of the two devices may not be the same. It is necessary to rearrange the data stored in the format of device 1 into a format that can be stored by device 2.

[0036] A second storage area of ​​512KB, 0x0002_0000 ~ 0x0002_ffff, is set up. Audio data is stored in this second storage area after being processed by Fast Fourier Transform (fft). Input data is placed in the second storage area after being processed by fft. The Fast Fourier Transform is performed by the first mathematical operation module in the data processing module.

[0037] The third storage area (0x0003_0000~0x004_7fff) of 768KB is set up for filtering and then for FFT operation. The calculation module will combine the filtering and fast Fourier transform (FFT) operations, and then put the data back into the third storage area after the operation is completed. The filtering and FFT operations are performed by the second mathematical operation module in the data processing module.

[0038] For each storage area, the linked list needs to be edited, specifically as follows:

[0039] For the first memory area of ​​512KB, the range 0x0001_0000 ~ 0x0001_ffff, if the single data input size is 128KB, then

[0040] This section can be divided into 4 segments, resulting in the following linked list:

[0041] 1.0x0001_0000 ~ 0x0001_3fff

[0042] 2.0x0001_4000 ~ 0x0001_7fff

[0043] 3.0x0001_8000 ~ 0x0001_bfff

[0044] 4.0x0001_c000 ~ 0x0001_ffff

[0045] Once the first 128KB segment is full, a segment address of 0x001_4000 will be generated, which is the next address immediately following the end of the first segment. Similarly, the second and third segments will generate segment addresses of 0x0001_8000, 0x0001_c000, and 0x0002_0000, respectively.

[0046] For the 512KB second storage area segment 0x0002_0000 ~ 0x0002_ffff, if the single data input size is 256KB, this segment can be divided into 2 segments, resulting in the following linked list:

[0047] 1.0x0002_0000 ~ 0x0002_7fff

[0048] 2.0x0002_8000 ~ 0x0002_ffff

[0049] Once the first 256KB segment is filled, a segment address of 0x002_8000 will be generated, which is the next address immediately following the end of the first segment. Similarly, once the second 256KB segment is filled, the segment address generated will be 0x003_0000.

[0050] For a 768KB segment from 0x0003_0000 to 0x004_7fff, if the single input data size is 256KB, this segment can be divided into 3 segments, resulting in the following linked list:

[0051] 1.0x0003_0000 ~ 0x0003_7fff

[0052] 2.0x0003_8000 ~ 0x0003_ffff

[0053] 3.0x0004_0000 ~ 0x0004_7fff

[0054] Once the first 256KB segment is filled, a segment address of 0x0003_8000 will be generated, which is the next address immediately following the end of the first segment. This process continues, and after the second and third 256KB segments are filled, the resulting segment addresses will be 0x0004_0000 and 0x005_8000, respectively.

[0055] The linked list after segmenting the first, second, and third storage areas is shown in Figure 2. Specific Implementation

[0056] This embodiment performs data transmission according to the memory array segmentation method of specific embodiment 1, as shown in Figure 1. Taking the transmission of data from device 1 to device 2 as an example, the following explanation is provided:

[0057] Step 1. Based on the transmission purpose and characteristics of the transmitted data, partition and segment the memory array, and select the function modules to be called in the data processing module; and store the segmentation information of the memory array in the linked list information of the memory management module;

[0058] The segmentation information is determined based on the storage area to be accessed. For example, if the data needs to access the first, second, and third storage areas, then the segmentation information includes the addresses of all segments after these three storage areas are segmented.

[0059] In the segmentation information of the memory array described in step 1, each segment address is marked as a default available segment address;

[0060] In step 1, you can also set the cache level of the IO port cache module;

[0061] Step 2. Device 1 continuously inputs data packets into the IO port buffer module. According to the buffer level set in Step 1, when the data volume reaches the buffer level, data transmission from the IO port buffer module begins.

[0062] In step 2, while caching each data packet, as long as there is subsequent data, the address of the available segment at the beginning of the linked list information of the memory management module is stored in the linked list information of the data packet; if there is no subsequent data, the above operation of storing the available segment address is not performed.

[0063] For example, in Specific Embodiment 1, when the first storage area is segmented, the address of the first available segment is 0x0001_4000, which is the starting address of the second segment of the first storage area.

[0064] Step 3. Begin receiving data and parsing data packets, and set the subsequent data processing method based on the parsed information;

[0065] A typical data packet format is shown in Figure 3. Taking 32-bit data as an example, the first 32-bit data is the data packet header information, which includes basic information about this data transmission, such as the transmission path from device 1 to device 2, the format being 32-bit, and the I2S bus protocol being used. For example, a specific implementation of a data packet header information is as follows:

[0066] Input data for 0x1:I2S0

[0067] Input data for 0x2:I2S1

[0068] 0x3: Asynchronous sampling input data

[0069] 0x4: Device 1

[0070] 0x5: Device 2

[0071] 0x20: I2S0 data sent to device 1

[0072] 0x21: I2S1 data sent to device 1

[0073] 0x32: Asynchronous sampling of input data to device 2.

[0074] The second part, consisting of 32 bits of data, contains the linked list information to be used. It stores the address of the available segment stored in step 2. The linked list information is followed by the data to be transmitted.

[0075] In step 3, an interrupt arbitration signal is only required when the first data packet is input, and the start of data reception is determined based on the interrupt arbitration information; subsequent data packet inputs do not require an interrupt arbitration signal.

[0076] Step 4. Data Storage and Processing

[0077] Step 41. Based on the data packet header information parsed in Step 3 and the linked list information of the memory management module, determine whether there is a function operation. If so, execute the corresponding function operation and store the new data obtained after execution in the corresponding storage area. If it is found that no function operation is required, store the data directly in the corresponding storage area.

[0078] For example, in step 1, the address information and segmentation information of the first storage area have already been stored in the linked list information of the memory management module. In step 3, the parsed data has been segmented into 128-bit segments and needs to be rearranged first. Therefore, the received data packet is first rearranged by the data reassembly module before being stored in the first storage area.

[0079] If it is determined in step 3 that no rearrangement operation is required, the first 128-bit data packet received is directly stored in the first segment of the first storage area.

[0080] In step 41, since the function operation occupies the subsequent segment address, the occupied subsequent segment address is marked as unavailable in the linked list information of the memory management module;

[0081] In real-world scenarios, due to the lower limit of the data volume required for function operations, each data packet does not need to undergo function operations every time. At the same time, the data volume obtained after performing function operations can be stored in the storage area occupied by the original data, or it can be stored in the storage area corresponding to the new available segment address. It may be larger than the original data. When it is larger than the storage space occupied by the original data, the excess part is stored in the currently available storage area, such as the location adjacent to the original data storage area, and the segment address of the occupied part is marked as unavailable.

[0082] For example, assuming that a Fourier transform calculation requires at least 512 bits of data, but each data packet only has 128 bits, the first three data packets are not used for function calculations. Instead, they are directly stored in the first three segments of the first storage area. When the fourth data segment arrives, the data packet header is parsed and it is found that a Fourier transform calculation is required. The data processing module then retrieves the first three data packets from the first three segments of the first storage area and performs a Fourier transform calculation together with the currently received fourth data packet. The calculation result is then stored back in the first storage area. If the first storage area does not have enough space for the calculated result, it can be stored in the adjacent second storage area, and the occupied segment address of the second storage area is marked as unavailable.

[0083] Step 42. After the current data packet is stored, check whether the data packet's linked list information contains a segment address. If so, return to step 2 and continue to receive subsequent data packets. Execute steps 2 to 4 in sequence, and mark the obtained segment address as unavailable in the linked list information of the memory management module.

[0084] In step 2, the first data storage requires an interrupt arbitration signal to trigger storage. The data is stored in the first segment of the first storage area. After the first segment is full, in step 4, the parsing reveals that the linked list information of the second data packet has the address 0x001_4000, which is the next adjacent address after the first segment is full. Therefore, data transmission and processing automatically continue, and subsequent data packet storage no longer requires interrupt arbitration. This process continues until the next data packet is found to have not been transmitted. At this point, further data storage stops, and the currently stored data is processed and output. The system waits for the next interrupt signal to arrive before restarting storage.

[0085] If the segment address is not included, proceed to step 5.

[0086] In step 4, function operations and data transfer can be performed simultaneously. Function operations that require additional storage space can continue to occupy the available memory address ranges. To ensure smooth data transfer, unnecessary function operations can be avoided initially; for example, function operations that significantly increase the data volume after execution can be skipped.

[0087] Step 5. After the data transmission is completed, the data that was not fully processed during the data transmission process and is stored in various storage areas will continue to be processed by functions.

[0088] During function processing, the linked list information of the current memory management module is called again, and the processing result is stored in the segment corresponding to the address marked as an available segment.

[0089] After all data has been processed, wait for the next data transmission.

[0090] For example, the data is first rearranged by the data reorganization module before being stored in the first storage area;

[0091] The first mathematical operation module performs Fourier operations on the data stored in the first storage area, and then stores the data in the second storage area after the operation.

[0092] The second mathematical operation module performs filtering and Fourier operations on the data stored in the second storage area, and then stores the data in the third storage area after the operation.

[0093] Until all function operations have been executed.

[0094] In another specific implementation, the data is input from the DMA port. The difference from the previous embodiment is that step 2 does not require input to the IO port buffer module. The available segment address in the DMA port is stored in the linked list information of the data packet, and the process directly proceeds to step 3. The data packet header is parsed, and the data packet header can store the start address, destination address, data length, and whether burst mode is required for the DMA transfer.

[0095] When data is input from both the DMA port and an external device simultaneously, priorities can be preset. For example, data from the external device can be processed first, or data from the DMA port can be processed first.

[0096] When processing data, external devices first parse the data packets to determine which types of data should be prioritized, deferred, or interrupted. This avoids waiting for lower-priority data to finish processing before continuing; instead, it interrupts existing data processing based on priority and directly processes newer, higher-priority data. After setting priorities, multiple external devices can access the data simultaneously. If the external devices support multiplexing, some data can be processed by multiplexing system 1, and some by multiplexing system 2, providing greater flexibility in processing.

[0097] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a prerequisite for a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the scope of patent protection of the present invention. The scope of patent protection of the present invention shall still be determined by its claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention shall also be included within the scope of protection of the present invention.

Claims

1. A memory data exchange and transmission processing method, characterized in that, Includes the following steps: Step 1. Based on the transmission purpose and characteristics of the transmitted data, partition and segment the memory array, and select the function modules to be called in the data processing module; and store the segmentation information of the memory array in the linked list information of the memory management module; in the segmentation information of the memory array mentioned in Step 1, each segment address is marked as the default available segment address; Step 2. Input data into the IO port buffer module. When data input begins, an interrupt arbitration message needs to be issued. In Step 2, while buffering each data packet, as long as there is subsequent data, the address of the available segment at the beginning of the linked list information in the memory management module is stored into the linked list information of the data packet. If there is no subsequent data, the above operation of storing the available segment address is not performed. Step 3. Begin receiving data and parsing data packets, and set the subsequent data processing and storage methods based on the parsed information; Step 4. Data storage and processing; Step 41. Based on the data packet header information parsed in Step 3 and the linked list information of the memory management module, determine whether there is a function operation. If so, execute the corresponding function operation and store the new data obtained after execution in the corresponding storage area. If it is found that no function operation is required, store the data directly in the corresponding storage area. Step 42. After the current data packet is stored, check whether the data packet's linked list information contains a segment address. If so, return to step 2 and continue to receive subsequent data packets. Execute steps 2 to 4 in sequence, and mark the obtained segment address as unavailable in the linked list information of the memory management module. Step 5. After the data transmission is completed, continue to process the data that has not been processed during the data transmission and is stored in various storage areas; after all data has been processed, wait for the next data transmission.

2. The memory data exchange and transmission processing method as described in claim 1, characterized in that, Step 1 also includes setting the cache level of the IO port cache module; Step 2, based on the cache level set in Step 1, starts transmitting data from the IO port cache module when the data volume reaches the cache level.

3. The memory data exchange and transmission processing method as described in claim 1, characterized in that, In step 3, the decision to start data reception is only made based on the interruption arbitration information when the first data packet is input; subsequent data reception does not require the interruption arbitration signal.

4. The memory data exchange and transmission processing method as described in claim 1, characterized in that, In step 41, if a function operation occupies a subsequent segment address, the occupied subsequent segment address is marked as unavailable in the linked list information of the memory management module.

5. The memory data exchange and transmission processing method as described in claim 1, characterized in that, In step 41, no function operation is performed on data whose data volume increases after the function operation.

6. A memory data transmission device, characterized in that, The device includes a memory management module, a memory array, and a data processing module, and includes at least two I / O port buffer modules. The memory management module is used to partition and segment the memory array. The data processing module includes a function routing module and multiple function modules. The function routing module is used to plan the calling order of each function module. The memory data transmission device also includes a data transmission management module, which is used to execute the memory data exchange and transmission processing method according to any one of claims 1-5.

7. The memory data transmission device as claimed in claim 6, characterized in that, The memory management module also includes a memory protection module, a clock management module (CMU), and a reset management module (GMU).

8. The memory data transmission apparatus as described in claim 6, characterized in that, The memory data transfer device also includes a DMA interface.

Images