Daisy chain simulation board card and battery management system hardware-in-loop test method

Abstract

The invention discloses a daisy chain simulation board card and a battery management system hardware-in-the-loop test method, the daisy chain simulation board card is connected between a simulation control server and a BMS controller, test data sent by the simulation control server is received through a real-time communication module, the test data is cached in a cache module, and the cache module is connected with the BMS controller. The signal conversion module obtains a daisy chain instruction signal sent by the BMS controller and feeds back a daisy chain response signal to the BMS controller, the signal processing module analyzes the daisy chain instruction signal, and the read-write control module executes corresponding read-write operation on the cache module according to an analysis result. The daisy chain simulation board card can simulate a BMS slave board to communicate with a real BMS controller (a main board and / or slave board), BMS daisy chain communication simulation is achieved, the BMS daisy chain simulation board card is applied to HIL testing, the requirement for independent and rapid testing of the main board can be met, the development period of the BMS controller can be shortened, testing equipment can be simplified, and the equipment purchasing cost can be reduced.

Description

Technical Field

[0001] This application belongs to the field of battery management system technology, and particularly relates to a daisy chain simulation board and a hardware-in-the-loop testing method for a battery management system. Background Technology

[0002] Daisy-chain communication is a widely used communication technology in Battery Management Systems (BMS). It allows multiple analog front-end (AFE) chips to communicate in series, simplifying wiring and reducing costs. Besides communication between AFEs, daisy-chain communication has also replaced CAN communication between the BMS mainboard and slave boards, becoming a common communication method between BMS master and slave boards. This has facilitated the evolution of BMS architecture from a distributed to a centralized architecture, playing a crucial role in new energy vehicles and energy storage systems.

[0003] In the current mainstream centralized BMS architecture, the BMS motherboard and slave boards use daisy-chain communication, which is a proprietary communication method of major AFE manufacturers and is not universal. General bus testing tools cannot directly meet the testing requirements of BMS daisy-chain communication. Summary of the Invention

[0004] This application provides a daisy-chain simulation board and a hardware-in-the-loop testing method for a battery management system. The daisy-chain simulation board is used to simulate a BMS slave board and communicate with a real BMS controller (motherboard and / or slave board), realizing BMS daisy-chain communication simulation. Applying it to BMS hardware-in-the-loop testing can meet the testing requirements of BMS daisy-chain communication.

[0005] In a first aspect, embodiments of this application provide a daisy-chain simulation board for hardware-in-the-loop testing of a battery management system. The daisy-chain simulation board is connected between a simulation control server and a battery management system controller. The daisy-chain simulation board includes: A real-time communication module is used to connect to the simulation control server; A caching module, connected to the real-time communication module, is used to cache test data sent by the simulation control server; The signal conversion module is connected to the battery management system controller via a daisy-chain communication bus. It is used to acquire the daisy-chain command signal sent by the battery management system controller and convert the daisy-chain command signal into a first target waveform signal. A waveform processing module, connected to the signal conversion module, is used to analyze and process the first target waveform signal; A read / write control module is connected between the waveform processing module and the cache module. It is used to perform corresponding read / write operations on the cache module according to the parsing result of the first target waveform signal, and to transmit the generated response signal to the waveform processing module. The waveform processing module is also used to generate a second target waveform signal based on the response signal; The signal conversion module is also used to convert the second target waveform signal into a daisy-chain response signal and transmit it to the daisy-chain communication bus.

[0006] Secondly, embodiments of this application also provide a hardware-in-the-loop testing method for a battery management system, applied to the daisy-chain simulation board provided in the first aspect of this application, wherein the daisy-chain simulation board is connected between a simulation control server and a battery management system controller, and the method includes: The signal conversion module acquires the daisy-chain command signal sent by the battery management system controller and converts the daisy-chain command signal into a first target waveform signal. The first target waveform signal is analyzed and processed by the waveform processing module; Based on the parsing result of the first target waveform signal, the read / write control module performs corresponding read / write operations on the cache module and transmits the generated response signal to the waveform processing module. The waveform processing module generates a second target waveform signal based on the response signal. The signal conversion module converts the second target waveform signal into a daisy-chain response signal and transmits it to the daisy-chain communication bus.

[0007] Thirdly, embodiments of this application also provide a hardware-in-the-loop testing system for a battery management system, including: the daisy-chain simulation board provided in the first aspect of this application.

[0008] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the hardware-in-the-loop testing method for the battery management system provided in the second aspect of this application.

[0009] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects: The daisy-chain simulation board and battery management system hardware-in-the-loop testing method provided in this application embodiment connect the daisy-chain simulation board between the simulation control server and the BMS controller. It receives test data sent by the simulation control server through a real-time communication module and caches the test data in a cache module. A signal conversion module acquires the daisy-chain command signal sent by the BMS controller and sends back the daisy-chain response signal to the BMS controller. A signal processing module parses and processes the daisy-chain command signal. A read / write control module performs corresponding read / write operations on the cache module based on the parsing results. This enables the daisy-chain simulation board to simulate communication between the BMS slave board and the real BMS controller (main board and / or slave board), realizing BMS daisy-chain communication simulation. Applying this to BMS hardware-in-the-loop testing can meet the needs for independent and rapid testing of the main board, shortening the BMS controller development cycle, simplifying testing equipment, and reducing equipment procurement costs. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a daisy chain simulation board provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 3 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 5 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 6 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 7 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 8 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 9 This is a schematic diagram of the structure of a daisy chain simulation board provided in another embodiment of this application; Figure 10 This is a schematic flowchart of a hardware-in-the-loop testing method for a battery management system provided in one embodiment of this application. Detailed Implementation

[0012] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0013] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0014] With the development of new energy vehicles and energy storage industries, the number of individual cells in battery modules is increasing. If physical battery cells or battery cell simulation boards are used for BMS functional testing, there are disadvantages such as large test equipment size, complex equipment integration and use, and high procurement costs.

[0015] On the other hand, in a centralized BMS architecture, the mainboard and slave boards of the BMS controller communicate via a daisy-chain method. However, general bus testing tools cannot directly meet the testing requirements of BMS daisy-chain communication, such as the need for independent and rapid testing of the BMS mainboard. As the development speed of complete vehicles increases, the development cycle requirements for automotive electronic controllers are also becoming more stringent. Most OEMs are beginning to focus on using daisy-chain simulation testing tools to more quickly handle the functional development and testing of controllers. The demand is gradually increasing, but there are currently few successful cases of using daisy-chain simulation in the domestic market. Daisy-chain simulation testing tools applied to hardware-in-the-loop (HIL) testing are still an area to be explored.

[0016] To address the aforementioned technical issues, this application provides a daisy-chain simulation board and a hardware-in-the-loop testing method for a battery management system. The daisy-chain simulation board connects to a simulation control server and a BMS controller. It receives test data from the simulation control server via a real-time communication module and caches the test data in a cache module. A signal conversion module acquires daisy-chain command signals sent by the BMS controller and sends daisy-chain response signals back to the BMS controller. A signal processing module parses and processes the daisy-chain command signals. A read / write control module performs corresponding read / write operations on the cache module based on the parsing results. This enables the daisy-chain simulation board to simulate communication between the BMS slave board and the real BMS controller (motherboard and / or slave board), achieving BMS daisy-chain communication simulation. Applying this to BMS hardware-in-the-loop testing meets the need for independent and rapid testing of the motherboard, shortens the development cycle of the BMS controller, simplifies testing equipment, and reduces equipment procurement costs.

[0017] The daisy chain simulation board provided in the embodiments of this application will be introduced first.

[0018] Figure 1 A schematic diagram of the structure of a daisy-chain simulation board provided in one embodiment of this application is shown. Figure 1 As shown, the daisy-chain simulation board 100 is connected between the simulation control server 200 and the battery management system controller (hereinafter referred to as "BMS controller") 300, and is used for hardware-in-the-loop testing of the battery management system.

[0019] The daisy-chain simulation board 100 communicates with the simulation control server 200 via a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe). When using the daisy-chain simulation board 100 for Battery Management System (HIL) testing, the simulation control server 200 runs the driver and test software to call and control the daisy-chain simulation board 100. The daisy-chain simulation board 100 also communicates with the BMS controller via the daisy-chain communication bus, parsing and processing the received daisy-chain commands from the BMS controller and providing targeted responses.

[0020] The daisy-chain simulation board 100 includes a main control chip 101 and a transceiver chip 102. The daisy-chain simulation prototype is built in the firmware of the main control chip 101, and the transceiver chip is used as an auxiliary circuit to realize the mutual conversion between daisy-chain communication and SPI communication, realize the conversion of physical layer communication signals, and realize the overall daisy-chain communication simulation function.

[0021] As an example, the main control chip 101 may include a Field Programmable Gate Array (FPGA) chip, on which the AFE chip is simulated by programming based on a hardware description language, so that the daisy chain simulation board 100 can simulate the BMS slave board communicating with the BMS motherboard.

[0022] As an example, transceiver chip 102 may include NXP's MC33664 / MC33665 transceiver, TI's BQ79600 transceiver, and ADI's ADI6822.

[0023] The BMS controller 300 may include a BMS motherboard and BMS slave boards.

[0024] As an example, such as Figure 2 As shown, the daisy-chain simulation board 100 is connected between the simulation control server 200 and the BMS motherboard 310. The daisy-chain simulation board 100 and the BMS motherboard 310 are connected through a daisy-chain communication interface. This daisy-chain simulation board 100 is used to simulate the entire daisy-chain node to test the BMS motherboard. During HIL testing, this daisy-chain simulation board 100 simulates multiple BMS slave boards.

[0025] As an example, such as Figure 3 As shown, the daisy-chain simulation board 100 is connected between the simulation control server 200 and the BMS motherboard 310. The daisy-chain simulation board 100 and the BMS motherboard 310 are connected through two daisy-chain communication interfaces, which have a loopback mode. When communication fails at one node in the daisy chain, the entire link can be restored through the other daisy-chain communication interface.

[0026] As an example, such as Figure 4 As shown, the daisy-chain simulation board 100 is connected between the BMS motherboard 310 and the BMS slave board 320, and also connected to the simulation control server 200. This daisy-chain simulation board 100 is used to simulate local daisy-chain nodes (e.g., the starting node of the daisy chain) to test the BMS motherboard and BMS slave boards. During HIL testing, the daisy-chain simulation board 100 simulates one or more BMS slave boards.

[0027] As an example, such as Figure 5 As shown, the BMS slave board 320 is connected to the daisy-chain simulation board 100 and the BMS motherboard 310. The daisy-chain simulation board 100 is also connected to the simulation control server 200. This daisy-chain simulation board 100 is used to simulate local daisy-chain nodes (e.g., end nodes) to test the BMS motherboard and BMS slave boards. During HIL testing, the daisy-chain simulation board 100 simulates one or more BMS slave boards.

[0028] It should be noted that it is possible to... Figure 4 As shown, the daisy-chain simulation board 100 is set at the starting node of the daisy chain to simulate one or more BMS slave boards at the starting end of the daisy chain; it can also be used as follows: Figure 5 As shown, the daisy-chain simulation board 100 is set at the end node of the daisy chain to simulate one or more BMS slave boards at the end of the daisy chain; or the daisy-chain simulation board 100 is set at the middle node of the daisy chain to simulate one or more BMS slave boards between two BMS slave boards. When testing the BMS motherboard and BMS slave boards, the starting ID of the simulation node of the daisy-chain simulation board 100 needs to be set on the simulation control server 200.

[0029] As an example, such as Figure 1 As shown, the main control chip 01 and the transceiver chip 102 are connected through a serial peripheral interface (SPI).

[0030] The SPI interface of transceiver chip 102 may include two three-wire SPI interfaces or one four-wire SPI interface. Taking the two three-wire SPI interfaces as an example, they are the receive serial peripheral interface (i.e., RX_SPI) and the transmit serial peripheral interface (i.e., TX_SPI).

[0031] The daisy-chain simulation board 100 provided in this application embodiment can simulate communication between the BMS slave board and the real BMS controller. For example, it can simulate the communication behavior between the BMS slave board and the BMS motherboard, and between BMS slave boards. It realizes BMS daisy-chain communication simulation. When applied to BMS hardware-in-the-loop testing, it can meet the requirements for independent and rapid testing of the motherboard and help shorten the development cycle of the BMS controller 300.

[0032] In one embodiment, such as Figure 6 As shown, the daisy chain simulation board 100 may include: a real-time communication module 10, a cache module 20, a read / write control module 30, a waveform processing module 40, and a signal conversion module 50.

[0033] Among them, combined Figure 1 The real-time communication module 10, the cache module 20, the read / write control module 30, and the waveform processing module 40 are mounted on the main control chip 101, and the signal conversion module 50 is mounted on the transceiver chip 102.

[0034] The real-time communication module 10 is used to connect to the simulation control server 200, and is responsible for communicating with the simulation control server 200, transmitting test data sent by the simulation control server 200 to the cache module 20, and transmitting specified data cached on the cache module 20 back to the simulation control server 200. As an example, the real-time communication module 10 may include a PCIe real-time communication module.

[0035] The caching module 20 is connected to the real-time communication module 10 and is used to cache test data sent by the simulation control server 200. The test data may include battery data, simulation configuration data, and all data required for simulating the AFE chip. Battery data may include voltage, current, and temperature values ​​of individual battery cells. Simulation configuration data may include simulation mode, number of link nodes, number of individual node cells, and node temperatures. As an example, faults can also be injected at the software level through the simulation control server 200 to test the fault response function of the BMS controller.

[0036] The signal conversion module 50 is connected to the BMS controller 300 via a daisy-chain communication bus. It acquires the daisy-chain command signals sent by the BMS controller 300 and converts these signals into a first target waveform signal. As an example, the first target waveform signal is an SPI waveform signal.

[0037] The waveform processing module 40 is connected to the signal conversion module 50 and is used to analyze and process the first target waveform signal. The waveform processing module 40 analyzes and processes the first target waveform signal, converting it into instructions that can be recognized and executed by the read / write control module 30.

[0038] The read / write control module 30 is connected between the waveform processing module 40 and the cache module 20. It performs corresponding read / write operations on the cache module 20 based on the parsing result of the first target waveform signal, i.e., identifying the instruction corresponding to the first target waveform signal. After completing the corresponding read / write operation, the read / write control module 30 also generates a response signal and transmits it to the waveform processing module 40. The waveform processing module 40 then generates a second target waveform signal based on the response signal. As an example, the waveform processing module 40 encapsulates the response signal according to a predefined communication protocol and converts it into the second target waveform signal. The second target waveform signal may include an SPI waveform signal.

[0039] The waveform processing module 40 transmits the second target waveform signal to the signal conversion module 50, which converts the second target waveform signal into a daisy-chain response signal and transmits the daisy-chain response signal to the daisy-chain communication bus. The daisy-chain response signal can be transmitted to the BMS motherboard through the daisy-chain communication bus, thereby realizing communication between the daisy-chain simulation board 100 and the BMS motherboard.

[0040] When conducting independent testing of the BMS motherboard, the daisy chain simulation board 100 can simulate the entire daisy chain node, that is, replace all the BMS motherboards and corresponding battery cells on the daisy chain. It does not require the configuration of real BMS slave boards and battery cells, which simplifies the testing equipment and helps to reduce equipment procurement costs.

[0041] When testing BMS motherboards and BMS slave boards, the daisy chain simulation board 100 can simulate local daisy chain nodes, that is, replace part of the BMS motherboard and corresponding battery cells on the daisy chain. Only the BMS slave board under test and the corresponding battery cells need to be configured, which simplifies the testing equipment and helps to reduce equipment procurement costs.

[0042] This application provides a daisy-chain simulation board 100. The daisy-chain simulation board 100 receives test data sent by a simulation control server 200 through a real-time communication module 10 and caches the test data in a cache module 20. It acquires daisy-chain command signals sent by a BMS controller 300 through a signal conversion module 50 and sends daisy-chain response signals back to the BMS controller 300. A waveform processing module 40 parses and processes the daisy-chain command signals. A read / write control module 30 performs corresponding read / write operations on the cache module 20 based on the parsing results. This enables the daisy-chain simulation board 100 to simulate communication between a BMS slave board and a real BMS controller 300 (motherboard and / or slave board), realizing BMS daisy-chain communication simulation. Applying this to BMS hardware-in-the-loop testing can meet the needs for independent and rapid testing of the motherboard, shortening the development cycle of the BMS controller 300, simplifying testing equipment, and reducing equipment procurement costs.

[0043] In one embodiment, such as Figure 7 As shown, the waveform processing module 40 includes a waveform acquisition and processing module 41 and a waveform generation module 42. The waveform acquisition and processing module 41 and the waveform generation module 42 are respectively connected to the read and write control module 30 and to the signal conversion module 50.

[0044] The waveform acquisition and processing module 41 is used to analyze and process the first target waveform signal, and convert it into instructions that can be recognized and executed by the read and write control module 30.

[0045] The waveform generation module 42 receives the response signal transmitted by the read / write control module 30, generates a second target waveform signal based on the response signal, and transmits the target waveform signal to the signal conversion module 50. The signal conversion module 50 converts the second target waveform signal into a daisy-chain response signal and transmits the daisy-chain response signal to the daisy-chain communication bus, realizing the daisy-chain emulation board's response to the received daisy-chain command signal. That is, the daisy-chain emulation board simulates the interaction between the BMS slave board and the BMS motherboard. Simultaneously, the waveform acquisition and processing module and the waveform generation module are set up separately, allowing the two modules to operate independently and achieve parallel processing, avoiding mutual interference and influence, which is beneficial to improving the quality of data processing and signal generation.

[0046] In one embodiment, such as Figure 8 As shown, the waveform acquisition and processing module 41 includes a waveform acquisition unit 411, a parsing unit 412, and a processing unit; the waveform acquisition unit 411 is connected to the signal conversion module 50, the parsing unit 412 is connected between the waveform acquisition unit 411 and the processing unit, and the processing unit is connected to the read / write control module 30.

[0047] The waveform acquisition unit 411 is used to acquire and buffer the first target waveform signal and transmit the first target waveform signal to the analysis unit 412.

[0048] The parsing unit 412 is used to split and verify the first target waveform according to the provisions of the set communication protocol, extract the target information in the first target waveform signal, and transmit the target information to the processing unit.

[0049] The processing unit converts target information into target instructions and sends the target instructions to the read / write control module 30. The target instructions can be recognized by the read / write control module 30, and in response to the target instructions, the read / write control module 30 performs corresponding read / write operations on the cache module 20. As an example, the target instructions include a data acquisition instruction for acquiring the temperature value of the battery cell at node X. The read / write control module 30 reads the temperature value of the corresponding battery cell cached on the cache module 20, generates a response signal based on the read temperature value, and transmits the response signal to the waveform generation module 42, which generates a second target waveform based on the response signal.

[0050] For example, such as Figure 8As shown, the signal conversion module 50 converts the daisy-chain instruction signal into a first target waveform signal (SPI waveform signal), and transmits the first target waveform signal to the waveform acquisition unit 411 through the RX_SPI interface. The waveform acquisition unit 411 acquires high and low levels bit by bit and stores the acquired level data in a designated register. After acquiring one frame, the data stored in the register is transmitted to the parsing unit 412, which extracts the target information according to the bit field according to the set communication protocol. The parsing unit 412 also has a Cyclic Redundancy Check (CRC) function; it will only proceed to the next step if the CRC check passes. If the CRC check fails, a CRC error indication is output. The processing unit converts the target information into a target instruction that can be recognized and executed by the read / write control module 30.

[0051] In one embodiment, such as Figure 8 As shown, the processing unit includes a first processing unit 413, the cache module 20 includes a first cache unit 21, and the read / write control module 30 includes a first read / write control unit 31. The first processing unit 413 is connected to the first read / write control unit 31, and the first read / write control unit 31 is connected to the first cache unit 21.

[0052] The target commands include motherboard commands, which are control commands sent by the BMS motherboard. For example, a data acquisition command is used to collect data such as the voltage, current, and temperature of individual battery cells. Another example is an online query command, used to confirm whether the connection to the BMS slave board is normal.

[0053] In this embodiment, the first processing unit 413 is used to transmit motherboard instructions to the first read / write control unit 31, and the first read / write control unit 31 performs corresponding read / write operations on the first cache unit 21.

[0054] In one embodiment, such as Figure 9 As shown, the cache module 20 also includes a second cache unit 22, and the read / write control module 30 also includes a second read / write control unit 32; the first processing unit 413 is connected to the second read / write control unit 32, the second read / write control unit 32 is connected to the first cache unit 21 and the second cache unit 22 respectively, and the second cache unit 22 is connected to the real-time communication module 10.

[0055] The cache module 20 includes a first cache unit 21 and a second cache unit 22. The first cache unit 21 is used to simulate the internal registers of the AFE chip and is a cache area with the largest opening depth. The second cache unit 22 is used to cache battery data sent by the simulation control server 200 during HIL testing, such as the voltage, current and temperature values ​​of individual battery cells.

[0056] The motherboard instructions include acquisition instructions. The first processing unit 413 is used to transmit the acquisition instructions to the first read / write control unit 31 and the second read / write control unit 32. The second read / write control unit 32 reads the battery data cached in the second cache unit 22 and writes the battery data into the first cache unit 21. Then, the first read / write control unit 31 reads the battery data on the first cache unit 21.

[0057] For example, the second read / write control unit 32 is configured to continuously detect whether the BMS motherboard enables the AFE chip to collect battery data (i.e., the collection instruction). If the collection instruction is detected, the battery data of the corresponding battery cell stored in the second cache unit 22 is read and the read battery data is written to the first cache unit 21.

[0058] This embodiment uses dual buffers and an independent read / write control unit to separate the data acquisition end (i.e., the second buffer unit 22) and the data output end (i.e., the first buffer unit 21), thereby achieving parallel processing of "acquisition-transmission". When the second buffer unit 22 continuously receives new battery data, the first buffer unit 21 simultaneously outputs the stored historical data to the outside, avoiding the delay caused by buffering and optimizing the data update rate.

[0059] In one embodiment, such as Figure 8 or Figure 9 As shown, the first read / write control unit 31 is connected to the waveform generation module 42; the first read / write control unit 31 is also used to transmit the generated response signal to the waveform generation module 42 after performing the corresponding read / write operation on the first cache unit 21, and the waveform generation module 42 generates the corresponding second target waveform signal according to the response signal.

[0060] For example, for the read command of the BMS motherboard, the first read / write control unit 31 reads the response data in the first cache module and generates the corresponding response signal; the waveform generation module 42 generates the corresponding second target waveform signal according to the response signal, and then the signal conversion module 50 converts the second target waveform signal into a daisy-chain response signal to realize the feedback of response data to the BMS motherboard.

[0061] In one embodiment, such as Figure 8 As shown in Figure 9, the waveform generation module 42 also includes an encapsulation unit 421 and a waveform transmission unit 422; the encapsulation unit is connected to the first read / write control unit 31, and the waveform transmission unit 422 is connected between the encapsulation unit 421 and the signal conversion module 50.

[0062] In this embodiment, the first read / write control unit 31 transmits the response signal to the register corresponding to the encapsulation unit 421. The encapsulation unit 421 reads the response data in the register, encapsulates the response data into a frame structure according to the set communication protocol, and stores the encapsulated frame data packet in a designated register; then, it triggers the waveform sending unit 422 to serialize the frame data packet in the register bit by bit, and generates high and low level waveform signals (i.e., SPI waveform signals) on the pins, and transmits the SPI waveform signals to the signal conversion module 50 through the TX_SPI interface.

[0063] For example, the frame structure encapsulation process may include adding a frame start flag, filling address codes, writing valid waveform data, calculating and appending CRC check bits, and adding a frame end flag, ultimately generating a complete frame data packet that conforms to the protocol specification.

[0064] In one embodiment, such as Figure 8 As shown in Figure 9, the processing unit further includes a second processing unit 414, the cache module 20 further includes a third cache unit 23, and the read / write control module 30 further includes a write control unit 33; the write control unit 33 is connected between the second processing unit 414 and the third cache unit 23, and the third cache unit 23 is connected to the real-time communication module 10.

[0065] The target information includes response information, the target instruction includes board response instruction, and the second processing unit 414 is used to transmit the board response instruction to the write control unit 33, and the write control unit 33 writes the response information to the third buffer unit 23.

[0066] For example, the third cache unit 23 is used to cache battery data extracted from the daisy-chain response signal, such as the voltage, current and temperature values ​​of individual battery cells, and transmit the extracted data back to the simulation control server 200 through the real-time communication module 10.

[0067] In this embodiment, the signal conversion module 50 is also used to acquire the daisy-chain response signal in the daisy-chain communication bus and convert the daisy-chain response signal into an SPI waveform signal. Following the same processing path as the daisy-chain instruction signal, the SPI waveform signal is acquired and parsed. When the extracted target information is determined to be response information, the second processing unit 414 generates a slave board response instruction based on the response information, and the control unit 33 writes the response information to the third buffer unit 23 according to the slave board response instruction. By re-acquiring the daisy-chain response signal sent by the daisy-chain simulation board 100, it is possible to verify whether the daisy-chain response signal was successfully sent. The re-acquired response information can also be compared with the acquired response data to verify the integrity and consistency of the data.

[0068] In one embodiment, such as Figure 8As shown in Figure 9, the cache module 20 also includes a fourth cache unit 24, which is connected to the real-time communication module 10. The fourth cache unit 24 is used to cache the configuration data sent by the simulation control server 200.

[0069] Users can input configuration data through the interactive interface of the simulation control server 200. Configuration data may include simulation mode, number of link nodes, number of individual nodes, and node temperatures, etc.

[0070] In one embodiment, such as Figure 7 As shown, the daisy chain simulation board 100 may also include: a simulation front-end working status management module.

[0071] The simulation front-end working status management module 60 is connected to the waveform acquisition and processing module 41 and the waveform generation module 42 respectively; the simulation front-end working status management module 60 is used to control the working status of the daisy chain simulation board 100.

[0072] In this embodiment, the simulated front-end working state management module 60 constructs a state machine according to the working state specified in the AFE chip manual, and performs real-time control and management of the working state of the daisy chain simulation board 100.

[0073] For example, the analog front-end working status management module 60 can parse the signals received from the waveform acquisition and processing module 41, identify the instructions and data contained therein, and update its own working status. The analog front-end working status management module 60 can also send instructions to the waveform generation module 42 according to its own working status and the received external instructions, so that the waveform generation module 42 generates a specific SPI waveform signal.

[0074] In one embodiment, for daisy-chain communication with addressing mode, the daisy-chain emulation board further includes an address generation module. The address generation module is used to assign virtual addresses to each emulation node device according to the configured emulation mode, so that the BMS motherboard can accurately communicate with each emulation node.

[0075] Based on the same inventive concept, this application also provides a hardware-in-the-loop testing system for a battery management system, including the daisy-chain simulation board provided in the above embodiments, which has corresponding beneficial effects, and will not be described in detail here.

[0076] Based on the same inventive concept, this application also provides a hardware-in-the-loop testing method for a battery management system, applied to the daisy-chain simulation board provided in the above embodiments.

[0077] like Figure 10 As shown, the hardware-in-the-loop testing method for the battery management system may include the following steps: S110~S150.

[0078] S110. Obtain the daisy-chain command signal sent by the battery management system controller through the signal conversion module, and convert the daisy-chain command signal into the first target waveform signal.

[0079] Combination Figure 6 The signal conversion module 50 is connected to the BMS controller 300 via a daisy-chain communication bus.

[0080] In this step, during the HIL test, the signal conversion module 50 receives the daisy-chain command signal sent by the BMS controller 300, converts the daisy-chain command signal into a first target waveform signal, and transmits the first target waveform signal to the waveform processing module 40. As an example, the first target waveform signal is an SPI waveform signal.

[0081] S120. The first target waveform signal is analyzed and processed by the waveform processing module.

[0082] Combination Figure 6 The waveform processing module 40 is connected to the signal conversion module 50.

[0083] In this step, the waveform processing module 40 analyzes and processes the first target waveform signal, converting it into instructions that can be recognized and executed by the read / write control module 30.

[0084] S130. The read / write control module performs corresponding read / write operations on the cache module based on the parsing results of the first target waveform signal, and transmits the generated response signal to the waveform processing module.

[0085] Combination Figure 6 The read / write control module 30 is connected between the waveform processing module 40 and the cache module 20.

[0086] In this step, the read / write control module 30 performs corresponding read / write operations on the cache module 20 based on the parsing result of the first target waveform signal, i.e., the instruction corresponding to the first target waveform signal. After the corresponding read / write operations are completed, the read / write control module 30 also generates a response signal and transmits the response signal to the waveform processing module 40.

[0087] S140. The waveform processing module generates a second target waveform signal based on the response signal.

[0088] In this step, the waveform processing module 40 generates a second target waveform signal based on the response signal. As an example, the waveform processing module 40 encapsulates the response signal according to a predefined communication protocol and converts it into the second target waveform signal. The second target waveform signal may include an SPI waveform signal.

[0089] S150: The second target waveform signal is converted into a daisy-chain response signal through the signal conversion module and transmitted to the daisy-chain communication bus.

[0090] In this step, the signal conversion module 50 converts the second target waveform signal into a daisy-chain response signal and transmits the daisy-chain response signal to the daisy-chain communication bus. The daisy-chain response signal can be transmitted to the BMS motherboard through the daisy-chain communication bus, thereby realizing the communication between the daisy-chain simulation board 100 and the BMS motherboard.

[0091] When conducting independent testing of the BMS motherboard, the daisy chain simulation board 100 can simulate the entire daisy chain node, that is, replace all the BMS motherboards and corresponding battery cells on the daisy chain. It does not require the configuration of real BMS slave boards and battery cells, which simplifies the testing equipment and helps to reduce equipment procurement costs.

[0092] When testing BMS motherboards and BMS slave boards, the daisy chain simulation board 100 can simulate local daisy chain nodes, that is, replace part of the BMS motherboard and corresponding battery cells on the daisy chain. Only the BMS slave board under test and the corresponding battery cells need to be configured, which simplifies the testing equipment and helps to reduce equipment procurement costs.

[0093] The battery management system hardware-in-the-loop testing method provided in this application embodiment is applied to the daisy-chain simulation board provided in the above embodiment of this application. It receives test data sent by the simulation control server through a real-time communication module and caches the test data in a cache module. A signal conversion module acquires the daisy-chain command signal sent by the BMS controller and sends back the daisy-chain response signal to the BMS controller. A signal processing module parses and processes the daisy-chain command signal. A read / write control module performs corresponding read / write operations on the cache module based on the parsing results. This enables the daisy-chain simulation board to simulate communication between the BMS slave board and the real BMS controller (motherboard and / or slave board), realizing BMS daisy-chain communication simulation. Applying this method to BMS hardware-in-the-loop testing can meet the need for independent and rapid testing of the motherboard, shortening the development cycle of the BMS controller and simplifying testing equipment, thus reducing equipment procurement costs.

[0094] In one embodiment, such as Figure 7 As shown, the waveform processing module 40 includes a waveform acquisition and processing module 41 and a waveform generation module 42.

[0095] Accordingly, S120 may include the following steps: using a waveform acquisition and processing module to analyze and process the first target waveform signal.

[0096] S140 may include the following steps: the waveform generation module is used to generate a second target waveform signal based on the response signal.

[0097] In this embodiment, the waveform acquisition and processing module 41 parses and processes the first target waveform signal, converting it into instructions that can be recognized and executed by the read / write control module 30. The read / write control module 30 executes the corresponding read / write operation according to the instructions and generates a response signal, which is transmitted to the waveform generation module 42. The waveform generation module 42 receives the response signal transmitted by the read / write control module 30, generates a second target waveform signal based on the response signal, and transmits the target waveform signal to the signal conversion module 50. The signal conversion module 50 converts the second target waveform signal into a daisy-chain response signal and transmits the daisy-chain response signal to the daisy-chain communication bus, realizing the daisy-chain emulation board's response to the received daisy-chain instruction signal, that is, the daisy-chain emulation board simulates the interaction between the BMS slave board and the BMS motherboard.

[0098] In one embodiment, such as Figure 9 As shown, the waveform acquisition and processing module 41 includes a waveform acquisition unit 411, a parsing unit 412, and a first processing unit 413. The waveform acquisition unit 411 is connected to the signal conversion module 50, and the parsing unit 412 is connected between the waveform acquisition unit 411 and the processing unit. The cache module 20 includes a first cache unit 21 and a second cache unit. The read / write control module 30 includes a first read / write control unit 31 and a second read / write control unit. The first read / write control unit 31 is connected between the first processing unit 413 and the first cache unit 21, and the second read / write control unit 32 is connected between the first processing unit 413 and the second cache unit 22. The first cache unit 21 is used to simulate the internal registers of the AFE chip and is a cache area with the largest opening depth. The second cache unit 22 is used to cache battery data sent by the simulation control server 200 during HIL testing, such as the voltage, current, and temperature values ​​of individual battery cells.

[0099] Accordingly, the motherboard instructions include acquisition instructions. The step S130, "by using the read / write control module to perform corresponding read / write operations on the cache module based on the analysis results of the first target waveform signal," may include the following steps: The second read / write control unit reads the battery data cached in the second cache unit and writes the battery data into the first cache unit; The battery data on the first cache unit is read by the first read / write control unit.

[0100] This embodiment uses dual buffers and an independent read / write control unit to separate the data acquisition end (i.e., the second buffer unit 22) and the data output end (i.e., the first buffer unit 21), thereby achieving parallel processing of "acquisition-transmission". When the second buffer unit 22 continuously receives new battery data, the first buffer unit 21 simultaneously outputs the stored historical data to the outside, avoiding the delay caused by buffering and optimizing the data update rate.

[0101] In one embodiment, such as Figure 8 or Figure 9 As shown, the processing unit also includes a second processing unit 414, the cache module 20 also includes a third cache unit 23, and the read / write control module 30 also includes a write control unit 33; the write control unit 33 is connected between the second processing unit 414 and the third cache unit 23, and the third cache unit 23 is connected to the real-time communication module 10.

[0102] The target information includes response information, and the target instructions include response instructions from the board. Accordingly, the battery management system hardware-in-the-loop testing method also includes the following steps: The daisy-chain response signal in the daisy-chain communication bus is obtained through the signal conversion module; The waveform acquisition and processing module acquires and analyzes the target waveform signal corresponding to the daisy chain response signal. When it is determined that the extracted target information is response information, the second processing unit 414 generates a slave board response command based on the response information. The control unit 33 writes the response information to the third buffer unit 23 according to the slave board response command.

[0103] The hardware-in-the-loop testing method for the battery management system provided in this application verifies whether the daisy-chain response signal sent by the daisy-chain simulation board 100 has been successfully sent by retrieving the daisy-chain response signal. It can also compare the retrieved response information with the collected response data to verify the integrity and consistency of the data.

[0104] Furthermore, in conjunction with the hardware-in-the-loop testing method for the battery management system described in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the hardware-in-the-loop testing methods for the battery management system described in the above embodiments.

[0105] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0106] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable-ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0107] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0108] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0109] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A daisy-chain simulation board for hardware-in-the-loop testing of a battery management system, characterized in that, The daisy-chain simulation board is connected between the simulation control server and the battery management system controller. The daisy-chain simulation board includes: A real-time communication module is used to connect to the simulation control server; A caching module, connected to the real-time communication module, is used to cache test data sent by the simulation control server; The signal conversion module is connected to the battery management system controller via a daisy-chain communication bus. It is used to acquire the daisy-chain command signal sent by the battery management system controller and convert the daisy-chain command signal into a first target waveform signal. A waveform processing module, connected to the signal conversion module, is used to analyze and process the first target waveform signal; A read / write control module is connected between the waveform processing module and the cache module. It is used to perform corresponding read / write operations on the cache module according to the parsing result of the first target waveform signal, and to transmit the generated response signal to the waveform processing module. The waveform processing module is also used to generate a second target waveform signal based on the response signal; The signal conversion module is also used to convert the second target waveform signal into a daisy-chain response signal and transmit it to the daisy-chain communication bus.

2. The daisy-chain simulation board according to claim 1, characterized in that, The waveform processing module includes a waveform acquisition and processing module and a waveform generation module; The waveform acquisition and processing module and the waveform generation module are respectively connected to the read and write control module and to the signal conversion module; The waveform acquisition and processing module is used to analyze and process the first target waveform signal; The waveform generation module is used to generate a second target waveform signal based on the response signal.

3. The daisy-chain simulation board according to claim 2, characterized in that, The waveform acquisition and processing module includes a waveform acquisition unit, a parsing unit, and a processing unit; The waveform acquisition unit is connected to the signal conversion module, the parsing unit is connected between the waveform acquisition unit and the processing unit, and the processing unit is connected to the read / write control module. The waveform acquisition unit is used to acquire and buffer the first target waveform signal, and transmit the first target waveform signal to the parsing unit; The parsing unit is used to split and verify the first target waveform according to the provisions of the set communication protocol, extract the target information in the first target waveform signal, and transmit the target information to the processing unit; The processing unit is used to convert the target information into target instructions and send the target instructions to the read / write control module.

4. The daisy-chain simulation board according to claim 3, characterized in that, The processing unit includes a first processing unit, the cache module includes a first cache unit, and the read / write control module includes a first read / write control unit. The first processing unit is connected to the first read / write control unit, and the first read / write control unit is connected to the first cache unit. The target instruction includes a motherboard instruction. The first processing unit is used to transmit the motherboard instruction to the first read / write control unit, and the first read / write control unit performs the corresponding read / write operation on the first cache unit.

5. The daisy-chain simulation board according to claim 4, characterized in that, The cache module further includes a second cache unit, and the read / write control module further includes a second read / write control unit; The first processing unit is connected to the second read / write control unit, the second read / write control unit is connected to the first cache unit and the second cache unit respectively, and the second cache unit is connected to the real-time communication module; The motherboard instructions include acquisition instructions. The first processing unit is used to transmit the acquisition instructions to the first read / write control unit and the second read / write control unit. The second read / write control unit reads the battery data cached in the second cache unit and writes the battery data into the first cache unit. Then, the first read / write control unit reads the battery data on the first cache unit.

6. The daisy-chain simulation board according to claim 4 or 5, characterized in that, The first read / write control unit is connected to the waveform generation module; The first read / write control unit is further configured to transmit the generated response signal to the waveform generation module after performing the corresponding read / write operation on the first cache unit, and the waveform generation module generates the corresponding second target waveform signal according to the response signal.

7. The daisy-chain simulation board according to claim 6, characterized in that, The waveform generation module further includes an encapsulation unit and a waveform transmission unit; The encapsulation unit is connected to the first read / write control unit, and the waveform transmission unit is connected between the encapsulation unit and the signal conversion module.

8. The daisy-chain simulation board according to claim 3, characterized in that, The processing unit further includes a second processing unit, the cache module further includes a third cache unit, and the read / write control module further includes a write control unit; The write control unit is connected between the second processing unit and the third cache unit, and the third cache unit is connected to the real-time communication module. The target information includes response information, and the target instruction includes a slave board response instruction. The second processing unit is used to transmit the slave board response instruction to the write control unit, and the write control unit writes the response information to the third cache unit.

9. The daisy-chain simulation board according to claim 8, characterized in that, Also includes: Simulates front-end working status management module; The simulated front-end working status management module is connected to the waveform acquisition and processing module and the waveform generation module respectively; the simulated front-end working status management module is used to control the working status of the daisy-chain simulation board. The caching module further includes a fourth caching unit, which is connected to the real-time communication module and is used to cache the configuration data sent by the simulation control server.

10. A hardware-in-the-loop testing method for a battery management system, characterized in that, The method, applied to the daisy-chain simulation board as described in any one of claims 1-9, wherein the daisy-chain simulation board is connected between the simulation control server and the battery management system controller, comprises: The signal conversion module acquires the daisy-chain command signal sent by the battery management system controller and converts the daisy-chain command signal into a first target waveform signal. The first target waveform signal is analyzed and processed by the waveform processing module; Based on the parsing result of the first target waveform signal, the read / write control module performs corresponding read / write operations on the cache module and transmits the generated response signal to the waveform processing module. The waveform processing module generates a second target waveform signal based on the response signal. The signal conversion module converts the second target waveform signal into a daisy-chain response signal and transmits it to the daisy-chain communication bus.

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