Pixel circuit and display device including same

Abstract

A pixel circuit according to an embodiment and a display device including the same are disclosed. The pixel circuit includes: a light emitting element; a first driving element configured to drive the light emitting element; a second driving element configured to drive the first driving element; a capacitor connected to a gate electrode of the second driving element; a first switching element configured to apply a data voltage to a second electrode of the capacitor; a second switching element configured to apply an off voltage to the first electrode of the capacitor; a third switching element connected between the first electrode of the capacitor and the first electrode of the second driving element; a fourth switching element configured to apply a pixel ground voltage to the first electrode of the second driving element; a fifth switching element configured to apply a pixel driving voltage to a second electrode of the second driving element; and a sixth switching element connected between the light emitting element and the first driving element.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0131581, filed on September 27, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to pixel circuits and display devices including such pixel circuits. Background Technology

[0004] Various flat panel display devices are known, such as liquid crystal displays (LCDs) and electroluminescent displays (EMDs). EMDs display input images by emitting light themselves without backlighting, using light-emitting elements located on each pixel within the pixel. Based on the material of the light-emitting layer, the light-emitting elements of EMDs can be classified into organic and inorganic light-emitting elements.

[0005] Recently, display devices using light-emitting diodes (LEDs) (inorganic light-emitting elements) as pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect the organic materials from moisture, and they are more reliable and have a longer lifespan than organic light-emitting diodes (OLEDs). In addition, LEDs offer fast illumination speed, excellent luminous efficiency, and shock resistance. Summary of the Invention

[0006] Each of the multiple pixels includes a driving element that controls the driving current flowing through the light-emitting element based on a voltage (Vgs) applied between the gate electrode and the source electrode. The electrical characteristics of the driving element may deteriorate over time and vary from pixel to pixel.

[0007] Furthermore, since the light emission time of the light-emitting element is controlled by using the driving current, it is difficult to utilize the light-emitting element only within its maximum efficiency range, thus driving the light-emitting element with high power consumption.

[0008] This disclosure aims to address all the aforementioned necessities and issues.

[0009] This disclosure provides a pixel circuit capable of reducing power consumption and a display device including the pixel circuit.

[0010] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0011] A pixel circuit according to embodiments of the present disclosure may include: a light-emitting element; a first driving element configured to drive the light-emitting element; a second driving element configured to drive the first driving element; a capacitor connected to the gate electrode of the second driving element; a first switching element configured to apply a data voltage to a second electrode of the capacitor; a second switching element configured to apply a turn-off voltage to the first electrode of the capacitor; a third switching element connected between the first electrode of the capacitor and the first electrode of the second driving element; a fourth switching element configured to apply a pixel ground voltage to the first electrode of the second driving element; a fifth switching element configured to apply a pixel driving voltage to the second electrode of the second driving element; and a sixth switching element connected between the light-emitting element and the first driving element.

[0012] A display device according to embodiments of the present disclosure may include: a pixel array, wherein a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output data voltages to the plurality of data lines; and a gate driver configured to output gate signals to the plurality of gate lines, wherein each pixel circuit in the pixel circuit includes: a light-emitting element; a first driving element for driving the light-emitting element; a second driving element for driving the first driving element; a capacitor connected to the gate electrode of the second driving element; a first switching element configured to apply a data voltage to a second electrode of the capacitor; a second switching element configured to apply a turn-off voltage to the first electrode of the capacitor; a third switching element connected between the first electrode of the capacitor and the first electrode of the second driving element; a fourth switching element configured to apply a pixel ground voltage to the first electrode of the second driving element; a fifth switching element configured to apply a pixel driving voltage to the second electrode of the second driving element; and a sixth switching element connected between the light-emitting element and the first driving element.

[0013] In this disclosure, a first driving element for driving a light-emitting element and a second driving element for driving the first driving element are configured, and the on-time of the second driving unit for turning off the first driving element is controlled by using a data voltage, thereby enabling the maximum efficiency range to be utilized by adjusting the light-emitting time of the light-emitting element according to the data voltage.

[0014] In this disclosure, the first driving element is used as a switching element, and the threshold voltage of the second driving element is compensated so that the emission time of the light-emitting element can be controlled by using data voltages that are unbiased between pixels.

[0015] In this disclosure, PWM drive can be applied based on the maximum efficiency range of the light-emitting element.

[0016] Low-power driving is possible in this disclosure because the maximum efficiency range of the light-emitting element is used.

[0017] The effects of this specification are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description and the appended claims other effects not mentioned. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure;

[0021] Figure 3 It is shown Figure 2 The diagram shows the driving timing of the pixel circuit.

[0022] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E It is used to describe according to Figure 3 A diagram illustrating the operating principle of a pixel circuit;

[0023] Figure 5A and Figure 5B It is a graph used to describe the emission time according to the data voltage;

[0024] Figure 6 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure;

[0025] Figure 7 It is shown Figure 6 The diagram shows the driving timing of the pixel circuit; and

[0026] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E It is used to describe according to Figure 7 A diagram illustrating the operating principle of a pixel circuit. Detailed Implementation

[0027] The advantages and features of this specification, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below, and may be implemented in different forms. The embodiments are provided only to fully disclose this disclosure and to fully convey the scope of this disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0028] Since the shapes, dimensions, scales, angles, numbers, etc., disclosed in the drawings used to describe embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same parts. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the essential points of this disclosure.

[0029] When using terms such as "comprising," "having," or "consisting of" as used in this specification, additional parts may be added unless "only" is used. Unless otherwise expressly stated, the singular form of a component includes the plural form.

[0030] When explaining components, it should be understood that the tolerance range is included, even in the absence of a separate, explicit description.

[0031] When describing positional relationships, such as when the positional relationship between two parts is described as "on top of", "above", "below", "adjacent to", etc., one or more other parts may be located between the two parts unless "immediately following" or "directly" is used.

[0032] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical spirit of this disclosure, the first component mentioned below can also be the second component.

[0033] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0034] The following implementations can be combined or integrated with each other in part or in whole, and can be linked and operated in various technical ways. The implementations can be performed independently or in conjunction with each other.

[0035] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0036] In the display device disclosed herein, the pixel circuit and gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs, etc.

[0037] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage.

[0038] A transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage, and the gate off-voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage, and the gate off-voltage can be a high gate voltage.

[0039] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1 The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0041] The display panel 100 may be, but is not limited to, a panel with a rectangular structure, having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a heterogeneous panel, at least a portion of which is curved or elliptical.

[0042] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. These power lines may be commonly connected to pixel circuitry to supply the voltage required to drive the pixels 101.

[0043] Each pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gate lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0044] Pixels can be arranged as real-color pixels and pentile pixels. By driving two sub-pixels with different colors as a single pixel 101 and using a preset pixel rendering algorithm, pentile pixels can achieve a higher resolution than real-color pixels. This pixel rendering algorithm can compensate for the inadequacy of color representation in each pixel by utilizing the colors of light emitted from neighboring pixels.

[0045] The display area AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in a pixel line share a gate line 103. Sub-pixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal period is the time obtained by dividing a frame period by the total number of pixel lines L1 to Ln.

[0046] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device where an image is displayed on a screen and the actual object in the background is visible. The display panel 100 can be made of a flexible display panel.

[0047] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of the display panel driving circuitry. Gate on-state voltage and gate off-state voltage can be supplied to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be supplied to pixel 101 via a power line commonly connected to pixel 101.

[0048] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0049] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is not shown. The data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0050] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive a gamma reference voltage and generate a gamma compensation voltage for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is supplied to a digital-to-analog converter (hereinafter referred to as "DAC") disposed in each channel of the data driver 110.

[0051] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage for the pixel data.

[0052] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gate driver 120 may be disposed in at least one of the left and right non-display areas NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0053] Under the control of timing controller 130, gate driver 120 sequentially outputs gate signal pulses to gate line 103. Gate driver 120 can sequentially supply gate signals to gate line 103 by shifting the gate signal pulses using shift registers. When multiple gate signals are applied to each pixel, gate driver 120 may include multiple shift registers. Gate signals may include light emission signals (or EM signals) and scan signals input to pixel circuitry through multiple gate lines.

[0054] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal period (1H).

[0055] The timing controller 130 can control the display panel driving circuit by generating data timing control signals for controlling the operation timing of the data driver 110 and gate timing control signals for controlling the operation timing of the gate driver 120 based on timing signals Vsync, Hsync, and DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0056] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into the swing width between the gate turn-on voltage and the gate turn-off voltage, and supply it to the gate driver 120.

[0057] The host system 300 may include a motherboard from one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, and wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it to the timing controller 130 along with timing signals.

[0058] Figure 2 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure. Figure 3 It is shown Figure 2 The diagram shows the driving timing of the pixel circuit. Figures 4A to 4E It is used to describe according to Figure 3 A diagram illustrating the operating principle of the pixel circuit, and Figure 5A and Figure 5B It is a graph used to describe the emission time according to the data voltage.

[0059] Reference Figure 2 and Figure 3 The pixel circuit according to a first embodiment of this disclosure includes a light-emitting element (LD), a first driving element DT1 and a second driving element DT2 supplying current to the light-emitting element LD, a plurality of switching elements T1, T2, T3, T4, T5 and T6 switching the current path connected to the first driving element DT1, a first capacitor Cst and a second capacitor C2. The first driving element DT1, the second driving element DT2 and the switching elements T1, T2, T3, T4, T5 and T6 can be implemented using n-channel transistors, but are not limited thereto.

[0060] A light-emitting element (LD) may include an anode electrode, a cathode electrode, and a light-emitting layer. The cathode electrode of the LD may be connected to a first power line PL1 to which a pixel driving voltage EVDD is applied. The anode electrode of the LD may be connected to a first driving element DT1. The LD may be, but is not limited to, a light-emitting element such as an OLED, a miniature LED, or a microLED. In the case of a miniature LED or microLED, the LD may have a vertical structure, wherein electrodes are arranged on the upper and lower portions of the semiconductor chip in which the LD is integrated, but is not limited to this. The semiconductor chip in which the LD is integrated may be implemented in a lateral structure or a flip-chip structure.

[0061] The first driving element DT1 can drive the light-emitting element LD in response to the voltage of the first node n1. The first driving element DT1 includes a gate electrode connected to the first node n1, a first electrode connected to a first power line PL1 to which a pixel driving voltage VDD is applied, and a second electrode connected to the second node n2.

[0062] The second driving element DT2 can drive the first driving element DT1 in response to the voltage of the third node n3. When turned on by the voltage of the third node n3, the second driving element DT2 can connect the fifth node n5, to which the second pixel ground voltage VSS2 is applied, to the first node n1 to discharge the voltage of the first node n1 to the second pixel ground voltage VSS2, thereby controlling the emission time of the light-emitting element LD by turning off the first driving element DT1. The second driving element DT2 includes a gate electrode connected to the third node n3, a first electrode connected to the fifth node n5, and a second electrode connected to the first node n1.

[0063] In this implementation, the light-emitting time of the light-emitting element can be controlled by using a first driving element DT1 and a second driving element DT2. The first driving element DT1 can be used as a switching element, and the second driving element DT2 can control the on-time of the first driving element DT1.

[0064] The first switching element T1 supplies a data voltage Vdata to the gate electrode of the second driving element DT2 in response to a first scan signal [SCAN1(N)]. The first switching element T1 includes a gate electrode to which the first scan signal SCAN1(N) is applied, a first electrode connected to a data line DL to which the data voltage is applied, and a second electrode connected to a third node n3.

[0065] The second switching element T2 applies a turn-off voltage Voff to the fourth node n4 in response to the second scan signal [SCAN2(N)]. The second switching element T2 includes a gate electrode to which the second scan signal [SCAN2(N)] is applied, a first electrode connected to the fourth power line PL4 to which the turn-off voltage Voff is applied, and a second electrode connected to the fourth node n4.

[0066] The third switching element T3 connects the fourth node n4 and the fifth node n5 in response to the third scan signal [SCAN3(N)]. The third switching element T3 includes a gate electrode to which the third scan signal [SCAN3(N)] is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0067] The fourth switching element T4 discharges the voltage of the fifth node n5 to the second pixel ground voltage VSS2 in response to the fourth scan signal [SCAN4(N)]. The fourth switching element T4 includes a gate electrode to which the fourth scan signal [SCAN4(N)] is applied, a first electrode connected to the third power line PL3 to which the second pixel ground voltage VSS2 is applied, and a second electrode connected to the fifth node n5.

[0068] The fifth switching element T5 connects the first power line to the first node n1 in response to the fifth scan signal [SCAN5(N)]. The fifth switching element T5 includes a gate electrode to which the fifth scan signal [SCAN5(N)] is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the first node n1.

[0069] The sixth switching element T6 connects the second node n2 to the anode of the light-emitting element LD in response to the light-emitting control signal [EM(N)]. The sixth switching element T6 includes a gate electrode to which the light-emitting control signal [EM(N)] is applied, a first electrode connected to the second node n2, and a second electrode connected to the anode electrode of the light-emitting element LD.

[0070] A first capacitor Cst is connected between the third node n3 and the fourth node n4. The first capacitor Cst can store the threshold voltage Vth of the second driving element DT2. The first electrode of the first capacitor Cst is connected to the fourth node n4, and its second electrode is connected to the third node n3.

[0071] The second capacitor C2 is connected between the first node n1 and ground. The second capacitor C2 can stably maintain the voltage applied to the first node n1. For example, when the pixel driving voltage VDD is applied to the first node n1, the second capacitor C2 can maintain the pixel driving voltage VDD applied to the first node n1 unchanged.

[0072] The pixel circuits described in this article are merely non-limiting examples.

[0073] according to Figure 2 The pixel circuit of the first embodiment can operate in the following driving sequence: initialization and data writing phase Ti / w, sensing phase Tsen, storage phase Tsav, light emission phase Tem, and non-light emission phase Toff.

[0074] Reference Figure 3 and Figure 4A During the initialization and data writing phase Ti / w, the second switching element T2 and the fifth to sixth switching elements T5 are turned off, while the first switching element T1 is turned on, causing the data voltage Vdata to be applied to the third node n3. Therefore, the voltage of the third node n3 becomes "Vdata".

[0075] The third switching element T3 to the fourth switching element T4 are turned on, and the voltage of the fourth node n4 is discharged to the second pixel ground voltage VSS2 and initialized. Therefore, the voltage of the fourth node n4 becomes "VSS2 = 0".

[0076] Reference Figure 3 and Figure 4B During the sensing phase Tsen, the first switching element T1 is turned on, and the data voltage Vdata is applied to the third node n3; the third switching element T3 and the fifth switching element T5 are turned on, and the threshold voltage Vth of the second driving element DT2 is sensed and stored in the first capacitor Cst connected to the fourth node n2. Therefore, the voltage of the third node n3 becomes "Vdata", and the voltages of the fourth node n4 and the fifth node n5 become "Vdata-Vth".

[0077] In this implementation, since the first driving element DT1 is used as a switching element, the threshold voltage of the first driving element DT1 is not compensated, but the threshold voltage of the second driving element DT2 is compensated.

[0078] Reference Figure 3 and Figure 4C During the storage phase Tsav, the third switching element T3 to the fourth switching element T4 are turned on, the second pixel ground voltage VSS2 is applied to the fourth node n4, and the threshold voltage Vth stored in the first capacitor Cst is stored in the third node n3. Therefore, the voltage of the fourth node n4 becomes "0", and the voltage of the third node n3 becomes "Vdata+Vth".

[0079] At this time, current flows through the first driving element DT1 to the light-emitting element LD, thereby causing the light-emitting element LD to emit light.

[0080] Reference Figure 3 and Figure 4DDuring the light-emitting phase Tem, the second switching element T2 is turned on, and the turn-off voltage Voff is applied to the first capacitor Cst to increase the voltage of the third node n3.

[0081] The voltage at the third node n3 becomes “Vdata+Vth+Voff” and the turn-off voltage Voff is increased. Here, the turn-off voltage Voff, which is a variable voltage value, can be a voltage value increased by a preset amount, but is not limited to this.

[0082] The sixth switching element T6 is turned on, and current flows through the driving element DT, causing the light-emitting element LD to emit light.

[0083] Reference Figure 3 and Figure 4E During the non-light-emitting phase Toff, the second switching element T2 remains in the on state, the voltage of the third node n3 increases, the second driving element DT2 is turned on, and the voltage of the first node n1 is discharged to the second pixel ground voltage VSS2, causing the first driving element DT1 to be turned off, and the light-emitting element LD does not emit light.

[0084] The voltage 'Vdata+Vth+Voff' of the third node n3 rises to the gate turn-on voltage that enables the second driving element DT2 to conduct or rises to a level higher than the gate turn-on voltage that enables the second driving element DT2 to conduct. Therefore, when the second driving element DT2 is turned on, the first driving element DT1 is turned off.

[0085] Here, the voltage at the third node n3 varies depending on the data voltage Vdata and the turn-off voltage Voff. Since the turn-off voltage Voff increases by a constant amount, the time required for it to increase to the gate turn-on voltage can vary depending on the data voltage Vdata.

[0086] For example, assuming the gate on-state voltage is 3V, such as Figure 5A As shown, when the data voltage Vdata is 0V, the turn-off voltage Voff should be 3V to achieve the gate turn-on voltage.

[0087] On the other hand, such as Figure 5B As shown, when the data voltage Vdata is 2V, if the turn-off voltage Voff becomes 1V, the gate turn-on voltage is reached, which shortens the light emission time.

[0088] Therefore, the emission time of the light-emitting element can vary according to the data voltage Vdata. That is, in the first embodiment, depending on the data voltage and the turn-off voltage, the higher the data voltage, the shorter the emission time, and the lower the data voltage, the longer the emission time.

[0089] Figure 6This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure. Figure 7 It is shown Figure 6 The diagram shows the driving timing of the pixel circuit, and Figures 8A to 8E It is used to describe according to Figure 7 A diagram illustrating the operating principle of a pixel circuit.

[0090] Reference Figure 6 and Figure 7 The pixel circuit according to the second embodiment of this disclosure includes a light-emitting element LD, a first driving element DT1 and a second driving element D2 supplying current to the light-emitting element LD, a plurality of switching elements T1, T2, T3, T3a, T4, T5 and T6 switching the current path connected to the first driving element DT1, a first capacitor Cst and a second capacitor C2. The first driving element DT1, the second driving element DT2 and the switching elements T1, T2, T3, T7, T4, T5 and T6 can be implemented using n-channel transistors, but are not limited thereto.

[0091] A light-emitting element (LD) may include an anode electrode, a cathode electrode, and a light-emitting layer. The cathode electrode of the LD may be connected to a second power line PL2 to which a first pixel ground voltage VSS1 is applied. The anode electrode of the LD may be connected to a first driving element DT1. The LD may be a light-emitting element such as an OLED, a miniature LED, or a micro LED, but is not limited thereto.

[0092] The first driving element DT1 can drive the light-emitting element LD in response to the voltage of the first node n1. The first driving element DT1 includes a gate electrode connected to the first node n1, a first electrode connected to a first power line PL1 to which a pixel driving voltage VDD is applied, and a second electrode connected to the second node n2.

[0093] The second driving element DT2 can drive the first driving element DT1 in response to the voltage of the third node n3. When turned on by the voltage of the third node n3, the second driving element DT2 can connect the fifth node n5, to which the second pixel ground voltage VSS2 is applied, to the first node n1 to discharge the voltage of the first node n1 to the second pixel ground voltage VSS2, thereby controlling the emission time of the light-emitting element LD by turning off the first driving element DT1. The second driving element DT2 includes a gate electrode connected to the third node n3, a first electrode connected to the fifth node n5, and a second electrode connected to the first node n1.

[0094] The first switching element T1 supplies a data voltage Vdata to the gate electrode of the second driving element DT2 in response to a first scan signal [SCAN1(N)]. The first switching element T1 includes a gate electrode to which the first scan signal SCAN1(N) is applied, a first electrode connected to a data line DL to which the data voltage is applied, and a second electrode connected to a third node n3.

[0095] The second switching element T2 applies a turn-off voltage Voff to the fourth node n4 in response to the second scan signal [SCAN2(N)]. The second switching element T2 includes a gate electrode to which the second scan signal [SCAN2(N)] is applied, a first electrode connected to the fourth power line PL4 to which the turn-off voltage Voff is applied, and a second electrode connected to the fourth node n4.

[0096] The third switching element T3 connects the fourth node n4 and the fifth node n5 in response to the third scan signal [SCAN3(N)]. The third switching element T3 includes a gate electrode to which the third scan signal [SCAN3(N)] is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fifth node n5.

[0097] The seventh switching element T7 applies a reference voltage Vref to the third node n3 in response to the third scan signal [SCAN3(N)]. The seventh switching element T7 includes a gate electrode to which the third scan signal [SCAN3(N)] is applied, a first electrode connected to a reference voltage line RL to which the reference voltage Vref is applied, and a second electrode connected to the third node n3.

[0098] The fourth switching element T4 discharges the voltage of the fifth node n5 to the second pixel ground voltage VSS2 in response to the fourth scan signal [SCAN4(N)]. The fourth switching element T4 includes a gate electrode to which the fourth scan signal [SCAN4(N)] is applied, a first electrode connected to the third power line PL3 to which the second pixel ground voltage VSS2 is applied, and a second electrode connected to the fifth node n5.

[0099] The fifth switching element T5 connects the first power line to the first node n1 in response to the fifth scan signal [SCAN5(N)]. The fifth switching element T5 includes a gate electrode to which the fifth scan signal [SCAN5(N)] is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the first node n1.

[0100] The sixth switching element T6 connects the second node n2 to the anode of the light-emitting element LD in response to the light-emitting control signal EM(N). The sixth switching element T6 includes a gate electrode to which the light-emitting control signal [EM(N)] is applied, a first electrode connected to the second node n2, and a second electrode connected to the anode electrode of the light-emitting element LD.

[0101] The first capacitor Cst is connected between the third node n3 and the fourth node n4. The first capacitor Cst can store the threshold voltage Vth of the second driving element DT2.

[0102] The second capacitor C2 is connected between the first node n1 and ground. The second capacitor C2 can stably maintain the voltage applied to the first node n1.

[0103] The pixel circuits described in this article are merely non-limiting examples.

[0104] according to Figure 6 The pixel circuit in the second embodiment can operate in the following driving sequence: initialization phase Tini, sensing phase Tsen, data writing phase Tsav, light emission phase Tem, and non-light emission phase Toff.

[0105] Reference Figure 7 and Figure 8A During the initialization phase Ti, the first switching element T1 to the second switching element T2 and the fifth switching element T5 to the sixth switching element T6 are turned off, the seventh switching element T7 is turned on, and a reference voltage Vref is applied to the third node n3 for initialization. Therefore, the voltage of the third node n3 becomes "Vref".

[0106] The third switching element T3 and the fourth switching element T4 are turned on, and the second pixel ground voltage VSS2 is applied to the fourth node n4 for initialization. Therefore, the voltage of the fourth node n4 becomes "VSS2 = 0".

[0107] Reference Figure 7 and Figure 8B During the sensing phase Tsen, the first switching element T1 through the second switching element T2, the fourth switching element T4, and the sixth switching element T6 are turned off, the third switching element T3 is turned on, a reference voltage Vref is applied to the third node n3, the seventh switching element T7 and the fifth switching element T5 are turned on, and the threshold voltage Vth of the second driving element DT2 is sensed and stored in the first capacitor Cst connected to the fourth node n4. Therefore, the voltage at the third node n3 becomes “Vref”, and the voltages at the fourth node n4 and the fifth node n5 become “Vref-Vth”.

[0108] Here, in the second embodiment, since the reference voltage Vref is applied to the third node n3 for initialization via the reference voltage line RL connected to all pixels, and then the sensing phase is performed, it is possible to jointly sense the threshold voltage of the second driving element DT2 in all pixels.

[0109] Reference Figure 7and Figure 8C During the data writing phase Tw, the second switching element T2, the third switching element T3, the seventh switching element T7, the fourth switching element T4, and the fifth to sixth switching elements T5 are turned off, while the first switching element T1 is turned on, causing the data voltage Vdata to be applied to the third node n3. Therefore, the voltage of the third node n3 becomes "Vref + Vdata".

[0110] Reference Figure 7 and Figure 8D During the light-emitting phase Tem, the first switching element T1, the third switching element T3, the seventh switching element T7, and the fifth switching element T5 are turned off, the second switching element T2 is turned on, and the turn-off voltage Voff is applied to the first capacitor Cst to increase the voltage of the third node n3.

[0111] The voltage at the third node n3 becomes “Vref+Vdata+Vth+Voff” and increases due to the turn-off voltage Voff.

[0112] The sixth switching element T6 is turned on, and current flows through the driving element DT, causing the light-emitting element LD to emit light.

[0113] Reference Figure 7 and Figure 8E During the non-light-emitting phase Toff, the first switching element T1, the third switching element T3, the seventh switching element T7, and the fifth switching element T5 are turned off, the second switching element T2 remains on to increase the voltage of the third node n3, the second driving element DT2 is turned on, and the voltage of the first node n1 discharges to the second pixel ground voltage VSS2, so that the first driving element DT1 is turned off and the light-emitting element LD does not emit light.

[0114] The voltage 'Vref+Vdata+Vth+Voff' of the third node n3 rises to the gate turn-on voltage that enables the second driving element DT2 to conduct or rises to a level higher than the gate turn-on voltage that enables the second driving element DT2 to conduct. Therefore, when the second driving element DT2 is turned on, the first driving element DT1 is turned off.

[0115] Here, the voltage at the third node n3 varies depending on the data voltage Vdata and the turn-off voltage Voff. Since the turn-off voltage Voff increases by a constant amount, the time required for it to increase to the gate turn-on voltage can vary depending on the data voltage Vdata.

[0116] Therefore, in the second embodiment, depending on the data voltage and the turn-off voltage, the higher the data voltage, the shorter the emission time, and the lower the data voltage, the longer the emission time.

[0117] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit comprising: a light emitting element; a first drive element configured to drive the light emitting element; a second drive element configured to drive the first drive element; a capacitor connected to a gate electrode of the second drive element; a first switching element configured to apply a data voltage to a second electrode of the capacitor; a second switching element configured to apply an off voltage to a first electrode of the capacitor; a third switching element connected between the first electrode of the capacitor and a first electrode of the second drive element; a fourth switching element configured to apply a pixel ground voltage to the first electrode of the second drive element; a fifth switching element configured to apply a pixel drive voltage to a second electrode of the second drive element; and a sixth switching element connected between the light emitting element and the first drive element. The off voltage includes a voltage value that rises to a preset amplitude.

2. The pixel circuit of claim 1, wherein, A light emitting time of the light emitting element varies according to an amplitude of the data voltage.

3. The pixel circuit of claim 2, wherein, 4. The pixel circuit according to claim 1, wherein: the first drive element includes a gate electrode connected to a first node, a first electrode connected between first power lines to which the pixel drive voltage is applied, and a second electrode connected to a second node; the second drive element includes a gate electrode connected to a third node, a first electrode connected to a fifth node, and a second electrode connected to the first node; the first electrode of the capacitor is connected to a fourth node and the second electrode of the capacitor is connected to the third node; the first switching element includes a gate electrode to which a first scan signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node; the second switching element includes a gate electrode to which a second scan signal is applied, a first electrode to which the off voltage is applied, and a second electrode connected to the fourth node; the third switching element includes a gate electrode to which a third scan signal is applied, a first electrode connected to the fourth node, and a second electrode connected to the fifth node; the fourth switching element includes a gate electrode to which a fourth scan signal is applied, a first electrode to which the pixel ground voltage is applied, and a second electrode connected to the fifth node; the fifth switching element includes a gate electrode to which a fifth scan signal is applied, a first electrode to which the pixel drive voltage is applied, and a second electrode connected to the first node; and the sixth switching element includes a gate electrode to which a light emitting control signal is applied, a first electrode connected to the second node, and a second electrode connected to the light emitting element.

5. The pixel circuit according to claim 4, wherein: the pixel circuit is driven in the order of an initialization and data write stage, a sensing stage, a storage stage, a light emitting stage, and a non-light emitting stage; and the pixel circuit is driven in the order of an initialization and data write stage, a sensing stage, a storage stage, a light emitting stage, and a non-light emitting stage; and ​ In the initialization and data write stage, the first switching element is turned on to apply the data voltage to the third node, and the third and fourth switching elements are turned on to apply the pixel ground voltage to the fourth node.

6. The pixel circuit of claim 5, wherein, In the sensing stage, the first switching element is turned on to apply the data voltage to the third node, and the third and fifth switching elements are turned on to store the threshold voltage of the second driving element in the capacitor.

7. The pixel circuit of claim 6, wherein, In the storage stage, the third and fourth switching elements are turned on to apply the pixel ground voltage to the fourth node, and the sixth switching element is turned on to emit light from the light emitting element.

8. The pixel circuit of claim 7, wherein, In the light emission stage, the second switching element is turned on to apply the off voltage to the fourth node, and the sixth switching element is turned on to emit light from the light emitting element.

9. The pixel circuit of claim 8, wherein, In the non-light emission stage, the second switching element is turned on to apply the off voltage to the fourth node, and the fourth switching element is turned on to discharge the voltage of the first and fifth nodes to the pixel ground voltage.

10. The pixel circuit according to claim 4, further comprising: a seventh switching element including a gate electrode to which the third scan signal is applied, a first electrode to which a reference voltage is applied, and a second electrode connected to the third node.

11. The pixel circuit according to claim 10, wherein: the pixel circuit is driven in the order of an initialization stage, a sensing stage, a data write stage, a light emission stage, and a non-light emission stage; and in the initialization stage, the seventh switching element is turned on to apply the reference voltage to the third node, and the third and fourth switching elements are turned on to apply the pixel ground voltage to the fourth node.

12. The pixel circuit of claim 11, wherein, in the sensing stage, the seventh switching element is turned on to apply the reference voltage to the third node, and the third and fifth switching elements are turned on to store the threshold voltage of the second driving element in the capacitor.

13. The pixel circuit of claim 12, wherein, in the data write stage, the first switching element is turned on to apply the data voltage to the third node.

14. The pixel circuit of claim 13, wherein, in the light emission stage, the second switching element is turned on to apply the off voltage to the fourth node, and the sixth switching element is turned on to emit light from the light emitting element.

15. The pixel circuit of claim 14, wherein, in the non-light emission stage, the second switching element is turned on to apply the off voltage to the fourth node, and the fourth switching element is turned on to discharge the voltage of the first and fifth nodes to the pixel ground voltage.

16. The pixel circuit of claim 4, wherein, the pixel circuit further includes a second capacitor connected between the first node and ground.

17. A display device comprising: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits according to any one of claims 1 to 16 are arranged; a data driver configured to output a data voltage to the plurality of data lines; and and a gate driver configured to output gate signals to the plurality of gate lines.

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