Gate driver, display device including the same, and electronic device including the display device

Abstract

The invention relates to a gate driver, a display device including the same, and an electronic device including the display device. The gate driver includes: an input circuit that transmits an input signal to a first control node based on a clock signal; a control circuit transmitting a first power supply voltage to a third control node based on an input signal, and transmitting the first power supply voltage to a second control node based on the first power supply voltage and a voltage of the third control node; a first output circuit that outputs a gate signal having a second power supply voltage or a third power supply voltage based on a voltage of the first control node and a voltage of the second control node; and a second output circuit that outputs a carry signal having a third power supply voltage or the first power supply voltage based on a voltage of the second control node, where the carry signal has a phase opposite to a phase of the gate signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a gate driver, a display device including the same, and an electronic device including the same. BACKGROUND

[0002] Generally, a display device can include a display panel and a display panel driver. The display panel can include gate lines, emission lines, data lines, and pixels. The display panel driver can include a gate driver for providing a gate signal to the gate lines, an emission driver for providing an emission signal to the emission lines, a data driver for providing a data voltage to the data lines, and a driving controller for controlling the gate driver, the emission driver, and the data driver. SUMMARY

[0003] In a display device, due to the deterioration of a transistor included in a gate driver thereof, a characteristic of the transistor can be changed. Due to the characteristic of the transistor being changed, a level of an output signal of the gate driver can become unstable.

[0004] Embodiments of the present application provide a gate driver having high stability and high reliability.

[0005] Another embodiment of the present application provides a display device including the same.

[0006] Still another embodiment of the present application provides an electronic device including the same.

[0007] However, embodiments of the present disclosure are not limited to the embodiments described herein and can be variously extended without departing from the spirit and scope of the present disclosure.

[0008] According to an embodiment, a gate driver includes an input circuit that transfers an input signal to a first control node based on a clock signal, a control circuit that transfers a first power voltage to a third control node based on the input signal, and transfers the first power voltage to a second control node based on the first power voltage and a voltage of the third control node, a first output circuit that outputs a gate signal having a second power voltage or a third power voltage based on a voltage of the first control node and a voltage of the second control node, and a second output circuit that outputs a carry signal having the third power voltage or the first power voltage based on the voltage of the second control node, wherein the carry signal has a phase opposite to a phase of the gate signal.

[0009] In an embodiment, the input circuit can include a first transistor including a control electrode receiving the clock signal, a first electrode receiving the input signal, and a second electrode connected to the first control node.

[0010] In an embodiment, the control circuit can include a second transistor including a control electrode receiving the first supply voltage, a first electrode connected to the third control node, and a second electrode connected to the second control node, and a third transistor including a control electrode receiving the input signal, a first electrode connected to the third control node, and a second electrode receiving the first supply voltage.

[0011] In an embodiment, the control circuit can further include a fourth transistor including a control electrode connected to the first control node, a first electrode receiving the third supply voltage, and a second electrode connected to the third control node, and a second capacitor including a first electrode receiving the third supply voltage and a second electrode connected to the first control node.

[0012] In an embodiment, the first output circuit can include a fifth transistor including a control electrode connected to the first control node, a first electrode receiving the third supply voltage, and a second electrode connected to the first output node, a sixth transistor including a control electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode receiving the second supply voltage, and a first capacitor including a first electrode connected to the second control node and a second electrode connected to the first output node.

[0013] In an embodiment, the second output circuit can include a seventh transistor including a control electrode connected to the second control node, a first electrode receiving the third supply voltage, and a second electrode connected to the second output node, and an eighth transistor including a control electrode connected to the second control node, a first electrode connected to the second output node, and a second electrode receiving the first supply voltage.

[0014] In an embodiment, the third transistor and the eighth transistor can be N-type transistors.

[0015] In an embodiment, the first transistor, the second transistor, and the fourth transistor to the seventh transistor can be P-type transistors.

[0016] In an embodiment, the third transistor can further include a second control electrode receiving a fourth supply voltage.

[0017] In an embodiment, a level of the fourth supply voltage can be lower than a level of the first supply voltage.

[0018] In an embodiment, the eighth transistor can further include a second control electrode connected to the control electrode of the eighth transistor.

[0019] In an embodiment, a level of the first supply voltage can be lower than a level of the second supply voltage, and a level of the third supply voltage can be higher than the level of the second supply voltage.

[0020] In an embodiment, a level of the first power voltage can be higher than a level of the second power voltage, and a level of the third power voltage can be higher than a level of the first power voltage.

[0021] According to an embodiment, a display apparatus includes a display panel including pixels, a gate driver outputting a gate signal to the pixels, a data driver outputting a data voltage to the pixels, and a driving controller controlling the gate driver and the data driver. In such an embodiment, the gate driver includes an input circuit transmitting an input signal to a first control node based on a clock signal, a control circuit transmitting a first power voltage to a third control node based on the input signal, and transmitting the first power voltage to a second control node based on the first power voltage and a voltage of the third control node, a first output circuit outputting a gate signal having a second power voltage or a third power voltage based on a voltage of the first control node and a voltage of the second control node, and a second output circuit outputting a carry signal having the third power voltage or the first power voltage based on the voltage of the second control node, wherein the carry signal has a phase opposite to a phase of the gate signal.

[0022] In an embodiment, the input circuit can include a first transistor including a control electrode receiving the clock signal, a first electrode receiving the input signal, and a second electrode connected to the first control node.

[0023] In an embodiment, the control circuit can include a second transistor including a control electrode receiving the first power voltage, a first electrode connected to the third control node, and a second electrode connected to the second control node, and a third transistor including a control electrode receiving the input signal, a first electrode connected to the third control node, and a second electrode receiving the first power voltage.

[0024] In an embodiment, the control circuit can further include a fourth transistor including a control electrode connected to the first control node, a first electrode receiving the third power voltage, and a second electrode connected to the third control node, and a second capacitor including a first electrode receiving the third power voltage and a second electrode connected to the first control node.

[0025] In an embodiment, the first output circuit can include a fifth transistor including a control electrode connected to the first control node, a first electrode receiving the third power voltage, and a second electrode connected to a first output node, a sixth transistor including a control electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode receiving the second power voltage, and a first capacitor including a first electrode connected to the second control node and a second electrode connected to the first output node.

[0026] In an embodiment, the second output circuit can include a seventh transistor including a control electrode connected to the second control node, a first electrode receiving the third power voltage, and a second electrode connected to the second output node, and an eighth transistor including a control electrode connected to the second control node, a first electrode connected to the second output node, and a second electrode receiving the first power voltage.

[0027] According to an embodiment, an electronic device includes a processor that outputs an input control signal and input image data, a display panel including pixels, a gate driver that outputs a gate signal to the pixels, a data driver that outputs a data voltage to the pixels, and a driving controller that controls the gate driver and the data driver based on the input control signal and the input image data. In such an embodiment, the gate driver includes an input circuit that transfers an input signal to a first control node based on a clock signal, a control circuit that transfers a first power voltage to a third control node based on the input signal, and transfers the first power voltage to a second control node based on the first power voltage and a voltage of the third control node, a first output circuit that outputs a gate signal having a second power voltage or a third power voltage based on a voltage of the first control node and a voltage of the second control node, and a second output circuit that outputs a carry signal having the third power voltage or the first power voltage based on the voltage of the second control node, wherein the carry signal has a phase opposite to a phase of the gate signal.

[0028] In an embodiment, the gate driver can include first to eighth transistors. In such an embodiment, the third transistor and the eighth transistor can be implemented as N-type transistors, and the first transistor, the second transistor, and the fourth to seventh transistors can be implemented as P-type transistors.

[0029] In such an embodiment, the first transistor, the second transistor, and the fourth to seventh transistors are implemented as P-type transistors, so that driving currents of the first transistor, the second transistor, and the fourth to seventh transistors can be increased. Accordingly, stability and reliability of the gate driver can be improved.

[0030] In such an embodiment, the third transistor and the eighth transistor are implemented as N-type transistors, so that a leakage current of the eighth transistor can be reduced. Accordingly, stability and reliability of the gate driver can be improved. In addition, power consumption of the display device can be reduced.

[0031] In an embodiment, the first power voltage and the second power voltage can be less than about zero (0) volts (V), and the third power voltage can be greater than about zero (0) V. The level of the first power voltage can be lower than the level of the second power voltage.

[0032] When the first power voltage is applied to the second electrode of the third transistor and the third power voltage is applied to the control electrode of the third transistor, a difference between the voltage of the control electrode of the third transistor and the voltage of the second electrode of the third transistor can be greater than the threshold voltage of the third transistor. Accordingly, the third transistor can be turned on, and the third transistor can transmit the first power voltage to the third control node. Accordingly, the third control node can maintain the level of the first power voltage, and stability and reliability of the gate driver can be improved.

[0033] When the first power voltage is applied to the second electrode of the third transistor and the first power voltage is applied to the control electrode of the third transistor, the third transistor can be turned off. Accordingly, a leakage current of the third transistor can be reduced, and the voltage of the third control node can stably maintain the level of the first power voltage or the level of the third power voltage. Accordingly, stability and reliability of the gate driver can be improved. In addition, since the leakage current of the third transistor is reduced, power consumption of the display device can be reduced.

[0034] When the voltage of the second control node has the level of the boosted voltage, a difference between the voltage of the control electrode of the sixth transistor and the voltage of the first electrode of the sixth transistor can be increased. Accordingly, even when the threshold voltage of the sixth transistor is changed, the difference between the voltage of the control electrode of the sixth transistor and the voltage of the first electrode of the sixth transistor can be greater than the threshold voltage of the sixth transistor. That is, the sixth transistor can be turned on. Accordingly, the sixth transistor can stably transmit the second power voltage to the first output node, and the first stage can stably output the first gate signal having the level of the second power voltage. Accordingly, stability and reliability of the gate driver can be improved.

[0035] When the voltage of the second control node has the third power voltage, a difference between the voltage of the control electrode of the eighth transistor and the voltage of the second electrode of the eighth transistor can be greater than the threshold voltage of the eighth transistor. Accordingly, the eighth transistor can be turned on, and the eighth transistor can transmit the first power voltage to the first output node. Accordingly, the first stage can stably output the first carry signal having the level of the first power voltage, and stability and reliability of the gate driver can be improved.

[0036] When the voltage of the second control node has a level of the boosted voltage, the eighth transistor can be turned off. Accordingly, the leakage current of the eighth transistor can be reduced, and the first stage can stably output the first gate signal having a level of the third power voltage. Accordingly, the stability and reliability of the gate driver can be improved. In addition, since the leakage current of the eighth transistor is reduced, the power consumption of the display apparatus can be reduced.

[0037] In an embodiment, the first power voltage and the second power voltage can be less than about zero (0) V, and the third power voltage can be greater than about zero (0) V. The level of the first power voltage can be higher than the level of the second power voltage. In such an embodiment in which the level of the first power voltage is higher than the level of the second power voltage, the power consumption of the display apparatus can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0038] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0039] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment.

[0040] Figure 2 is a block diagram illustrating an embodiment of a gate driver included in the display apparatus of Figure 1 .

[0041] Figure 3 is a circuit diagram illustrating an embodiment of a first stage included in the gate driver of Figure 2 .

[0042] Figure 4 is a signal timing diagram illustrating an operation of the first stage of Figure 3 .

[0043] Figure 5 is a circuit diagram illustrating an operation of the first stage of Figure 3 in a first period.

[0044] Figure 6 is a circuit diagram illustrating an operation of the first stage of Figure 3 in a second period.

[0045] Figure 7 is a circuit diagram illustrating an operation of the first stage of Figure 3 in a third period.

[0046] Figure 8 is a circuit diagram illustrating an operation of the first stage of Figure 3 in a fourth period.

[0047] Figure 9 is a block diagram illustrating an embodiment of a gate driver included in the display apparatus of Figure 1a circuit diagram illustrating an embodiment of a pixel included in a display panel in a display device of

[0048] Figure 10 a circuit diagram illustrating an embodiment of a first stage in a gate driver included in a display device of Figure 2 a circuit diagram illustrating another embodiment of a first stage in a gate driver included in a display device of

[0049] Figure 11 a block diagram illustrating another embodiment of a gate driver included in a display device of Figure 1

[0050] Figure 12 a circuit diagram illustrating an embodiment of a first stage in a gate driver included in a display device of Figure 11

[0051] Figure 13 a circuit diagram illustrating another embodiment of a first stage in a gate driver included in a display device of Figure 11

[0052] Figure 14 a circuit diagram illustrating another embodiment of a first stage in a gate driver included in a display device of Figure 11

[0053] Figure 15 a circuit diagram illustrating another embodiment of a first stage in a gate driver included in a display device of Figure 11

[0054] Figure 16 a block diagram illustrating an electronic device according to an embodiment.

[0055] Figure 17 a diagram illustrating an embodiment in which an electronic device of Figure 16 DETAILED DESCRIPTION

[0056] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout.

[0057] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0058] ​​​​​​It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms“a,”“an” and“at least one” do not denote a limitation of quantity, and are intended to cover both the singular and plural forms. Thus, the terms“a” and“at least one” are used interchangeably herein. For example, the term“a” means“one or more.” The terms“or” has the same meaning as“and / or” as defined below. As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms“comprises” and / or“comprising,” or“includes” and / or“including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0060] In addition, relative terms such as“lower” or“bottom” and“upper” or“top” can be used herein to describe one element’s or portion’s relationship to another element or portion as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the“lower” side of other elements would then be oriented on the“upper” sides of the other elements. The term“lower” can then encompass both an orientation of“lower” and“upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as“below” or“beneath” other elements would then be oriented“above” the other elements. The terms“below” or“beneath” can then encompass both an orientation of above and below, depending on the particular orientation of the figure.

[0061] “About” or “approximately,” as used herein when used in connection with a quantity, includes the stated value and means the acceptable variation of that value by an ordinarily skilled person in the art. For example, “about” can mean within one or more standard deviations, or within 30%, 20%, 10%, or 5% of the stated value.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] Embodiments are described herein with reference to schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as linear may

[0064] Hereinafter, a display apparatus according to an embodiment will be described in greater detail with reference to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same or like parts.

[0065] Figure 1 is a block diagram illustrating a display apparatus 1 according to an embodiment.

[0066] Referring to Figure 1 An embodiment of the display apparatus 1 can include a display panel 100 and a display panel driver 700. The display panel driver 700 can include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0067] The display panel 100 can have a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0068] The display panel 100 can include gate lines GL, data lines DL, emission lines EL, and pixels PX electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL can extend in a first direction D1, the data lines DL can extend in a second direction D2 crossing the first direction D1, and the emission lines EL can extend in the first direction D1.

[0069] The driving controller 200 can receive input image data IMG and input control signals CONT from an external processor. In an embodiment, for example, the input image data IMG can include red image data, green image data, and blue image data. In some embodiments, the input image data IMG can further include white image data. In another embodiment, for example, the input image data IMG can include magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0070] The driving controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input control signals CONT and the input image data IMG.

[0071] The driving controller 200 can generate the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signals CONT, and can output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0072] The driving controller 200 can generate the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signals CONT, and can output the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0073] The driving controller 200 can generate the data signal DATA based on the input image data IMG. The driving controller 200 can output the data signal DATA to the data driver 500.

[0074] The driving controller 200 can generate the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signals CONT, and can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0075] The driving controller 200 can generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and can output the fourth control signal CONT4 to the emission driver 600.

[0076] The gate driver 300 can generate a gate signal transmitted to the pixel PX through the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate signal can include a write gate signal, a compensation gate signal, and an initialization gate signal.

[0077] In an embodiment, the gate driver 300 can be integrated on the peripheral area of the display panel 100. In an embodiment, the gate driver 300 can be mounted on the peripheral area of the display panel 100.

[0078] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 can output the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to the data signal DATA.

[0079] In an embodiment, the gamma reference voltage generator 400 can be provided or included in the driving controller 200 or the data driver 500.

[0080] The data driver 500 can receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can convert the data signal DATA having a digital type into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 can output the data voltage to the data line DL.

[0081] In an embodiment, the data driver 500 can be integrated on the peripheral area of the display panel 100. In an embodiment, the data driver 500 can be mounted on the peripheral area of the display panel 100.

[0082] The emission driver 600 can generate an emission signal transmitted to the pixel PX through the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EL.

[0083] In an embodiment, the emission driver 600 can be integrated on the peripheral area of the display panel 100. In an embodiment, the emission driver 600 can be mounted on the peripheral area of the display panel 100.

[0084] Figure 2 is a block diagram illustrating an embodiment of a gate driver 300 included in a display device 1 of FIG. Figure 1

[0085] Referring to Figure 2 , an embodiment of the gate driver 300 can include stages. In an embodiment, for example, the gate driver 300 can include a first stage ST[1] and a second stage ST[2]. In addition, the gate driver 300 can include an nth stage ST[n], where n is a natural number greater than 1.

[0086] Each of the stages can receive a first power voltage VGL1, a second power voltage VGL2, and a third power voltage VGH. In an embodiment, for example, the first power voltage VGL1 and the second power voltage VGL2 can be less than about zero (0) volts (V), and the third power voltage VGH can be greater than about 0 V. In an embodiment, for example, a level of the first power voltage VGL1 can be lower than a level of the second power voltage VGL2. In an embodiment, for example, a level of the first power voltage VGL1 can be higher than a level of the second power voltage VGL2.

[0087] Each of the stages can receive a first clock signal CLK1 or a second clock signal CLK2. In addition, each of the stages can receive an input signal. The input signal can be a start signal FLM or a carry signal CR of a previous stage. In an embodiment, for example, the input signal applied to the first stage ST[1] can be the start signal FLM. The input signal applied to the second stage ST[2] can be a first carry signal CR[1] of the first stage ST[1]. The input signal applied to the third stage ST[3] can be a second carry signal CR[2] of the second stage ST[2]. In this manner, the input signal applied to the nth stage ST[n] can be an n-1th carry signal CR[n-1] of an n-1th stage.

[0088] A phase of the first clock signal CLK1 and a phase of the second clock signal CLK2 can be different from each other. In an embodiment, for example, the phase of the first clock signal can be opposite to the phase of the second clock signal CLK2.

[0089] Each of the stages can output a gate signal SS and a carry signal CR. A phase of the gate signal SS can be opposite to a phase of the carry signal CR.

[0090] ​The first stage ST[1] can receive the first power voltage VGL1, the second power voltage VGL2, and the third power voltage VGH. In addition, the first stage ST[1] can receive the first clock signal CLK1 and an input signal. The input signal applied to the first stage ST[1] can be a start signal FLM. The first stage ST[1] can output a first gate signal SS[1] and a first carry signal CR[1] based on the first clock signal CLK1 and the start signal FLM.

[0091] The second stage ST[2] can receive the first power voltage VGL1, the second power voltage VGL2, and the third power voltage VGH. In addition, the second stage ST[2] can receive the second clock signal CLK2 and an input signal. The input signal applied to the second stage ST[2] can be the first carry signal CR[1] output from the first stage ST[1]. The second stage ST[2] can output a second gate signal SS[2] and a second carry signal CR[2] based on the second clock signal CLK2 and the first carry signal CR[1].

[0092] In this way, the nth stage ST[n] can receive the first power voltage VGL1, the second power voltage VGL2, and the third power voltage VGH. In addition, the nth stage ST[n] can receive the first clock signal CLK1 and an input signal. The input signal applied to the nth stage ST[n] can be the (n-1)th carry signal CR[n-1] output from the (n-1)th stage ST[n-1]. The nth stage ST[n] can output an nth gate signal SS[n] and an nth carry signal CR[n] based on the first clock signal CLK1 and the (n-1)th carry signal CR[n-1].

[0093] Figure 3 is a circuit diagram illustrating an embodiment of the first stage ST[1] included in the gate driver 300 of Figure 2 is a circuit diagram illustrating an embodiment of the first stage ST[1] included in the gate driver 300 of

[0094] Referring to Figure 3 , the embodiment of the first stage ST[1] can include an input circuit 10, a control circuit 20, a first output circuit 30, and a second output circuit 40. For ease of explanation and description, hereinafter, the first stage ST[1] among the stages will be mainly described, and any repetitive detailed description of the other stages will be omitted.

[0095] In an embodiment, the input circuit 10 can include a first transistor T1. The input circuit 10 can transmit the start signal FLM to a first control node QB based on the first clock signal CLK1.

[0096] The first transistor T1 can include a control electrode that receives the first clock signal CLK1, a first electrode that receives the start signal FLM, and a second electrode that is connected to the first control node QB.

[0097] In an embodiment, the control circuit 20 can include a second transistor T2 to a fourth transistor T4 and a second capacitor C2. The control circuit 20 can control a voltage of the first control node QB and a voltage of the second control node Q based on the start signal FLM.

[0098] The second transistor T2 can include a control electrode receiving the first power voltage VGL1, a first electrode connected to the third control node A, and a second electrode connected to the second control node Q.

[0099] The third transistor T3 can include a control electrode receiving the start signal FLM, a first electrode connected to the third control node A, and a second electrode receiving the first power voltage VGL1.

[0100] The fourth transistor T4 can include a control electrode connected to the first control node QB, a first electrode receiving the third power voltage VGH, and a second electrode connected to the third control node A.

[0101] The second capacitor C2 can include a first electrode receiving the third power voltage VGH and a second electrode connected to the first control node QB.

[0102] In an embodiment, the first output circuit 30 can include a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. The first output circuit 30 can output a first gate signal SS[1] based on the voltage of the first control node QB and the voltage of the second control node Q.

[0103] The fifth transistor T5 can include a control electrode connected to the first control node QB, a first electrode receiving the third power voltage VGH, and a second electrode connected to the first output node NO1.

[0104] The sixth transistor T6 can include a control electrode connected to the second control node Q, a first electrode connected to the first output node NO1, and a second electrode receiving the second power voltage VGL2.

[0105] The first capacitor C1 can include a first electrode connected to the second control node Q and a second electrode connected to the first output node NO1.

[0106] In an embodiment, the second output circuit 40 can include a seventh transistor T7 and an eighth transistor T8. The second output circuit 40 can output a first carry signal CR[1] based on the voltage of the second control node Q.

[0107] The seventh transistor T7 can include a control electrode connected to the second control node Q, a first electrode receiving the third power voltage VGH, and a second electrode connected to the second output node NO2.

[0108] The eighth transistor T8 can include a control electrode connected to the second control node Q, a first electrode connected to the second output node NO2, and a second electrode receiving the first power supply voltage VGL1.

[0109] The third transistor T3 and the eighth transistor T8 can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be implemented as P-type transistors. In an embodiment, for example, the third transistor T3 and the eighth transistor T8 can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be implemented as P-type low temperature poly silicon (LTPS) transistors.

[0110] In an embodiment, the third transistor T3 and the eighth transistor T8 are implemented as N-type transistors, so that a leakage current of the third transistor T3 and the eighth transistor T8 can be reduced. Accordingly, stability and reliability of the gate driver 300 can be improved. In addition, power consumption of the display device 1 can be reduced.

[0111] In an embodiment, the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 are implemented as P-type transistors, so that a driving current of the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be increased. Accordingly, stability and reliability of the gate driver 300 can be improved.

[0112] In an embodiment, the first power supply voltage VGL1 and the second power supply voltage VGL2 can be less than about zero (0) V, and the third power supply voltage VGH can be greater than about zero (0) V. In addition, a level of the first power supply voltage VGL1 can be lower than a level of the second power supply voltage VGL2.

[0113] When a level of the first gate signal SS[1] is reduced from a level of the third power supply voltage VGH to a level of the second power supply voltage VGL2, the second control node Q can have a boosted voltage VQ (see Figure 4 ). The boosted voltage (VQ in Figure 4 ) can be calculated (or satisfy) by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ (see Figure 4 ), VGL1 denotes the first power supply voltage VGL1, Vth_T2 denotes a threshold voltage of the second transistor T2, VGH denotes the third power supply voltage VGH, and VGL2 denotes the second power supply voltage VGL2.

[0114] In an embodiment, the sixth transistor T6 is implemented as a P-type transistor and a voltage of the second control node Q has a boosted voltage VQ (seeFigure 4 In the embodiment in which the level of the second power supply voltage VGL2 is lower than the level of the first power supply voltage VGL1, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, even when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second power supply voltage VGL2 to the first output node NO1, and the first stage ST[1] can stably output the first gate signal SS[1] having the level of the second power supply voltage VGL2. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0115] In the embodiment, the first power supply voltage VGL1 and the second power supply voltage VGL2 can be less than approximately zero (0) V, and the third power supply voltage VGH can be greater than approximately zero (0) V. In addition, the level of the first power supply voltage VGL1 can be higher than the level of the second power supply voltage VGL2.

[0116] In such an embodiment, the level of the first power supply voltage VGL1 is higher than the level of the second power supply voltage VGL2, so that the power consumption of the display device 1 can be reduced.

[0117] In the embodiment in which the eighth transistor T8 is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the eighth transistor T8 can transfer the first power supply voltage VGL1 to the second output node NO2. Accordingly, the first stage ST[1] can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300 can be improved.

[0118] In the embodiment in which the seventh transistor T7 is implemented as a P-type transistor, the eighth transistor T8 is implemented as an N-type transistor, the seventh transistor T7 is turned on, and the voltage of the second control node Q has the boosted voltage VQ (see FIG. 6), the difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the eighth transistor T8 can transfer the first power supply voltage VGL1 to the second output node NO2. Accordingly, the first stage ST[1] can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300 can be improved. Figure 4In the embodiment where the voltage level is ), the eighth transistor T8 can be turned off. Accordingly, the leakage current of the eighth transistor T8 can be reduced, and the first stage ST[1] can stably output the first gate signal SS[1] with the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display device 1 can be reduced.

[0119] In an embodiment where the third transistor T3 is implemented as an N-type transistor and the level of the start signal FLM rises from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the third transistor T3 and the voltage of the second electrode of the third transistor T3 can be increased. This difference can be greater than the threshold voltage of the third transistor T3. Accordingly, the third transistor T3 can be turned on, and it can transmit the first power supply voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1, thus improving the stability and reliability of the gate driver 300.

[0120] In an embodiment where the third transistor T3 is implemented as an N-type transistor and the start signal FLM has the level of the first power supply voltage VGL1, the third transistor T3 can be turned off. Accordingly, the leakage current of the third transistor T3 can be reduced, and the voltage of the third control node A can be stably maintained at the level of the first power supply voltage VGL1 or the level of the third power supply voltage VGH. Consequently, the stability and reliability of the gate driver 300 can be improved. Furthermore, since the leakage current of the third transistor T3 is reduced, the power consumption of the display device 1 can be reduced.

[0121] Figure 4 It is a diagram. Figure 3 The signal timing diagram of the first-level ST[1] operation, Figure 5 It is a diagram. Figure 3 The circuit diagram of the operation of the first stage ST[1] in the first time period TP1. Figure 6 It is a diagram. Figure 3 The circuit diagram of the operation of the first stage ST[1] in the second time period TP2. Figure 7 It is a diagram. Figure 3 The circuit diagram of the operation of the first stage ST[1] in the third time period TP3, and Figure 8 It is a diagram. Figure 3 The circuit diagram of the operation of the first stage ST[1] in the fourth time period TP4.

[0122] refer to Figure 4The period in which the signal is applied to the first stage ST[1] can include a first period TP1, a second period TP2, a third period TP3, and a fourth period TP4.

[0123] Referring to Figure 4 and Figure 5 The first clock signal CLK1 can have a level of the third power voltage VGH in the first period TP1. The start signal FLM can have a level of the third power voltage VGH.

[0124] The first transistor T1 can be turned off in response to the first clock signal CLK1. Accordingly, the voltage of the first control node QB can be maintained at a level of the first power voltage VGL1. The voltage of the first control node QB can be stably maintained by the second capacitor C2.

[0125] The third transistor T3 can be turned on in response to the start signal FLM having a level of the third power voltage VGH. The fourth transistor T4 can be turned on in response to the voltage of the first control node QB. The voltage of the third control node A can have a high control voltage VGH'. The level of the high control voltage VGH' can be lower than the level of the third power voltage VGH and can be higher than the level of the first power voltage VGL1. The level of the high control voltage VGH' can be closer to the level of the third power voltage VGH than the level of the first power voltage VGL1.

[0126] The second transistor T2 can be turned on by the first power voltage VGL1. The second transistor T2 can transfer the voltage of the third control node A to the second control node Q. Accordingly, the voltage of the second control node Q can have the high control voltage VGH'. In addition, the high control voltage VGH' can be a voltage sufficient to turn off (or high enough to turn off) the sixth transistor T6.

[0127] The fifth transistor T5 can be turned on in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned off in response to the voltage of the second control node Q. The fifth transistor T5 can transfer the third power voltage VGH to the first output node NO1, and the voltage of the first output node NO1 can have a level of the third power voltage VGH. Accordingly, the first stage ST[1] can output the first gate signal SS[1] having a level of the third power voltage VGH.

[0128] The seventh transistor T7 can be turned off in response to the voltage of the second control node Q, and the eighth transistor T8 can be turned on in response to the voltage of the second control node Q. The eighth transistor T8 can transmit the first power voltage VGL1 to the second output node NO2, and the voltage of the second output node NO2 can have the level of the first power voltage VGL1. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the first power voltage VGL1.

[0129] In an embodiment in which the eighth transistor T8 is implemented as an N-type transistor, a difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the first stage ST[1] can stably output the first power voltage VGL1 as the first carry signal CR[1]. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0130] Reference Figure 4 and Figure 6 The first clock signal CLK1 can be switched between the level of the first power voltage VGL1 and the level of the third power voltage VGH. The start signal FLM can maintain the level of the third power voltage VGH.

[0131] When the level of the first clock signal CLK1 decreases from the level of the third power voltage VGH to the level of the first power voltage VGL1, the first transistor T1 can be turned on in response to the first clock signal CLK1 having the level of the first power voltage VGL1. The first transistor T1 can transmit the start signal FLM to the first control node QB. Accordingly, the voltage of the first control node QB can have the level of the third power voltage VGH.

[0132] The third transistor T3 can be turned on in response to the start signal FLM. The third transistor T3 can transmit the first power voltage VGL1 to the third control node A. Accordingly, the level of the voltage of the third control node A can decrease from the level of the third power voltage VGH to the level of the first power voltage VGL1.

[0133] In the embodiment in which the third transistor T3 is implemented as an N-type transistor, a difference between a voltage of the control electrode of the third transistor T3 and a voltage of the second electrode of the third transistor T3 can be greater than a threshold voltage of the third transistor T3. Accordingly, the third transistor T3 can be turned on, and the third transistor T3 can transmit the first power voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain a level of the first power voltage VGL1, and can improve stability and reliability of the gate driver 300.

[0134] The second transistor T2 can be turned on in response to the first power voltage VGL1. The second transistor T2 can transmit the voltage of the third control node A to the second control node Q. Accordingly, a level of the voltage of the second control node Q can decrease from a level of the third power voltage VGH to a level of the first power voltage VGL1.

[0135] The fifth transistor T5 can be turned off in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned on in response to the voltage of the second control node Q. Accordingly, the sixth transistor T6 can transmit the second power voltage VGL2 to the first output node NO1, and a level of the voltage of the first output node NO1 can decrease from a level of the third power voltage VGH to a level of the second power voltage VGL2. Accordingly, the first stage ST[1] can output the first gate signal SS[1] having the level of the second power voltage VGL2.

[0136] When the level of the voltage of the first output node NO1 decreases from the level of the third power voltage VGH to the level of the second power voltage VGL2, the voltage of the second control node Q can be boosted by coupling of the first capacitor C1. Accordingly, the level of the voltage of the second control node Q can decrease from the level of the first power voltage VGL1 to a level of a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first power voltage VGL1, Vth_T2 denotes a threshold voltage of the second transistor T2, VGH denotes the third power voltage VGH, and VGL2 denotes the second power voltage VGL2.

[0137] In the embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the level of the voltage of the second control node Q is lowered from the level of the first power supply voltage VGL1 to the level of the boosted voltage VQ, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. The difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. Accordingly, the sixth transistor T6 can be turned on, and the first stage ST[1] can stably output the second power supply voltage VGL2 as the first gate signal SS[1]. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0138] The seventh transistor T7 can be turned on in response to the voltage of the second control node Q having the level of the boosted voltage VQ, and the eighth transistor T8 can be turned off in response to the voltage of the second control node Q having the level of the boosted voltage VQ. Accordingly, the seventh transistor T7 can transmit the third power supply voltage VGH to the second output node NO2, and the level of the voltage of the second output node NO2 can be raised from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0139] In the embodiment in which the eighth transistor T8 is implemented as an N-type transistor, the eighth transistor T8 can be turned off, and the leakage current of the eighth transistor T8 can be reduced. Since the leakage current of the eighth transistor T8 is reduced, the first stage ST[1] can stably output the first carry signal CR[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display device 1 can be reduced.

[0140] The level of the first clock signal CLK1 can be raised from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH. The start signal FLM can maintain the level of the third power supply voltage VGH.

[0141] The first transistor T1 can be turned off in response to the first clock signal CLK1 having the level of the third power supply voltage VGH. The voltage of the first control node QB can be maintained at the level of the third power supply voltage VGH by the second capacitor C2.

[0142] The fourth transistor T4 can be turned off in response to the voltage of the first control node QB, and the third transistor T3 can be turned on in response to the start signal FLM. Accordingly, the voltage of the third control node A can maintain the level of the first power voltage VGL1. Also, the voltage of the second control node Q can maintain the level of the boosted voltage VQ.

[0143] The fifth transistor T5 can be turned off in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned on in response to the voltage of the second control node Q. Accordingly, the sixth transistor T6 can transmit the second power voltage VGL2 to the first output node NO1, and the voltage of the first output node NO1 can maintain the level of the second power voltage VGL2. Accordingly, the first stage ST[1] can output the second power voltage VGL2 as the first gate signal SS[1].

[0144] The seventh transistor T7 can be turned on in response to the voltage of the second control node Q, and the eighth transistor T8 can be turned off in response to the voltage of the second control node Q. Accordingly, the seventh transistor T7 can transmit the third power voltage VGH to the second output node NO2, and the voltage of the second output node NO2 can maintain the level of the third power voltage VGH. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the third power voltage VGH.

[0145] The level of the first clock signal CLK1 can decrease from the level of the third power voltage VGH to the level of the first power voltage VGL1. The start signal FLM can maintain the level of the third power voltage VGH.

[0146] The first transistor T1 can be turned on in response to the first clock signal CLK1 having the first power voltage VGL1. The first transistor T1 can transmit the start signal FLM to the first control node QB. Accordingly, the voltage of the first control node QB can maintain the level of the third power voltage VGH.

[0147] The fourth transistor T4 can be turned off in response to the voltage of the first control node QB, and the third transistor T3 can be turned on in response to the start signal FLM. Accordingly, the voltage of the third control node A can maintain the level of the first power voltage VGL1. Also, the voltage of the second control node Q can maintain the level of the boosted voltage VQ.

[0148] The fifth transistor T5 can be turned off in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned on in response to the voltage of the second control node Q. Accordingly, the sixth transistor T6 can transmit the second power voltage VGL2 to the first output node NO1, and the voltage of the first output node NO1 can maintain the level of the second power voltage VGL2. Accordingly, the first stage ST[1] can output the second power voltage VGL2 as the first gate signal SS[1].

[0149] The seventh transistor T7 can be turned on in response to the voltage of the second control node Q, and the eighth transistor T8 can be turned off in response to the voltage of the second control node Q. Accordingly, the seventh transistor T7 can transmit the third power voltage VGH to the second output node NO2, and the voltage of the second output node NO2 can maintain the level of the third power voltage VGH. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the third power voltage VGH.

[0150] Reference Figure 4 and Figure 7 In the third period TP3, the level of the first clock signal CLK1 can rise from the level of the first power voltage VGL1 to the level of the third power voltage VGH. The level of the start signal FLM can fall from the level of the third power voltage VGH to the level of the first power voltage VGL1.

[0151] The first transistor T1 can be turned off in response to the first clock signal CLK1 having the level of the third power voltage VGH. The voltage of the first control node QB can be stably maintained at the level of the third power voltage VGH by the second capacitor C2.

[0152] The fourth transistor T4 can be turned off in response to the voltage of the first control node QB.

[0153] The third transistor T3 can be turned off in response to the start signal FLM having the level of the first power voltage VGL1. Accordingly, the voltage of the third control node A can maintain the level of the first power voltage VGL1. Also, the voltage of the second control node Q can maintain the level of the boosted voltage VQ.

[0154] In an embodiment in which the third transistor T3 is implemented as an N-type transistor, the third transistor T3 can be turned off. Accordingly, the leakage current of the third transistor T3 can be reduced, and the voltage of the third control node A can be stably maintained at the level of the first power voltage VGL1. Accordingly, the stability and reliability of the gate driver 300 can be improved. Also, since the leakage current of the third transistor T3 is reduced, the power consumption of the display device 1 can be reduced.

[0155] The fifth transistor T5 can be turned off in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned on in response to the voltage of the second control node Q. Accordingly, the sixth transistor T6 can transmit the second power voltage VGL2 to the first output node NO1, and the voltage of the first output node NO1 can maintain the level of the second power voltage VGL2. Accordingly, the first stage ST[1] can output the second power voltage VGL2 as the first gate signal SS[1].

[0156] In an embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, a difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. The difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. Accordingly, the sixth transistor T6 can be turned on, and the first stage ST[1] can stably output the second power voltage VGL2 as the first gate signal SS[1]. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0157] The seventh transistor T7 can be turned on in response to the voltage of the second control node Q, and the eighth transistor T8 can be turned off in response to the voltage of the second control node Q. Accordingly, the seventh transistor T7 can transmit the third power voltage VGH to the second output node NO2, and the voltage of the second output node NO2 can maintain the level of the third power voltage VGH. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the third power voltage VGH.

[0158] In an embodiment in which the eighth transistor T8 is implemented as an N-type transistor, the eighth transistor T8 can be turned off, and the leakage current of the eighth transistor T8 can be reduced. Since the leakage current of the eighth transistor T8 is reduced, the first stage ST[1] can stably output the first carry signal CR[1] having the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display apparatus 1 can be reduced.

[0159] Reference Figure 4 and Figure 8 In the fourth period TP4, the level of the first clock signal CLK1 can decrease from the level of the third power voltage VGH to the level of the first power voltage VGL1. The start signal FLM can maintain the level of the first power voltage VGL1.

[0160] The first transistor T1 can be turned on in response to the first clock signal CLK1 having a level of the first power voltage VGL1. The first transistor T1 can transmit the start signal FLM to the first control node QB. Accordingly, the level of the voltage of the first control node QB can decrease from the level of the third power voltage VGH to the level of the first power voltage VGL1.

[0161] The third transistor T3 can be turned off in response to the start signal FLM.

[0162] The fourth transistor T4 can be turned on in response to the voltage of the first control node QB having the level of the first power voltage VGL1. The fourth transistor T4 can transmit the third power voltage VGH to the third control node A. Accordingly, the level of the voltage of the third control node A can increase from the level of the first power voltage VGL1 to the level of the third power voltage VGH.

[0163] In an embodiment in which the third transistor T3 is implemented as an N-type transistor, the third transistor T3 can be turned off. Accordingly, the leakage current of the third transistor T3 can be reduced, and the voltage of the third control node A can stably maintain the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the third transistor T3 is reduced, the power consumption of the display device 1 can be reduced.

[0164] The second transistor T2 can be turned on in response to the first power voltage VGL1. The second transistor T2 can transmit the voltage of the third control node A to the second control node Q. Accordingly, the level of the voltage of the second control node Q can increase from the level of the boosted voltage VQ to the level of the third power voltage VGH.

[0165] The fifth transistor T5 can be turned on in response to the voltage of the first control node QB, and the sixth transistor T6 can be turned off in response to the voltage of the second control node Q. The fifth transistor T5 can transmit the third power voltage VGH to the first output node NO1, and the level of the voltage of the first output node NO1 can increase from the level of the second power voltage VGL2 to the level of the third power voltage VGH. Accordingly, the first stage ST[1] can output the first gate signal SS[1] having the level of the third power voltage VGH.

[0166] The seventh transistor T7 can be turned off in response to the voltage of the second control node Q, and the eighth transistor T8 can be turned on in response to the voltage of the second control node Q. The eighth transistor T8 can transmit the first power voltage VGL1 to the second output node NO2, and the level of the voltage of the second output node NO2 can be decreased from the level of the third power voltage VGH to the level of the first power voltage VGL1. Accordingly, the first stage ST[1] can output the first carry signal CR[1] having the level of the first power voltage VGL1.

[0167] In an embodiment in which the eighth transistor T8 is implemented as an N-type transistor, a difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the first stage ST[1] can stably output the first power voltage VGL1 as the first carry signal CR[1]. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0168] Figure 9 is a circuit diagram illustrating an embodiment of a pixel PX included in a display panel 100 included in a display device 1 of Figure 1

[0169] Referring to Figure 9 , an embodiment of the pixel PX can include first to seventh pixel transistors PT1 to PT7, a storage capacitor CST, and a light emitting element EE, but the pixel PX is not limited thereto.

[0170] In an embodiment, a gate signal SS output from a stage included in the gate driver 300 can be applied to the pixel PX. In an embodiment, for example, the nth gate signal SS[n] can be a write gate signal GW[n] applied to the second pixel transistor PT2. In an embodiment, for example, the nth gate signal SS[n] can be a compensation gate signal GC[n] applied to the third pixel transistor PT3. In an embodiment, for example, the nth gate signal SS[n] can be an initialization gate signal GI[n] applied to the fourth pixel transistor PT4.

[0171] The first pixel transistor PT1 can include a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The first pixel transistor PT1 can generate a driving current based on a difference between the voltage of the first pixel node PN1 and the voltage of the second pixel node PN2.

[0172] ​The second pixel transistor PT2 can include a control electrode that receives a write gate signal GW[n], a first electrode that receives a data voltage VDATA, and a second electrode connected to a second pixel node PN2. The second pixel transistor PT2 can transfer the data voltage VDATA to the second pixel node PN2 in response to the write gate signal GW[n].

[0173] The third pixel transistor PT3 can include a control electrode that receives a compensation gate signal GC[n], a first electrode connected to a third pixel node PN3, and a second electrode connected to the first pixel node PN1. The third pixel transistor PT3 can diode-connect the control electrode of the first pixel transistor PT1 and the second electrode of the first pixel transistor PT1 in response to the compensation gate signal GC[n].

[0174] The fourth pixel transistor PT4 can include a control electrode that receives an initialization gate signal GI[n], a first electrode that receives an initialization voltage VINT, and a second electrode connected to the first pixel node PN1. The fourth pixel transistor PT4 can transfer the initialization voltage VINT to the first pixel node PN1 in response to the initialization gate signal GI[n].

[0175] The fifth pixel transistor PT5 can include a control electrode that receives an emission signal EM[n], a first electrode that receives a first pixel power supply voltage ELVDD, and a second electrode connected to the second pixel node PN2.

[0176] The sixth pixel transistor PT6 can include a control electrode that receives the emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to a fourth pixel node PN4.

[0177] The fifth pixel transistor PT5 and the sixth pixel transistor PT6 can control emission of the light emitting element EE in response to the emission signal EM[n].

[0178] The seventh pixel transistor PT7 can include a control electrode that receives a previous write gate signal GW[n-1], a first electrode that receives an anode initialization voltage VAIN T, and a second electrode connected to the fourth pixel node PN4. The seventh pixel transistor PT7 can transfer the anode initialization voltage VAIN T to the fourth pixel node PN4 in response to the previous write gate signal GW[n-1].

[0179] The storage capacitor CST can include a first electrode that receives the first pixel power supply voltage ELVDD and a second electrode connected to the first pixel node PN1. The storage capacitor CST can store the data voltage VDATA.

[0180] The light emitting element EE can include an anode connected to the fourth pixel node PN4 and a cathode receiving the second pixel power supply voltage ELVSS. The light emitting element EE can emit light based on a drive current. A magnitude of the drive current is determined based on a level of the data voltage VDATA, such that a magnitude of the light emission of the light emitting element EE (or an intensity of the light emitted by the light emitting element EE) can be determined based on the level of the data voltage VDATA.

[0181] Figure 10 is a circuit diagram illustrating another embodiment of the first stage ST[1]a included in Figure 2 a gate driver 300.

[0182] Referring to Figure 10 , the embodiment of the first stage ST[1]a can include an input circuit 10, a control circuit 20, a first output circuit 30, and a second output circuit 40a. Except for a structure of the seventh transistor T7a of the second output circuit 40a, Figure 10 the first stage ST[1]a illustrated in Figure 3 is substantially the same as the first stage ST[1] of Figure 3 . Thus, the same reference numerals will be used to refer to parts that are the same as or similar to parts described above with reference to

[0183] In an embodiment, as illustrated in Figure 10 , the seventh transistor T7a can include a control electrode connected to the third control node A, a first electrode receiving the third power supply voltage VGH, and a second electrode connected to the second output node NO2.

[0184] The seventh transistor T7a can be turned on when a voltage of the third control node A has a level of the first power supply voltage VGL1. In addition, the seventh transistor T7a can be turned off when the voltage of the third control node A has the third power supply voltage VGH.

[0185] The third transistor T3 and the eighth transistor T8 can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7a can be implemented as P-type transistors. In an embodiment, for example, the third transistor T3 and the eighth transistor T8 can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7a can be implemented as LTPS transistors.

[0186] In an embodiment, the first power supply voltage VGL1 and the second power supply voltage VGL2 can be less than about zero (0) V, and the third power supply voltage VGH can be greater than about zero (0) V. In addition, a level of the first power supply voltage VGL1 can be lower than a level of the second power supply voltage VGL2.

[0187] In addition, when the level of the first gate signal SS[1] is decreased from the level of the third power voltage VGH to the level of the second power voltage VGL2, the second control node Q can have a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first power voltage VGL1, Vth_T2 denotes the threshold voltage of the second transistor T2, VGH denotes the third power voltage VGH, and VGL2 denotes the second power voltage VGL2.

[0188] In the embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, even when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second power voltage VGL2 to the first output node NO1, and the first stage ST[1]a can stably output the first gate signal SS[1] having the level of the second power voltage VGL2. Accordingly, the stability and reliability of the gate driver 300 can be improved.

[0189] In the embodiment, the first power voltage VGL1 and the second power voltage VGL2 can be less than about zero (0) V, and the third power voltage VGH can be greater than about zero (0) V. In addition, the level of the first power voltage VGL1 can be higher than the level of the second power voltage VGL2.

[0190] In such an embodiment, the level of the first power voltage VGL1 is higher than the level of the second power voltage VGL2, so that the power consumption of the display device 1 can be reduced.

[0191] In the embodiment in which the eighth transistor T8 is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the eighth transistor T8 can transmit the first power supply voltage VGL1 to the first output node NO1. Accordingly, the first stage ST[1]a can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300 can be improved.

[0192] In the embodiment in which the seventh transistor T7a is implemented as a P-type transistor and the voltage of the third control node A has the level of the first power supply voltage VGL1, the seventh transistor T7a can be turned on. In addition, when the eighth transistor T8 is implemented as an N-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the eighth transistor T8 can be turned off. Accordingly, the leakage current of the eighth transistor T8 can be reduced, and the first stage ST[1]a can stably output the first gate signal SS[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display device 1 can be reduced.

[0193] In the embodiment in which the third transistor T3 is implemented as an N-type transistor and the level of the start signal FLM is raised from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the third transistor T3 and the voltage of the second electrode of the third transistor T3 can be increased. The difference between the voltage of the control electrode of the third transistor T3 and the voltage of the second electrode of the third transistor T3 can be greater than the threshold voltage of the third transistor T3. Accordingly, the third transistor T3 can be turned on, and the third transistor T3 can transmit the first power supply voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300 can be improved.

[0194] In an embodiment in which the third transistor T3 is implemented as an N-type transistor and the start signal FLM has a level of the first power voltage VGL1, the third transistor T3 can be turned off. Accordingly, a leakage current of the third transistor T3 can be reduced, and a voltage of the third control node A can stably maintain a level of the first power voltage VGL1 or a level of the third power voltage VGH. Accordingly, stability and reliability of the gate driver 300 can be improved. In addition, since the leakage current of the third transistor T3 is reduced, power consumption of the display device 1 can be lowered.

[0195] Figure 11 is a block diagram illustrating another embodiment of the gate driver 300a included in the display device 1 of Figure 1

[0196] Referring to Figure 11 , the gate driver 300a can include stages. In an embodiment, for example, the gate driver 300a can include a first stage ST[1]b and a second stage ST[2]b. In addition, the gate driver 300a can include an nth stage ST[n]b. Except that the fourth power voltage VGL3 is applied to the stages, Figure 11 The gate driver 300a shown in Figure 2 is substantially the same as the gate driver 300 of Figure 2 . Accordingly, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous embodiments of

[0197] In an embodiment, each of the stages can receive the first power voltage VGL1, the second power voltage VGL2, the third power voltage VGH, and the fourth power voltage VGL3. In an embodiment, for example, the first power voltage VGL1, the second power voltage VGL2, and the fourth power voltage VGL3 can be less than about zero (0) V, and the third power voltage VGH can be greater than about zero (0) V. In an embodiment, for example, a level of the first power voltage VGL1 can be lower than a level of the second power voltage VGL2, and a level of the fourth power voltage VGL3 can be lower than a level of the first power voltage VGL1. In an embodiment, for example, a level of the first power voltage VGL1 can be higher than a level of the second power voltage VGL2, and a level of the fourth power voltage VGL3 can be lower than a level of the first power voltage VGL1.

[0198] Each of the stages can receive the first clock signal CLK1 or the second clock signal CLK2. In addition, each of the stages can receive the input signal.

[0199] Figure 12 is a block diagram illustrating another embodiment of the gate driver 300a included in the display device 1 of Figure 11 ​a circuit diagram of an embodiment of the first stage ST[1]b in the gate driver 300a.

[0200] Referring to Figure 12 , the embodiment of the first stage ST[1]b can include the input circuit 10, the control circuit 20b, the first output circuit 30, and the second output circuit 40. Except that the fourth power voltage VGL3 is applied to the third transistor T3b included in the control circuit 20b, Figure 12 the first stage ST[1]b shown in Figure 3 is substantially the same as the first stage ST[1] of Figure 3 . Accordingly, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous embodiment of

[0201] In an embodiment, as shown in Figure 12 , the third transistor T3b can include a control electrode that receives the start signal FLM, a first electrode connected to the third control node A, and a second electrode that receives the first power voltage VGL1. In addition, the third transistor T3b can further include a second control electrode that receives the fourth power voltage VGL3.

[0202] In an embodiment, the third transistor T3b can be implemented as an N-type transistor, and a level of the fourth power voltage VGL3 can be lower than a level of the first power voltage VGL1. Since the fourth power voltage VGL3 is applied to the second control electrode of the third transistor T3b, a threshold voltage of the third transistor T3b can be offset. Accordingly, the third transistor T3b can maintain an initialization threshold voltage, and stability and reliability of the gate driver 300a can be improved.

[0203] In an embodiment, the third transistor T3b and the eighth transistor T8 can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be implemented as P-type transistors. In an embodiment, for example, the third transistor T3b and the eighth transistor T8 can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be implemented as LTPS transistors.

[0204] In an embodiment in which the third transistor T3b and the eighth transistor T8 are implemented as N-type transistors, a leakage current of the third transistor T3b and the eighth transistor T8 can be reduced. Accordingly, stability and reliability of the gate driver 300a can be improved. In addition, power consumption of the display device 1 can be reduced.

[0205] In the embodiment in which the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 are implemented as P-type transistors, the driving current of the first transistor T1, the second transistor T2, and the fourth transistor T4 through the seventh transistor T7 can be increased. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0206] In an embodiment, the first supply voltage VGL1, the second supply voltage VGL2, and the fourth supply voltage VGL3 can be less than about zero (0) V, and the third supply voltage VGH can be greater than about zero (0) V. In addition, the level of the first supply voltage VGL1 can be lower than the level of the second supply voltage VGL2, and the level of the fourth supply voltage VGL3 can be lower than the level of the first supply voltage VGL1.

[0207] In addition, when the level of the first gate signal SS[1] is decreased from the level of the third supply voltage VGH to the level of the second supply voltage VGL2, the second control node Q can have a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first supply voltage VGL1, Vth_T2 denotes the threshold voltage of the second transistor T2, VGH denotes the third supply voltage VGH, and VGL2 denotes the second supply voltage VGL2.

[0208] In an embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, even when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second supply voltage VGL2 to the first output node NO1, and the first stage ST[1]b can stably output the first gate signal SS[1] having the level of the second supply voltage VGL2. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0209] In an embodiment, the first supply voltage VGL1, the second supply voltage VGL2, and the fourth supply voltage VGL3 can be less than about zero (0) V, and the third supply voltage VGH can be greater than about zero (0) V. In addition, the level of the first supply voltage VGL1 can be higher than the level of the second supply voltage VGL2, and the level of the fourth supply voltage VGL3 can be lower than the level of the first supply voltage VGL1.

[0210] In such an embodiment, the level of the first power supply voltage VGL1 is higher than the level of the second power supply voltage VGL2, so that the power supply voltage of the display device 1 can be reduced.

[0211] In an embodiment in which the eighth transistor T8 is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the eighth transistor T8 can transmit the first power supply voltage VGL1 to the first output node NO1. Accordingly, the first stage ST[1]b can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0212] In an embodiment in which the seventh transistor T7 is implemented as a P-type transistor, the eighth transistor T8 is implemented as an N-type transistor, the seventh transistor T7 is turned on, and the voltage of the second control node Q has the level of the boosted voltage VQ, the eighth transistor T8 can be turned off. Accordingly, the leakage current of the eighth transistor T8 can be reduced, and the first stage ST[1]b can stably output the first gate signal SS[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display device 1 can be reduced.

[0213] In an embodiment in which the third transistor T3b is implemented as an N-type transistor and the level of the start signal FLM is raised from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be increased. The difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be greater than the threshold voltage of the third transistor T3b. Accordingly, the third transistor T3b can be turned on, and the third transistor T3b can transmit the first power supply voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0214] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the start signal FLM has a level of the first power supply voltage VGL1, the third transistor T3b can be turned off. Accordingly, the leakage current of the third transistor T3b can be reduced, and the voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1 or the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the third transistor T3b is reduced, the power consumption of the display device 1 can be lowered.

[0215] Figure 13 is a circuit diagram illustrating another embodiment of the first stage ST[1]c included in the gate driver 300a of Figure 11

[0216] Referring to Figure 13 , the embodiment of the first stage ST[1]c can include the input circuit 10, the control circuit 20b, the first output circuit 30, and the second output circuit 40c. Except that the eighth transistor T8c further includes a second control electrode, Figure 13 The first stage ST[1]c shown in Figure 12 is substantially the same as the first stage ST[1]b of Figure 12 . Therefore, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous embodiments of

[0217] The eighth transistor T8c can include a control electrode connected to the second control node Q, a first electrode connected to the second output node NO2, and a second electrode that receives the first power supply voltage VGL1. In addition, the eighth transistor T8c can further include a second control electrode connected to the control electrode of the eighth transistor T8c.

[0218] Since the control electrode of the eighth transistor T8c is connected to the second control electrode of the eighth transistor T8c, the voltage of the second control electrode of the eighth transistor T8c can be the same as the voltage of the second control node Q.

[0219] ​In the embodiment in which the voltage of the second control node Q has the level of the boosted voltage VQ, the threshold voltage of the eighth transistor T8c can be offset since the voltage of the second control node Q having the level of the boosted voltage VQ is applied to the second control electrode of the eighth transistor T8c. The eighth transistor T8c can maintain the initialized threshold voltage. The eighth transistor T8c can be turned off, and the leakage current of the eighth transistor T8c can be reduced. The first stage ST[1]c can stably output the first gate signal SS[1] having the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8c is reduced, the power consumption of the display device 1 can be lowered.

[0220] In the embodiment, the third transistor T3b and the eighth transistor T8c can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7 can be implemented as P-type transistors. In the embodiment, for example, the third transistor T3b and the eighth transistor T8c can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7 can be implemented as LTPS transistors.

[0221] In the embodiment in which the third transistor T3b and the eighth transistor T8c are implemented as N-type transistors, the leakage current of the third transistor T3b and the eighth transistor T8c can be reduced. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, the power consumption of the display device 1 can be lowered.

[0222] In the embodiment in which the third transistor T3b can be implemented as an N-type transistor and the level of the fourth power voltage VGL3 can be lower than the level of the first power voltage VGL1, the threshold voltage of the third transistor T3b can be offset since the fourth power voltage VGL3 is applied to the second control electrode of the third transistor T3b. Accordingly, the third transistor T3b can maintain the initialized threshold voltage, and the stability and reliability of the gate driver 300a can be improved.

[0223] In the embodiment in which the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7 are implemented as P-type transistors, the driving current of the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7 can be increased. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0224] In an embodiment, the first power voltage VGL1, the second power voltage VGL2, and the fourth power voltage VGL3 can be less than about zero (0) V, and the third power voltage VGH can be greater than about zero (0) V. Also, a level of the first power voltage VGL1 can be lower than a level of the second power voltage VGL2, and a level of the fourth power voltage VGL3 can be lower than a level of the first power voltage VGL1.

[0225] Also, when the level of the first gate signal SS[1] is lowered from the level of the third power voltage VGH to the level of the second power voltage VGL2, the second control node Q can have a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first power voltage VGL1, Vth_T2 denotes the threshold voltage of the second transistor T2, VGH denotes the third power voltage VGH, and VGL2 denotes the second power voltage VGL2.

[0226] In an embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, a difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, even when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second power voltage VGL2 to the first output node NO1, and the first stage ST[1]c can stably output the first gate signal SS[1] having the level of the second power voltage VGL2. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0227] In an embodiment, the first power voltage VGL1, the second power voltage VGL2, and the fourth power voltage VGL3 can be less than about zero (0) V, and the third power voltage VGH can be greater than about zero (0) V. Also, a level of the first power voltage VGL1 can be higher than a level of the second power voltage VGL2, and a level of the fourth power voltage VGL3 can be lower than a level of the first power voltage VGL1.

[0228] In such an embodiment, the level of the first power voltage VGL1 is higher than the level of the second power voltage VGL2, so that the power voltage of the display apparatus 1 can be lowered.

[0229] In the embodiment in which the eighth transistor T8c is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8c and the voltage of the second electrode of the eighth transistor T8c can be increased. The difference between the voltage of the control electrode of the eighth transistor T8c and the voltage of the second electrode of the eighth transistor T8c can be greater than the threshold voltage of the eighth transistor T8c. Accordingly, the eighth transistor T8c can be turned on, and the eighth transistor T8c can transmit the first power supply voltage VGL1 to the first output node NO1. Accordingly, the first stage ST[1]c can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0230] In the embodiment in which the seventh transistor T7 is implemented as a P-type transistor, the eighth transistor T8c is implemented as an N-type transistor, the seventh transistor T7 is turned on, and the voltage of the second control node Q has the level of the boosted voltage VQ, the eighth transistor T8c can be turned off. Accordingly, the leakage current of the eighth transistor T8c can be reduced, and the first stage ST[1]c can stably output the first gate signal SS[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8c is reduced, the power consumption of the display apparatus 1 can be lowered.

[0231] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the level of the start signal FLM is raised from the level of the first power supply voltage VGL1 to the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be increased. The difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be greater than the threshold voltage of the third transistor T3b. Accordingly, the third transistor T3b can be turned on, and the third transistor T3b can transmit the first power supply voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0232] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the start signal FLM has the level of the first power supply voltage VGL1, the third transistor T3b can be turned off. Accordingly, the leakage current of the third transistor T3b can be reduced, and the voltage of the third control node A can stably maintain the level of the first power supply voltage VGL1 or the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the third transistor T3b is reduced, the power consumption of the display device 1 can be lowered.

[0233] Figure 14 is a circuit diagram illustrating another embodiment of the first stage ST[1]d included in the gate driver 300a of Figure 11

[0234] Referring to Figure 14 , the embodiment of the first stage ST[1]d can include the input circuit 10, the control circuit 20b, the first output circuit 30, and the second output circuit 40d. Except for the structure of the seventh transistor T7d of the second output circuit 40d, Figure 14 The first stage ST[1]d shown in Figure 12 is substantially the same as the first stage ST[1]b of Figure 12 . Therefore, the same reference numerals will be used to refer to parts that are the same as or similar to those described in the previous embodiments of

[0235] In the embodiment, as shown in Figure 14 , the seventh transistor T7d can include a control electrode connected to the third control node A, a first electrode receiving the third power supply voltage VGH, and a second electrode connected to the second output node NO2.

[0236] The seventh transistor T7d can be turned on when the voltage of the third control node A has the level of the first power supply voltage VGL1. In addition, the seventh transistor T7d can be turned off when the voltage of the third control node A has the level of the third power supply voltage VGH.

[0237] In the embodiment, the third transistor T3b can be implemented as an N-type transistor, and the level of the fourth power supply voltage VGL3 can be lower than the level of the first power supply voltage VGL1. Since the fourth power supply voltage VGL3 is applied to the second control electrode of the third transistor T3b, the threshold voltage of the third transistor T3b can be offset. Accordingly, the third transistor T3b can maintain an initialized threshold voltage, and the stability and reliability of the gate driver 300a can be improved.

[0238] ​In an embodiment, the third transistor T3b and the eighth transistor T8 can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be implemented as P-type transistors. In an embodiment, for example, the third transistor T3b and the eighth transistor T8 can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be implemented as LTPS transistors.

[0239] In an embodiment in which the third transistor T3b and the eighth transistor T8 are implemented as N-type transistors, the leakage current of the third transistor T3b and the eighth transistor T8 can be reduced. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, the power consumption of the display device 1 can be reduced.

[0240] In an embodiment in which the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d are implemented as P-type transistors, the driving current of the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be increased. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0241] In an embodiment, the first power supply voltage VGL1, the second power supply voltage VGL2, and the fourth power supply voltage VGL3 can be less than about zero (0) V, and the third power supply voltage VGH can be greater than about zero (0) V. In addition, the level of the first power supply voltage VGL1 can be lower than the level of the second power supply voltage VGL2, and the level of the fourth power supply voltage VGL3 can be lower than the level of the first power supply voltage VGL1.

[0242] In addition, when the level of the first gate signal SS[1] is reduced from the level of the third power supply voltage VGH to the level of the second power supply voltage VGL2, the second control node Q can have a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first power supply voltage VGL1, Vth_T2 denotes the threshold voltage of the second transistor T2, VGH denotes the third power supply voltage VGH, and VGL2 denotes the second power supply voltage VGL2.

[0243] In the embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second power voltage VGL2 to the first output node NO1, and the first stage ST[1]d can stably output the first gate signal SS[1] having the level of the second power voltage VGL2. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0244] In the embodiment, the first power voltage VGL1, the second power voltage VGL2, and the fourth power voltage VGL3 can be less than approximately zero (0) V, and the third power voltage VGH can be greater than approximately zero (0) V. In addition, the level of the first power voltage VGL1 can be higher than the level of the second power voltage VGL2, and the level of the fourth power voltage VGL3 can be lower than the level of the first power voltage VGL1.

[0245] In such an embodiment, the level of the first power voltage VGL1 is higher than the level of the second power voltage VGL2, so that the power voltage of the display device 1 can be reduced.

[0246] In the embodiment in which the eighth transistor T8 is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be increased. The difference between the voltage of the control electrode of the eighth transistor T8 and the voltage of the second electrode of the eighth transistor T8 can be greater than the threshold voltage of the eighth transistor T8. Accordingly, the eighth transistor T8 can be turned on, and the eighth transistor T8 can transfer the first power voltage VGL1 to the first output node NO1. Accordingly, the first stage ST[1]d can stably output the first carry signal CR[1] having the level of the first power voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0247] In the embodiment in which the seventh transistor T7d is implemented as a P-type transistor, the eighth transistor T8 is implemented as an N-type transistor, the seventh transistor T7d is turned on, and the voltage of the second control node Q has the level of the boosted voltage VQ, the eighth transistor T8 can be turned off. Accordingly, the leakage current of the eighth transistor T8 can be reduced, and the first stage ST[1]d can stably output the first gate signal SS[1] having the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8 is reduced, the power consumption of the display device 1 can be lowered.

[0248] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the level of the start signal FLM is raised from the level of the first power voltage VGL1 to the level of the third power voltage VGH, the difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be increased. The difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be greater than the threshold voltage of the third transistor T3b. Accordingly, the third transistor T3b can be turned on, and the third transistor T3b can transmit the first power voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0249] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the start signal FLM has the level of the first power voltage VGL1, the third transistor T3b can be turned off. Accordingly, the leakage current of the third transistor T3b can be reduced, and the voltage of the third control node A can stably maintain the level of the first power voltage VGL1 or the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the third transistor T3b is reduced, the power consumption of the display device 1 can be lowered.

[0250] Figure 15 is a circuit diagram illustrating another embodiment of the first stage ST[1]e included in the gate driver 300a of Figure 11 is a circuit diagram illustrating another embodiment of the first stage ST[1]e included in the gate driver 300a of

[0251] Referring to Figure 15 , the embodiment of the first stage ST[1]e can include the input circuit 10, the control circuit 20b, the first output circuit 30, and the second output circuit 40e. Except that the eighth transistor T8e further includes a second control electrode, Figure 15 the first stage ST[1]e shown in Figure 14the first-stage ST[1]d is substantially the same. Therefore, the same reference numerals will be used to refer to portions that are the same or similar to those described in the previous embodiments, and any repetitive detailed description thereof will be omitted or simplified. Figure 14 the same or similar to those described in the previous embodiments, and any repetitive detailed description thereof will be omitted or simplified.

[0252] In an embodiment, as shown in FIG. 1A, the first-stage ST[1]e can include the first transistor T1, the second transistor T2, the third transistor T3b, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7b, and the eighth transistor T8e. Figure 15 The eighth transistor T8e includes a control electrode connected to the second control node Q, a first electrode connected to the second output node NO2, and a second electrode receiving the first power supply voltage VGL1. In addition, the eighth transistor T8e can further include a second control electrode connected to the control electrode of the eighth transistor T8e.

[0253] Since the control electrode of the eighth transistor T8e is connected to the second control electrode of the eighth transistor T8e, the voltage of the second control electrode of the eighth transistor T8e can be the same as the voltage of the second control node Q.

[0254] In an embodiment, when the voltage of the second control node Q has the level of the boosted voltage VQ, since the voltage of the second control node Q having the level of the boosted voltage VQ is applied to the second control electrode of the eighth transistor T8e, the threshold voltage of the eighth transistor T8e can be offset. The eighth transistor T8e can maintain the initialized threshold voltage. The eighth transistor T8e can be turned off, and the leakage current of the eighth transistor T8e can be reduced. The first-stage ST[1]e can stably output the first gate signal SS[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8e is reduced, the power consumption of the display device 1 can be lowered.

[0255] In an embodiment, the third transistor T3b can be implemented as an N-type transistor, and the level of the fourth power supply voltage VGL3 can be lower than the level of the first power supply voltage VGL1. Since the fourth power supply voltage VGL3 is applied to the second control electrode of the third transistor T3b, the threshold voltage of the third transistor T3b can be offset. Accordingly, the third transistor T3b can maintain the initialized threshold voltage, and the stability and reliability of the gate driver 300a can be improved.

[0256] In an embodiment, the third transistor T3b and the eighth transistor T8e can be implemented as N-type transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be implemented as P-type transistors. In an embodiment, for example, the third transistor T3b and the eighth transistor T8e can be implemented as N-type metal oxide transistors, and the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be implemented as LTPS transistors.

[0257] In the embodiment in which the third transistor T3b and the eighth transistor T8e are implemented as N-type transistors, the leakage current of the third transistor T3b and the eighth transistor T8e can be reduced. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, the power consumption of the display device 1 can be reduced.

[0258] In the embodiment in which the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d are implemented as P-type transistors, the driving current of the first transistor T1, the second transistor T2, and the fourth transistor T4 to the seventh transistor T7d can be increased. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0259] In the embodiment, the first power supply voltage VGL1, the second power supply voltage VGL2, and the fourth power supply voltage VGL3 can be less than about zero (0) V, and the third power supply voltage VGH can be greater than about zero (0) V. In addition, the level of the first power supply voltage VGL1 can be lower than the level of the second power supply voltage VGL2, and the level of the fourth power supply voltage VGL3 can be lower than the level of the first power supply voltage VGL1.

[0260] In addition, when the level of the first gate signal SS[1] is reduced from the level of the third power supply voltage VGH to the level of the second power supply voltage VGL2, the second control node Q can have a boosted voltage VQ. The boosted voltage VQ can be calculated by the following equation: VQ = VGL1 - |Vth_T2| - (VGH - VGL2), where VQ denotes the boosted voltage VQ, VGL1 denotes the first power supply voltage VGL1, Vth_T2 denotes the threshold voltage of the second transistor T2, VGH denotes the third power supply voltage VGH, and VGL2 denotes the second power supply voltage VGL2.

[0261] In the embodiment in which the sixth transistor T6 is implemented as a P-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be increased. Accordingly, when the threshold voltage of the sixth transistor T6 is changed, the difference between the voltage of the control electrode of the sixth transistor T6 and the voltage of the first electrode of the sixth transistor T6 can be greater than the threshold voltage of the sixth transistor T6. That is, the sixth transistor T6 can be turned on. Accordingly, the sixth transistor T6 can stably transfer the second power supply voltage VGL2 to the first output node NO1, and the first stage ST[1]e can stably output the first gate signal SS[1] having the level of the second power supply voltage VGL2. Accordingly, the stability and reliability of the gate driver 300a can be improved.

[0262] In an embodiment, the first power supply voltage VGL1, the second power supply voltage VGL2, and the fourth power supply voltage VGL3 can be less than approximately zero (0) V, and the third power supply voltage VGH can be greater than approximately zero (0) V. In addition, the level of the first power supply voltage VGL1 can be higher than the level of the second power supply voltage VGL2, and the level of the fourth power supply voltage VGL3 can be lower than the level of the first power supply voltage VGL1.

[0263] In such an embodiment, the level of the first power supply voltage VGL1 is higher than the level of the second power supply voltage VGL2, so that the power supply voltage of the display device 1 can be reduced.

[0264] In an embodiment in which the eighth transistor T8e is implemented as an N-type transistor and the voltage of the second control node Q has the level of the third power supply voltage VGH, the difference between the voltage of the control electrode of the eighth transistor T8e and the voltage of the second electrode of the eighth transistor T8e can be increased. The difference between the voltage of the control electrode of the eighth transistor T8e and the voltage of the second electrode of the eighth transistor T8e can be greater than the threshold voltage of the eighth transistor T8e. Accordingly, the eighth transistor T8e can be turned on, and the eighth transistor T8e can transmit the first power supply voltage VGL1 to the first output node NO1. Accordingly, the first stage ST[1]e can stably output the first carry signal CR[1] having the level of the first power supply voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0265] In an embodiment in which the seventh transistor T7d is implemented as a P-type transistor and the voltage of the third control node A has the level of the first power supply voltage VGL1, the seventh transistor T7d can be turned on. In addition, when the eighth transistor T8e is implemented as an N-type transistor and the voltage of the second control node Q has the level of the boosted voltage VQ, the eighth transistor T8e can be turned off. Accordingly, the leakage current of the eighth transistor T8e can be reduced, and the first stage ST[1]e can stably output the first gate signal SS[1] having the level of the third power supply voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the eighth transistor T8e is reduced, the power consumption of the display device 1 can be reduced.

[0266] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the level of the start signal FLM is raised from the level of the first power voltage VGL1 to the level of the third power voltage VGH, the difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be increased. The difference between the voltage of the control electrode of the third transistor T3b and the voltage of the second electrode of the third transistor T3b can be greater than the threshold voltage of the third transistor T3b. Accordingly, the third transistor T3b can be turned on, and the third transistor T3b can transmit the first power voltage VGL1 to the third control node A. The voltage of the third control node A can stably maintain the level of the first power voltage VGL1, and the stability and reliability of the gate driver 300a can be improved.

[0267] In the embodiment in which the third transistor T3b is implemented as an N-type transistor and the start signal FLM has the level of the first power voltage VGL1, the third transistor T3b can be turned off. Accordingly, the leakage current of the third transistor T3b can be reduced, and the voltage of the third control node A can stably maintain the level of the first power voltage VGL1 or the level of the third power voltage VGH. Accordingly, the stability and reliability of the gate driver 300a can be improved. In addition, since the leakage current of the third transistor T3b is reduced, the power consumption of the display device 1 can be lowered.

[0268] Figure 16 is a block diagram illustrating an electronic device 1000 according to an embodiment, and Figure 17 is a diagram illustrating an embodiment in which Figure 16 the electronic device 1000 is implemented as a smart phone.

[0269] Referring to Figure 16 and Figure 17 , an embodiment of the electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 can be Figure 1 the display device 1 of FIG. 1. Furthermore, the electronic device 1000 can further include a port for communication with a video card, a sound card, a memory card, a universal serial bus (USB) device, or other electronic devices, etc.

[0270] In an embodiment, as Figure 17 illustrated in FIG. 1, the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, or a head-mounted display (HMD) device, etc.

[0271] The processor 1010 can perform various computing functions. The processor 1010 can be a microprocessor, a central processing unit (CPU), or an application processor (AP), etc. The processor 1010 can be coupled to other components via an address bus, a control bus, or a data bus, etc. Further, the processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0272] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 the drive controller 200.

[0273] The memory device 1020 can store data for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device, etc.

[0274] The storage device 1030 can include a solid state drive (SSD) device, a hard disk drive (HDD) device, or a CD-ROM device, etc.

[0275] The I / O device 1040 can include an input device such as a keyboard, a keypad, a mouse device, a touch panel, and a touch screen, etc. and an output device such as a printer or a speaker, etc. In some embodiments, the display device 1060 can be included in the I / O device 1040.

[0276] The power supply 1050 can provide power for the operation of the electronic device 1000.

[0277] The display device 1060 can be connected to other components through a bus or other communication link.

[0278] The present application can be applied to a display device and an electronic device (e.g., a television (TV), a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal computer (PC), a home electronic device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.) including the display device.

[0279] The present application should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete and will fully convey the inventive concept of the present application to those skilled in the art.

[0280] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the present application as defined by the appended claims.

Claims

1. A gate driver, comprising: The input circuit transmits the input signal to the first control node based on a clock signal; A control circuit that transmits a first power supply voltage to a third control node based on the input signal, and transmits the first power supply voltage to a second control node based on the first power supply voltage and the voltage of the third control node. A first output circuit outputs a gate signal having a second power supply voltage or a third power supply voltage based on the voltage of the first control node and the voltage of the second control node. as well as The second output circuit outputs a carry signal with the third power supply voltage or the first power supply voltage based on the voltage of the second control node, wherein the carry signal has a phase opposite to that of the gate signal.

2. The gate driver according to claim 1, wherein, The input circuit includes: The first transistor includes a control electrode that receives the clock signal, a first electrode that receives the input signal, and a second electrode connected to the first control node.

3. The gate driver according to claim 2, wherein, The control circuit includes: The second transistor includes a control electrode receiving the first power supply voltage, a first electrode connected to the third control node, and a second electrode connected to the second control node; and... The third transistor includes a control electrode that receives the input signal, a first electrode connected to the third control node, and a second electrode that receives the first power supply voltage.

4. The gate driver according to claim 3, wherein, The control circuit further includes: The fourth transistor includes a control electrode connected to the first control node, a first electrode receiving the third power supply voltage, and a second electrode connected to the third control node; and The second capacitor includes a first electrode that receives the third power supply voltage and a second electrode that is connected to the first control node.

5. The gate driver according to claim 4, wherein, The first output circuit includes: The fifth transistor includes a control electrode connected to the first control node, a first electrode receiving the third power supply voltage, and a second electrode connected to the first output node; The sixth transistor includes a control electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode receiving the second power supply voltage; and The first capacitor includes a first electrode connected to the second control node and a second electrode connected to the first output node.

6. The gate driver according to claim 5, wherein, The second output circuit includes: The seventh transistor includes a control electrode connected to the second control node, a first electrode receiving the third power supply voltage, and a second electrode connected to the second output node; and The eighth transistor includes a control electrode connected to the second control node, a first electrode connected to the second output node, and a second electrode that receives the first power supply voltage.

7. The gate driver according to claim 6, wherein, The third transistor and the eighth transistor are N-type transistors.

8. The gate driver according to claim 7, wherein, The first transistor, the second transistor, and the fourth to seventh transistors are P-type transistors.

9. The gate driver according to claim 6, wherein, The third transistor further includes a second control electrode that receives a fourth power supply voltage.

10. The gate driver according to claim 9, wherein, The level of the fourth power supply voltage is lower than the level of the first power supply voltage.

11. The gate driver according to claim 6, wherein, The eighth transistor further includes a second control electrode connected to the control electrode of the eighth transistor.

12. The gate driver according to claim 6, wherein, The level of the first power supply voltage is lower than the level of the second power supply voltage, and The level of the third power supply voltage is higher than the level of the second power supply voltage.

13. The gate driver according to claim 6, wherein, The level of the first power supply voltage is higher than the level of the second power supply voltage, and The level of the third power supply voltage is higher than the level of the first power supply voltage.

14. A display device, comprising: Display panel, including pixels; The gate driver according to any one of claims 1 to 13, wherein the gate driver outputs the gate signal to the pixel; A data driver that outputs a data voltage to the pixel; and A drive controller that controls the gate driver and the data driver.

15. An electronic device comprising: The processor outputs input control signals and input image data; as well as The display device according to claim 14, The drive controller controls the gate driver and the data driver based on the input control signal and the input image data.

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