Display panel and display device including same

Abstract

Embodiments of the present disclosure relate to a display panel and a display device including the same. Each of sub-pixels in a display panel includes: a first driver configured to receive a pixel driving voltage, a first pixel data voltage, and a plurality of gate signals as inputs and supply a current to a first light emitting element; a second driver configured to receive a pixel driving voltage, a second pixel data voltage, and a plurality of gate signals as inputs and supply a current to a second light emitting element; and a shared switching section including a plurality of transistors connected to the first driver and the second driver and configured to receive the first pixel data voltage and the second pixel data voltage as inputs.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0131260, filed on September 27, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display panel capable of changing viewing angle and a display device including the display panel. Background Technology

[0004] Variable viewing angle technology is being applied to display devices. Variable viewing angle technology allows video content or visual information reproduced on a display device to be visible only to users within a narrow viewing angle range, or to multiple users within a wide viewing angle range.

[0005] With the expansion of the market for future vehicles such as electric and autonomous vehicles, the demand for in-vehicle displays is growing rapidly. Research is underway on how to divide the screen of an in-vehicle display so that one part of the screen can be controlled with a narrow viewing angle while another part is controlled with a wide viewing angle. This technology can display private content or information that only specific users can see on pixels driven by a narrow viewing angle, while displaying shared content that multiple users can view together on pixels driven by a wide viewing angle. To achieve this, pixel technology that can freely control each pixel under both narrow and wide viewing angles is required. Summary of the Invention

[0006] The embodiments of this disclosure resolve the aforementioned disadvantages and / or problems.

[0007] This disclosure provides a display device that can separate the perspective of pixel data of different content without adding a data driver channel to each pixel and enhance privacy protection.

[0008] The problems addressed by the embodiments of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other problems not described in the following description.

[0009] A display panel according to one embodiment includes a plurality of data lines, a plurality of gate lines, a plurality of power lines, a plurality of mode selection lines, and a plurality of sub-pixels. Each of the sub-pixels includes a first light emitting element, a second light emitting element, a first driver configured to receive a pixel driving voltage, a first pixel data voltage, and a plurality of gate signals as inputs and supply a current to the first light emitting element, a second driver configured to receive the pixel driving voltage, a second pixel data voltage, and a plurality of gate voltages as inputs and supply a current to the second light emitting element, and a shared switching part configured to supply the first pixel data voltage to the first driver and supply the second pixel data voltage to the second driver.

[0010] The display panel can include a wide viewing angle lens overlapping with a light emitting area of the first light emitting element, and a narrow viewing angle lens overlapping with a light emitting area of the second light emitting element.

[0011] The first driver can include a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and configured to drive the first light emitting element for a first refresh frame period, a first capacitor connected between a first voltage node to which the pixel driving voltage is applied and the first node, a first switching transistor connected between the first node and the third node, and turned on in response to a gate high voltage of a first scan signal, and turned off in response to a gate low voltage of the first scan signal, a second switching transistor connected between the first node and a third voltage node to which an initialization voltage is applied, and turned on in response to a gate high voltage of a fourth scan signal, and turned off in response to a gate low voltage of the fourth scan signal, and a third switching transistor connected between the third node and a fourth node, and turned on in response to a gate low voltage of a second light emitting signal, and turned off in response to a gate high voltage of the second light emitting signal. The first light emitting element can include an anode electrode connected to the fourth node and a cathode electrode connected to a second voltage node to which a cathode voltage is applied.

[0012] The second driver can include a second driving transistor including a gate electrode connected to a fifth node, a first electrode connected to the second node or an eighth node, and a second electrode connected to a sixth node, and configured to drive the second light emitting element during a second refresh frame period; a second capacitor connected between the first voltage node and the fifth node; a fourth switching transistor connected between the fifth node and the sixth node, and turned on in response to a gate high voltage of a fifth scan signal, and turned off in response to a gate low voltage of the fifth scan signal; a fifth switching transistor connected between the fifth node and a third voltage node, and turned on in response to a gate high voltage of a sixth scan signal, and turned off in response to a gate low voltage of the sixth scan signal; and a sixth switching transistor connected between the sixth node and a seventh node, and turned on in response to a gate low voltage of a third light emitting signal, and turned off in response to a gate high voltage of the third light emitting signal. The second light emitting element can include an anode electrode connected to the seventh node and a cathode electrode connected to the second voltage node.

[0013] The shared switch part can include a seventh switching transistor connected between one data line and the second node, and turned on in response to a gate low voltage of a second scan signal, and turned off in response to a gate high voltage of the second scan signal; an eighth switching transistor connected between the second node and a fifth voltage node to which an on bias voltage is applied, and turned on in response to a gate low voltage of a third-first scan signal, and turned off in response to a gate high voltage of the third-first scan signal; a ninth switching transistor connected between the first voltage node and the second node, and turned on in response to a gate low voltage of a first light emitting signal, and turned off in response to a gate high voltage of the first light emitting signal; a tenth switching transistor connected between the fourth node and a fourth voltage node to which an anode reset voltage is applied, and turned on in response to a gate low voltage of a third-second scan signal, and turned off in response to a gate high voltage of the third-second scan signal; and an eleventh switching transistor connected between the seventh node and the fourth voltage node, and turned on in response to a gate low voltage of the third-second scan signal, and turned off in response to a gate high voltage of the third-second scan signal. Pulses of the third-first scan signal and the third-second scan signal are sequentially generated with the gate low voltage. A first pixel data voltage can be applied to the data line during a first refresh frame period, and a second pixel data voltage can be applied to the data line during a second refresh frame period.

[0014] The shared switch part can include a seventh switch transistor connected between the first data line and a second node and turned on in response to a gate low voltage of a second-first scan signal and turned off in response to a gate high voltage of the second-first scan signal, an eighth switch transistor connected between the second data line and an eighth node and turned on in response to a gate low voltage of a second-second scan signal and turned off in response to a gate high voltage of the second-second scan signal, a ninth switch transistor connected between the second node and a fifth voltage node to which an on bias voltage is applied and turned on in response to a gate low voltage of a third-first scan signal and turned off in response to a gate high voltage of the third-first scan signal, a tenth switch transistor connected between the first voltage node and the second node and turned on in response to a gate low voltage of a first emission signal and turned off in response to a gate high voltage of the first emission signal, an eleventh switch transistor connected between the second node and the eighth node and turned on in response to a gate low voltage of a first scan signal and turned off in response to a gate high voltage of the first scan signal, a twelfth switch transistor connected between the fourth node and a fourth voltage node to which an anode reset voltage is applied and turned on in response to a gate low voltage of a third-second scan signal and turned off in response to a gate high voltage of the third-second scan signal, and a thirteenth switch transistor connected between the seventh node and the fourth voltage node and turned on in response to a gate low voltage of the third-second scan signal and turned off in response to a gate high voltage of the third-second scan signal. Pulses of the third-first scan signal and the third-second scan signal are sequentially generated with the gate low voltage. When the first switch transistor is turned off, the eleventh switch transistor can be turned on, and when the first switch transistor is turned on, the eleventh switch transistor can be turned off.

[0015] The shared switch part can include a seventh switch transistor connected between the first data line and a second node and turned on in response to a gate low voltage of a second-first scan signal and turned off in response to a gate high voltage of the second-first scan signal, an eighth switch transistor connected between the second data line and an eighth node and turned on in response to a gate low voltage of a second-second scan signal and turned off in response to a gate high voltage of the second-second scan signal, a ninth switch transistor connected between the second node and a fifth voltage node to which an on bias voltage is applied and turned on in response to a gate low voltage of a third-first scan signal and turned off in response to a gate high voltage of the third-first scan signal, a tenth switch transistor connected between the first voltage node and the second node and turned on in response to a gate low voltage of a first emission signal and turned off in response to a gate high voltage of the first emission signal, an eleventh switch transistor connected between the fourth node and a fourth voltage node to which an anode reset voltage is applied and turned on in response to a gate low voltage of a third-second scan signal and turned off in response to a gate high voltage of the third-second scan signal, and a twelfth switch transistor connected between the seventh node and the fourth voltage node and turned on in response to a gate low voltage of the third-second scan signal and turned off in response to a gate high voltage of the third-second scan signal. Pulses of the third-first scan signal and the third-second scan signal are sequentially generated with the gate low voltage.

[0016] The display panel can further include a data switch part configured to apply a first pixel data voltage to the first data line and a sustain voltage to the second data line during a first refresh frame period, and to apply a second pixel data voltage to the second data line and the sustain voltage to the first data line during a second refresh frame period.

[0017] The data switch part can include: a first transistor and a second transistor connected in series between a first input node and a first data line; a third transistor and a fourth transistor connected in series between a second input node and the first data line; a fifth transistor and a sixth transistor connected in series between the first input node and a second data line; and a seventh transistor and an eighth transistor connected in series between the second input node and the second data line; wherein the first transistor and the seventh transistor are turned on in response to a gate turn-on voltage of a first selection signal from a first selection line of a plurality of mode selection lines, and are turned off in response to a gate turn-off voltage of the first selection signal. The third transistor and the fifth transistor can be turned on in response to a gate turn-on voltage of a second selection signal from a second selection line of the plurality of mode selection lines, and are turned off in response to a gate turn-off voltage of the second selection signal. The second transistor and the sixth transistor can be turned on in response to a gate turn-on voltage of a third selection signal from a third selection line of the plurality of mode selection lines, and are turned off in response to a gate turn-off voltage of the third selection signal. The fourth transistor and the eighth transistor can be turned on in response to a gate turn-on voltage of a fourth selection signal from a fourth selection line of the plurality of mode selection lines, and are turned off in response to a gate turn-off voltage of the fourth selection signal.

[0018] One or more of the first light emitting element and the second light emitting element can emit light within at least one of the first refresh frame period, the second refresh frame period, and a skip frame period in which pixel data is not updated.

[0019] A display device according to an embodiment includes a display panel including a sub-pixel, a data driver configured to supply a data voltage to a data line, and a gate driver configured to supply a gate signal to a gate line.

[0020] One or more of the first light emitting element and the second light emitting element can emit light within at least one of the first refresh frame period, the second refresh frame period, and a skip frame period in which pixel data is not updated.

[0021] According to an embodiment of the disclosure, the viewing angle of a pixel can be adjusted according to a user's use environment and a need for privacy protection of private content. Accordingly, the disclosure provides a display device that can not only achieve low power and process optimization but also separate pixel data of private content and pixel data of shared content in each pixel and enhance a privacy protection function.

[0022] According to an embodiment of the disclosure, privacy can be protected by reproducing a video of private content that needs privacy protection with a narrow viewing angle without interfering with viewing a video of shared content.

[0023] According to embodiments of the present disclosure, since a video of shared content can be reproduced in a wide viewing angle and a video of private content can be reproduced in a narrow viewing angle in one pixel, a phenomenon in which some pixels have a black gray level, i.e., which looks black when the wide viewing angle video and the narrow viewing angle video are displayed together, can be prevented.

[0024] According to embodiments of the present disclosure, shared content and private content can be reproduced in different viewing angles in a pixel without increasing the number of channels of data lines and data drivers.

[0025] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects not described will be understood by those skilled in the art from the following description and the attached claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a block diagram illustrating a display apparatus according to an embodiment of the present disclosure;

[0028] Figures 2A-2C is a diagram illustrating an example of a gate driver;

[0029] Figure 3 is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0030] Figure 4 is a diagram illustrating an example of a lens disposed in a sub-pixel;

[0031] Figure 5 is a circuit diagram illustrating an example of the pixel circuit shown in Figure 3 in detail;

[0032] Figure 6 is a waveform diagram illustrating a gate signal applied to the pixel circuit shown in Figure 5 in a first refresh frame period, a second refresh frame period, and a skip frame period;

[0033] Figure 7 is a waveform diagram illustrating an example of a gate signal applied to the pixel circuit shown in Figure 5 in a first refresh frame period;

[0034] Figures 8A-8E is a circuit diagram illustrating an operation of the pixel circuit shown in Figure 5 in a first refresh frame period;

[0035] Figure 9It is shown that during the second refresh frame period, it is applied to Figure 5 A waveform diagram of an example of the gate signal of the pixel circuit shown;

[0036] Figure 10A-10E It is shown in stages. Figure 5 The circuit diagram shown illustrates the operation of the pixel circuit during the second refresh frame period.

[0037] Figure 11 This is a circuit diagram showing a pixel circuit and a switching unit according to another embodiment of the present disclosure;

[0038] Figure 12 This is a circuit diagram showing a pixel circuit and a switching unit according to yet another embodiment of the present disclosure;

[0039] Figure 13 It is shown that the force applied during the first refresh frame period, the second refresh frame period, and the skip frame period is applied to Figure 11 and Figure 12 The waveform diagram of the gate signal of the pixel circuit shown;

[0040] Figures 14A-14E It is shown in stages. Figure 11 The circuit diagram shown illustrates the operation of the pixel circuit during the first refresh frame period.

[0041] Figures 15A-15E It is shown in stages. Figure 11 The circuit diagram shown illustrates the operation of the pixel circuit during the second refresh frame period; and

[0042] Figure 16A and Figure 16B It is shown in stages. Figure 11 The diagram shows the operation of the pixel circuit during the skip frame period. Detailed Implementation

[0043] The advantages and features of this disclosure, as well as the methods for implementing it, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope.

[0044] The shapes, dimensions, scales, angles, numbers, etc., shown in the accompanying drawings to illustrate embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0045] Terms such as “including,” “comprising,” “having,” and “containing” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0046] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0047] When describing the location or interconnection between two components, such as “on top of”, “above”, “below”, “near”, “connected to or coupled to”, “cross”, “intersect”, etc., unless “immediately adjacent” or “directly” is used, one or more other components may be inserted between them.

[0048] When describing time precedence relationships, such as "after", "following", "immediately following", "before", etc., it may not be sequential on a time basis unless "immediately" or "directly" is used.

[0049] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding the component.

[0050] The following implementation methods may be combined or integrated with each other in whole or in part, and may be connected and operated in various technical ways. The implementation methods may be performed independently or in connection with each other.

[0051] The pixel circuit and gate drive circuit of the display device may include multiple transistors. The transistors may be implemented as thin-film transistors (TFTs). The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon, etc.

[0052] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0053] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The transistor turns on in response to the gate on-voltage and turns off in response to the gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH, and the gate off-voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-voltage can be the gate low voltage VGL, and the gate off-voltage can be the gate high voltage VGH.

[0054] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0055] Reference Figure 1 The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0056] The display panel 100 may be, but is not limited to, a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a deformed panel that is at least partially curved or elliptical.

[0057] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes: a plurality of data lines 102; a plurality of gate lines 103 intersecting the data lines 102; and pixels arranged in a matrix. The display panel 100 may also include a plurality of power lines. The power lines are connected to constant voltage nodes of the pixel circuitry and supply the constant voltage required to drive the pixels 101. The power lines may be implemented as stripes or mesh wiring commonly connected to the pixels 101 of the display panel 100.

[0058] Each of the pixels 101 can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels for color implementation. Each of the pixels may also include a white sub-pixel. Each of the pixels may include pixel circuitry for driving a first light-emitting element and a second light-emitting element to selectively emit light according to a selected viewing mode. The light-emitting element may be a light-emitting element such as an organic light-emitting diode (OLED) or a micro light-emitting diode (LED). In the following description, a pixel may be interpreted as a sub-pixel.

[0059] The display array AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the X-axis in the pixel array of the display panel 100. Pixels arranged in a pixel line may share a gate line 103. Sub-pixels arranged along the Y-axis may share the same data line 102. A horizontal time period is obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0060] A touch sensor can be provided on the display panel 100 to sense touch input. The touch sensor can be arranged on the display panel 100 in an on-cell type or an add-on type, or it can be implemented as an in-cell type touch sensor embedded in the pixel array.

[0061] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device in which an image is displayed on a screen and the actual object is visible outside the display panel. The display panel 100 can be made as a flexible display panel that can be flexibly bent.

[0062] Power supply 150 receives input voltage from host system 200 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate high voltage, gate low voltage, pixel drive voltage, cathode voltage, initialization voltage, and IC drive voltage for display panel driving circuitry. Gate high voltage and gate low voltage can be supplied to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and initialization voltage can be supplied to pixel 101 via a power line commonly connected to pixel 101.

[0063] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage, and outputs a plurality of gamma reference voltages divided at predetermined voltage intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are supplied to a data driver 110. In the data driver 110, the gamma reference voltages are divided and subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator can be implemented as a programmable gamma circuit capable of adjusting each of the gamma reference voltages according to digital data. The timing controller 130, the host system 200, or a separate external device can update the digital data to be stored in the registers of the programmable gamma circuit via a communication interface.

[0064] The display panel driving circuit, under the control of the timing controller 130, writes pixel data of the input image into pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit may also include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into the source driver integrated circuit (IC).

[0065] Data driver 110 receives pixel data of an input image as a digital signal from timing controller 130 and outputs a data voltage. The input image can be image data including various content such as private content, shared content, etc. Data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each gray level through a voltage divider circuit. The gamma compensation voltage for each gray level is supplied to a digital-to-analog converter (“DAC”) disposed on each of the channels of data driver 110. Data driver 110 samples and latches the pixel data and then inputs the digital data to the DAC. The DAC converts the pixel data into a gamma compensation voltage and outputs a pixel data voltage.

[0066] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gate driver 120 may be disposed in a non-display area NA on at least one of the right or left sides outside the display area AA in the display panel 100, or at least a portion of the gate driver 120 may be disposed within the display area AA.

[0067] Gate driver 120 can be disposed in the non-display areas NA on both sides of display panel 100, wherein display area AA of display panel 100 is inserted between non-display areas NA, and gate pulses can be supplied from both sides of gate line 103 in a double-fed manner. In another embodiment, gate driver 120 can be disposed in at least one of the left and right non-display areas NA of display panel 100 to supply gate signal to gate line 103 in a single-fed manner. Gate driver 120 sequentially outputs gate signal pulses to gate line 103 under the control of timing controller 130. Gate driver 120 can sequentially supply gate signal to gate line 103 by shifting the gate signal pulses using shift register or edge trigger.

[0068] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the digital video data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical and horizontal time periods can be known by counting the data enable signal DE, and therefore, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a time period of one horizontal time period (1H).

[0069] The timing controller 130 generates, based on the timing signals Vsync, Hsync, and DE received from the host system 200, a data timing control signal for controlling the operating timing of the data driver 110, a gate timing control signal for controlling the operating timing of the gate driver 120, and a mode selection signal for controlling the viewing angle mode of each of the pixels 101, thereby controlling the pixels 101 and the display panel driving circuit. The timing controller 130 can synchronize the data driving circuit 110 and the gate driver 120 by controlling the operating timing of the display panel driving circuit.

[0070] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 via the level shifter 140. The level shifter 140 can convert the voltage level of the gate timing signal received from the timing controller 130 into a swing width between the gate low voltage and the gate high voltage, and supply it to the gate driver 120. The clock signal output from the level shifter 140 may include a start signal and a clock for independently controlling the rising edge, gate on-voltage period, and polling edge of each of the gate signals.

[0071] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can send the image signal along with a timing control signal to the timing controller 130. The host system 200 can send a mode signal for controlling the viewing angle, along with the image signal and a flag signal indicating the presence or absence of personal content requiring privacy protection, to the timing controller 130. The timing controller 130 can control the gate signal output from the gate driver 120 in the viewing angle mode selected by the mode signal from the host system 200, and control the data driver 110 in the selected viewing angle mode. The timing controller 130 can output a mode selection signal based on the mode signal from the host system 200.

[0072] When multiple gate signals are applied to each pixel, gate driver 120 may include multiple gate drivers. Figures 2A-2CThe diagram shows the first scan signals SCAN1(1) to SCAN1(n), the second scan signals SCAN2(1) to SCAN2(n), the third scan signals SCAN3(1) to SCAN3(n), the fourth scan signals SCAN4(1) to SCAN4(n), the fifth scan signals SCAN5(1) to SCAN5(n), the sixth scan signals SCAN6(1) to SCAN6(n), the first luminous emission signals EM1(1) to EM1(n), and the second EM signals EM2(1) to EM2(n) input to the pixel circuit via multiple gate lines. In the following text, the “luminous emission signal” is referred to as the “EM signal”. In this case, the gate driver 120 includes a first gate driver 121 that outputs first scan signals SCAN1(1) to SCAN1(n), a second gate driver 122 that outputs second scan signals SCAN2(1) to SCAN2(n), a third gate driver 123 that outputs third scan signals SCAN3(1) to SCAN3(n), a fourth gate driver 124 that outputs fourth scan signals SCAN4(1) to SCAN4(n), a fifth gate driver 125 that outputs fifth scan signals SCAN5(1) to SCAN5(n), a sixth gate driver 126 that outputs sixth scan signals SCAN6(1) to SCAN6(n), a seventh gate driver 127 that outputs first EM signals EM1(1) to EM1(n), an eighth gate driver 128 that outputs second EM signals EM2(1) to EM2(n), and a ninth gate driver 129 that outputs third EM signals EM3(1) to EM3(n). Figures 2A-2C In the given (ni), i is a positive integer less than n.

[0073] The start signals VST1 to VST9 and the clock signals S1CLK to E3CLK can be input to the gate drivers 121 to 129 respectively. Each of the gate drivers 121 to 129 includes a plurality of cascaded signal transmission sections ST1 to ST9. The signal transmission sections ST1 to ST9 of the gate drivers 121 to 129 receive the start signals VST1 to VST9 and the clock signals S1CLK to E3CLK, and sequentially output the gate signals SCAN1(1) to SCAN1(n), SCAN2(1) to SCAN2(n), SCAN3(1) to SCAN3(n), SCAN4(1) to SCAN4(n), SCAN5(1) to SCAN5(n), SCAN6(1) to SCAN6(n), EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n). The waveforms of the gate signals SCAN1(1) to SCAN1(n), SCAN2(1) to SCAN2(n), SCAN3(1) to SCAN3(n), SCAN4(1) to SCAN4(n), SCAN5(1) to SCAN5(n), SCAN6(1) to SCAN6(n), EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n) can be as follows: Figure 6 The waveforms of the gate signals SCAN1(1) to SCAN1(n), SCAN2(1) to SCAN2(n), SCAN3(1) to SCAN3(n), SCAN4(1) to SCAN4(n), SCAN5(1) to SCAN5(n), and SCAN6(1) to SCAN6(n) are adjusted by the subpixel-based view mode modulation start signals VST1 to VST9 and clocks S1CLK to E3CLK to match the selected view mode.

[0074] Figure 3 This is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure. Figure 4 This is a diagram showing an example of a lens set in a sub-pixel.

[0075] Reference Figure 3 and Figure 4 Each of the sub-pixels of the display panel 100 includes a first light-emitting element EL1, a second light-emitting element EL2, a first driver 10, a second driver 20, and a shared switch section 30.

[0076] Each of the first light-emitting element EL1 and the second light-emitting element EL2 can be a light-emitting element such as an organic light-emitting diode (OLED) or a micro-light-emitting element (LED), but this disclosure is not limited thereto. The first light-emitting element EL1 can be driven to emit light in a first viewing angle mode. When the first light-emitting element EL1 emits light, the light from the first light-emitting element EL1 can be diffused by the first lens 42 and emitted with a wide viewing angle. The second light-emitting element EL2 can be driven to emit light in a second viewing angle mode. When the second light-emitting element EL2 emits light, the light from the second light-emitting element EL2 can be converged by the second lens 44 and emitted with a narrow viewing angle.

[0077] The first driver 10 receives a pixel driving voltage EVDD, a first pixel data voltage Vdata, and gate signals SCAN1(n), SCAN4(n), and EM2(n) as inputs, and supplies current to the first light-emitting element EL1 to drive the first light-emitting element EL1. The first driver 10 may include a first capacitor and multiple transistors. The second driver 20 receives a pixel driving voltage EVDD, a second pixel data voltage Vdata, and gate signals SCAN5(n), SCAN6(n), and EM3(n) as inputs, and supplies current to the second light-emitting element EL2 to drive the second light-emitting element EL2. The second driver 20 may include a second capacitor and multiple transistors.

[0078] The shared switch unit 30 includes a plurality of transistors electrically connected to the first driver 10 and the second driver 20. The shared switch unit 30 receives the first pixel data voltage and the second pixel data voltage as inputs, receives gate signals SCAN2(n), SCAN3(n), SCAN3(n+1) and EM1(n) as inputs, and selectively transmits the data voltage Vdata to the first driver 10 and the second driver 20.

[0079] Reference Figure 3 The first lens 42 is a lens disposed above the first light-emitting element EL1 for a wide viewing angle. The first lens 42 overlaps with the light-emitting area of ​​the first light-emitting element EL1. The first lens 42 can be implemented as a semi-cylindrical lens to limit the upper and lower viewing angles and widen the right and left viewing angles. The first lens 42 is long in the left-right direction (or X-axis direction) of the display panel 100 and narrow in the up-down direction (Y-axis direction) of the display panel 100. The first lens 42 causes the light from the first light-emitting element EL1 to converge in the up-down direction and diffuse the light from the first light-emitting element EL1 with a wide viewing angle in the left-right direction, so that the light from the first light-emitting element EL1 travels with a wide viewing angle in the left-right direction.

[0080] The second lens 44 is a lens disposed above the second light-emitting element EL2 for a narrow viewing angle. The second lens 44 overlaps with the light-emitting area of ​​the second light-emitting element EL2. The second lens 44 may be a hemispherical lens that is thicker at the center and thinner towards the edges in the vertical and horizontal directions. The second lens 44 converges the light from the second light-emitting element EL2 so that the light emitted from the second light-emitting element EL2 travels with a narrow viewing angle in the vertical and horizontal directions.

[0081] The first lens 42 and the second lens 44 can be implemented using a transparent medium or transparent insulating layer pattern disposed in the display panel 100, but this disclosure is not limited thereto. The first lens 42 and the second lens 44 can prevent light from the pixels from reflecting off the windshield of the vehicle and remaining visible on the screen of the display device by limiting the vertical viewing angle of the pixels.

[0082] The display panel driving circuit can be driven at a variable refresh rate (VRR) under the control of the timing controller 130 or the host system 200. For example, the timing controller 130 can reduce the power consumption of the display device by analyzing the input video and reducing the refresh rate when the input video does not change within a preset time. For example, the display panel driving circuit can reduce the power consumption of the display device by controlling the data writing period to be longer under the control of the timing controller 130 by reducing the refresh rate of pixel P when a still image has been input for a given time or longer. The display device can operate in standby mode, or the driving circuit of the display panel 100 can reduce the refresh rate in response to a user command. The refresh rate can be reduced on an always-on display (AOD) screen. An AOD screen is a portion of the display area AA in standby mode on which preset information, such as brief information like battery charging status and time, is displayed.

[0083] The timing controller 130 or the host system 200 can control the viewing angle of a pixel to a first viewing angle during the first frame period by controlling the display panel driving circuit. The timing controller 130 or the host system 200 can control the viewing angle of a pixel to a second viewing angle during the second frame period by controlling the display panel driving circuit. The timing controller 130 or the host system 200 can use a variable refresh rate to change the viewing angle of each pixel. In this case, the first frame period can be a frame period of a pixel-driven period with a high refresh rate, and the second frame period can be a frame period of a pixel-driven period with a relatively low refresh rate, but this disclosure is not limited thereto. The refresh rate can be the frequency at which data is written to a pixel in a refresh frame. When pixel data of general-purpose video is written to a pixel, the pixel data can be written to the pixel at a refresh rate equal to or higher than 60Hz or 120Hz. When the aforementioned low-speed drive event occurs, a low-speed drive mode can be advanced, and pixel data can be written to the pixel at a refresh rate lower than 60Hz (e.g., at a frequency of 1Hz to 10Hz). When the refresh rate is 1Hz, pixel data can be written to the pixel within one refresh frame period per second, and the 119 frame periods can be skipped frame periods or blank periods where no pixel data is written and the data voltage charged in the previous refresh frame period is maintained. When the refresh rate is 120Hz, pixel data can be written to the pixel within 120 refresh frame periods per second.

[0084] Figure 5 It is shown in detail Figure 3 The circuit diagram is an example of a pixel circuit. Figure 5 The pixel circuit shown can be a pixel circuit for a sub-pixel in the nth (where n is a natural number) pixel line. Figure 6 It is shown that the force applied during the first refresh frame period, the second refresh frame period, and the skip frame period is applied to Figure 5 The waveform diagram of the gate signal of the pixel circuit shown is shown.

[0085] Reference Figure 5 and Figure 6 The pixel circuit is connected to the data line to which the pixel data voltage Vdata is applied and the gate lines to which the gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n) and EM3(n) are applied.

[0086] The pixel circuit can be connected to power nodes to which a constant voltage is applied, such as a first voltage node to which a pixel drive voltage EVDD is applied, a second voltage node to which a cathode voltage EVSS is applied, a third voltage node to which an initialization voltage Vini is applied, a fourth voltage node to which an anode reset voltage VAR is applied, and a fifth voltage node to which a conduction bias voltage VOBS is applied. The cathode voltage EVSS can be the pixel ground voltage. The power lines to which the voltage nodes are connected can collectively connect to all pixels on the display panel 100.

[0087] The pixel drive voltage EVDD and cathode voltage EVSS can be set to voltages that allow the drive transistor DT1 to operate in the saturation region. The pixel drive voltage EVDD can be set to a voltage of 2V to 4V, and the cathode voltage EVSS can be set to a voltage of -9V to -7V, but this disclosure is not limited thereto.

[0088] The anode reset voltage VAR can be from -13V to -10V, but this disclosure is not limited thereto. For example, the anode reset voltage VAR can be distinguished by the color of the sub-pixels. The anode reset voltage VAR can initialize the anode electrodes of the light-emitting elements EL1 and EL2. The on-bias voltage VOBS can be from 4V to 6V, but this disclosure is not limited thereto. The on-bias voltage VOBS can improve the hysteresis of the driving transistor DT1 by changing the direction of the current flowing in the driving transistor DT1.

[0089] The initialization voltage Vini can be set to a voltage lower than the lower limit of the data voltage Vdata and higher than the cathode voltage EVSS, but this disclosure is not limited thereto. For example, the data voltage Vdata can have a dynamic range of 2V to 6V. Within this dynamic range, the voltage level of the data voltage Vdata can be selected based on the grayscale value of the pixel data. In this case, the initialization voltage Vini can be set to a voltage from -6V to -3V, but this disclosure is not limited thereto.

[0090] Gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n), and EM3(n) may include pulses that oscillate between a gate high voltage VGH and a gate low voltage VGL. The gate high voltage VGH of gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n), and EM3(n) may be set to a voltage higher than the pixel drive voltage EVDD, while the gate low voltage VGL may be set to a voltage lower than the cathode voltage EVSS. For example, the gate high voltage may be set to a voltage between 5V and 10V, while the gate low voltage may be set to a voltage between -18V and -10V.

[0091] The first driver 10 includes a first driving transistor DT1, a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, and a first capacitor Cst1. The first driving transistor DT1 and the third switching transistor T3 can be implemented using a p-channel LTPS TFT with good on-current characteristics, but this disclosure is not limited thereto. The first switching transistor T1 and the second switching transistor T2 can be implemented using an n-channel oxide TFT with low off-current, but this disclosure is not limited thereto. Off-current is the leakage current flowing through the semiconductor channel of the transistor in the off-state.

[0092] The first driving transistor DT1 generates current based on the gate-source voltage Vgs during the first refresh frame period RFR1 and drives the first light-emitting element EL1. The first driving transistor DT1 includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. A first capacitor Cst1 is connected between the first voltage node to which the pixel driving voltage EVDD is applied and the first node n1.

[0093] The first light-emitting element EL1 can be driven by current from the first driving transistor DT1 and can emit light. The anode electrode of the first light-emitting element EL1 is connected to the fourth node n4, and the cathode electrode of the first light-emitting element EL1 is connected to the second voltage node to which the cathode voltage EVSS is applied.

[0094] A first switching transistor T1 is connected between a first node n1 and a third node n3. The first switching transistor T1 is turned on in response to a high gate voltage VGH of the first scan signal SCAN1(n) and can be turned off in response to a low gate voltage VGL of the first scan signal SCAN1(n). When the first switching transistor T1 is on, the first node n1 is electrically connected to the third node n3. The first switching transistor T1 includes a gate electrode connected to a first gate line to which the first scan signal SCAN1(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0095] The second switching transistor T2 is connected between the first node n1 and the third voltage node to which the initialization voltage Vini is applied. The second switching transistor T2 can be turned on in response to a high gate voltage VGH of the fourth scan signal SCAN4(n) and turned off in response to a low gate voltage of the fourth scan signal SCAN4(n). When the second switching transistor T2 is on, the initialization voltage Vini is applied to the first node n1. The second switching transistor T2 includes a gate electrode connected to the fourth gate line to which the fourth scan signal SCAN4(n) is applied, a first electrode connected to the first node n1, and a second electrode to which the initialization voltage Vini is applied.

[0096] The third switching transistor T3 is connected between the third node n3 and the fourth node n4. The third switching transistor T3 can be turned on in response to a low gate voltage VGL of the second EM signal EM2(n). When the third switching transistor T3 is turned on, the third node n3 can be electrically connected to the fourth node n4. The third switching transistor T3 includes a gate electrode connected to the eighth gate line to which the second EM signal EM2(n) is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0097] The second driver 20 includes a second driving transistor DT2, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, and a second capacitor Cst2. The second driving transistor DT2 and the sixth switching transistor T6 can be implemented using a p-channel LTPS TFT, but this disclosure is not limited thereto. The fourth switching transistor T4 and the fifth switching transistor T5 can be implemented using an n-channel oxide TFT, but this disclosure is not limited thereto.

[0098] The second driving transistor DT2 generates current according to the gate-source voltage Vgs during the second refresh frame period RFR2 and drives the second light-emitting element EL2. The second driving transistor DT2 includes a gate electrode connected to the fifth node n5, a first electrode connected to the second node n2, and a second electrode connected to the sixth node n6. The second capacitor Cst2 is connected between the first voltage node to which the pixel driving voltage EVDD is applied and the fifth node n5.

[0099] The second light-emitting element EL2 can be driven by current from the second driving transistor DT2 and can emit light. The anode electrode of the second light-emitting element EL2 is connected to the seventh node n7, and the cathode electrode of the second light-emitting element EL2 is connected to the second voltage node to which the cathode voltage EVSS is applied.

[0100] A fourth switching transistor T4 is connected between the fifth node n5 and the sixth node n6. The fourth switching transistor T4 can be turned on in response to a high gate voltage VGH of the fifth scan signal SCAN5(n) and turned off in response to a low gate voltage VGL of the fifth scan signal SCAN5(n). When the fourth switching transistor T4 is on, the fifth node n5 is electrically connected to the sixth node n6. The fourth switching transistor T4 may include a gate electrode connected to the fifth gate line to which the fifth scan signal SCAN5(n) is applied, a first electrode connected to the fifth node n5, and a second electrode connected to the sixth node n6.

[0101] A fifth switching transistor T5 is connected between the fifth node n5 and the third voltage node to which the initialization voltage Vini is applied. The fifth switching transistor T5 can be turned on in response to a high gate voltage VGH of the sixth scan signal SCAN6(n) and turned off in response to a low gate voltage VGL of the sixth scan signal SCAN6(n). When the fifth switching transistor T5 is on, the initialization voltage Vini is applied to the fifth node n5. The fifth switching transistor T5 includes a gate electrode connected to the sixth gate line to which the sixth scan signal SCAN6(n) is applied, a first electrode connected to the fifth node n5, and a second electrode to which the initialization voltage Vini is applied.

[0102] A sixth switching transistor T6 is connected between the sixth node n6 and the seventh node n7. The sixth switching transistor T6 can be turned on in response to a low gate voltage VGL of the third EM signal EM3(n) and turned off in response to a high gate voltage VGH of the third EM signal EM3(n). When the sixth switching transistor T6 is on, the sixth node n6 is electrically connected to the seventh node n7. The sixth switching transistor T6 includes a gate electrode connected to the ninth gate line to which the third EM signal EM3(n) is applied, a first electrode connected to the sixth node n6, and a second electrode connected to the seventh node n7.

[0103] The shared switching section 30 includes a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, a tenth switching transistor T10, and an eleventh switching transistor T11. The seventh to eleventh switching transistors T7 can be implemented using p-channel LTPS TFTs, but this disclosure is not limited thereto.

[0104] The first pixel data voltage is applied to the data line DL during the first refresh frame period RFR1. The second pixel data voltage is applied to the data line DL during the second refresh frame period RFR2. Therefore, pixel data with different contents can be sequentially written to sub-pixels via a single data line DL.

[0105] A seventh switching transistor T7 is connected between the data line DL, to which the applied data voltage Vdata is applied, and the second node n2. The seventh switching transistor T7 can be turned on in response to a low gate voltage VGL of the second scan signal SCAN2(n) and turned off in response to a high gate voltage VGH of the second scan signal SCAN2(n). When the seventh switching transistor T7 is on, the data line DL, to which the applied pixel data voltage Vdata is applied, is electrically connected to the second node n2, and the data voltage Vdata is applied to the second node n2. The seventh switching transistor T7 includes a gate electrode connected to the second gate line to which the second scan signal SCAN2(n) is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0106] An eighth switching transistor T8 is connected between the second node n2 and the fifth voltage node to which an on-bias voltage VOBS is applied. The eighth switching transistor T8 can be turned on in response to a low gate voltage VGL of the third-first scan signal SCAN3(n) and turned off in response to a high gate voltage VGH of the third-first scan signal SCAN3(n). When the eighth switching transistor T8 is on, the on-bias voltage VOBS is applied to the second node n2. The eighth switching transistor T8 includes a gate electrode connected to the third-first gate line to which the third-first scan signal SCAN3(n) is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0107] A ninth switching transistor T9 is connected between a first voltage node and a second node n2 to which the pixel driving voltage EVDD is applied. The ninth switching transistor T9 can be turned on in response to a low gate voltage VGL of the first EM signal EM1(n) and turned off in response to a high gate voltage VGH of the first EM signal EM1(n). When the ninth switching transistor T9 is on, the pixel driving voltage EVDD is applied to the second node n2. The ninth switching transistor T9 includes a gate electrode connected to the seventh gate line to which the first EM signal EM1(n) is applied, a first electrode connected to the first voltage node, and a second electrode connected to the second node n2.

[0108] The tenth switching transistor T10 is connected between the fourth node n4 and the fourth voltage node to which the anode reset voltage VAR is applied. The tenth switching transistor T10 can be turned on in response to a low gate voltage VGL of the third-second scan signal SCAN3(n+1) and turned off in response to a high gate voltage VGH of the third-second scan signal SCAN3(n+1). When the tenth switching transistor T10 is on, the anode reset voltage VAR is applied to the fourth node n4. The tenth switching transistor T10 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth voltage node.

[0109] The eleventh switching transistor T11 is connected between the seventh node n7 and the fourth voltage node to which the anode reset voltage VAR is applied. The eleventh switching transistor T11 can be turned on in response to a low gate voltage VGL of the third-second scan signal SCAN3(n+1) and turned off in response to a high gate voltage VGH of the third-second scan signal SCAN3(n+1). When the eleventh switching transistor T11 is on, the anode reset voltage VAR is applied to the seventh node n7. The eleventh switching transistor T11 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the seventh node n7, and a second electrode connected to the fourth voltage node.

[0110] The pulses of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated sequentially with a low gate voltage VGL. The pulse of the third-first scan signal SCAN3(n) is applied to the gate electrode of the eighth switching transistor T8 in the pixel of the nth pixel line, and to the gate electrodes of the tenth switching transistor T10 and the eleventh switching transistor T11 in the pixel of the (n-1)th pixel line. Subsequently, the pulse of the third-second scan signal SCAN3(n+1) is applied to the gate electrodes of the tenth switching transistor T10 and the eleventh switching transistor T11 in the pixel of the nth pixel line, and to the gate electrode of the eighth switching transistor T8 in the pixel of the (n+1)th pixel line. Therefore, in each pixel line, the tenth switching transistor T10 and the eleventh switching transistor T11 can be turned on after the eighth switching transistor T8 is turned on.

[0111] Reference Figure 6 The first refresh frame period RFR1 is the frame period in which the first pixel data voltage Vdata is charged into the first capacitor Cst1. The first pixel data can be shared content data reproduced at a wide viewing angle. The second refresh frame period RFR2 is the frame period in which the second pixel data voltage Vdata is charged into the second capacitor Cst2. The second pixel data can be private content or content that requires privacy protection. The skip frame period SFR is a period in low-speed drive mode where, when the refresh rate is below 60Hz, no new data voltage is charged and the data voltage charged into the first capacitor Cst1 or the second capacitor Cst2 is maintained within the previous refresh frame period. The pulse of the second scan signal SCAN2(n), synchronized with the pixel data voltage Vdata, is applied to the pixel circuit during the first refresh frame period RFR1 and the second refresh frame period RFR2, but is not generated during the skip frame period SFR.

[0112] In each of the first refresh frame period RFR1, the second refresh frame period RFR2, and the skip frame period SFR, one or more of the light-emitting elements EL1 and EL2 may emit light after the capacitors Cst1 and Cst2 are programmed using pixel data. After the sub-pixel is programmed using first pixel data during the first refresh frame period RFR1, one or more of the light-emitting elements EL1 and EL2 of the sub-pixel may emit light during the emission period of the first refresh frame. After the sub-pixel is programmed using second pixel data during the second refresh frame period RFR2, one or more of the light-emitting elements EL1 and EL2 of the sub-pixel may emit light. During the skip frame period SFR, one or more of the light-emitting elements EL1 and EL2 of the sub-pixel may emit light without updating the pixel data. In each of the first refresh frame period RFR1, the second refresh frame period RFR2, and the skip frame period SFR, the light-emitting elements EL1 and EL2 may be selectively driven according to the data voltage charged in the capacitors Cst1 and Cst2 and the second EM signal EM2(n) and the third EM signal EM3(n).

[0113] In each of the first refresh frame period RFR1, the second refresh frame period RFR2, and the skip frame period SFR, when the third switching transistor T3 is turned on in response to the second EM signal EM2(n), the current generated by the gate-source voltage of the first driving transistor DT1 charged in the first capacitor Cst1 can be supplied to the first light-emitting element EL1, and the first pixel data can be reproduced with a wide viewing angle. When the sixth switching transistor T6 is turned on in response to the third EM signal EM3(n), the current generated by the gate-source voltage of the second driving transistor DT2 charged in the second capacitor Cst2 can be supplied to the second light-emitting element EL2, and the second pixel data can be reproduced with a narrow viewing angle.

[0114] In low-speed drive mode, after the first pixel data is written to the pixel during the first refresh frame period RFR1, the second pixel data can be written to the pixel during the second refresh frame period RFR2. The third frame period to the 120th frame period can be controlled as a skip frame period, so pixel data can not be written, and the sub-pixels can be driven using the voltage stored in capacitors Cst1 and Cst2.

[0115] Figures 7-8E This diagram illustrates the phased operation of the pixel circuit during the first refresh frame period. Figure 7 It is shown that the force applied during the first refresh frame period is applied to Figure 5 The waveform diagram shows an example of the gate signal of the pixel circuit shown. Figures 8A-8E It is shown in stages. Figure 5 The diagram shows the operation of the pixel circuit during the first refresh frame period.Figures 8A-8E In the diagram, "X" indicates a transistor that is in the off state, and the arrow represents the current path.

[0116] Reference Figures 7-8E The first refresh frame period RFR1 may include a first period P11, a second period P12, a third period P13, a fourth period P14, and a fifth period P15. During the first refresh frame period RFR1, the voltages of the fifth scan signal SCAN5(n) and the sixth scan signal SCAN6(n) input to the second driver 20 may be the gate low voltage VGL, and the voltage of the third EM signal EM3(n) may be the gate high voltage VGH. In this case, during the first refresh frame period RFR1, the switching transistors T4, T5, and T6 of the second driver 20 remain in the off state.

[0117] During the first time period P11, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of the gate low voltage VGL that are sequentially shifted during the first time period P11. The voltage of the second scan signal SCAN2(n) is a gate high voltage VGH during the first time period P11. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the first time period P11. Therefore, during the first time period P11, as... Figure 8A As shown, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0118] During the first time period P11, such as Figure 8A As shown, the switching transistors T1 to T6, the seventh switching transistor T7, and the ninth switching transistor T9 of the first driver 10 and the second driver 20 are turned off in response to the gate turn-off voltage (VGH or VGL). During the first time period P11, driving transistors DT1 and DT2 can be turned on; however, since the third switching transistor T3 and the sixth switching transistor T6 are in the off state, no current can be supplied to the light-emitting elements EL1 and EL2. Furthermore, since the voltage difference between the anode reset voltage VAR and the cathode voltage EVSS is less than the threshold voltage of each of the light-emitting elements EL1 and EL2, the light-emitting elements EL1 and EL2 do not emit light during the first time period P11.

[0119] During the second time period P12, the voltages of the fifth scan signal SCAN5(n) and the sixth scan signal SCAN6(n) are the gate low voltage VGL, and the voltages of the other gate signals SCAN1(n), SCAN2(n), SCAN3(n), SCAN3(n+1), SCAN4(n), EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. Therefore, during the second time period P12, as Figure 8B As shown, the first switching transistor T1 and the second switching transistor T2 are turned on, and the initialization voltage Vini is applied to the first node n1 and the third node n3. The other switching transistors T3 to T11 are in the off state. During the second time period P12, since the light-emitting elements EL1 and EL2 are in the off state, the light-emitting elements EL1 and EL2 do not emit light.

[0120] During the third time period P13, the voltage of the second scan signal SCAN2(n) is generated by a pulse of the gate low voltage VGL, synchronized with the first pixel data voltage Vdata. During the third time period P13, the voltages of the first scan signal SCAN1(n), the third scan signals SCAN3(n) and SCAN3(n+1), and the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH, and the voltage of the fourth scan signal SCAN4(n) is the gate low voltage VGL. During the third time period P13, the voltages of the fifth scan signal SCAN5(n) and the sixth scan signal SCAN6(n) are maintained at the gate low voltage VGL. Figure 8C As shown, when the seventh switching transistor T7 is turned on in response to the low gate voltage VGL of the second scan signal SCAN2(n), the first pixel data voltage Vdata is applied to the second node n2. The data voltage Vdata is also applied to the first node n1 and the third node n3 via the first driving transistor DT1, which is in the on state. When the third time period P13 ends, the voltage of the second node n2 is the data voltage Vdata, and the voltage of each of the first node n1 and the third node n3 is the voltage corresponding to the sum of the data voltage Vdata and the threshold voltage Vth of the first driving transistor DT1. During the third time period P13, since the fourth node n4 and the seventh node n7 are in the floating state and the light-emitting elements EL1 and EL2 are in the off state, the light-emitting elements EL1 and EL2 do not emit light.

[0121] During the fourth time period P14, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of gate low voltage VGL that are sequentially shifted during the fourth time period P14. The voltage of the second scan signal SCAN2(n) is a gate high voltage VGH during the fourth time period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the fourth time period P14. Therefore, during the fourth time period P14, as... Figure 8D As shown, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7. During the fourth period P14, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T7, and the ninth switching transistor T9 are turned off.

[0122] During the fifth time period P15, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL, and the voltages of the second scan signal SCAN2(n), the third scan signal SCAN3(n), and SCAN3(n+1) are gate high voltages VGH. During the fifth time period P15, the voltages of the first EM signal EM1(n) and the second EM signal EM2(n) can be gate low voltages VGL, and the voltage of the third EM signal EM3(n) can be gate high voltages VGH. In this case, as... Figure 8E As shown, during the fifth time period P15, the third switching transistor T3 and the ninth switching transistor T9 are turned on, forming a current path between the pixel driving voltage EVDD and the first light-emitting element EL1, and the first light-emitting element EL1 can emit light. In this case, the first light-emitting element EL1 can emit light with a brightness corresponding to the grayscale value of the first pixel data by the current generated according to the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1. During the fifth time period P15, the other switching transistors T1, T2, T4 to T8, T10 and T11, except for the third switching transistor T3 and the ninth switching transistor T9, can be in the off state.

[0123] During the fifth time period P15, the voltages of the first EM signal EM1(n), the second EM signal EM2(n), and the third EM signal EM3(n) can be the gate low voltage VGL. In this case, during the fifth time period P15, the third switching transistor T3, the sixth switching transistor T6, and the ninth switching transistor T9 can be turned on. The first light-emitting element EL1 can emit light through the current generated by the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1, and the second light-emitting element EL2 can emit light through the current generated by the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. Therefore, in a pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0124] Figures 9-10E This diagram illustrates the phased operation of the pixel circuit during the second refresh frame period. Figure 9 It is shown that during the second refresh frame period, it is applied to Figure 5 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figures 10A-10E It is shown Figure 5 The diagram shows the operation of the pixel circuit during the second refresh frame period. Figures 10A-10E In the diagram, "X" indicates a transistor that is in the off state, and the arrow represents the current path.

[0125] Reference Figures 9-10E The second refresh frame period RFR2 may include a first period P21, a second period P22, a third period P23, a fourth period P24, and a fifth period P25. During the second refresh frame period RFR2, the voltages of the first scan signal SCAN1(n) and the fourth scan signal SCAN4(n) input to the first driver 10 may be a low gate voltage VGL, and the voltage of the second EM signal EM2(n) may be a high gate voltage VGH. In this case, during the second refresh frame period RFR2, the switching transistors T1, T2, and T3 of the first driver 10 remain in the off state.

[0126] During the first time period P21, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of the gate low voltage VGL that are sequentially shifted during the first time period P21. The voltage of the second scan signal SCAN2(n) is a gate high voltage VGH during the first time period P21. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the first time period P21. Therefore, during the first time period P21, as... Figure 10A As shown, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0127] During the first time period P21, such as Figure 10A As shown, the switching transistors T1 to T6, the seventh switching transistor T7, and the ninth switching transistor T9 of the first driver 10 and the second driver 20 are turned off in response to the gate turn-off voltage (VGH or VGL). During the first time period P21, driving transistors DT1 and DT2 can be turned on; however, since the third switching transistor T3 and the sixth switching transistor T6 are in the off state, no current can be supplied to the light-emitting elements EL1 and EL2. Furthermore, since the voltage difference between the anode reset voltage VAR and the cathode voltage EVSS is less than the threshold voltage of each of the light-emitting elements EL1 and EL2, the light-emitting elements EL1 and EL2 do not emit light during the first time period P21.

[0128] During the second time period P22, the voltages of the first scan signal SCAN1(n) and the fourth scan signal SCAN4(n) are the gate low voltage VGL, and the voltages of the other gate signals SCAN2(n), SCAN3(n), SCAN3(n+1), SCAN5(n), SCAN6(n), EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. Therefore, during the second time period P22, as Figure 10B As shown, the fourth switching transistor T4 and the fifth switching transistor T5 are turned on, and the initialization voltage Vini is applied to the fifth node n5 and the sixth node n6. The other switching transistors T1, T2, T3, and T6 through T11 are turned off. During the second time period P22, since the light-emitting elements EL1 and EL2 are turned off, they do not emit light.

[0129] During the third time period P23, the voltage of the second scan signal SCAN2(n) is generated by a pulse of the gate low voltage VGL, synchronized with the second pixel data voltage Vdata. During the third time period P23, the voltages of the third scan signals SCAN3(n), SCAN3(n+1), and the fifth scan signal SCAN5(n), as well as the EM signals EM1(n), EM2(n), and EM3(n), are the gate high voltage VGH, and the voltage of the sixth scan signal SCAN6(n) is the gate low voltage VGL. During the third time period P23, the voltages of the first scan signal SCAN1(n) and the fourth scan signal SCAN4(n) are maintained at the gate low voltage VGL. Figure 10C As shown, when the seventh switching transistor T7 is turned on in response to the low gate voltage VGL of the second scan signal SCAN2(n), the second pixel data voltage Vdata is applied to the second node n2. The data voltage Vdata is also applied to the fifth node n5 and the sixth node n6 via the second driving transistor DT2, which is in the on state. When the third time period P23 ends, the voltage of the second node n2 is the data voltage Vdata, and the voltage of each of the fifth node n5 and the sixth node n6 is the voltage corresponding to the sum of the data voltage Vdata and the threshold voltage Vth of the second driving transistor DT2. During the third time period P23, since the fourth node n4 and the seventh node n7 are in the floating state and the light-emitting elements EL1 and EL2 are in the off state, the light-emitting elements EL1 and EL2 do not emit light.

[0130] During the fourth time period P24, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of gate low voltage VGL that are sequentially shifted during the fourth time period P24. The voltage of the second scan signal SCAN2(n) is a gate high voltage VGH during the fourth time period P24. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the fourth time period P24. Therefore, during the fourth time period P24, as... Figure 10D As shown, the eighth switching transistor T8, the tenth switching transistor T10, and the eleventh switching transistor T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7. During the fourth period P24, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T7, and the ninth switching transistor T9 are turned off.

[0131] During the fifth time period P25, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL, and the second scan signal SCAN2(n), the third scan signal SCAN3(n), and SCAN3(n+1) are gate high voltages VGH. During the fifth time period P25, the voltages of the first EM signal EM1(n) and the third EM signal EM3(n) can be gate low voltages VGL, and the voltage of the second EM signal EM2(n) can be gate high voltages VGH. In this case, as... Figure 10E As shown, during the fifth time period P25, the sixth switching transistor T6 and the ninth switching transistor T9 are turned on, forming a current path between the pixel driving voltage EVDD and the second light-emitting element EL2, and the second light-emitting element EL2 can emit light. In this case, the second light-emitting element EL2 can emit light with a brightness corresponding to the grayscale value of the second pixel data by the current generated according to the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. During the fifth time period P25, the other switching transistors T1 to T5, T7, T8, T10, and T11, except for the sixth switching transistor T6 and the ninth switching transistor T9, can be in the off state.

[0132] During the fifth time period P25, the voltages of the first EM signal EM1(n), the second EM signal EM2(n), and the third EM signal EM3(n) can be the gate low voltage VGL. In this case, during the fifth time period P25, the third switching transistor T3, the sixth switching transistor T6, and the ninth switching transistor T9 can be turned on. The first light-emitting element EL1 can emit light through the current generated by the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1, and the second light-emitting element EL2 can emit light through the current generated by the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. Therefore, in a pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0133] To compensate for pixel brightness fluctuations when the pixel refresh rate decreases, such as Figures 11-16BAs shown, a preset dwell voltage Vpark can be applied to the data line. The dwell voltage Vpark can be applied to the data line connected to an undriven driver in the pixel circuit. The dwell voltage Vpark can be set to a voltage from 2V to 5V, but this disclosure is not limited thereto. Since the IR drop of the pixel driving voltage EVDD applied to the sub-pixel increases due to high brightness, the dwell voltage Vpark, which is most suitable for preventing flicker, can be set to a low voltage. Then, since the IR drop of the pixel driving voltage EVDD decreases due to low brightness, the dwell voltage Vpark can be set to a high voltage. For example, when the brightness of the display panel is 450 nits during the refresh frame period, the dwell voltage Vpark applied to the data line during the next skip frame period can be increased to 2.1V. When the brightness of the display panel is 200 nits during the refresh frame period, the dwell voltage Vpark applied to the data line during the next skip frame period can be increased to 2.5V. When the display brightness is 20 nits during the refresh frame period, the dwell voltage Vpark applied to the data line during the next skip frame period can be increased to 2.9V. Here, brightness can be average brightness.

[0134] Figure 11 and Figure 12 An embodiment is shown that includes a pixel circuit and a data switch unit through which the viewing angle can be changed and a dwell voltage can be applied. In these embodiments, with Figure 5 The configurations of the pixel circuits shown are substantially the same, indicated by the same reference numerals, and their redundant descriptions will not be repeated.

[0135] Reference Figure 11 Each of the sub-pixels of the display panel 100 includes a first driver 10 that drives a first light-emitting element EL1, a second driver 20 that drives a second light-emitting element EL2, a shared switch section 30 connected to the first driver 10 and the second driver 20, and a data switch section 40 connected to the shared switch section 30.

[0136] The first driver 10 includes a first driving transistor DT1, a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, and a first capacitor Cst1. The first light-emitting element EL1 can be driven by a current generated according to the gate-source voltage of the first driving transistor DT1 charged into the first capacitor Cst1, and can emit light in a first viewing angle mode. When the first light-emitting element EL1 emits light, the light can propagate with a wide viewing angle.

[0137] The second driver 20 includes a second driving transistor DT2, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, and a second capacitor Cst2. The second driving transistor DT2 includes a gate electrode connected to a fifth node n5, a first electrode connected to an eighth node n8, and a second electrode connected to a sixth node n6. The second light-emitting element EL2 can be driven by a current generated according to the gate-source voltage of the second driving transistor DT2 charged into the second capacitor Cst2, and can emit light in a second viewing angle mode. When the second light-emitting element EL2 emits light, the light can propagate with a narrow viewing angle.

[0138] The shared switching section 30 includes a seventh switching transistor T27 to a thirteenth switching transistor T33. The seventh switching transistor T27 to the thirteenth switching transistor T33 can be implemented using a p-channel LTPS TFT, but this disclosure is not limited thereto.

[0139] Gate driver 120 may include a gate driver that outputs a second-first scan signal SCAN2(n) controlling the seventh switching transistor T27 and a gate driver that outputs a second-second scan signal SCAN2'(n) controlling the eighth switching transistor T28. For example... Figure 13 As shown, the second-first scan signal SCAN2(n) can include a pulse of the gate low voltage VGL generated during the first refresh frame period RFR1. Figure 13 As shown, the second-second scan signal SCAN2'(n) may include a pulse of the gate low voltage VGL generated during the second refresh frame period RFR2.

[0140] Under the control of the timing controller 130, the data switching unit 40 can apply a pixel data voltage Vdata to the first data line DL1 and a dwell voltage Vpark to the second data line DL2 during the first refresh frame period RFR1. The data switching unit 40 can also apply a pixel data voltage Vdata to the second data line DL2 and a dwell voltage Vpark to the first data line DL1 during the second refresh frame period RFR2. Furthermore, the data switching unit 40 can apply a dwell voltage Vpark to both the first data line DL1 and the second data line DL2 during the skip frame period SFR.

[0141] A seventh switching transistor T27 is connected between the first data line DL1 and the second node n2. The seventh switching transistor T27 can be turned on in response to a low gate voltage VGL of the second-first scan signal SCAN2(n) and turned off in response to a high gate voltage VGH of the second-first scan signal SCAN2(n). When the seventh switching transistor T27 is on, the first data line DL1 is electrically connected to the second node n2. The seventh switching transistor T27 includes a gate electrode connected to the second-first gate line to which the second-first scan signal SCAN2(n) is applied, a first electrode connected to the first data line DL1, and a second electrode connected to the second node n2.

[0142] The eighth switching transistor T28 is connected between the second data line DL2 and the eighth node n8. The eighth switching transistor T28 can be turned on in response to a low gate voltage VGL of the second-second scan signal SCAN2'(n) and turned off in response to a high gate voltage VGH of the second-second scan signal SCAN2'(n). When the eighth switching transistor T28 is on, the second data line DL2 is electrically connected to the eighth node n8. The eighth switching transistor T28 includes a gate electrode connected to the second-second gate line to which the second-second scan signal SCAN2'(n) is applied, a first electrode connected to the second data line DL2, and a second electrode connected to the eighth node n8.

[0143] The ninth switching transistor T29 is connected between the second node n2 and the fifth voltage node to which the on-bias voltage VOBS is applied. The ninth switching transistor T29 can be turned on in response to a low gate voltage VGL of the third-first scan signal SCAN3(n) and turned off in response to a high gate voltage VGH of the third-first scan signal SCAN3(n). When the ninth switching transistor T29 and the eleventh switching transistor T31 are on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8. The ninth switching transistor T29 includes a gate electrode connected to the third-first gate line to which the third-first scan signal SCAN3(n) is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0144] The tenth switching transistor T30 is connected between the first voltage node and the second node n2 where the pixel driving voltage EVDD is applied. The tenth switching transistor T30 can be turned on in response to a low gate voltage VGL of the first EM signal EM1(n) and turned off in response to a high gate voltage VGH of the first EM signal EM1(n). When the tenth switching transistor T30 and the eleventh switching transistor T31 are on, the pixel driving voltage EVDD is applied to the second node n2 and the eighth node n8. The tenth switching transistor T30 includes a gate electrode connected to the seventh gate line where the first EM signal EM1(n) is applied, a first electrode connected to the first voltage node, and a second electrode connected to the second node n2.

[0145] Eleventh switching transistor T31 is connected between second node n2 and eighth node n8, and can be turned on in response to a low gate voltage VGL of the first scan signal SCAN1(n), and turned off in response to a high gate voltage VGH of the first scan signal SCAN1(n). When eleventh switching transistor T31 is turned on, second node n2 is electrically connected to eighth node n8. Eleventh switching transistor T31 includes a gate electrode connected to a first gate line to which the first scan signal SCAN1(n) is applied, a first electrode connected to second node n2, and a second electrode connected to eighth node n8.

[0146] The first switching transistor T1 and the eleventh switching transistor T31 can be implemented by different types of transistors and can operate in opposite directions to each other in response to the pulse of the first scan signal SCAN1(n). For example, as Figures 14A-14E As shown, when the first switching transistor T1 is off, the eleventh switching transistor T31 can be turned on. When the first switching transistor T1 is on, the eleventh switching transistor T31 can be turned off.

[0147] When the twelfth switching transistor T32 is turned on, the anode reset voltage VAR is applied to the fourth node n4. The twelfth switching transistor T32 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth voltage node to which the anode reset voltage VAR is applied.

[0148] When the thirteenth switching transistor T33 is turned on, the anode reset voltage VAR is applied to the seventh node n7. The thirteenth switching transistor T33 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the seventh node n7, and a second electrode connected to the fourth voltage node.

[0149] The data switching unit 40 includes a first switching crystal M1 to an eighth switching transistor M8. The first transistor M1 to the eighth transistor M8 can be implemented using a p-channel LTPS TFT that turns on in response to a low gate voltage VGL and turns off in response to a high gate voltage VGH, but this disclosure is not limited thereto. The data switching unit 40 can be integrated into a driver IC with a data driver 110, or it can be located in the non-display area NA of the display panel 100. Each of the transistors M1 to M8 in the data switching unit 40 can be turned on / off under the control of a timing controller 130. The level shifter 140 can output selection signals SEL1 to SEL4 that swing between a low gate voltage VGL and a high gate voltage VGH in response to a clock input from the timing controller 130.

[0150] A first transistor M1 and a second transistor M2 are connected in series between the first input node IN1 and the first data line DL1. A data voltage Vdata or a dwell voltage Vpark output from the first channel of the data driver 110 can be applied to the first input node IN1. In another embodiment, the dwell voltage Vpark can be output from the power supply 150. The first transistor M1 can be turned on in response to a low gate voltage VGL of the first select signal SEL1. When the first transistor M1 is turned on, the first input node IN1 is electrically connected to the second transistor M2. The first transistor M1 includes a gate electrode connected to the first select line to which the first select signal SEL1 is applied, a first electrode connected to the first input node IN1, and a second electrode connected to the first electrode of the second transistor M2.

[0151] The second transistor M2 can be turned on in response to a low gate voltage VGL of the third selection signal SEL3. When the second transistor M2 is turned on, the second electrode of the first transistor M1 is electrically connected to the first data line DL1. The second transistor M2 includes a gate electrode connected to the third selection line to which the third selection signal SEL3 is applied, a first electrode connected to the second electrode of the first transistor M1, and a second electrode connected to the first data line DL1.

[0152] The third transistor M3 and the fourth transistor M4 are connected in series between the second input node IN2 and the first data line DL1. A data voltage Vdata or a dwell voltage Vpark output from the second channel of the data driver 110 can be applied to the second input node IN2. The dwell voltage Vpark can be output from the power supply 150. The third transistor M3 can be turned on in response to a low gate voltage VGL of the second select signal SEL2. When the third transistor M3 is turned on, the second input node IN2 is electrically connected to the first electrode of the fourth transistor M4. The third transistor M3 includes a gate electrode connected to the second select line to which the second select signal SEL2 is applied, a first electrode connected to the second input node IN2, and a second electrode connected to the first electrode of the fourth transistor M4.

[0153] The fourth transistor M4 can be turned on in response to a low gate voltage VGL of the fourth select signal SEL4. When the fourth transistor M4 is turned on, the second electrode of the third transistor M3 is electrically connected to the first data line DL1. The fourth transistor M4 includes a gate electrode connected to the fourth select line to which the fourth select signal SEL4 is applied, a first electrode connected to the second electrode of the third transistor M3, and a second electrode connected to the first data line DL1.

[0154] A fifth transistor M5 and a sixth transistor M6 are connected in series between the first input node IN1 and the second data line DL2. The fifth transistor M5 can be turned on in response to a low gate voltage VGL of the second select signal SEL2. When the fifth transistor M5 is turned on, the first input node IN1 is electrically connected to the first electrode of the sixth transistor M6. The fifth transistor M5 includes a gate electrode connected to the second select line to which the second select signal SEL2 is applied, a first electrode connected to the first input node IN1, and a second electrode connected to the first electrode of the sixth transistor M6.

[0155] The sixth transistor M6 can be turned on in response to a low gate voltage VGL of the third select signal SEL3. When the sixth transistor M6 is turned on, the second electrode of the fifth transistor M5 is electrically connected to the second data line DL2. The sixth transistor M6 includes a gate electrode connected to the third select line to which the third select signal SEL3 is applied, a first electrode connected to the second electrode of the fifth transistor M5, and a second electrode connected to the second data line DL2.

[0156] A seventh transistor M7 and an eighth transistor M8 are connected in series between the second input node IN2 and the second data line DL2. The seventh transistor M7 can be turned on in response to a low gate voltage VGL of the first select signal SEL1. When the seventh transistor M7 is turned on, the second input node IN2 is electrically connected to the first electrode of the eighth transistor M8. The seventh transistor M7 includes a gate electrode connected to the first select line to which the first select signal SEL1 is applied, a first electrode connected to the second input node IN2, and a second electrode connected to the first electrode of the eighth transistor M8.

[0157] The eighth transistor M8 can be turned on in response to a low gate voltage VGL of the fourth select signal SEL4. When the eighth transistor M8 is turned on, the second electrode of the seventh transistor M7 is electrically connected to the second data line DL2. The eighth transistor M8 includes a gate electrode connected to the fourth select line to which the fourth select signal SEL4 is applied, a first electrode connected to the second electrode of the seventh transistor M7, and a second electrode connected to the second data line DL2.

[0158] Reference Figure 12 Each sub-pixel of the display panel 100 includes a first driver 10 that drives a first light-emitting element EL1, a second driver 20 that drives a second light-emitting element EL2, a shared switch section 30 connected to the first driver 10 and the second driver 20, and a data switch section 40 connected to the shared switch section 30. The first driver 10, the second driver 20, and the data switch section 40 are as described above. Figure 11 The pixel circuits shown are essentially the same.

[0159] The first driving transistor DT1 includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3, and generates a current for driving the first light-emitting element EL1. The second driving transistor DT2 includes a gate electrode connected to a fifth node n5, a first electrode connected to a second node n2, and a second electrode connected to a sixth node n6, and generates a current for driving the second light-emitting element EL2.

[0160] The shared switching section 30 includes a seventh switching transistor T37 to a twelfth switching transistor T42. The seventh switching transistor T37 to the twelfth switching transistor T42 can be implemented using a p-channel LTPS TFT, but this disclosure is not limited thereto.

[0161] A seventh switching transistor T37 is connected between the first data line DL1 and the second node n2. The seventh switching transistor T37 can be turned on in response to a low gate voltage VGL of the second-first scan signal SCAN2(n). When the seventh switching transistor T37 is turned on, the first data line DL1 is electrically connected to the second node n2. An eighth switching transistor T38 is connected between the second data line DL2 and the second node n2. The eighth switching transistor T38 can be turned on in response to a low gate voltage VGL of the second-second scan signal SCAN2'(n). When the eighth switching transistor T38 is turned on, the second data line DL2 is electrically connected to the second node n2.

[0162] The seventh switching transistor T37 includes a gate electrode connected to a second-first gate line to which a second-first scan signal SCAN2(n) is applied, a first electrode connected to a first data line DL1, and a second electrode connected to a second node n2. The eighth switching transistor T38 includes a gate electrode connected to a second-second gate line to which a second-second scan signal SCAN2'(n) is applied, a first electrode connected to a second data line DL2, and a second electrode connected to a second node n2.

[0163] A ninth switching transistor T39 is connected between the second node n2 and the fifth voltage node to which an on-bias voltage VOBS is applied. The ninth switching transistor T39 can be turned on in response to a low gate voltage VGL of the third-first scan signal SCAN3(n). When the ninth switching transistor T39 is turned on, the on-bias voltage VOBS is applied to the second node n2. The ninth switching transistor T39 includes a gate electrode connected to the third-first gate line to which the third-first scan signal SCAN3(n) is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0164] The tenth switching transistor T40 is connected between the first voltage node and the second node n2 to which the pixel driving voltage EVDD is applied. The tenth switching transistor T40 is turned on in response to the low gate voltage VGL of the first EM signal EM1(n) and applies the pixel driving voltage EVDD to the second node n2.

[0165] When the eleventh switching transistor T41 is turned on, the anode reset voltage VAR is applied to the fourth node n4. The eleventh switching transistor T41 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth voltage node to which the anode reset voltage VAR is applied.

[0166] When the twelfth switching transistor T42 is turned on, the anode reset voltage VAR is applied to the seventh node n7. The twelfth switching transistor T42 includes a gate electrode connected to the third-second gate line to which the third-second scan signal SCAN3(n+1) is applied, a first electrode connected to the seventh node n7, and a second electrode connected to the fourth voltage node.

[0167] In the following text, reference will be made to Figures 13-1 6 Descriptions Figure 11 The operation of the pixel circuit shown. Figure 11 The pixel circuit shown is Figure 12 The pixel circuit shown differs in that it provides a switching transistor T31 that selectively connects the second node n2 and the eighth node n8, while the rest of the operation is essentially the same. Therefore, the details will not be repeated. Figure 12 A description of the operation of the pixel circuit shown.

[0168] Figure 13 It is shown that the force applied during the first refresh frame period, the second refresh frame period, and the skip frame period is applied to Figure 11 and Figure 12 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figures 14A-14E It is shown in stages. Figure 11 The diagram shows the operation of the pixel circuit during the first refresh frame period. Figures 15A-15E It is shown in stages. Figure 11 The diagram shows the operation of the pixel circuit during the second refresh frame period. Figure 16A and Figure 16B It is shown in stages. Figure 11 The diagram shows the operation of the pixel circuitry during the skipped frame period. Figures 14A-16B In the diagram, "X" indicates a transistor that is in the off state, and the arrow represents the current path.

[0169] Reference Figures 13-14E The first refresh frame period RFR1 may include a first period P11, a second period P12, a third period P13, a fourth period P14, and a fifth period P15. During the first refresh frame period RFR1, the voltages of the fifth scan signal SCAN5(n) and the sixth scan signal SCAN6(n) input to the second driver 20 may be the gate low voltage VGL, and the voltage of the second scan signal SCAN2'(n) may be the gate high voltage VGH. In this case, during the first refresh frame period RFR1, the switching transistors T4, T5, and T6 of the second driver 20, as well as the eighth transistor T28, remain in the off state.

[0170] During the first time period P11 of the first refresh frame period RFR1, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of the gate low voltage VGL that are sequentially shifted during the first time period P11. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are gate high voltages VGH during the first time period P11. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the first time period P11. Therefore, during the first time period P11, as Figure 14A As shown, the ninth switching transistor T29, the eleventh switching transistor T31, the twelfth switching transistor T32 and the thirteenth switching transistor T33 are turned on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0171] During the first time period P11, such as Figure 14A As shown, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T27, the eighth switching transistor T28, and the tenth switching transistor T30 are turned off in response to the gate turn-off voltage (VGH or VGL). During the first time period P11, the light-emitting elements EL1 and EL2 do not emit light.

[0172] During the second period P12 of the first refresh frame period RFR1, the voltages of the fifth scan signal SCAN5(n) and the sixth scan signal SCAN6(n) are gate low voltage VGL, and the voltages of the other gate signals SCAN1(n), SCAN2(n), SCAN2'(n), SCAN3(n), SCAN3(n+1), SCAN4(n), EM1(n), EM2(n), and EM3(n) are gate high voltage VGH. Therefore, during the second period P12, as Figure 14B As shown, the first switching transistor T1 and the second switching transistor T2 are turned on, and the initialization voltage Vini is applied to the first node n1 and the third node n3. The other switching transistors T3 to T33 are turned off. During the second time period P12, the light-emitting elements EL1 and EL2 do not emit light.

[0173] During the third period P13 of the first refresh frame period RFR1, the data switching unit 40 supplies the first pixel data voltage Vdata to the first data line DL1 and the resident voltage Vpark to the second data line DL2. The selection signals SEL1 to SEL4 of the transistors M1 to M8 controlling the data switching unit 40 can be updated during the third period P13 and then maintained until the second period P12 of the next refresh frame period RFR1. In another embodiment, during periods other than the third periods P13 and P23 of refresh frame periods RFR1 and RFR2 and the first period P31 and second period P32 of skip frame period SFR, the voltages of the selection signals SEL1 to SEL4 can be maintained at the low gate voltage VGL of the conducting transistors M1 to M8 or at the high gate voltage VGH of the turning transistors M1 to M8.

[0174] During the third time period P13, the voltages of the first selection signal SEL1, the third selection signal SEL3, and the fourth selection signal SEL4 are the gate low voltage VGL, and the voltage of the second selection signal SEL2 is the gate high voltage VGH. Therefore, as Figure 14C As shown, the first transistor M1, the second transistor M2, the seventh transistor M7 and the eighth transistor M8 are turned on, the first pixel data voltage Vdata is applied to the first data line DL1, and the dwell voltage Vpark is applied to the second data line DL2.

[0175] During the third time period P13, the voltage of the second-first scan signal SCAN2(n) is generated by pulses of the gate low voltage VGL synchronized with the pixel data voltage Vdata. During the third time period P13, the voltages of the first scan signal SCAN1(n), the second-second scan signal SCAN2'(n), and the third scan signals SCAN3(n) and SCAN3(n+1), as well as the EM signals EM1(n), EM2(n), and EM3(n), are the gate high voltage VGH. During the third time period P13, the voltages of the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are maintained at the gate low voltage VGL. Figure 14CAs shown, when the seventh switching transistor T27 is turned on in response to the low gate voltage VGL of the second-first scan signal SCAN2(n), the first pixel data voltage Vdata is applied to the second node n2. The data voltage Vdata is also applied to the first node n1 and the third node n3 via the first driving transistor DT1, which is in the on state. When the third time period P13 ends, the voltage of the second node n2 is the data voltage Vdata, and the voltage of each of the first node n1 and the third node n3 is the voltage corresponding to the sum of the data voltage Vdta and the threshold voltage Vth of the first driving transistor DT1. During the third time period P13, the light-emitting elements EL1 and EL2 do not emit light.

[0176] During the fourth period P14 of the first refresh frame period RFR1, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of gate low voltage VGL that are sequentially shifted during the fourth period P14. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are gate high voltages VGH during the fourth period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the fourth period P14. Therefore, during the fourth period P14, as Figure 14D As shown, the ninth switching transistor T29, the eleventh switching transistor T31, the twelfth switching transistor T32 and the thirteenth switching transistor T33 are turned on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0177] During the fourth period P14, such as Figure 14D As shown, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T27, the eighth switching transistor T28, and the tenth switching transistor T30 are turned off in response to the gate turn-off voltage (VGH or VGL). During the fourth period P14, the light-emitting elements EL1 and EL2 do not emit light.

[0178] During the fifth period P15 of the first refresh frame period RFR1, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL, and the voltages of the second scan signals SCAN2(n), SCAN2'(n), and the third scan signals SCAN3(n) and SCAN3(n+1) are gate high voltages VGH. During the fifth period P15, the voltages of the first EM signal EM1(n) and the second EM signal EM2(n) can be gate low voltages VGL, and the voltage of the third EM signal EM3(n) can be gate high voltages VGH. In this case, during the fifth period P15, the third switching transistor T3 and the tenth switching transistor T30 are turned on and can emit light. In this case, the first light-emitting element EL1 can emit light with a brightness corresponding to the grayscale value of the first pixel data by the current generated according to the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1. During the fifth time period P15, the other switching transistors T1, T2, T4 to T6, T27, T28, T29 and T31 to T33, except for the third switching transistor T3 and the tenth switching transistor T30, can be in the off state.

[0179] During the fifth time period P15, the voltages of the first EM signal EM1(n), the second EM signal EM2(n), and the third EM signal EM3(n) can be the gate low voltage VGL. In this case, during the fifth time period P15, as... Figure 14E As shown, the third switching transistor T3, the sixth switching transistor T6, and the tenth switching transistor T30 can be turned on. The first light-emitting element EL1 can emit light by the current generated according to the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1, and the second light-emitting element EL2 can emit light by the current generated according to the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. Therefore, in a pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0180] Reference Figure 13 and Figures 15A-15EThe second refresh frame period RFR2 may include a first period P21, a second period P22, a third period P23, a fourth period P24, and a fifth period P25. During the second refresh frame period RFR2, the voltages input to the first scan signal SCAN1(n) and the fourth scan signal SCAN4(n) of the first driver 10 may be a gate low voltage VGL, and the voltage of the second-first scan signal SCAN2(n) may be a gate high voltage VGH. In this case, during the second refresh frame period RFR2, the switching transistors T1, T2, and T3 and the seventh switching transistor T27 of the first driver 20 remain in the off state.

[0181] During the first period P21 of the second refresh frame period RFR2, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of the gate low voltage VGL that are sequentially shifted during the first period P21. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are gate high voltages VGH during the first period P21. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the first period P21. Therefore, during the first period P21, as Figure 15A As shown, the ninth switching transistor T29, the eleventh switching transistor T31, the twelfth switching transistor T32 and the thirteenth switching transistor T33 are turned on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0182] During the first time period P21, such as Figure 15A As shown, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T27, the eighth switching transistor T28, and the tenth switching transistor T30 are turned off in response to the gate turn-off voltage (VGH or VGL). During the first time period P21, the light-emitting elements EL1 and EL2 do not emit light.

[0183] During the second time period P22 of the second refresh frame period RFR2, the voltages of the first scan signal SCAN1(n) and the fourth scan signal SCAN4(n) are gate low voltage VGL, and the voltages of the other gate signals SCAN2(n), SCAN2'(n), SCAN3(n), SCAN3(n+1), SCAN4(n), SCAN5(n), SCAN6(n), EM1(n), EM2(n), and EM3(n) are gate high voltage VGH. Therefore, during the second time period P22, as Figure 15B As shown, the fourth switching transistor T4 and the fifth switching transistor T5 are turned on, and the initialization voltage Vini is applied to the fifth node n5 and the sixth node n6. The other switching transistors T1, T2, T3, and T6 through T33 are turned off. During the second time period P22, the light-emitting elements EL1 and EL2 do not emit light.

[0184] During the third period P23 of the second refresh frame period RFR2, the data switching unit 40 supplies the second pixel data voltage Vdata to the second data line DL2 and supplies the dwell voltage Vpark to the first data line DL1.

[0185] During the third time period P23, the voltages of the second selection signal SEL2, the third selection signal SEL3, and the fourth selection signal SEL4 are the gate low voltage VGL, and the voltage of the first selection signal SEL1 is the gate high voltage VGH. Therefore, as Figure 15C As shown, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned on, the second pixel data voltage Vdata is applied to the second data line DL2, and the dwell voltage Vpark is applied to the first data line DL1.

[0186] During the third time period P23, the voltage of the second scan signal SCAN2'(n) is generated by a pulse of the gate low voltage VGL synchronized with the second pixel data voltage Vdata. During the third time period P23, the voltages of the fifth scan signal SCAN5(n), the second scan signal SCAN2'(n), the third scan signals SCAN3(n) and SCAN3(n+1), and the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. During the third time period P23, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), and the sixth scan signal SCAN6(n) are maintained at the gate low voltage VGL. Figure 15CAs shown, when the eighth switching transistor T28 is turned on in response to the low gate voltage VGL of the second-second scan signal SCAN2'(n), the second pixel data voltage Vdata is applied to the eighth node n8. The data voltage Vdata is also applied to the fifth node n5 and the sixth node n6 via the second driving transistor DT2, which is in the on state. When the third time period P23 ends, the voltage of the eighth node n8 is the data voltage Vdata, and the voltage of each of the fifth node n5 and the sixth node n6 is the voltage corresponding to the sum of the data voltage Vdata and the threshold voltage Vth of the second driving transistor DT2. During the third time period P23, the light-emitting elements EL1 and EL2 do not emit light.

[0187] During the fourth period P24 of the second refresh frame period RFR2, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of gate low voltage VGL that are sequentially shifted during the fourth period P24. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are gate high voltages VGH during the fourth period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are gate high voltages VGH during the fourth period P24. Therefore, during the fourth period P24, as Figure 15D As shown, the ninth switching transistor T29, the eleventh switching transistor T31, the twelfth switching transistor T32 and the thirteenth switching transistor T33 are turned on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0188] During the fourth period P24, such as Figure 15D As shown, the switching transistors T1 to T6 of the first driver 10 and the second driver 20, the seventh switching transistor T27, the eighth switching transistor T28, and the tenth switching transistor T30 are turned off in response to the gate turn-off voltage (VGH or VGL). During the fourth period P24, the light-emitting elements EL1 and EL2 do not emit light.

[0189] During the fifth period P25 of the second refresh frame period RFR2, the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL, and the voltages of the second scan signals SCAN2(n), SCAN2'(n), and the third scan signals SCAN3(n) and SCAN3(n+1) are gate high voltages VGH. During the fifth period P25, the voltages of the first EM signal EM1(n) and the third EM signal EM3(n) can be gate low voltages VGL, and the voltage of the second EM signal EM2(n) can be gate high voltages VGH. In this case, during the fifth period P25, the sixth switching transistor T6 and the tenth switching transistor T30 are turned on and can emit light. In this case, the second light-emitting element EL2 can emit light with a brightness corresponding to the grayscale value of the second pixel data by the current generated according to the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. During the fifth time period P25, the other switching transistors T1 to T6, T27, T28, T29 and T31 to T33, except for the sixth switching transistor T6 and the tenth switching transistor T30, can be in the off state.

[0190] During the fifth time period P25, the voltages of the first EM signal EM1(n), the second EM signal EM2(n), and the third EM signal EM3(n) can be the gate low voltage VGL. In this case, during the fifth time period P25, as... Figure 15E As shown, the third switching transistor T3, the sixth switching transistor T6, and the tenth switching transistor T30 can be turned on. The first light-emitting element EL1 can emit light through the current generated by the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1, and the second light-emitting element EL2 can emit light through the current generated by the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. Therefore, in a pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0191] Reference Figure 13 , Figure 16A and Figure 16B The skip frame period (SFR) can include a first period P31, a second period P32, and a third period P33. During the period between the first period P31 and the second period P32, all switching transistors T1 to T33 can be turned off, and master nodes n1 and n7 can be floated.

[0192] During the first time period P31 and the second time period P32 of the skip frame period (SFR), the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) can be the gate low voltage VGL, and the voltages of the second scan signals SCAN2(n) and SCAN2'(n), as well as the EM signals EM1, EM2, and EM3, can be the gate high voltage VGH. The voltages of the third-first scan signal SCAN3(n) and the third-second scan signal SCAN3(n+1) are generated by pulses of the gate low voltage VGL that are sequentially shifted during the first time period P31. Therefore, during the first time period P31 and the second time period P32, the switching transistors T1 to T6, the seventh switching transistor T27, the eighth switching transistor T28, and the tenth switching transistor T30 of the first driver 10 and the second driver 20 are turned off. During the first time period P31 and the second time period P32, as Figure 16A As shown, the ninth switching transistor T29, the eleventh switching transistor T31, the twelfth switching transistor T32 and the thirteenth switching transistor T33 are turned on, the on-bias voltage VOBS is applied to the second node n2 and the eighth node n8, and the anode reset voltage VAR is applied to the fourth node n4 and the seventh node n7.

[0193] During the third period P33 of the skip frame period (SFR), the voltages of the first scan signal SCAN1(n), the fourth scan signal SCAN4(n), the fifth scan signal SCAN5(n), and the sixth scan signal SCAN6(n) are gate low voltages VGL, and the voltages of the second scan signals SCAN2(n), SCAN2'(n), and the third scan signals SCAN3(n) and SCAN3(n+1) are gate high voltages VGH. During the third period P33, the voltages of the first EM signal EM1(n) and the second EM signal EM2(n) can be gate low voltages VGL, and the voltage of the third EM signal EM3(n) can be gate high voltages VGH. In this case, during the third period P33, the third switching transistor T3 and the tenth switching transistor T30 are turned on and can emit light. In this case, the first light-emitting element EL1 can emit light with a brightness corresponding to the grayscale value of the first pixel data by the current generated according to the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1. Simultaneously, during the third time period P33, the voltages of the first EM signal EM1(n) and the third EM signal EM3(n) can be the gate low voltage VGL, and the voltage of the second EM signal EM2(n) can be the gate high voltage VGH. In this case, during the third time period P33, the sixth switching transistor T6 and the tenth switching transistor T30 are turned on and can emit light. In this case, the second light-emitting element EL2 can emit light with a brightness corresponding to the grayscale value of the second pixel data by the current generated according to the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2.

[0194] During the third time period P33, the voltages of the first EM signal EM1(n), the second EM signal EM2(n), and the third EM signal EM3(n) can be the gate low voltage VGL. In this case, during the third time period P33, as... Figure 16B As shown, the third switching transistor T3, the sixth switching transistor T6, and the tenth switching transistor T30 can be turned on. The first light-emitting element EL1 can emit light through the current generated by the gate-source voltage Vgs of the first driving transistor DT1 charged into the first capacitor Cst1, and the second light-emitting element EL2 can emit light through the current generated by the gate-source voltage Vgs of the second driving transistor DT2 charged into the second capacitor Cst2. Therefore, in a pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0195] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, camera devices, camcorders, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0196] The objectives to be achieved by this disclosure, the means to achieve those objectives, and the effects of this disclosure described above do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the disclosure of this disclosure.

[0197] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: Multiple data cables; Multiple gate lines; Multiple power lines; Multiple mode selection lines; as well as Multiple sub-pixels, Each of the sub-pixels includes: First light-emitting element; Second light-emitting element; A first driver is configured to receive a pixel driving voltage, a first pixel data voltage and a plurality of gate signals as inputs and to supply current to the first light-emitting element; A second driver is configured to receive the pixel driving voltage, the second pixel data voltage, and a plurality of gate signals as inputs and to supply current to the second light-emitting element; and A shared switching unit is configured to supply the first pixel data voltage to the first driver and the second pixel data voltage to the second driver.

2. The display panel according to claim 1, further comprising: A wide-viewing-angle lens that overlaps with the light-emitting area of ​​the first light-emitting element; as well as A narrow-viewing-angle lens that overlaps with the light-emitting area of ​​the second light-emitting element.

3. The display panel according to claim 1, wherein, The first driver includes: The first driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and is configured to drive the first light-emitting element during a first refresh frame period. A first capacitor is connected between a first voltage node to which the pixel driving voltage is applied and the first node; A first switching transistor is connected between the first node and the third node, and is turned on in response to a high gate voltage of the first scan signal and turned off in response to a low gate voltage of the first scan signal. A second switching transistor is connected between the first node and a third voltage node to which an initialization voltage is applied, and is turned on in response to a high gate voltage of a fourth scan signal, and turned off in response to a low gate voltage of the fourth scan signal; and A third switching transistor is connected between the third and fourth nodes, and turns on in response to a low gate voltage of the second light-emitting signal, and turns off in response to a high gate voltage of the second light-emitting signal. The first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second voltage node to which a cathode voltage is applied.

4. The display panel according to claim 3, wherein, The second driver includes: The second driving transistor includes a gate electrode connected to the fifth node, a first electrode connected to the second node or the eighth node, and a second electrode connected to the sixth node, and is configured to drive the second light-emitting element during the second refresh frame period. A second capacitor is connected between the first voltage node and the fifth node; A fourth switching transistor is connected between the fifth node and the sixth node, and is turned on in response to a high gate voltage of the fifth scan signal and turned off in response to a low gate voltage of the fifth scan signal. A fifth switching transistor, connected between the fifth node and the third voltage node, is turned on in response to a high gate voltage of the sixth scan signal and turned off in response to a low gate voltage of the sixth scan signal; and A sixth switching transistor, connected between the sixth and seventh nodes, is turned on in response to a low gate voltage of the third light-emitting signal and turned off in response to a high gate voltage of the third light-emitting signal. The second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second voltage node.

5. The display panel according to claim 4, wherein, The shared switch unit includes: A seventh switching transistor is connected between a data line and the second node, and is turned on in response to a low gate voltage of the second scan signal and turned off in response to a high gate voltage of the second scan signal; An eighth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and is turned on in response to a low gate voltage of the third-first scan signal and turned off in response to a high gate voltage of the third-first scan signal. A ninth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. A tenth switching transistor, connected between the fourth node and the fourth voltage node to which an anode reset voltage is applied, turns on in response to a low gate voltage of the third-second scan signal and turns off in response to a high gate voltage of the third-second scan signal; and The eleventh switching transistor is connected between the seventh node and the fourth voltage node, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage. The first pixel data voltage is applied to the data line during the first refresh frame period, and the second pixel data voltage is applied to the data line during the second refresh frame period. The shared switch is configured to receive the first pixel data voltage and the second pixel data voltage as input via the data line.

6. The display panel according to claim 4, wherein, The shared switch unit includes: A seventh switching transistor is connected between the first data line and the second node, and is turned on in response to a low gate voltage of the second-first scan signal, and turned off in response to a high gate voltage of the second-first scan signal; An eighth switching transistor is connected between the second data line and the eighth node, and is turned on in response to a low gate voltage of the second-second scan signal, and turned off in response to a high gate voltage of the second-second scan signal; A ninth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and is turned on in response to a low gate voltage of the third-first scan signal and turned off in response to a high gate voltage of the third-first scan signal. A tenth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. The eleventh switching transistor is connected between the second node and the eighth node, and is turned on in response to a low gate voltage of the first scan signal and turned off in response to a high gate voltage of the first scan signal. A twelfth switching transistor is connected between the fourth node and the fourth voltage node to which an anode reset voltage is applied, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal; and A thirteenth switching transistor is connected between the seventh node and the fourth voltage node, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage. When the first switching transistor is off, the eleventh switching transistor is on, and when the first switching transistor is on, the eleventh switching transistor is off. The shared switch is configured to receive the first pixel data voltage via the first data line and the second pixel data voltage via the second data line.

7. The display panel according to claim 4, wherein, The shared switch unit includes: A seventh switching transistor is connected between the first data line and the second node, and is turned on in response to a low gate voltage of the second-first scan signal, and turned off in response to a high gate voltage of the second-first scan signal; An eighth switching transistor is connected between the second data line and the eighth node, and is turned on in response to a low gate voltage of the second-second scan signal, and turned off in response to a high gate voltage of the second-second scan signal; A ninth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and is turned on in response to a low gate voltage of the third-first scan signal and turned off in response to a high gate voltage of the third-first scan signal. A tenth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. An eleventh switching transistor is connected between the fourth node and the fourth voltage node to which an anode reset voltage is applied, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal; and A twelfth switching transistor, connected between the seventh node and the fourth voltage node, is turned on in response to a low gate voltage of the third-second scan signal and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage.

8. The display panel according to claim 6 or 7, further comprising: A data switching unit is configured to apply a first pixel data voltage to the first data line and apply a dwell voltage to the second data line during the first refresh frame period, and to apply a second pixel data voltage to the second data line and apply the dwell voltage to the first data line during the second refresh frame period.

9. The display panel according to claim 8, wherein, The data switching unit includes: A first transistor and a second transistor are connected in series between the first input node and the first data line; A third transistor and a fourth transistor are connected in series between the second input node and the first data line; The fifth and sixth transistors are connected in series between the first input node and the second data line; and The seventh and eighth transistors are connected in series between the second input node and the second data line; and The first transistor and the seventh transistor are turned on in response to a gate-on voltage of a first selection signal from a first selection line among the plurality of mode selection lines, and turned off in response to a gate-off voltage of the first selection signal. The third transistor and the fifth transistor are turned on in response to a gate on-voltage of a second selection signal from a second selection line among the plurality of mode selection lines, and turned off in response to a gate off-voltage of the second selection signal. The second transistor and the sixth transistor are turned on in response to a gate on-voltage of a third selection signal from a third selection line among the plurality of mode selection lines, and turned off in response to a gate off-voltage of the third selection signal. The fourth transistor and the eighth transistor are turned on in response to a gate-on voltage of a fourth selection signal from the fourth selection line of the plurality of mode selection lines, and turned off in response to a gate-off voltage of the fourth selection signal.

10. The display panel according to any one of claims 5, 6, and 7, wherein, One or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period during which pixel data is not updated.

11. A display device, comprising: The display panel includes multiple data lines, multiple gate lines, multiple power lines, and multiple sub-pixels; A data driver configured to supply data voltage to the data lines; as well as A gate driver configured to supply a gate signal to the gate line. Each of the sub-pixels includes: First light-emitting element; Second light-emitting element; A first driver is configured to receive a pixel driving voltage, a first pixel data voltage and a plurality of gate signals as inputs and to supply current to the first light-emitting element; A second driver is configured to receive the pixel driving voltage, the second pixel data voltage, and a plurality of gate signals as inputs and to supply current to the second light-emitting element; and A shared switching unit is configured to supply the first pixel data voltage to the first driver and the second pixel data voltage to the second driver.

12. The display device according to claim 11, further comprising: A wide-viewing-angle lens that overlaps with the light-emitting area of ​​the first light-emitting element; as well as A narrow-viewing-angle lens that overlaps with the light-emitting area of ​​the second light-emitting element.

13. The display device according to claim 11, wherein, The first driver includes: The first driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, and is configured to drive the first light-emitting element during a first refresh frame period. A first capacitor is connected between a first voltage node to which the pixel driving voltage is applied and the first node; A first switching transistor is connected between the first node and the third node, and is turned on in response to a high gate voltage of the first scan signal and turned off in response to a low gate voltage of the first scan signal. A second switching transistor is connected between the first node and a third voltage node to which an initialization voltage is applied, and is turned on in response to a high gate voltage of a fourth scan signal, and turned off in response to a low gate voltage of the fourth scan signal; and A third switching transistor is connected between the third and fourth nodes, and turns on in response to a low gate voltage of the second light-emitting signal, and turns off in response to a high gate voltage of the second light-emitting signal. The first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second voltage node to which a cathode voltage is applied.

14. The display device according to claim 13, wherein, The second driver includes: The second driving transistor includes a gate electrode connected to the fifth node, a first electrode connected to the second node or the eighth node, and a second electrode connected to the sixth node, and is configured to drive the second light-emitting element during the second refresh frame period. A second capacitor is connected between the first voltage node and the fifth node; A fourth switching transistor is connected between the fifth node and the sixth node, and is turned on in response to a high gate voltage of the fifth scan signal and turned off in response to a low gate voltage of the fifth scan signal. A fifth switching transistor, connected between the fifth node and the third voltage node, is turned on in response to a high gate voltage of the sixth scan signal and turned off in response to a low gate voltage of the sixth scan signal; and A sixth switching transistor, connected between the sixth and seventh nodes, is turned on in response to a low gate voltage of the third light-emitting signal and turned off in response to a high gate voltage of the third light-emitting signal. The second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second voltage node.

15. The display device according to claim 14, wherein, The shared switch unit includes: A seventh switching transistor is connected between a data line and the second node, and is turned on in response to a low gate voltage of the second scan signal and turned off in response to a high gate voltage of the second scan signal; An eighth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and is turned on in response to a low gate voltage of the third-first scan signal and turned off in response to a high gate voltage of the third-first scan signal. A ninth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. A tenth switching transistor, connected between the fourth node and the fourth voltage node to which an anode reset voltage is applied, turns on in response to a low gate voltage of the third-second scan signal and turns off in response to a high gate voltage of the third-second scan signal; and The eleventh switching transistor is connected between the seventh node and the fourth voltage node, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage, and The first pixel data voltage is applied to the data line during the first refresh frame period, and the second pixel data voltage is applied to the data line during the second refresh frame period.

16. The display device according to claim 14, wherein, The shared switch unit includes: A seventh switching transistor is connected between the first data line and the second node, and is turned on in response to a low gate voltage of the second-first scan signal, and turned off in response to a high gate voltage of the second-first scan signal. An eighth switching transistor is connected between the second data line and the eighth node, and is turned on in response to a low gate voltage of the second-second scan signal, and turned off in response to a high gate voltage of the second-second scan signal. A ninth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and turns on in response to a low gate voltage of the third-first scan signal, and turns off in response to a high gate voltage of the third-first scan signal. A tenth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. An eleventh switching transistor is connected between the second node and the eighth node, and is turned on in response to a low gate voltage of the first scan signal and turned off in response to a high gate voltage of the first scan signal. The twelfth switching transistor is connected between the fourth node and the fourth voltage node to which the anode reset voltage is applied, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. A thirteenth switching transistor is connected between the seventh node and the fourth voltage node, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage, and When the first switching transistor is turned off, the eleventh switching transistor is turned on, and when the first switching transistor is turned on, the eleventh switching transistor is turned off.

17. The display device according to claim 14, wherein, The shared switch unit includes: A seventh switching transistor is connected between the first data line and the second node, and is turned on in response to a low gate voltage of the second-first scan signal, and turned off in response to a high gate voltage of the second-first scan signal. An eighth switching transistor is connected between the second data line and the eighth node, and is turned on in response to a low gate voltage of the second-second scan signal, and turned off in response to a high gate voltage of the second-second scan signal. A ninth switching transistor is connected between the second node and a fifth voltage node to which a conduction bias voltage is applied, and turns on in response to a low gate voltage of the third-first scan signal, and turns off in response to a high gate voltage of the third-first scan signal. A tenth switching transistor is connected between the first voltage node and the second node, and is turned on in response to a low gate voltage of the first light-emitting signal, and turned off in response to a high gate voltage of the first light-emitting signal. The eleventh switching transistor is connected between the fourth node and the fourth voltage node to which the anode reset voltage is applied, and is turned on in response to a low gate voltage of the third-second scan signal, and turned off in response to a high gate voltage of the third-second scan signal. A twelfth switching transistor, connected between the seventh node and the fourth voltage node, is turned on in response to a low gate voltage of the third-second scan signal and turned off in response to a high gate voltage of the third-second scan signal. The pulses of the third-first scan signal and the third-second scan signal are generated sequentially with a low gate voltage.

18. The display device according to any one of claims 15, 16, and 17, wherein, One or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period during which pixel data is not updated.

19. The display device according to claim 16 or 17, further comprising: A data switching unit is configured to apply a first pixel data voltage to the first data line and apply a dwell voltage to the second data line during the first refresh frame period, and to apply a second pixel data voltage to the second data line and apply the dwell voltage to the first data line during the second refresh frame period.

20. The display device according to claim 19, wherein, The data switching unit includes: The first transistor and the second transistor are connected in series between the first input node and the first data line. The third and fourth transistors are connected in series between the second input node and the first data line. The fifth and sixth transistors are connected in series between the first input node and the second data line, and The seventh and eighth transistors are connected in series between the second input node and the second data line. The first transistor and the seventh transistor are turned on in response to a gate-on voltage of a first selection signal from a first selection line among a plurality of mode selection lines, and turned off in response to a gate-off voltage of the first selection signal. The third transistor and the fifth transistor are turned on in response to a gate on-voltage of a second selection signal from a second selection line among the plurality of mode selection lines, and turned off in response to a gate off-voltage of the second selection signal. The second transistor and the sixth transistor are turned on in response to a gate on-voltage of a third selection signal from a third selection line among the plurality of mode selection lines, and turned off in response to a gate off-voltage of the third selection signal. The fourth transistor and the eighth transistor are turned on in response to a gate-on voltage of a fourth selection signal from the fourth selection line of the plurality of mode selection lines, and turned off in response to a gate-off voltage of the fourth selection signal.

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