Command processing circuit, command processing method, and PIM device

Abstract

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

Description

Technical Field

[0001] This disclosure relates to the field of Processing-In-Memory (PIM), and particularly to a command processing circuit, command processing method, and PIM device. Background Technology

[0002] In traditional computer architectures, data is stored in memory, and the processor is responsible for reading data from memory, processing it, and then writing the results back to memory. This approach suffers from data transfer bottlenecks, especially when dealing with large-scale data and complex computational tasks, where frequent data transfers consume significant time and energy. To address this issue, the concept of Processing In Memory (PIM) was proposed. PIM devices can perform both data storage and direct arithmetic operations, thus improving data processing speed. Summary of the Invention

[0003] This disclosure provides a command processing circuit, a command processing method, and a PIM device, which at least help avoid mode switching and improve system performance.

[0004] In a first aspect, embodiments of this disclosure provide a command processing circuit applied to a PIM device, comprising:

[0005] The PIM command identification module is electrically connected to the command address bus of the PIM device and is configured to receive command signals through the command address bus and determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, the command signal is sent to the regular command processing module; if the currently received command signal is determined to be a PIM-related command, the command signal is sent to the PIM command processing module.

[0006] The PIM command processing module is electrically connected to the PIM command recognition module and is configured to receive the PIM-related commands, decode the PIM-related commands, and perform corresponding operations based on the decoding results.

[0007] The conventional command processing module, which is electrically connected to the PIM command recognition module, is configured to receive the DRAM conventional commands and decode them.

[0008] In some embodiments, the PIM-related commands include: a PIM mode activation command, a PIM operation command, a PIM execution command, and a no-operation command; the PIM mode activation command is used to indicate entering PIM mode; the PIM operation command includes at least an addition command and a multiplication command, and the PIM operation command is stored in the PIM command processing module; the PIM execution command is used to retrieve the PIM operation command from the PIM command processing module and send it to the execution module of the PIM device.

[0009] In some embodiments, the DRAM conventional commands include at least: read commands, write commands, and refresh commands.

[0010] In some embodiments, the PIM command recognition module is further configured to determine the command signal received within a preset time after receiving the PIM mode activation command as the PIM-related command, and send it to the PIM command processing module.

[0011] In some embodiments, the PIM command recognition module includes:

[0012] The first identification unit is configured to receive the command signal, determine the command signal according to the PIM command truth table, and if it is determined that the currently received command signal is the PIM mode activation command, then output a first flag signal of valid state, otherwise output a first flag signal of invalid state; if it is determined that the currently received command signal is the PIM execution command, then output a second flag signal of valid state, otherwise output a second flag signal of invalid state.

[0013] The timing unit is configured to receive the first flag signal, clear the first flag signal in response to the valid state, and start timing. When the timing result is less than the preset time and greater than 0, it outputs the third flag signal in the valid state; otherwise, it outputs the third flag signal in the invalid state.

[0014] The judgment unit is configured to receive the first flag signal, the second flag signal, and the third flag signal; if at least one of them is valid, it determines that the currently received command signal is the PIM-related command and sends the command signal to the PIM command processing module; otherwise, it determines that the currently received command signal is the DRAM regular command and sends the command signal to the regular command processing module.

[0015] In some embodiments, the command address bus transmits the PIM operation command within a preset time period after transmitting the PIM mode enable command.

[0016] In some embodiments, the PIM command processing module includes:

[0017] The second identification unit is configured to receive the PIM-related commands, decode and determine the PIM-related commands according to the PIM command truth table, and if the currently received PIM-related command is determined to be a PIM mode activation command, output a valid PIM mode activation command indication signal; otherwise, output an invalid PIM mode activation command indication signal. If the currently received PIM-related command is determined to be a PIM operation command, output a valid PIM operation command indication signal; otherwise, output an invalid PIM operation command indication signal. If the currently received PIM-related command is determined to be a PIM execution command, output a valid PIM execution command indication signal; otherwise, output an invalid PIM execution command indication signal.

[0018] The command register is configured to store the PIM operation command in response to the valid PIM operation command indication signal, and to output the PIM operation command to the execution module of the PIM device in response to the valid PIM execution command indication signal.

[0019] In some embodiments, the PIM command processing module further includes:

[0020] A counter is configured to be electrically connected to the second identification unit, count the PIM operation commands in response to the valid PIM operation command indication signal, and output a count value; the count value is cleared to zero when the PIM device is first powered on.

[0021] The address decoding module, electrically connected to the second identification unit, the counter, and the command register, is configured to decode the count value and / or the PIM execution command and output an address signal; wherein the PIM execution command includes the location information of the PIM operation command to be retrieved in the command register, and the address signal is used to indicate the address of the command register.

[0022] In some embodiments, the command register receives the address signal, and in response to a valid PIM operation command indication signal, stores the PIM operation command to the corresponding address according to the address signal; and in response to a valid PIM execution command indication signal, retrieves and outputs the corresponding PIM operation command according to the address signal.

[0023] In some embodiments, the counter resets its count value to zero in response to a valid PIM mode enable command indication signal.

[0024] In some embodiments, the address decoding module decodes the PIM execution command in response to a valid PIM execution command indication signal and outputs the address signal; and decodes the count value in response to an invalid PIM execution command indication signal and outputs the address signal.

[0025] Secondly, embodiments of this disclosure provide a command processing method applied to a PIM device, comprising:

[0026] Receive command signals via the command address bus;

[0027] Determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, then send the command signal to the regular command processing module; if the currently received command signal is determined to be a PIM-related command, then send the command signal to the PIM command processing module.

[0028] The PIM command processing module decodes the PIM-related commands and performs corresponding operations based on the decoding results.

[0029] The conventional command processing module decodes the DRAM conventional commands and performs corresponding operations based on the decoding results.

[0030] In some embodiments, determining the type of the currently received command signal includes: judging the command signal according to the PIM command truth table; determining the PIM mode enable command, the PIM execution command, and the command signals received within a preset time after the PIM mode enable command as PIM-related commands; and determining the rest as DRAM regular commands.

[0031] In some embodiments, the PIM command processing module decodes the PIM-related commands and performs corresponding operations based on the decoding results, including:

[0032] Identify the PIM-related commands;

[0033] If a PIM operation command is detected, the counter is incremented by 1, and the counter value is decoded to obtain an address signal. The PIM operation command is then stored in the command register according to the address signal.

[0034] If the PIM execution command is detected, the PIM execution command is decoded to obtain an address signal. Based on the address signal, the corresponding PIM operation command is retrieved from the command register and output.

[0035] Thirdly, embodiments of this disclosure provide a PIM device, which includes at least the command processing circuitry described in the first aspect.

[0036] The technical solutions provided in this disclosure have at least the following advantages:

[0037] By first determining the type of the command signal and then sending it to the corresponding command processing module for operation, it is no longer necessary to set the storage mode and PIM mode in different time periods or switch between modes. This allows for normal DRAM read / write and PIM unit operations, improving the efficiency of the PIM device and enhancing system performance. Attached Figure Description

[0038] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of a PIM device provided in an embodiment of the present disclosure;

[0040] Figure 2 This is a schematic diagram of the structure of a command processing circuit provided in an embodiment of the present disclosure;

[0041] Figure 3 A signal waveform diagram of a PIM command recognition module provided in an embodiment of this disclosure;

[0042] Figure 4 This is a flowchart illustrating a command processing method provided in an embodiment of the present disclosure. Detailed Implementation

[0043] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] Dynamic Random Access Memory (DRAM)

[0045] Synchronous Dynamic Random Access Memory (SDRAM)

[0046] Double Data Rate SDRAM (DDR)

[0047] Low-power DDR (LPDDR)

[0048] Processing-in-Memory (PIM)

[0049] Command (CMD)

[0050] Multiplication (MUL)

[0051] Addition operation (ADD)

[0052] Command Register (CR)

[0053] Command / Address Bus (CA Bus)

[0054] PIM devices can perform both data storage and arithmetic operations. Data storage can be implemented in storage mode using conventional memory arrays, such as DRAM arrays. Arithmetic operations can be performed in PIM mode using the relevant arithmetic units within the PIM device. Because the command address bus (CA Bus) is shared, PIM devices often operate in two phases: storage mode and PIM mode, handled in storage-related read / write commands, and arithmetic commands handled in PIM mode. This requires mode switching, which consumes significant time and reduces system performance.

[0055] Based on this, this disclosure provides a command processing circuit applied to a PIM device, comprising: a PIM command identification module electrically connected to the command address bus of the PIM device, configured to receive command signals via the command address bus and determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, then the command signal is sent to a regular command processing module; if the currently received command signal is determined to be a PIM-related command, then the command signal is sent to the PIM command processing module; a PIM command processing module electrically connected to the PIM command identification module, configured to receive PIM-related commands, decode the PIM-related commands, and perform corresponding operations based on the decoding results; and a regular command processing module electrically connected to the PIM command identification module, configured to receive DRAM regular commands and decode the DRAM regular commands. Thus, through the design of the command processing circuit, the PIM device can perform normal DRAM read / write operations and PIM unit calculations without mode switching, improving the operating efficiency of the PIM device and enhancing system performance.

[0056] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0057] In one embodiment of this disclosure, see Figure 1 This illustration shows a schematic diagram of a PIM device 70 provided in an embodiment of the present disclosure, wherein the PIM device 70 includes a command processing circuit 10. For example... Figure 1 As shown, the command processing circuit 10 includes:

[0058] The PIM command recognition module 20 is electrically connected to the command address bus of the PIM device 70 and is configured to receive command signals through the command address bus and determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, the command signal is sent to the regular command processing module 40; if the currently received command signal is determined to be a PIM related command, the command signal is sent to the PIM command processing module 30.

[0059] The PIM command processing module 30, electrically connected to the PIM command recognition module 20, is configured to receive PIM-related commands, decode the PIM-related commands, and perform corresponding operations based on the decoding results.

[0060] The conventional command processing module 40 is electrically connected to the PIM command recognition module 20 and is configured to receive DRAM conventional commands and decode them.

[0061] The PIM device 70 also includes a receiver (RX) and a command sampling module 60. The receiver receives command address signals (Command / Address, CMD / ADD) and a clock signal CK_t. In the command sampling module, the clock signal CK_t samples the command address signals CMD / ADD and outputs the command signal. The PIM command identification module 20 receives the command signal via the command address bus and determines the type of the currently received command signal. If it is determined to be a regular DRAM command, the command signal is sent to the regular command processing module 40; if it is determined to be a PIM-related command, the command signal is sent to the PIM command processing module 30. By first determining the type of the command signal and then sending it to the corresponding command processing module for appropriate operation, it is no longer necessary to set the storage mode and PIM mode in different time periods, nor is it necessary to switch between modes, thus improving the efficiency of the PIM device and enhancing system performance.

[0062] The regular command processing module 40 receives DRAM regular commands, decodes the command signals according to the DRAM command truth table, determines the specific type of the DRAM regular command, and sends it to the corresponding functional module to perform the corresponding operation on the DRAM memory array. In some embodiments, DRAM regular commands include at least: read commands, write commands, and refresh commands. It is understood that DRAM regular commands may also include activation commands, precharge commands, and power-saving modes, etc.

[0063] The PIM command processing module 30 receives PIM-related commands, decodes them, and performs corresponding operations based on the decoding results. In some embodiments, the PIM-related commands include: a PIM mode activation command, a PIM operation command, a PIM execution command, and a no-operation command. The PIM mode activation command indicates entry into PIM mode; the PIM operation command includes at least addition and multiplication commands, and is stored in the PIM command processing module 30; the PIM execution command retrieves the PIM operation command from the PIM command processing module 30 and sends it to the execution module 50 of the PIM device to perform the corresponding operation.

[0064] The PIM command processing module 30 decodes the command signals according to the PIM command truth table, determines the specific type of the PIM-related command based on the decoding result, and performs corresponding processing. Specifically, if a PIM operation command is received, it is stored in the PIM command processing module 30; if a PIM execution command is received, it retrieves the PIM operation command from the PIM command processing module 30 and sends it to the execution module 50 of the PIM device. Since the storage mode and PIM mode are no longer set in different time periods, and PIM operations are no longer performed centrally, the sending of PIM operation commands is more flexible. PIM operation commands can be temporarily stored and retrieved and executed when a PIM execution command is received. In this way, the operation of the PIM device is more flexible and efficient. It is understood that in addition to addition and multiplication commands, PIM operation commands can also include shift commands and fill commands, which can be set according to system needs.

[0065] In some embodiments, the PIM command identification module 20 is further configured to determine the command signals received within a preset time after receiving the PIM mode enable command as PIM-related commands and send them to the PIM command processing module 30. Since both DRAM regular commands and PIM-related commands are transmitted through a common command address bus, and some PIM operation commands and DRAM regular commands may have overlapping truth tables, determining the command signals received within a preset time after receiving the PIM mode enable command as PIM-related commands can improve the compatibility between PIM-related commands and DRAM regular commands.

[0066] In some embodiments, the command address bus transmits the PIM operation command within a preset time after transmitting the PIM mode enable command. This ensures that even if the truth tables of the PIM operation command and regular DRAM commands overlap, the PIM operation command can still be identified as a PIM-related command and sent to the PIM command processing module 30. In other words, the overlap of the truth tables of the PIM operation command and regular DRAM commands does not affect the operation of the PIM device, thus saving on the PIM instruction set. It is important to note that the truth tables of the PIM mode enable command and the PIM execution command cannot overlap with those of regular DRAM commands to avoid misjudgment. This approach saves on the PIM instruction set and allows the PIM device to be compatible with both PIM-related commands and regular DRAM commands.

[0067] Understandably, the preset time can be designed based on system requirements and the number of PIM operation commands that can be temporarily stored in the PIM command processing module 30. System requirements include the computational needs of the GPU / CPU / SOC over a period of time. Generally speaking, the more PIM operation commands that can be temporarily stored in the PIM command processing module 30, the longer the preset time can be set.

[0068] In some embodiments, such as Figure 2 As shown, the PIM command recognition module 20 includes:

[0069] The first identification unit 21 is configured to receive a command signal, judge the command signal according to the PIM command truth table, and if the currently received command signal is determined to be a PIM mode start command, output a first flag signal of valid state, otherwise output a first flag signal of invalid state; if the currently received command signal is determined to be a PIM execution command, output a second flag signal of valid state, otherwise output a second flag signal of invalid state.

[0070] The timing unit 22 is configured to receive a first flag signal, clear the first flag signal in response to the valid state, and start timing. When the timing result is less than a preset time and greater than 0, it outputs a third flag signal in the valid state; otherwise, it outputs a third flag signal in the invalid state.

[0071] The judgment unit 23 is configured to receive a first flag signal, a second flag signal, and a third flag signal. If at least one of them is valid, the currently received command signal is determined to be a PIM-related command, and the command signal is sent to the PIM command processing module 30. Otherwise, the currently received command signal is determined to be a DRAM regular command, and the command signal is sent to the regular command processing module 40.

[0072] The first identification unit 21 determines the specific type of PIM-related commands based on the PIM command truth table, identifying PIM mode enable commands and PIM execution commands, and outputs corresponding flag signals. The first identification unit 21 can be implemented using a decoder and some logic circuits, specifically designed according to the truth table. The timing unit 22 starts timing after recognizing the PIM mode enable command. When the timing result is less than a preset time but greater than 0, it outputs a third flag signal indicating a valid state. This is to ensure that all command signals received within a preset time after receiving the PIM mode enable command are classified as PIM-related commands. The timing unit 22 can be implemented using a counter circuit and some logic circuits. The judgment unit 23 determines the type of command signal based on the states of the first, second, and third flag signals. If at least one of them is valid, it is determined to be a PIM-related command; otherwise, it is determined to be a DRAM regular command. In this way, the PIM mode enable command, the PIM execution command, and command signals received within a preset time after the PIM mode enable command are all classified as PIM-related commands. Since the command address bus transmits the PIM operation command within a preset time after transmitting the PIM mode enable command, the PIM operation command can also be determined as a PIM-related command and sent to the PIM command processing module 30. The determination unit 23 can be implemented by a multiplexer and some logic circuits. Specifically, it can be implemented by selecting NAND gates, NOR gates, and inverters based on the levels of the valid and invalid states.

[0073] refer to Figure 3 The diagram illustrates the signal waveform of the PIM command recognition module 20 under one specific scenario. Ck_t and CK_c represent the sampling command address signal CA. <x:0>clock signal and a complementary clock signal. MUL represents a multiplication command in the PIM operation command, and ADD represents an addition command in the PIM operation command. In this embodiment, the valid state is high level, and the invalid state is low level. When the currently received command signal is a PIM mode start command, in the next clock cycle, the first identification unit 21 sets the first flag signal to high level; at the same time, the timing unit 22 starts timing, and sets the third flag signal to high level. At this time, the judgment unit 23 judges the received command signal as a PIM related command, and sends the PIM mode start command to the PIM command processing module 30, while the signal received by the regular command processing module 40 is 000…000, which cannot be decoded into any DRAM regular command. The multiplication command MUL and the addition command ADD after the PIM mode start command are within the preset time, so the third flag signal still maintains in the high level state, so the judgment unit 23 judges the multiplication command MUL and the addition command ADD as PIM related commands, and sends them to the PIM command processing module 30, while the signal received by the regular command processing module 40 is still 000…000. After the preset time, the timing unit 22 sets the third flag signal to low level, at this time, the DRAM read command READ is received, and the first flag signal and the second flag signal output by the first identification unit 21 are both low level, so in the next clock cycle, the judgment unit 23 judges the received command signal as a DRAM regular command, and sends it to the regular command processing module 40. While the signal received by the PIM command processing module 30 is 000…000, which cannot be decoded into any PIM related command. When the currently received command signal is a PIM execution command, in the next clock cycle, the first identification unit 21 sets the second flag signal to high level, and the judgment unit 23 judges the received command signal as a PIM related command, and sends the PIM execution command to the PIM command processing module 30, while the signal received by the regular command processing module 40 is 000…000, which cannot be decoded into any DRAM regular command. Since the reception and transmission of the command address signal both need clock and flip-flop for sampling, the generation of the flag signal and the judgment of the command type are usually delayed by one clock cycle than the receiving time. In some cases, it is delayed by two to three clock cycles. Generally, it is designed according to the performance requirements and actual situation of the circuit.

[0074] In some embodiments, as shown in FIG. 3, the PIM command processing module 30 includes: Figure 2

[0075] ​The second identification unit 31 is configured to receive a PIM related command, decode and judge the PIM related command according to a PIM command truth table, output a valid state PIM mode opening command indication signal if it is judged that the currently received PIM related command is a PIM mode opening command, otherwise output an invalid state PIM mode opening command indication signal; output a valid state PIM operation command indication signal if it is judged that the currently received PIM related command is a PIM operation command, otherwise output an invalid state PIM operation command indication signal; output a valid state PIM execution command indication signal if it is judged that the currently received PIM related command is a PIM execution command, otherwise output an invalid state PIM execution command indication signal.

[0076] The command register 32 is configured to store the PIM operation command in response to the valid state PIM operation command indication signal, and output the PIM operation command to the execution module 50 of the PIM device 70 in response to the valid state PIM execution command indication signal.

[0077] The second identification unit 31 judges the specific type of the PIM related command according to the PIM command truth table, can identify the PIM mode opening command, the PIM operation command and the PIM execution command, and output the corresponding indication signal. The second identification unit 31 can be realized by a decoder and some logic circuits, and the specific design needs to be made according to the truth table. The command register 32 can store the PIM operation command, and in response to the PIM execution command, call the corresponding PIM operation command. Since the storage mode and the PIM mode are no longer set in time periods, and the PIM operation is no longer concentrated, the sending of the PIM operation command is more flexible, which can be temporarily stored first, and then called and executed after receiving the PIM execution command. In this way, the operation of the PIM device is more flexible and efficient, and the switching between modes is not needed, which improves the system performance.

[0078] In some embodiments, as shown in FIG. 1, Figure 2 The PIM command processing module 30 further includes:

[0079] The counter 33 is electrically connected with the second identification unit 31, counts the PIM operation command in response to the valid state PIM operation command indication signal, and outputs a count value; and clears the count value when the PIM device 70 is powered on for the first time.

[0080] The address decoding module 34 is electrically connected with the second identification unit 31, the counter 33 and the command register 32, and is configured to decode the count value and / or the PIM execution command, and output an address signal; wherein the PIM execution command contains position information of the PIM operation command to be invoked in the command register 32, and the address signal is used to indicate the address of the command register 32.

[0081] The counter 33 counts the PIM operation commands, so as to provide the address of the PIM operation command stored in the command register 32. The address decoding module 34 decodes the count value into the address signal required by the command register 32. For example, the PIM device 70 receives the first PIM operation command after initial power-on, the count value is 1, which is represented in binary as 001, and the address signal obtained after decoding by the address decoding module 34 is 000…0001, so the first PIM operation command is stored at the position 000…0001 in the command register 32; the second PIM operation command is received, the count value becomes 2, which is represented in binary as 010, and the address signal obtained after decoding by the address decoding module 34 is 000…0010, so the second PIM operation command is stored at the position 000…0010 in the command register 32; the third PIM operation command is received, the count value becomes 3, which is represented in binary as 011, and the address signal obtained after decoding by the address decoding module 34 is 000…0100, so the third PIM operation command is stored at the position 000…0100 in the command register 32; the fourth PIM operation command is received, the count value becomes 4, which is represented in binary as 100, and the address signal obtained after decoding by the address decoding module 34 is 000…1000, so the third PIM operation command is stored at the position 000…1000 in the command register 32; and so on.

[0082] The address decoding module 34 can also decode the PIM execution command. The PIM execution command contains the position information of the PIM operation command to be invoked in the command register 32. For example, if the PIM execution command is to invoke the third PIM operation command mentioned above, the PIM execution command is 011, and the address signal obtained after decoding by the address decoding module 34 is 000…0100, so the PIM operation command stored at the position is invoked. It can be understood that the address decoding module 34 can be implemented by a decoder and some logic circuits according to the address format of the command register 32.

[0083] In some embodiments, the command register 32 receives the address signal, and in response to the PIM operation command indication signal in the active state, stores the PIM operation command to the corresponding address according to the address signal; and in response to the PIM execution command indication signal in the active state, invokes and outputs the corresponding PIM operation command according to the address signal.

[0084] When the PIM operation command indication signal in the active state is received, the command register 32 stores the currently received PIM operation command to the corresponding position according to the address signal output by the address decoding module 34 at this time. When the PIM execution command indication signal in the active state is received, the command register 32 retrieves the corresponding PIM operation command according to the address signal output by the address decoding module 34 at this time, and outputs the PIM operation command to the execution module 50 of the PIM device 70 to execute the corresponding operation. It can be understood that the command register 32 needs to be based on the respective indication signals and address signals to correctly store and output the PIM operation command, so as to avoid errors in operation.

[0085] In some embodiments, the counter 33 clears the count value in response to the PIM mode start command indication signal in the active state. The counter 33 clears the count value when the PIM device 70 is powered on for the first time, and if the capacity of the command register 32 is large enough, the count value can not be cleared in the running of the PIM device 70, and the count value is always accumulated to store all PIM operation commands in the command register 32. If it is desired to save the capacity of the command register 32, the count value can be cleared every time the PIM mode start command is received, and the counting is restarted, which means that the PIM operation command received after each PIM mode start command will overwrite the PIM operation command stored in the command register 32 after the last PIM mode start command. It should be noted that the PIM execution command after the PIM mode start command can only retrieve the PIM operation command stored in the command register 32. In some cases, the count value can also be cleared after a plurality of PIM mode start commands. For example, the counter 33 can clear the count value once every M PIM mode start command indication signals in the active state, and M is an integer greater than 0, which can be selected according to actual needs and the capacity of the command register.

[0086] In some embodiments, the address decoding module 34 decodes the PIM execution command to output the address signal in response to the PIM execution command indication signal in the active state, and decodes the count value to output the address signal in response to the PIM execution command indication signal in the inactive state. The address decoding module 34 can also include a multiplexer, the control end of the multiplexer receives the PIM execution command indication signal, two input ends respectively receive the PIM execution command and the count value, and if the PIM execution command indication signal is in the active state, the PIM execution command is output to be decoded; if the PIM execution command indication signal is in the inactive state, the count value is output to be decoded. In this way, the PIM execution command and the count value can share a set of decoding circuits, and the circuit devices of the address decoding module 34 can be saved.

[0087] As can be seen from the above analysis, the PIM command recognition module 20 determines the type of the currently received command signal. If it is determined to be a DRAM regular command, the command signal is sent to the regular command processing module 40; if it is determined to be a PIM-related command, the command signal is sent to the PIM command processing module 30. The PIM command processing module 30 further identifies the PIM-related commands. If a PIM operation command is identified, the counter 33 is incremented by 1, and the address decoding module 34 decodes the count value of the counter 33 to obtain the address signal. Based on the address signal, the PIM operation command is stored in the command register 32. If a PIM execution command is identified, the address decoding module 34 decodes the PIM execution command to obtain the address signal. Based on the address signal, the corresponding PIM operation command is retrieved from the command register 32 and output to the execution module 50 of the PIM device 70.

[0088] In summary, the command processing circuit provided in this embodiment first determines the type of the command signal and then sends it to the corresponding command processing module for operation. This eliminates the need to set the storage mode and PIM mode in different time periods or switch between modes, thus enabling normal DRAM read / write and PIM unit operations. This improves the efficiency of the PIM device and enhances system performance.

[0089] In another embodiment of this disclosure, see [reference needed]. Figure 4 This illustrates a flowchart of a command processing method provided in an embodiment of this disclosure. Figure 4 As shown, this method is applied to a PIM device and includes:

[0090] S101, Receive command signals via the command address bus;

[0091] S102. Determine the type of the currently received command signal;

[0092] S103. If it is determined that the currently received command signal is a DRAM regular command, then the command signal is sent to the regular command processing module and step S105 is performed.

[0093] S104. If it is determined that the currently received command signal is a PIM-related command, the command signal is sent to the PIM command processing module and step S106 is performed.

[0094] S105, the regular command processing module decodes the DRAM regular commands and performs corresponding operations based on the decoding results;

[0095] S106, the PIM command processing module decodes PIM-related commands and performs corresponding operations based on the decoding results.

[0096] This command processing method first determines the type of the command signal, and then sends it to the corresponding command processing module for operation. This eliminates the need to set the storage mode and PIM mode in different time periods, and also eliminates the need to switch between modes. It can then perform normal DRAM read and write operations and PIM unit operations, thereby improving the efficiency of PIM device operation and enhancing system performance.

[0097] In some embodiments, determining the type of the currently received command signal includes: judging the command signal according to the PIM command truth table; classifying the PIM mode enable command, the PIM execution command, and command signals received within a preset time after the PIM mode enable command as PIM-related commands; and classifying the rest as DRAM regular commands. In some embodiments, the command address bus transmits the PIM operation command within a preset time after transmitting the PIM mode enable command. Thus, even if the truth tables of the PIM operation command and the DRAM regular command overlap, the PIM operation command can still be determined as a PIM-related command and sent to the PIM command processing module 30. The PIM mode enable command is used to indicate entering PIM mode; the PIM operation command includes at least addition and multiplication commands, and the PIM operation command is stored in the PIM command processing module; the PIM execution command is used to retrieve the PIM operation command from the PIM command processing module and send it to the execution module of the PIM device to perform the corresponding operation.

[0098] In some embodiments, the PIM command processing module decodes PIM-related commands and performs corresponding operations based on the decoding results, including: identifying PIM-related commands; if a PIM operation command is identified, controlling a counter to increment by 1, decoding the counter value to obtain an address signal, and storing the PIM operation command in the command register according to the address signal; if a PIM execution command is identified, decoding the PIM execution command to obtain an address signal, and retrieving and outputting the corresponding PIM operation command from the command register according to the address signal. Since the storage mode and PIM mode are no longer set in time periods, and PIM operations are no longer performed centrally, the sending of PIM operation commands is more flexible. PIM operation commands can be temporarily stored and then retrieved and executed upon receiving a PIM execution command. This makes the PIM device more flexible and efficient in operation, eliminates the need for mode switching, and improves system performance.

[0099] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 1 This illustration shows a schematic diagram of the composition structure of a PIM device 70 provided in an embodiment of this disclosure. Figure 1 As shown, the PIM device 70 includes at least the aforementioned command processing circuit 10.

[0100] like Figure 1 As shown, the PIM device 70 also includes a receiver (RX), a command sampling module 60, and an execution module 50. The receiver receives a command address signal (Command / Address, CMD / ADD) and a clock signal CK_t. In the command sampling module, the clock signal CK_t samples the command address signal CMD / ADD and outputs the command signal. The execution module 50 can perform PIM-related operations. The PIM device 70 also includes a storage array, which is not shown in the figure.

[0101] The command processing circuit 10 included in the PIM device first determines the type of the command signal and then sends it to the corresponding command processing module for corresponding operation. This eliminates the need to set the storage mode and PIM mode in different time periods, and also eliminates the need to switch between modes. It can perform normal DRAM read and write operations and PIM unit operations, thereby improving the efficiency of the PIM device and enhancing system performance.

[0102] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A command processing circuit, characterized in that, Applied to PIM devices, including: The PIM command identification module is electrically connected to the command address bus of the PIM device and is configured to receive command signals through the command address bus and determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, the command signal is sent to the regular command processing module; if the currently received command signal is determined to be a PIM-related command, the command signal is sent to the PIM command processing module. The PIM command processing module is electrically connected to the PIM command recognition module and is configured to receive the PIM-related commands, decode the PIM-related commands, and perform corresponding operations based on the decoding results. The conventional command processing module, which is electrically connected to the PIM command recognition module, is configured to receive the DRAM conventional commands and decode them.

2. The command processing circuit according to claim 1, characterized in that, The PIM-related commands include: PIM mode activation command, PIM operation command, PIM execution command, and no operation command; the PIM mode activation command is used to indicate entering PIM mode; the PIM operation command includes at least an addition command and a multiplication command, and the PIM operation command is stored in the PIM command processing module; the PIM execution command is used to retrieve the PIM operation command from the PIM command processing module and send it to the execution module of the PIM device.

3. The command processing circuit according to claim 1, characterized in that, The DRAM conventional commands include at least: read commands, write commands, and refresh commands.

4. The command processing circuit according to claim 2, characterized in that, The PIM command recognition module is also used to determine the command signal received within a preset time after receiving the PIM mode activation command as the PIM-related command, and send it to the PIM command processing module.

5. The command processing circuit according to claim 4, characterized in that, The PIM command recognition module includes: The first identification unit is configured to receive the command signal, determine the command signal according to the PIM command truth table, and if the currently received command signal is determined to be the PIM mode activation command, output a first flag signal of valid state; otherwise, output a first flag signal of invalid state. If the currently received command signal is determined to be the PIM execution command, output a second flag signal of valid state; otherwise, output a second flag signal of invalid state. The timing unit is configured to receive the first flag signal, clear the first flag signal of valid state to zero, and start timing. When the timing result is less than the preset time and greater than 0, output a third flag signal of valid state; otherwise, output a third flag signal of invalid state. The judgment unit is configured to receive the first flag signal, the second flag signal, and the third flag signal; if at least one of them is valid, it determines that the currently received command signal is the PIM-related command and sends the command signal to the PIM command processing module; otherwise, it determines that the currently received command signal is the DRAM regular command and sends the command signal to the regular command processing module.

6. The command processing circuit according to claim 4, characterized in that, The command address bus transmits the PIM operation command within a preset time period after transmitting the PIM mode enable command.

7. The command processing circuit according to claim 2, characterized in that, The PIM command processing module includes: The second identification unit is configured to receive the PIM-related commands, decode and determine the PIM-related commands according to the PIM command truth table, and if the currently received PIM-related command is determined to be a PIM mode activation command, output a valid PIM mode activation command indication signal; otherwise, output an invalid PIM mode activation command indication signal. If the currently received PIM-related command is determined to be a PIM operation command, output a valid PIM operation command indication signal; otherwise, output an invalid PIM operation command indication signal. If the currently received PIM-related command is determined to be a PIM execution command, output a valid PIM execution command indication signal; otherwise, output an invalid PIM execution command indication signal. The command register is configured to store the PIM operation command in response to the valid PIM operation command indication signal, and to output the PIM operation command to the execution module of the PIM device in response to the valid PIM execution command indication signal.

8. The command processing circuit according to claim 7, characterized in that, The PIM command processing module also includes: A counter is configured to be electrically connected to the second identification unit, count the PIM operation commands in response to the valid PIM operation command indication signal, and output a count value; the count value is cleared to zero when the PIM device is first powered on. The address decoding module, electrically connected to the second identification unit, the counter, and the command register, is configured to decode the count value and / or the PIM execution command and output an address signal; wherein the PIM execution command includes the location information of the PIM operation command to be retrieved in the command register, and the address signal is used to indicate the address of the command register.

9. The command processing circuit according to claim 8, characterized in that, The command register receives the address signal, and in response to the valid PIM operation command indication signal, stores the PIM operation command to the corresponding address according to the address signal; in response to the valid PIM execution command indication signal, retrieves and outputs the corresponding PIM operation command according to the address signal.

10. The command processing circuit according to claim 8, characterized in that, The counter is reset to zero in response to the PIM mode enable command indication signal in the valid state.

11. The command processing circuit according to claim 8, characterized in that, The address decoding module, in response to the valid PIM execution command indication signal, decodes the PIM execution command and outputs the address signal; in response to the invalid PIM execution command indication signal, decodes the count value and outputs the address signal.

12. A command processing method, characterized in that, Applied to PIM devices, including: Receive command signals via the command address bus; Determine the type of the currently received command signal; if the currently received command signal is determined to be a DRAM regular command, then send the command signal to the regular command processing module; if the currently received command signal is determined to be a PIM-related command, then send the command signal to the PIM command processing module. The PIM command processing module decodes the PIM-related commands and performs corresponding operations based on the decoding results; the regular command processing module decodes the DRAM regular commands and performs corresponding operations based on the decoding results.

13. The command processing method according to claim 12, characterized in that, The determination of the type of the currently received command signal includes: judging the command signal according to the PIM command truth table; determining the PIM mode enable command, PIM execution command, and command signals received within a preset time after the PIM mode enable command as PIM-related commands; and determining the rest as DRAM regular commands.

14. The command processing method according to claim 13, characterized in that, The PIM command processing module decodes the PIM-related commands and performs corresponding operations based on the decoding results, including: Identify the PIM-related commands; If a PIM operation command is detected, the counter is incremented by 1, and the counter value is decoded to obtain an address signal. The PIM operation command is then stored in the command register according to the address signal. If the PIM execution command is detected, the PIM execution command is decoded to obtain an address signal. Based on the address signal, the corresponding PIM operation command is retrieved from the command register and output.

15. A PIM device, characterized in that, Includes the command processing circuit as described in any one of claims 1-11.

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