Oscillator circuit, oscillator, and chip
By employing a closed-loop feedback circuit and a progressively increasing bias current design in the ring oscillator, the problems of high shoot-through current and high power consumption of CMOS inverters are solved, realizing a low-power, high-frequency oscillator circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-03-27
AI Technical Summary
Existing ring oscillators suffer from high shoot-through current and high power consumption during switching due to the direct connection of the CMOS inverter to the power supply voltage and ground.
A closed-loop feedback circuit is formed by the oscillation unit and the first inverter chain, and the bias current and clamping charging current are provided to the first inverter chain in the loop through the current generation unit. The gradient bias current design with progressively increasing bias current constrains the transient shoot-through current and reduces dynamic power consumption.
It effectively reduces the overall power consumption of the oscillator circuit while ensuring the stability of signal switching speed and oscillation frequency, thus realizing a low-power, high-frequency oscillator circuit.
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Figure CN121749904A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and more particularly to an oscillator circuit, an oscillator, and a chip. Background Technology
[0002] A clock signal is a periodic signal that provides an accurate and stable timing reference for the internal circuitry of a chip, ensuring the correctness and reliability of the operation of various components within the chip. A ring oscillator is a common on-chip clock source that can generate high-precision clock signals.
[0003] Currently, ring oscillators are typically implemented using cascaded CMOS inverters. Each cascaded CMOS inverter is directly connected between the power supply voltage and ground, and oscillation is generated by the switching characteristics of transistors.
[0004] However, the CMOS inverter in the oscillator generates a large power-to-ground current during each logic state flip, resulting in high power consumption of the oscillator. Summary of the Invention
[0005] In view of this, embodiments of this application provide an oscillator circuit, an oscillator, and a chip to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of the embodiments of this application, an oscillator circuit is provided, comprising: an oscillation unit, a first inverter chain, and a current generating unit; the output terminal of the oscillation unit is electrically connected to the input terminal of the first inverter chain, a first input terminal of the oscillation unit is electrically connected to the output terminal of the first inverter chain, a second input terminal of the oscillation unit is electrically connected to the output terminal of the current generating unit, and the input terminal of the current generating unit is used to connect a reference current; the first inverter chain includes N first inverters, the N first inverters are cascaded, and the input terminal of the first-stage first inverter serves as the first inverter... The input terminal of the inverter chain is the output terminal of the first inverter of the Nth stage, and the power supply terminals of the N first inverters are electrically connected to the output terminal of the current generating unit. The ground terminals of the N first inverters are grounded, where N is an integer greater than 1. The oscillation unit is used to control the first inverter chain to output a periodic signal. The current generating unit is used to output a bias current proportional to the reference current, and the bias current output to the power supply terminal of the first inverter of the i-th stage is less than the bias current output to the power supply terminal of the (i+1)-th stage first inverter, where i is a positive integer less than N.
[0007] In one possible implementation, the first inverter includes a first PMOS transistor and a first NMOS transistor; the gates of the first PMOS transistor and the first NMOS transistor are electrically connected, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the first PMOS transistor is electrically connected to the output terminal of the current generating unit, and the source of the first NMOS transistor is grounded.
[0008] In one possible implementation, the current generating unit includes: a second PMOS transistor and N third PMOS transistors; the drain of the second PMOS transistor is used to connect to the reference current, the gate of the second PMOS transistor is electrically connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is electrically connected to the source of each of the N third PMOS transistors; the gates of all N third PMOS transistors are electrically connected to the gates of the second PMOS transistors, and the drain of the i-th third PMOS transistor among the N third PMOS transistors is electrically connected to the source of the first PMOS transistor in the i-th stage first inverter.
[0009] In one possible implementation, the width-to-length ratio of the i-th third PMOS transistor among the N third PMOS transistors is less than the width-to-length ratio of the (i+1)-th third PMOS transistor.
[0010] In one possible implementation, the oscillation unit includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a capacitor, and a resistor; the drain of the second NMOS transistor is electrically connected to the output terminal of the current generating unit, the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor and the drain of the second NMOS transistor, the source of the second NMOS transistor is electrically connected to a first terminal of the resistor, and the second terminal of the resistor is grounded; the drain of the third NMOS transistor is electrically connected to the output terminal of the current generating unit, and is also electrically connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor in the first stage first inverter, the source of the third NMOS transistor is electrically connected to a first terminal of the capacitor, and the second terminal of the capacitor is grounded; the drain of the fourth NMOS transistor is electrically connected to a first terminal of the capacitor, and the source of the fourth NMOS transistor is electrically connected to a second terminal of the capacitor.
[0011] In one possible implementation, the oscillation period of the oscillator circuit ,in, R Let be the resistance value of the resistor. C Let be the capacitance value of the capacitor. I 2 represents the drain current value of the second NMOS transistor. I 3 represents the drain current value of the third NMOS transistor.
[0012] In one possible implementation, the current generating unit further includes: a fourth PMOS transistor and a fifth PMOS transistor; the gate of the fourth PMOS transistor is electrically connected to the gate of the second PMOS transistor, the source of the fourth PMOS transistor is electrically connected to the source of the second PMOS transistor, and the drain of the fourth PMOS transistor is electrically connected to the drain of the second NMOS transistor; the gate of the fifth PMOS transistor is electrically connected to the gate of the second PMOS transistor, the source of the fifth PMOS transistor is electrically connected to the source of the second PMOS transistor, and the drain of the fifth PMOS transistor is electrically connected to the drain of the third NMOS transistor.
[0013] In one possible implementation, the oscillator circuit further includes a second inverter chain; the input terminal of the second inverter chain is electrically connected to the output terminal of the first inverter chain, and the output terminal of the second inverter chain is electrically connected to the first input terminal of the oscillation unit; the second inverter chain includes M second inverters, the M second inverters are cascaded, the input terminal of the first stage second inverter serves as the input terminal of the second inverter chain, and the output terminal of the Mth stage second inverter serves as the output terminal of the second inverter chain, where M is a positive integer.
[0014] In one possible implementation, the gate of the fourth NMOS transistor is electrically connected to the output terminal of the Nth-stage first inverter, or the gate of the fourth NMOS transistor is electrically connected to the output terminal of the Mth-stage second inverter.
[0015] According to a second aspect of the embodiments of this application, an oscillator is provided, including the oscillator circuit as described in the first aspect of the embodiments of this application.
[0016] According to a third aspect of the embodiments of this application, a chip is provided, including an oscillator as described in the second aspect of the embodiments of this application.
[0017] According to the oscillator circuit provided in the embodiments of this application, a closed-loop feedback loop is formed by the oscillation unit and the first inverter chain. The bias current provided to the first inverter chain in the loop by the current generation unit effectively clamps the charging current of the first inverter in the first inverter chain during signal switching, thereby constraining the transient shoot-through current from the power supply to ground and reducing the dynamic power consumption of the circuit. Simultaneously, the current generation unit provides a gradient bias current that increases progressively from the previous stage to the next stage for the first inverter chain in the loop. This allows the previous stage inverter, which directly processes the output signal of the oscillation unit, to operate under low current, further suppressing dynamic power consumption from the source of the oscillation loop. The subsequent stage inverter, driven by a larger current, effectively compensates for the delay introduced by the current limiting in the previous stage. Combined with the fast discharge capability maintained by grounding the ground terminal of the first inverter, the overall circuit ensures the signal switching speed and oscillation frequency stability of the entire loop, enabling the oscillator circuit to stably output a periodic clock signal. Compared with the prior art, the solution provided in this embodiment can solve the problem of high shoot-through current and high power consumption when the existing ring oscillator is flipped due to the direct connection of the CMOS inverter to the power supply voltage and ground, thereby reducing the overall power consumption of the oscillator circuit. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0019] Figure 1 This is a circuit diagram of a prior art oscillator circuit; Figure 2 This is a circuit diagram of an oscillator circuit provided in an embodiment of this application; Figure 3 This is a circuit diagram of another oscillator circuit provided in an embodiment of this application. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0021] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0022] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0023] As mentioned earlier, a clock signal is a periodic signal that provides an accurate and stable timing reference for the internal circuitry of a chip, ensuring the correctness and reliability of the operation of various components within the chip. A ring oscillator is a common on-chip clock source that can generate high-precision clock signals. Figure 1 This is a circuit diagram of a prior art oscillator circuit, such as... Figure 1 As shown, ring oscillators are currently typically implemented using cascaded CMOS inverters. Each cascaded CMOS inverter is directly connected between the power supply voltage and ground, relying on the switching characteristics of transistors to generate oscillation. However, each logic state transition of the CMOS inverters in the oscillator generates a large through-current from the power supply to ground, resulting in high power consumption for the oscillator.
[0024] In this embodiment, the oscillator circuit includes an oscillation unit, a first inverter chain, and a current generating unit. The output terminal of the oscillation unit is electrically connected to the input terminal of the first inverter chain. The first input terminal of the oscillation unit is electrically connected to the output terminal of the first inverter chain, and the second input terminal of the oscillation unit is electrically connected to the output terminal of the current generating unit. The input terminal of the current generating unit is used to connect a reference current IB. The first inverter chain includes N first inverters cascaded together. The input terminal of the first-stage first inverter serves as the input terminal of the first inverter chain, and the output terminal of the Nth-stage first inverter serves as the output terminal of the first inverter chain. The power supply terminals of the N first inverters are respectively electrically connected to the output terminals of the current generating unit, and the ground terminals of the N first inverters are grounded, where N is an integer greater than 1. The oscillation unit can control the first inverter chain to output a periodic signal. The current generation unit can output a bias current proportional to the reference current IB, and the bias current output to the power supply terminal of the first inverter in the i-th stage is less than the bias current output to the power supply terminal of the first inverter in the (i+1)-th stage, where i is a positive integer less than N. By forming a closed-loop feedback circuit with the oscillation unit and the first inverter chain, and by providing the bias current to the first inverter chain in the loop through the current generation unit, the charging current of the first inverter in the first inverter chain during signal flipping can be effectively clamped, thereby constraining the transient shoot-through current from the power supply to ground and reducing the dynamic power consumption of the circuit. Simultaneously, the current generation unit provides a gradually increasing gradient bias current to the first inverter chain in the loop, from the front stage to the rear stage. This allows the front-stage inverter, which directly processes the output signal of the oscillation unit, to operate under low current, further suppressing dynamic power consumption from the source of the oscillation loop. The rear-stage inverter, driven by a larger current, effectively compensates for the delay introduced by the current limiting in the front stage. Combined with the fast discharge capability maintained by grounding the ground terminal of the first inverter, the overall signal switching speed and oscillation frequency stability of the entire loop can be ensured, thereby enabling the oscillator circuit to stably output a periodic clock signal. Compared with the prior art, the solution provided in this embodiment can solve the problem of high shoot-through current and high power consumption during switching caused by the direct connection of the CMOS inverter to the power supply voltage and ground in existing ring oscillators, reducing the overall power consumption of the oscillator circuit.
[0025] The oscillator circuit provided in this application is illustrated below through examples.
[0026] Figure 2 This is a circuit diagram of an oscillator circuit provided in an embodiment of this application, such as... Figure 2As shown, the oscillator circuit 100 includes an oscillation unit 101, a first inverter chain 102, and a current generating unit 103. The output terminal of the oscillation unit 101 is electrically connected to the input terminal of the first inverter chain 102, the first input terminal of the oscillation unit 101 is electrically connected to the output terminal of the first inverter chain 102, and the second input terminal of the oscillation unit 101 is electrically connected to the output terminal of the current generating unit 103. The input terminal of the current generating unit 103 is used to connect a reference current IB. The first inverter chain 102 includes N first inverters 1021, which are cascaded together. The input terminal of the first-stage first inverter 1021 serves as the input terminal of the first inverter chain 102, and the output terminal of the Nth-stage first inverter 1021 serves as the output terminal of the first inverter chain 102. The power supply terminals of the N first inverters 1021 are electrically connected to the output terminals of the current generating unit 103, and the ground terminals of the N first inverters 1021 are grounded, where N is an integer greater than 1. The oscillation unit 101 can control the first inverter chain 102 to output a periodic signal. The current generating unit 103 can output a bias current proportional to the reference current IB, and the bias current output to the power supply terminal of the i-th stage first inverter 1021 is less than the bias current output to the power supply terminal of the (i+1)-th stage first inverter 1021, where i is a positive integer less than N.
[0027] The input terminal of the current generation unit 103 is connected to an external reference current IB, and the output is a bias current proportional to the reference current IB, providing a stable operating bias for the oscillation unit 101 and the first inverter chain 102. The current generation unit 103 can be implemented by means of a resistor current limiting structure, a current mirror structure, or a programmable current generation structure of a digital-to-analog converter (DAC).
[0028] The output terminal of the oscillation unit 101 is electrically connected to the input terminal of the first inverter chain 102, and is used to transmit control signals to the first inverter chain 102. The first input terminal of the oscillation unit 101 is used to receive the output signal of the first inverter chain 102, forming a signal feedback loop. At the same time, the second input terminal of the oscillation unit 101 is electrically connected to the output terminal of the current generating unit 103, and receives the bias current provided by the current generating unit 103 to ensure the normal operation of its own oscillation logic.
[0029] The circuit oscillation process is as follows: Oscillating unit 101 generates a control signal (low or high level) at its output terminal based on its initial state, and outputs this control signal to the input terminal of the first inverter chain 102. The first inverter chain 102 performs delay and shaping operations on the control signal, generates a feedback signal, and transmits this feedback signal to the first input terminal of oscillation unit 101 through a feedback loop. Based on the signal output by the first inverter chain 102, oscillation unit 101 generates a new control signal after internal logic processing, and transmits it to the first inverter chain 102 again. After delay and shaping operations by the first inverter chain 102, a new feedback signal is generated and fed back to oscillation unit 101. This cycle repeats continuously, with oscillation unit 101 continuously controlling the first inverter chain 102 to output a periodic signal, causing the entire circuit to enter a stable oscillation state, ultimately outputting a periodic clock signal through the first inverter chain 102.
[0030] Figure 2 As an example, a first inverter chain 102 including two first inverters 1021 is shown. In other embodiments, the first inverter chain 102 may include a greater number of first inverters 1021.
[0031] The first inverter chain 102 comprises N first inverters 1021, each of which is a current-limited inverter, where N is a positive integer greater than 1. The N first inverters 1021 are cascaded. Except for the last stage, the output of the i-th stage first inverter 1021 (i=1, 2, ..., N-1) is connected to the input of the (i+1)-th stage first inverter 1021. That is, the output of the first stage is connected to the input of the second stage, the output of the second stage is connected to the input of the third stage, and so on, until the output of the (N-1)-th stage is connected to the input of the N-th stage. The input of the first stage first inverter 1021 serves as the input of the first inverter chain 102, used to receive the control signal output by the oscillation unit 101. The output of the N-th stage first inverter 1021 serves as the output of the first inverter chain 102, used to output a clock signal. Understandably, since each first inverter 1021 has a signal inversion function, the phase of the output signal of the first inverter chain 102 is determined by the number of inverter stages N. Specifically, if N is odd, that is, the first inverter chain 102 contains an odd number of inverter stages, then the first inverter chain 102 outputs a signal that is in phase with the control signal to the oscillation unit 101; if N is even, that is, the first inverter chain 102 contains an even number of inverter stages, then the first inverter chain 102 outputs a signal that is in phase with the control signal.
[0032] The power supply terminals of the N first inverters 1021 are electrically connected to the output terminals of the current generating unit 103. The bias current output by the current generating unit 103 to the power supply terminal of the i-th stage first inverter 1021 is less than the bias current output to the power supply terminal of the (i+1)-th stage first inverter 1021. That is, the bias current of the power supply terminal of the first stage first inverter 1021 is less than the bias current of the power supply terminal of the second stage first inverter 1021, the bias current of the power supply terminal of the second stage first inverter 1021 is less than the bias current of the power supply terminal of the third stage first inverter 1021, and so on. The bias current of the power supply terminal of the (N-1)-th stage first inverter 1021 is less than the bias current of the power supply terminal of the N-th stage first inverter 1021. The bias current of the current-limited inverter 1021 can be increased stepwise from stage 1 to stage N in a fixed ratio, or it can be freely configured according to actual needs, as long as it increases stepwise from stage 1 to stage N. There are no restrictions here.
[0033] It should be noted that the power supply terminal of the first inverter 1021 is connected to the current generation unit 103 instead of being directly connected to the standard voltage. Its charging current is clamped by the current provided by the current generation unit 103, thereby constraining the transient current from the power supply to ground during signal switching, thus reducing dynamic and short-circuit power consumption. Simultaneously, the ground terminal of the first inverter 1021 is directly grounded, maintaining its rapid discharge capability and avoiding excessive total delay. Furthermore, the front-end current-limited inverter 1021 (especially the first stage) in the first inverter chain 102 directly processes the original control signal output by the oscillation unit 101. The switching of this signal is the starting point of the loop oscillation and is most sensitive to dynamic power consumption. By configuring the first-stage first inverter 1021 with a minimum bias current, the charging current can be limited from the source, minimizing dynamic power consumption. As the signal propagates towards the back of the chain, its logic level gradually establishes itself, and the edges tend to stabilize, reducing its sensitivity to power consumption. The progressively increasing charging current for subsequent stages enhances their response speed during signal transitions (especially rising edges), effectively compensating for the additional delay introduced by the small current at the front end. This ensures that the total delay of the entire first inverter chain 102 meets the oscillation frequency requirements. This design significantly reduces overall power consumption compared to using a large drive current, while significantly shortening the overall delay compared to using a small drive current, achieving a balance between power consumption and performance.
[0034] In this embodiment, a closed-loop feedback loop is formed by the oscillation unit 101 and the first inverter chain 102, and the bias current provided by the current generation unit 103 to the first inverter chain 102 in the loop can effectively clamp the charging current of the first inverter 1021 in the first inverter chain 102 when the signal is flipped, thereby constraining the transient shoot-through current from the power supply to ground and reducing the dynamic power consumption of the circuit. At the same time, the current generation unit 103 provides a gradient bias current that increases step by step from the front stage to the rear stage to the first inverter chain 102 in the loop, so that the front-stage inverter that directly processes the output signal of the oscillation unit operates under a small current, which can further suppress dynamic power consumption from the source of the oscillation loop. The rear-stage inverter can effectively compensate for the delay introduced by the current limiting of the front stage by the larger current drive, and combined with the fast discharge capability maintained by the ground terminal of the first inverter 1021, the overall signal flipping speed and oscillation frequency stability of the entire loop can be ensured, thereby enabling the oscillator circuit 100 to stably output a periodic clock signal. Compared with the prior art, the solution provided in this embodiment can solve the problem of high shoot-through current and high power consumption when the existing ring oscillator is flipped due to the direct connection of the CMOS inverter to the power supply voltage and ground, thereby reducing the overall power consumption of the oscillator circuit.
[0035] In one possible implementation, such as Figure 2 As shown, the first inverter 1021 includes a first PMOS transistor PM1 and a first NMOS transistor NM1. The gates of the first PMOS transistor PM1 and NM1 are electrically connected, the drains of the first PMOS transistor PM1 and NM1 are electrically connected, the source of the first PMOS transistor PM1 is electrically connected to the output terminal of the current generating unit 103, and the source of the first NMOS transistor NM1 is grounded.
[0036] Each first inverter 1021 consists of a first PMOS transistor PM1 and a first NMOS transistor NM1 forming a basic inverting unit. The gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 are electrically connected, and the connection node serves as the input terminal of this stage's first inverter 1021, receiving the input signal. The drains of the first PMOS transistor PM1 and the first NMOS transistor NM1 are electrically connected, and the connection node serves as the output terminal of this stage's first inverter 1021. Through the complementary switching action of the first PMOS transistor PM1 and the first NMOS transistor NM1, the input signal is inverted and output. The source of the first PMOS transistor PM1 is electrically connected to the output terminal of the current generation unit 103, receiving the bias current output by the current generation unit 103. The specific value is determined according to the position of this stage's first inverter 1021 in the first inverter chain 102. The source of the first NMOS transistor NM1 is grounded. When the output low level flips, the source of the first NMOS transistor NM1 forms a low-impedance discharge path to ground, achieving fast discharge and reducing the falling edge delay.
[0037] In this embodiment, the first inverter 1021 includes a first PMOS transistor PM1 and a first NMOS transistor NM1. The gates of the first PMOS transistor PM1 and NM1 are electrically connected, the drains of the first PMOS transistor PM1 and NM1 are electrically connected, the source of the first PMOS transistor PM1 is electrically connected to the output of the current generation unit 103, and the source of the first NMOS transistor NM1 is grounded. When the first inverter 1021 outputs a high level, the conduction current of the first PMOS transistor PM1 is clamped by the bias current output by the current generation unit 103, which can constrain the transient peak current and thus significantly reduce dynamic power consumption. Furthermore, when the first inverter 1021 outputs a low level, the first NMOS transistor NM1 conducts to ground and discharges rapidly, which can reduce response delay. This achieves a balance between power consumption and delay, enabling the oscillator to maintain high frequency stability and signal quality while having low power consumption.
[0038] In one possible implementation, such as Figure 2 As shown, the current generating unit 103 includes a second PMOS transistor PM2 and N third PMOS transistors PM3. The drain of the second PMOS transistor PM2 is used to connect to the reference current IB. The gate of the second PMOS transistor PM2 is electrically connected to the drain of the second PMOS transistor PM2, and the source of the second PMOS transistor PM2 is electrically connected to the source of each of the N third PMOS transistors PM3. The gates of all N third PMOS transistors PM3 are electrically connected to the gate of the second PMOS transistor PM2. The drain of the i-th third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1 in the i-th stage first inverter 1021.
[0039] The second PMOS transistor PM2 and N third PMOS transistors PM3 form a current mirror structure. Specifically, the second PMOS transistor PM2 serves as the reference transistor. The drain of the second PMOS transistor PM2 receives a reference current IB, which acts as the reference current source for the entire current mirror circuit. The source of the second PMOS transistor PM2 is connected to the power supply voltage VDD. Simultaneously, the gate and drain of the second PMOS transistor PM2 are electrically connected, forming a diode connection structure. Under the combined effect of the power supply voltage VDD and the reference current IB, the second PMOS transistor PM2 operates in the saturation region. After the reference current IB flows into the drain of the second PMOS transistor PM2 operating in the saturation region, a specific bias voltage is established at the source of the second PMOS transistor PM2. This voltage is transmitted to all the third PMOS transistors PM3 through the common source, which is the core foundation for the current mirror structure to achieve current mirroring.
[0040] N third PMOS transistors PM3 serve as mirror current branches. The sources of all N third PMOS transistors PM3 are electrically connected to the sources of the second PMOS transistors PM2, and the gates of all N third PMOS transistors PM3 are electrically connected to the gates of the second PMOS transistors PM2. Therefore, the gate-source voltage of all third PMOS transistors PM3 is the same as that of the reference transistor, the second PMOS transistor PM2. According to the current characteristics of MOS transistors, the current flowing through the drain of each third PMOS transistor PM3 is proportional to the reference current IB. The drain of the i-th third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1 in the i-th stage first inverter 1021, providing a bias current to the source of each first PMOS transistor PM1.
[0041] In this embodiment, the current generating unit 103 includes a second PMOS transistor PM2 and N third PMOS transistors PM3. The drain of the second PMOS transistor PM2 is used to connect to the reference current IB. The gate of the second PMOS transistor PM2 is electrically connected to the drain of the second PMOS transistor PM2, and the source of the second PMOS transistor PM2 is electrically connected to the sources of the N third PMOS transistors PM3 respectively. The gates of all N third PMOS transistors PM3 are electrically connected to the gates of the second PMOS transistor PM2. The drain of the i-th third PMOS transistor PM3 is electrically connected to the source of the first PMOS transistor PM1 in the i-th stage first inverter 1021. By using the second PMOS transistor PM2 as the reference current branch, the reference current IB is mirrored into the mirror branch composed of the N third PMOS transistors PM3, which can provide accurate and mutually matched bias currents for each first inverter 1021 in the first inverter chain 102, improving the overall performance and reliability of the circuit.
[0042] Furthermore, the width-to-length ratio of the i-th third PMOS transistor among the N third PMOS transistors is less than that of the (i+1)-th third PMOS transistor.
[0043] Based on the current mirror structure composed of the second PMOS transistor PM2 and N third PMOS transistors PM3, the gate-source voltage of each third PMOS transistor PM3 is the same as that of the reference transistor, the second PMOS transistor PM2. According to the current characteristics of MOS transistors, the ratio of the current flowing through the drain of each third PMOS transistor PM3 to the reference current is equal to the ratio of the size (width-to-length ratio) of the third PMOS transistor PM3 itself to the size of the second PMOS transistor PM2. The width-to-length ratio of the i-th third PMOS transistor among the N third PMOS transistors is smaller than that of the (i+1)-th third PMOS transistor, making the bias current output to the power supply terminal of the i-th stage first inverter smaller than the bias current output to the power supply terminal of the (i+1)-th stage first inverter. Specifically, the third PMOS transistor PM3 connected to the first stage first inverter 1021 has the smallest size, and the corresponding output bias current is the smallest. The size of the third PMOS transistor PM3 increases with each subsequent stage, and the corresponding output bias current also increases accordingly. The output bias current is maximized when the size of the third PMOS transistor PM3 connected to the first inverter 1021 of the Nth stage reaches its maximum.
[0044] In this embodiment, by using the mirroring characteristic of the current mirror, the bias current input to the first PMOS transistor PM1 in each stage of the first inverter 1021 through the N third PMOS transistors PM3 can be increased step by step from the first stage to the Nth stage. This ensures that each stage of the first inverter 1021 can obtain the driving capability that matches its actual load size requirement, thereby achieving synergistic optimization of oscillator power consumption and delay characteristics, so that the oscillator has low power consumption while maintaining high frequency stability and signal quality.
[0045] In one possible implementation, such as Figure 2 As shown, the oscillation unit 101 includes a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a capacitor C, and a resistor R. The drain of the second NMOS transistor NM2 is electrically connected to the output terminal of the current generating unit 103. The gate of the second NMOS transistor NM2 is electrically connected to the gate of the third NMOS transistor NM3 and the drain of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is electrically connected to the first terminal of the resistor R, and the second terminal of the resistor R is grounded. The drain of the third NMOS transistor NM3 is electrically connected to the output terminal of the current generating unit 103, and is also electrically connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the first stage first inverter 1021. The source of the third NMOS transistor NM3 is electrically connected to the first terminal of the capacitor C, and the second terminal of the capacitor C is grounded. The drain of the fourth NMOS transistor NM4 is electrically connected to the first terminal of the capacitor C, and the source of the fourth NMOS transistor NM4 is electrically connected to the second terminal of the capacitor C.
[0046] The gate of the second NMOS transistor NM2 is electrically connected to its drain, forming a diode connection structure. Under normal bias conditions, the second NMOS transistor NM2 operates in the saturation region. The bias current output from the current generation unit 103 is input to the drain of the second NMOS transistor NM2, then outputs through the source of the second NMOS transistor NM2 to the first terminal of resistor R, and then through the second terminal of resistor R to ground, forming a fixed voltage drop across resistor R. The value of this voltage drop is the product of the resistance value and the bias current output from the current generation unit 103 to the drain of the second NMOS transistor NM2. Since the second NMOS transistor NM2 has a diode connection structure and operates in the saturation region, the voltage difference between its gate and source is fixed. Therefore, the gate voltage of the second NMOS transistor NM2 is equal to the fixed voltage drop across the resistor R connected to its source plus the fixed gate-source voltage difference, thus keeping the gate of the second NMOS transistor NM2 stable. Since the gate of the third NMOS transistor NM3 is electrically connected to the gate of the second NMOS transistor NM2, the gate voltage of the third NMOS transistor NM3 remains unchanged and serves as a reference voltage.
[0047] The gate of the fourth NMOS transistor NM4 receives a periodic feedback signal, which controls the periodic on and off of the fourth NMOS transistor NM4. Since the drain and source of the fourth NMOS transistor NM4 are connected in parallel across the capacitor C, the periodic on and off of the fourth NMOS transistor NM4 causes the capacitor C to charge and discharge periodically. This causes the source voltage of the third NMOS transistor NM3, which is electrically connected to the first terminal of the capacitor C, to change dynamically with the charging and discharging process of the capacitor C. Since the gate voltage of the third NMOS transistor NM3 remains constant, the dynamic change in the source voltage of the third NMOS transistor NM3 causes a change in the conduction state of the third NMOS transistor NM3, realizing the comparison between the reference voltage and the comparison voltage. This, in turn, causes the drain voltage of the third NMOS transistor NM3 to change dynamically, outputting a periodic control signal, triggering the inverter chain to flip periodically, generating a periodic clock signal, and feeding it back to the gate of the fourth NMOS transistor NM4, forming a self-sustaining oscillation.
[0048] The working principle of the oscillation unit 101 will be explained in detail below with reference to an embodiment in which the first input terminal of the oscillation unit 101 is directly electrically connected to the output terminal of the first inverter chain, that is, the gate of the fourth NMOS transistor NM4 is electrically connected to the output terminal of the Nth stage first inverter 1021: When the circuit starts up, the signal output by the first inverter 1021 of the Nth stage is low (0). The gate of the fourth NMOS transistor NM4 receives this low-level signal and is in the off state. At this time, the capacitor C is not short-circuited. The bias current output by the current generating unit 103 flows through the third NMOS transistor NM3 to charge the capacitor C. The voltage at the first terminal of the capacitor C rises linearly, causing the source voltage of the third NMOS transistor NM3 to rise synchronously. Since the gate voltage of the third NMOS transistor NM3 is fixed, when the source voltage of the third NMOS transistor NM3 is small, the gate-source voltage difference of the third NMOS transistor NM3 is large, and the drain voltage of the third NMOS transistor NM3 is low (close to ground level). As the source voltage of the third NMOS transistor NM3 rises, the gate-source voltage difference of the third NMOS transistor NM3 will gradually decrease, the conductivity of the third NMOS transistor NM3 will weaken, and it will gradually enter the linear region. The drain voltage of the third NMOS transistor NM3 will be pulled up by the bias current output by the current generating unit 103. The drain of the third NMOS transistor NM3 is electrically connected to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 in the first stage first inverter 1021. That is, the drain output level of the third NMOS transistor NM3 serves as the input of the first inverter chain 102. When the drain voltage of the third NMOS transistor NM3 rises to the input threshold voltage of the first stage first inverter 1021, the high level output of the drain of the third NMOS transistor NM3 triggers the first stage first inverter 1021 to flip, and outputs a high-level signal through the first inverter chain 102, which is then fed back to the gate of the fourth NMOS transistor NM4.
[0049] When the gate of the fourth NMOS transistor NM4 receives a high-level signal, it turns on, short-circuiting the capacitor C connected in parallel with the drain and source of the fourth NMOS transistor NM4. Capacitor C discharges rapidly through the fourth NMOS transistor NM4, causing the source voltage of the third NMOS transistor NM3 to drop rapidly to near ground. Due to the rapid decrease in the source voltage of the third NMOS transistor NM3, the gate-source voltage difference of the third NMOS transistor NM3 increases rapidly, enhancing its conductivity, and consequently causing its drain voltage to drop rapidly. When the drain voltage of the third NMOS transistor NM3 drops below the input threshold voltage of the first inverter 1021 in the first stage, the low-level output from the drain of the third NMOS transistor NM3 triggers the first inverter 1021 to flip, outputting a low-level signal through the first inverter chain 102, which is fed back to the gate of the fourth NMOS transistor NM4, causing it to turn off. Capacitor C stops discharging and re-enters the charging phase, thus achieving the periodic oscillation cycle of the circuit.
[0050] In this embodiment, a reference voltage is generated by a second NMOS transistor NM2 connected by a diode and a resistor R. Combined with a controlled discharge switch of a fourth NMOS transistor NM4 and a dynamic comparison mechanism of the charging and discharging voltage of a capacitor C using a third NMOS transistor NM3, self-sustaining oscillation can be achieved using small-scale devices, saving chip area and improving chip integration. Furthermore, by multiplexing the reference circuit and the charging circuit in the comparison circuit, a separate comparator and its bias circuit are eliminated, enabling low-power oscillation while ensuring frequency stability.
[0051] In one possible implementation, the oscillation period of the oscillator circuit 100 ,in, R Let R be the resistance value. C Let C be the capacitance value. I 2 represents the drain current value of the second NMOS transistor NM2. I 3 represents the drain current of the third NMOS transistor, NM3.
[0052] Under ideal operating conditions, the oscillator circuit 100 completes the discharge phase rapidly through the fourth NMOS transistor NM4, and the duration of the discharge phase is much shorter than the charging phase, so it can be ignored. The oscillation period of the oscillator circuit 100 is determined by the duration of the charging phase. During charging, the drain current of the third NMOS transistor NM3 varies with time. Ts The total charge provided by capacitor C is: (1) in, I 3 represents the drain current of the third NMOS transistor, NM3.
[0053] During the charging phase, the voltage of capacitor C rises from 0V at the end of discharging to the threshold voltage that triggers the switching. Vref (Reference voltage), the reference voltage is generated across resistor R by the current flowing through the drain of the second NMOS transistor NM2 (under ideal operating conditions, the gate-source voltage of NM2 can be ignored compared to the voltage drop across resistor R): (2) in, I 2 represents the drain current value of the second NMOS transistor NM2. R Let R be the resistance value.
[0054] During the charging process of capacitor C, that is, capacitor C charges from 0V to the reference voltage. Vref The charge increment stored in capacitor C is: (3) in, C Let C be the capacitance value.
[0055] During the charging phase, based on the principles of energy conservation and charge balance, the charging current... I 3 in the cycle Ts The total charge injected into capacitor C is equal to the charge required to charge capacitor C to the reference voltage, therefore: (4) The oscillation period of oscillator circuit 100 is obtained from equations (1)-(4). .
[0056] From the oscillation period formula of oscillator circuit 100, we can know that the period... Ts and , and current ratio I 2 / I Proportional to 3. This can be achieved by adjusting the current ratio. I 2 / I 3. The oscillation period can be flexibly adjusted. Ts Specifically, while maintaining R , C and current I With 3 unchanged, increase the drain current of the second NMOS transistor NM2. I 2. Increasing the reference voltage can extend the cycle. This is while maintaining R, C, and current. I With 2 unchanged, increase the drain current of the third NMOS transistor NM3. I 3. (Accelerating the charging rate of capacitor C) can shorten the cycle.
[0057] It should be noted that the oscillation period formula in this embodiment is derived based on an ideal model. In actual circuits, the gate-source voltage of NM2 should be considered. VGS 2. At this time, the actual reference voltage is Vref = I 2× R + VGS 2. The discharge time of the fourth NMOS transistor, NM4, should also be considered (it's non-zero but accounts for a very small percentage). However, these non-ideal factors will only cause a slight shift in the cycle and will not affect the ability to adjust the current ratio. I 2 / I The core function of "3. Flexible adjustment of oscillation period" does not change the oscillation period and R , C , I 2 / I The core proportional relationship of 3.
[0058] In this embodiment of the application, the oscillation period of the oscillator circuit 100 ,in, R Let R be the resistance value. C Let C be the capacitance value. I 2 represents the drain current value of the second NMOS transistor NM2. I 3 represents the drain current of the third NMOS transistor, NM3. Therefore, the frequency accuracy is determined by the passive components (resistor R, capacitor C) and the current mirror ratio. This is necessary when adjusting the oscillation period of oscillator circuit 100. Ts At this time, without changing the value of the difficult-to-integrate precision resistor R or capacitor C, only the drain current of the second NMOS transistor can be adjusted. I 2 and the drain current of the third NMOS transistor I The oscillation period of the oscillator circuit 100 can be adjusted by the ratio of 3. Ts This improves the flexibility of the period frequency control of the oscillator circuit 100.
[0059] In one possible implementation, such as Figure 2 As shown, the current generating unit 103 further includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5. The gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the second NMOS transistor NM2. The gate of the fifth PMOS transistor PM5 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fifth PMOS transistor PM5 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fifth PMOS transistor PM5 is electrically connected to the drain of the third NMOS transistor NM3.
[0060] Since the gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the second NMOS transistor NM2, the fourth PMOS transistor PM4 acts as a mirror current branch of the second PMOS transistor PM2, mirroring the reference current to generate a bias current, which forms a reference voltage on R through the second NMOS transistor NM2.
[0061] Since the gate of the fifth PMOS transistor PM5 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fifth PMOS transistor PM5 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fifth PMOS transistor PM5 is electrically connected to the drain of the third NMOS transistor NM3, the fifth PMOS transistor PM5 serves as another mirror current branch of the second PMOS transistor PM2, mirroring the reference current to generate a bias current, which in turn generates a comparison voltage on capacitor C through the third NMOS transistor NM3.
[0062] In this embodiment, the current generating unit 103 further includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5. The gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the second NMOS transistor NM2. The gate of the fifth PMOS transistor PM5 is electrically connected to the gate of the second PMOS transistor PM2, the source of the fifth PMOS transistor PM5 is electrically connected to the source of the second PMOS transistor PM2, and the drain of the fifth PMOS transistor PM5 is electrically connected to the drain of the third NMOS transistor NM3. By using the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 as mirror branches to generate bias current, high-precision current ratio control can be achieved, improving frequency stability. Furthermore, by adjusting the size ratio of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5, the current ratio can be adjusted. / To adjust the oscillation period of the oscillator circuit 100 This improves the adjustability and flexibility of the oscillator.
[0063] Figure 3 This is a circuit diagram of another oscillator circuit provided in an embodiment of this application, such as... Figure 3 As shown, the oscillator circuit 100 also includes a second inverter chain 104. The input terminal of the second inverter chain 104 is electrically connected to the output terminal of the first inverter chain 102, and the output terminal of the second inverter chain 104 is electrically connected to the first input terminal of the oscillation unit 101. The second inverter chain 104 includes M second inverters 1041, which are cascaded. The input terminal of the first-stage second inverter 1041 serves as the input terminal of the second inverter chain 104, and the output terminal of the M-th stage second inverter 1041 serves as the output terminal of the second inverter chain 104, where M is a positive integer.
[0064] After the circuit starts, the oscillation unit 101 generates a control signal (low or high level) based on the initial state and outputs it to the first inverter chain 102. The first inverter chain 102 processes the control signal and transmits it to the second inverter chain 104. The second inverter chain 104 shapes the signal to a standard logic level using its strong drive characteristics and adjusts the signal phase according to the stage M, generating a feedback signal that is transmitted to the first input terminal of the oscillation unit 101. Based on this feedback signal, the oscillation unit 101 generates a new control signal after internal logic processing and transmits it to the first inverter chain 102 again. After being processed sequentially by the first inverter chain 102 and the second inverter chain 104, a new feedback signal is generated and fed back to the oscillation unit 101. This cycle repeats until the entire circuit enters a stable oscillation state, ultimately outputting a high-quality periodic clock signal through the second inverter chain 104.
[0065] Figure 3 As an example, a second inverter chain 104 including two second inverters 1041 is shown. In other embodiments, the second inverter chain 104 may include one or more second inverters 1041.
[0066] The second inverter chain 104 comprises M second inverters 1041, each of which is a CMOS inverter, where M is a positive integer. When M equals 1, the second inverter chain 104 comprises only one second inverter 1041, the input of which serves as the input of the second inverter chain 104, and the output of which serves as the output of the second inverter chain 104. When M is greater than or equal to 2, the M second inverters 1041 are cascaded. Except for the last stage, the output of the j-th stage second inverter 1041 (j=1, 2, ..., M-1) is connected to the input of the (j+1)-th stage second inverter 1041. That is, the output of the first stage is connected to the input of the second stage, the output of the second stage is connected to the input of the third stage, and so on, until the output of the (M-1)-th stage is connected to the input of the M-th stage. The input terminal of the first-stage second inverter 1041 serves as the input terminal of the second inverter chain 104, used to receive the control signal output from the first inverter chain 102. The output terminal of the M-stage second inverter 1041 serves as the output terminal of the second inverter chain 104, used to output a clock signal. It can be understood that each stage of the second inverter 1041 converts the input signal into an inverted signal output. Therefore, when M is odd, the second inverter chain 104 outputs a signal inverted from the signal input to it; when M is even, it outputs a signal in phase with the signal input to it. The power supply terminals of the M second inverters 1041 are connected to a voltage source, and the ground terminals of the M second inverters 1041 are grounded. The voltage source can be a battery, a voltage regulator, or a system power supply, used to provide a standard power supply voltage.
[0067] It should be noted that although the power consumption of the second inverter 1041 (CMOS inverter) is higher than that of the first inverter 1021 (current-limited inverter) per flip, its extremely short delay means that the time it is in the active state in each oscillation cycle is very small. Moreover, its strong driving capability ensures the rapid flipping of the output signal and reduces the duration of short-circuit current during the switching process, thus achieving a balance between power consumption and performance at the system level.
[0068] To more intuitively demonstrate the power reduction effect of the oscillator circuit 100 in this embodiment, simulations were performed on both the prior art oscillator circuit OSC1 and the oscillator circuit 100 provided in this embodiment. The simulation results are summarized in the table below:
[0069] As can be seen from the table above, the transient current of the prior art oscillator circuit OSC1 at room temperature and pressure is 484.342 μA, the average current is 3.420 μA at a power supply voltage of 5V, and 0.9730 μA at a power supply voltage of 3V. The oscillator circuit 100 provided in this application embodiment has a transient current of 375.777 μA at room temperature and pressure, an average current of 0.378 μA at a power supply voltage of 5V, and an average current of 0.2958 μA at a power supply voltage of 3V. Therefore, the oscillator circuit 100 provided in this application embodiment, by multiplexing the reference circuit and charging circuit in the comparator circuit, eliminating the need for an independent comparator and its bias circuit, and combining an inverter chain consisting of the first inverter 1021 and the second inverter 1041, can significantly reduce the transient current and average current of the oscillator circuit 100, thereby reducing the system's power consumption.
[0070] In this embodiment, a first inverter chain 102, composed of cascaded first inverters 1021 at the front end, receives the signal output from the oscillation unit 101. This places the power-sensitive initial signal processing stage in a current-constrained environment, suppressing the large current generated during the initial signal establishment phase (especially during power-on and switching processes) and reducing overall dynamic power consumption. Simultaneously, a second inverter chain 104, composed of cascaded second inverters 1041 at the rear end, further processes the signal. The second inverter 1041, connected to a standard voltage, can quickly reshape and restore the logic signal output from the first inverter 1021 (which may not be at full amplitude) to the standard logic level, thanks to its strong driving capability and fast switching characteristics, while providing sufficient driving strength. The synergistic effect of the first inverter chain 102 and the second inverter chain 104 allows the overall circuit to maintain the required oscillation frequency and signal quality while achieving the low-power goal, ensuring the quality and stability of the feedback clock signal and maintaining reliable oscillation.
[0071] In one possible implementation, the gate of the fourth NMOS transistor NM4 is electrically connected to the output of the Nth stage first inverter 1021, or the gate of the fourth NMOS transistor NM4 is electrically connected to the output of the Mth stage second inverter 1041.
[0072] This embodiment provides two optional schemes for the gate connection of the fourth NMOS transistor NM4 in the oscillation unit 101 to adapt to different application scenarios. Specifically: In the first scheme, the gate of the fourth NMOS transistor NM4 is electrically connected to the output of the Nth-stage first inverter 1021. That is, the gate of the fourth NMOS transistor NM4 is electrically connected to the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1 in the Nth-stage first inverter 1021. In this case, the feedback loop is "oscillation unit 101 → first inverter chain 102 → oscillation unit 101". This scheme requires N (the number of first inverter chain stages) to be even so that the signal input to the oscillation unit 101 from the first inverter chain 102 is in phase with the signal fed back to the oscillation unit 101 from the first inverter chain 102, thus ensuring the overall oscillation logic. This scheme has a compact structure, requires no additional buffer stage, and directly reuses the output signal of the first inverter chain 102, simplifying circuit connections and reducing device redundancy. It is suitable for scenarios with strict chip area requirements.
[0073] In the second scheme, the gate of the fourth NMOS transistor NM4 is electrically connected to the output of the second inverter 1041 of the Mth stage. That is, the gate of the fourth NMOS transistor NM4 is electrically connected to the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1 in the second inverter 1041 of the Mth stage. In this case, the feedback loop is "oscillation unit 101 → first inverter chain 102 → second inverter chain 104 → oscillation unit 101". The signal phase is superimposed through the two inverter chains (each inverter chain realizes one signal inversion, and the total number of inversions is determined by N+M). Therefore, it is not necessary to restrict N to be even. As long as the sum of N (number of stages of the first inverter chain) and M (number of stages of the second inverter chain) is even, it can be guaranteed that the signal phase fed back to the oscillation unit 101 is adapted to its working logic and achieve stable oscillation. This solution provides a standard logic level through the second inverter chain 104, which can shape and restore the signal that may not reach full amplitude output by the first inverter chain 102 to the standard logic level, ensuring the quality of the feedback signal. At the same time, the second inverter chain 104 acts as a buffer isolation, which can reduce the sensitivity of the feedback path to the delay characteristics of the first inverter chain 102, improve the stability of the oscillation frequency and the robustness of the system, and is suitable for scenarios with high requirements for clock signal quality and reliability.
[0074] In this embodiment, by providing two optional connection schemes for the gate of the fourth NMOS transistor NM4, the single oscillator architecture can be compatible with two feedback path topologies while maintaining the consistency of the core structure of the oscillation unit 101. Scheme 1 directly connects to the first inverter of the Nth stage to meet area-sensitive scenarios, while Scheme 2 provides enhanced driving and signal shaping capabilities through the second inverter chain to meet high-performance requirements. This expands the applicability of the oscillator circuit 100 while ensuring the stability of the oscillation logic, improving the versatility and practicality of the oscillator circuit.
[0075] This application also provides an oscillator, which includes the oscillator circuit 100 in any of the above embodiments. Since it is based on the same inventive concept as the foregoing embodiments and can achieve the same effect, the specific implementation process can be found in the description of the foregoing embodiments, and will not be repeated here.
[0076] This application also provides a chip that includes the oscillator described in the above embodiments.
[0077] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.
[0078] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.
[0079] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.
Claims
1. An oscillator circuit, characterized in that, include: Oscillating unit, first inverter chain and current generating unit; The output terminal of the oscillation unit is electrically connected to the input terminal of the first inverter chain. The first input terminal of the oscillation unit is used to be electrically connected to the output terminal of the first inverter chain. The second input terminal of the oscillation unit is electrically connected to the output terminal of the current generating unit. The input terminal of the current generating unit is used to connect to a reference current. The first inverter chain includes N first inverters, which are cascaded together. The input terminal of the first-stage first inverter serves as the input terminal of the first inverter chain, and the output terminal of the Nth-stage first inverter serves as the output terminal of the first inverter chain. The power supply terminals of the N first inverters are respectively electrically connected to the output terminal of the current generating unit, and the ground terminals of the N first inverters are grounded. Here, N is an integer greater than 1. The oscillation unit is used to control the first inverter chain to output a periodic signal; The current generating unit is used to output a bias current proportional to the reference current, and the bias current output to the power supply terminal of the first inverter of the i-th stage is less than the bias current output to the power supply terminal of the first inverter of the (i+1)-th stage, where i is a positive integer less than N.
2. The oscillator circuit according to claim 1, characterized in that, The first inverter includes: a first PMOS transistor and a first NMOS transistor; The gate of the first PMOS transistor is electrically connected to the gate of the first NMOS transistor, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the first PMOS transistor is electrically connected to the output terminal of the current generating unit, and the source of the first NMOS transistor is grounded.
3. The oscillator circuit according to claim 2, characterized in that, The current generating unit includes: a second PMOS transistor and N third PMOS transistors; The drain of the second PMOS transistor is used to connect to the reference current, the gate of the second PMOS transistor is electrically connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is electrically connected to the sources of the N third PMOS transistors respectively. The gates of all N third PMOS transistors are electrically connected to the gates of the second PMOS transistors, and the drain of the i-th third PMOS transistor among the N third PMOS transistors is electrically connected to the source of the first PMOS transistor in the i-th stage first inverter.
4. The oscillator circuit according to claim 3, characterized in that, The width-to-length ratio of the i-th third PMOS transistor among the N third PMOS transistors is less than that of the (i+1)-th third PMOS transistor.
5. The oscillator circuit according to claim 3, characterized in that, The oscillation unit includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a capacitor, and a resistor; The drain of the second NMOS transistor is electrically connected to the output terminal of the current generating unit, the gate of the second NMOS transistor is electrically connected to the gate of the third NMOS transistor and the drain of the second NMOS transistor, the source of the second NMOS transistor is electrically connected to the first terminal of the resistor, and the second terminal of the resistor is grounded. The drain of the third NMOS transistor is electrically connected to the output terminal of the current generating unit, and is also electrically connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor in the first inverter of the first stage. The source of the third NMOS transistor is electrically connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded. The drain of the fourth NMOS transistor is electrically connected to the first terminal of the capacitor, and the source of the fourth NMOS transistor is electrically connected to the second terminal of the capacitor.
6. The oscillator circuit according to claim 5, characterized in that, The oscillation period of the oscillator circuit ,in, R Let be the resistance value of the resistor. C Let be the capacitance value of the capacitor. I 2 represents the drain current value of the second NMOS transistor. I 3 represents the drain current value of the third NMOS transistor.
7. The oscillator circuit according to claim 5, characterized in that, The current generating unit further includes: a fourth PMOS transistor and a fifth PMOS transistor; The gate of the fourth PMOS transistor is electrically connected to the gate of the second PMOS transistor, the source of the fourth PMOS transistor is electrically connected to the source of the second PMOS transistor, and the drain of the fourth PMOS transistor is electrically connected to the drain of the second NMOS transistor. The gate of the fifth PMOS transistor is electrically connected to the gate of the second PMOS transistor, the source of the fifth PMOS transistor is electrically connected to the source of the second PMOS transistor, and the drain of the fifth PMOS transistor is electrically connected to the drain of the third NMOS transistor.
8. The oscillator circuit according to any one of claims 5-7, characterized in that, The oscillator circuit also includes a second inverter chain; The input terminal of the second inverter chain is electrically connected to the output terminal of the first inverter chain, and the output terminal of the second inverter chain is electrically connected to the first input terminal of the oscillation unit. The second inverter chain includes M second inverters, which are cascaded together. The input terminal of the first-stage second inverter serves as the input terminal of the second inverter chain, and the output terminal of the M-th-stage second inverter serves as the output terminal of the second inverter chain, where M is a positive integer.
9. The oscillator circuit according to claim 8, characterized in that, The gate of the fourth NMOS transistor is electrically connected to the output terminal of the Nth stage first inverter, or the gate of the fourth NMOS transistor is electrically connected to the output terminal of the Mth stage second inverter.
10. An oscillator, characterized in that, Includes the oscillator circuit as described in any one of claims 1-9.
11. A chip, characterized in that, Includes the oscillator as described in claim 10.