Digital filter circuit for calculating exponential variance of signal, corresponding system on chip and method of operation

Abstract

The invention relates to a digital filter circuit for calculating an exponential variance of a signal, a corresponding system on chip and a method of operation. A digital signal processing method includes: applying a first infinite impulse response filtering operation to a digital input signal to produce a first filtered signal; performing a mathematical transformation on a combination of the digital input signal and the first filtered signal to produce a transformed signal; applying a second infinite impulse response filtering operation to the transformed signal to produce a second filtered signal; performing a scaling operation on the second filtered signal to generate a scaled signal; and combining the second filtered signal and the scaled signal to produce a digital output signal indicative of a statistical characteristic of the digital input signal.

Description

Cross-references to related applications

[0001] This application claims the benefit of Italian application No. 102024000021350, filed on 25 September 2024, which is incorporated herein by reference. Technical Field

[0002] This specification relates to a digital filter circuit for calculating the exponential variance of a signal, a corresponding system-on-chip, and an operating method. Background Technology

[0003] In the field of inductive wireless power transmission, ASK modulation can be used to exchange data between power transmitter devices PTx (i.e., charger devices) and power receiver devices PRx (i.e., typically portable electronic devices such as mobile phones, tablets, etc.).

[0004] Figure 1 This is an example diagram of a wireless power transfer system, which includes a charging pad 10 and a portable electronic device 14 (e.g., a smartphone). The charging pad 10 receives electrical energy from a power source via a power line 12, and the portable electronic device 14 includes a battery that can be inductively charged by the charging pad 10. For this purpose, the charging pad 10 includes a power transmitting coil 10a, and the device 14 includes a power receiving coil 14a. The power transmitting coil 10a and the power receiving coil 14b are configured to be inductively coupled when the portable device 14 is placed on the charging pad 10. For ease of explanation, both coils 10a and 14a... Figure 1 The component is depicted as separate from pad 10 and device 14.

[0005] Power transmitter 10 generates alternating current (AC) in power transmitting coil 10a to induce a time-varying magnetic field through power receiving coil 14a. Some wireless power transfer standards, such as the Qi standard, use communication protocols to exchange data between devices 10 and 14 to manage the charging process: for more details on the Qi standard for wireless charging systems, please refer to the Qi specification document version 1.3 from January 2021, which is publicly available at www.wirelesspowerconsortium.com. Essentially, in communication protocols like Qi, power transmitter 10 can send messages to power receiver 14 using frequency shift keying (FSK) modulation, and power receiver 14 can respond to power transmitter 10 using amplitude shift keying (ASK) modulation.

[0006] Figure 2This is a circuit diagram example of some internal components of devices 10 and 14 used for wireless power transmission (from device 10 to device 14, see the arrow labeled PT) and data exchange via ASK-based communication (from device 14 to device 10, see the arrow labeled DE). Essentially, the power transmitter 10 includes a coil 10a and an AC power supply that supplies AC voltage to the coil 10a. The AC power supply may include a pulse width modulation (PWM) square wave generator 11 that controls a power inverter 13 to generate the AC voltage. V AB The voltage is then applied to coil 10a via a series capacitor. Power receiver 14 includes coil 14a inductively coupled to coil 10a, a switchable capacitive network 15 disposed downstream of coil 14a, a bridge rectifier circuit 16 (e.g., diode bridge) disposed downstream of switchable capacitive network 15, a parallel RC circuit 17 disposed at the output of rectifier circuit 16, and a switchable load 18 (e.g., a resistor in series with an electronic switch) selectively coupled in parallel with RC circuit 17.

[0007] The voltage at the power transmitting coil 10a is a sine wave. W (by voltage) V AB The sine wave, generated by resonant filtering, carries the power to be transmitted to the power receiving coil 14a. The power receiver device 14 can slightly alter the amplitude of the power carrier by changing its internal load impedance (e.g., by selectively coupling the switchable load 18 to and decoupling the switchable load 18 from the RC circuit 17), and this mechanism (also known as backscatter modulation) is used to achieve ASK modulation of the carrier to transmit information from the power receiver to the power transmitter side. The power transmitter device 10 can sense the voltage across coil 10a (e.g., via generating an analog voltage signal). V ASKD The amplifier circuit 19a, and then the signal V ASKD An analog-to-digital converter (ADC) 19b is used to digitize the data, and the message transmitted by the power receiver device 14 is demodulated (e.g., via an ASK demodulator circuit 19c, which may include, for example, a digital I / Q demodulator) to achieve ASK demodulation. Therefore, the demodulation logic can be fully digital to use the ADC to monitor the voltage at coil 10a.

[0008] In particular, the Qi protocol can rely on, for example, Figure 3 The Manchester-style ASK encoding shown is called Biphasic Mark Code (BMC). The diagram illustrates a periodic... t CLK clock signal CLK and data signals DATA The waveform (obtained after ASK demodulation of a sinusoidal carrier wave). Essentially, if the digital signal... DATA If the value of a bit remains constant (high or low) throughout the clock cycle, it is interpreted as carrying a '0' bit; if its value changes during the clock cycle (rising or falling edge), it is interpreted as carrying a '1' bit. In other words, each bit of the raw data is represented by two logic states, which together form a bit: each logic 1 is represented as a pair of two distinct bits (10 or 01), and each logic 0 is represented as a pair of equal bits (00 or 11). Each logic level at the beginning of a unit is the opposite of the level at the end of the previous unit. According to the Qi protocol, the preamble can be given by a sequence of consecutive logic 1s (the number of which actually depends on the bit rate), so the message includes a start bit (always logic zero), a data byte, a parity bit (set to 1 if the data byte contains an even number of 1 bits), and finally a stop bit (always 1). According to the Qi protocol, the frequency of the clock signal... f CLK It can be 2kHz ± 4% (which also corresponds to the bit rate).

[0009] The input modulation signal of the ASK demodulator W and output demodulated signal DATA The waveform is shown again in Figure 4 In the middle. Assuming the modulating signal... W Sampling is performed by an ADC, therefore the entire demodulation process can be performed using digital hardware (e.g., within the power transmitting device 10, such as...). Figure 2 (As shown in the example) to execute.

[0010] Figure 5 This is an example of a circuit block diagram of the main block of the processing chain of the ASK demodulator circuit 50. The ADC 51 (which may or may not be considered part of the ASK demodulator) receives a modulated analog signal from the primary coil 10a. W (or modulated stream), and the signal W Convert to input digital signal x[n] .Signal x[n]The signal is passed to circuit 52 (bandpass to baseband), which converts the transmitted signal spectrum to the baseband domain (near DC). The output of circuit 52 is passed to image suppression filter circuit 53, which removes high-frequency artifacts generated by the preceding circuit 52. Due to the reduced bandwidth requirement, the output of filter circuit 53 is passed to decimation circuit 54, which applies decimation. The output of decimation circuit 54 is passed to high-pass filter circuit 55, which removes DC artifacts that typically occur during downconversion operated by decimation circuit 54. The output of filter circuit 55 is passed to limiter circuit 56, which accepts signals that are typically symmetrical to 0 and performs binary decisions based on a “threshold” parameter. Thus, limiter 56 essentially operates as a hysteresis comparator to compress information from multiple bits to a single bit (two levels). The output of limiter circuit 56 is passed to symbol decoder circuit 57, which identifies messages associated with ASK modulation and generates a digitally demodulated signal. DATA_out .

[0011] In some applications, it can be advantageous for the ASK demodulator to include logic configured to identify (detect) the presence of amplitude modulation on the input signal. The presence of amplitude modulation can be detected by demodulating the demodulated signal and estimating its energy. To estimate the energy of the signal, the exponential variance of the signal can be calculated, as long as its value indicates the energy of the signal. Digital signals x[n] The exponential variance (or exponentially weighted variance, denoted here as) σ 2 [n] or S[n] The following formula can be used to calculate: in α It is a parameter between 0 (inclusive) and 1 (exclusive), and is usually in the form of α =2 -k ,and μ[n] It is a signal x[n] The exponential average (or exponentially weighted average) can then be expressed as follows:

[0012] Therefore, it is desirable for the ASK demodulator to be configured to calculate the exponential mean and exponential variance of the input digital signal, for example, to detect the presence of ASK modulation on the input signal. According to some known solutions, the exponential moving variance can be calculated via firmware, but these solutions are typically hampered by long computation times. According to other known solutions, the exponential moving variance can be calculated using dedicated hardware IP blocks, but these solutions are typically hampered by high area overhead, the inability to reuse verified IP blocks, and the fact that dedicated IP blocks can only be used to calculate the exponential moving variance.

[0013] Various documents of interest in the field of digital signal processing include US2010 / 0109844A, US2020 / 0013421A1, US5,823,964A, US2021 / 0314201A1, US2005 / 0210091A1, and articles by MA Basiri M and NM Sk. "Configurable Folded IIR Filter Design" , in IEEE Transactions onCircuits and Systems II: Express Briefs, vol. 62, no. 12, pp. 1144-1148, Dec.2015, doi: 10.1109 / TCSII.2015.2468917. Summary of the Invention

[0014] The embodiments disclosed herein can provide improved hardware circuitry (digital filters) for calculating the exponential mean and exponential variance of digital signals, which can be used in ASK demodulator circuitry and occupy less silicon area than known solutions.

[0015] This specification relates to digital filter circuits that can be used to calculate the exponential mean and exponential variance of digital signals (e.g., for amplitude shift keying or ASK demodulator circuits).

[0016] One or more embodiments help to provide such improved hardware digital filter circuitry, corresponding system-on-chip, and operating methods.

[0017] One or more embodiments may relate to a corresponding system-on-a-chip (SoC).

[0018] One or more embodiments may involve corresponding operating methods.

[0019] According to one aspect of this specification, a digital filter circuit includes an input terminal configured to receive a digital input signal and an output terminal configured to provide a digital output signal. The digital output signal indicates the exponentially shifted variance of the digital input signal. The digital filter circuit includes a signal processing chain disposed between the input terminal and the output terminal. In the signal processing chain, a low-pass filter is applied to the digital input signal to generate a first intermediate signal indicating the exponentially shifted average of the digital input signal. The first intermediate signal is subtracted from the digital input signal to generate a second intermediate signal. The square of the second intermediate signal is calculated to generate a third intermediate signal. A low-pass filter is applied to the third intermediate signal to generate a fourth intermediate signal indicating the exponentially shifted average of the third intermediate signal. The fourth intermediate signal is right-shifted to generate a fifth intermediate signal. The fifth intermediate signal is subtracted from the fourth intermediate signal to generate a digital output signal.

[0020] Therefore, one or more embodiments may provide a digital filter circuit for calculating the exponential variance of a signal and having a low silicon footprint.

[0021] According to another aspect of this specification, a system-on-chip (e.g., a controller for a wireless power transmitter) includes: an analog-to-digital converter (ADC), a digital filter circuit according to one or more embodiments, and an ASK demodulator circuit. The ADC is configured to receive an analog amplitude-modulated signal and convert it into a digital input signal for the digital filter circuit. The digital filter circuit is configured to receive the digital input signal from the ADC and generate a digital output signal. The ASK demodulator circuit is configured to receive the digital output signal generated by the digital filter circuit.

[0022] According to another aspect of this specification, a method of operating a digital filter circuit or a system-on-chip according to one or more embodiments includes: receiving a digital input signal at an input terminal; applying a low-pass filter to the digital input signal to generate a first intermediate signal indicating an exponentially moving average of the digital input signal; subtracting the first intermediate signal from the digital input signal to generate a second intermediate signal; calculating the square of the second intermediate signal to generate a third intermediate signal; applying a low-pass filter to the third intermediate signal to generate a fourth intermediate signal indicating an exponentially moving average of the third intermediate signal; right-shifting the fourth intermediate signal to generate a fifth intermediate signal; and subtracting the fifth intermediate signal from the fourth intermediate signal to generate a digital output signal at an output terminal. Attached Figure Description

[0023] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0024] Figure 1 This is an example of a diagram of a wireless power transmission system;

[0025] Figure 2 yes Figure 1 Examples of circuit diagrams for some components of a wireless power transmission system device;

[0026] Figure 3 and Figure 4 It is a time diagram of the signal waveforms in the ASK demodulator circuit;

[0027] Figure 5 This is an example of a circuit block diagram of the main blocks of the processing chain in an ASK demodulator circuit.

[0028] Figure 6 This is an example of a circuit block diagram for a digital IIR DC tracking filter;

[0029] Figure 7 yes Figure 6 An example of a graph showing the magnitude of the transfer function of a digital IIR DC tracking filter;

[0030] Figure 8 This is an example of an operation block diagram that can be executed to calculate the exponential variance of a digital signal;

[0031] Figure 9 This is an example of an operation block diagram that can be executed to calculate the exponential variance of a digital signal;

[0032] Figure 10 This is an example of a circuit block diagram of an architecture for calculating the exponential variance of a digital filter according to one or more embodiments of this specification.

[0033] Figure 11 This is an example of a circuit block diagram of a folded architecture for calculating the exponential variance of a digital filter according to one or more embodiments of this specification.

[0034] Figure 12 It is applicable to one or more embodiments of this specification Figure 11 An example of a circuit block diagram for an improved digital IIR DC tracking filter; and

[0035] Figure 13 This is an example of a circuit block diagram including a digital filter IP block for calculating the exponential variance of a digital signal, according to one or more embodiments of this specification. Detailed Implementation

[0036] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or may be obtained by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0037] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in conjunction with that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more locations within this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0038] The titles and references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0039] In the accompanying drawings, unless the context otherwise indicates, the same parts or elements are indicated by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0040] It should be noted that digital signals x[n] The exponential average ( μ[n] ) and exponential variance ( σ 2 [n] or S[n] The equation is given by an equation that can be implemented using an Infinite Impulse Response (IIR) digital filter. To calculate the input signal... μ[n] and σ 2 [n] One or more embodiments may rely on the implementation of a low-area digital filter circuit, which may be referred to as an "IIR DC tracking filter".

[0041] The architecture of the digital IIR DC tracking filter 100 is as follows: Figure 6 The circuit block diagram is shown below. Filter 100 receives the input digital signal from ADC 102. x[n] (For example, a 16-bit signal). Optionally, filter 100 may include symbol expansion circuitry 103 that receives the input signal. x[n] And extend the signal x[n] The sign is changed to increase its bit length (e.g., from 16 bits to 32 bits), and a (copy) signal is generated. x'[n]The filter 100 includes a subtractor circuit 104, which subtracts signals from the signal... x'[n] Subtract the feedback signal from the output stage of filter 100. d2[n] (For example, a 32-bit signal) to generate a first intermediate signal s1[n] (For example, a 32-bit signal). In one or more embodiments where the sign extension circuit 103 is absent, the signal x[n] The signal is passed directly to the subtractor circuit 104, instead of being a signal. x'[n] .

[0042] Filter 100 includes adder circuit 106, which converts intermediate signals s1[n] Another feedback signal from another output stage of filter 100 d1[n] (For example, a 32-bit signal) are added together to produce a second intermediate signal. s2[n] (For example, a 32-bit signal). Optionally, filter 100 may include multiplexer circuitry 107 that receives an intermediate signal at a first input. s2[n] And receive the register initialization signal at the second input. init_stat (For example, a 32-bit signal). The multiplexer 107 is controlled by the control signal. init Control. The multiplexer 107 and associated initialization circuitry can be used to force the values ​​stored in the memory elements 108 of the filter circuit 100 to a desired initial state during the initial operation phase of the filter circuit 100.

[0043] If control signal init If asserted, the multiplexer 107 will initialize the register signal. init_stat Transmitted to its output as a signal s2'[n] (For example, a 32-bit signal), or if a control signal init If the assertion is cancelled, the multiplexer will convert the intermediate signal... s2[n] The signal is passed to its output. In one or more embodiments where the initialization circuit and multiplexer 107 are absent, the signal is passed directly. s2[n] Instead of signals s2'[n] The filter 100 includes a memory element 108 (e.g., a flip-flop FF) that receives a second intermediate signal. s2[n] (or s2'[n] ), stored signal s2[n] (or s2'[n] The value of ) is transmitted to its output according to the clock signal or enable signal of the filter circuit 100 (for ease of explanation, Figure 6 (Not visible in the middle).

[0044] The output of memory element 108 corresponds to the feedback signal passed to adder circuit 106. d1[n] The filter 100 includes a right shifter circuit 110 that receives signals from the memory element 108. d1[n], and shift control signals k (For example, a 4-bit signal), and by using the signal d1[n] Right shift by signal k The number of bits indicated by the decimal value is used to generate the signal. d2[n] For example, if the signal k Since it is a 4-bit signal, its value can be in the range of [0; 15], and therefore the shifter circuit 110 can shift the signal... d1[n] Shift the signal right by a minimum of 0 bits (i.e., no shift) to a maximum of 15 bits. Essentially, the operation of shifter circuit 110 corresponds to shifting the signal... d1[n] The decimal value multiplied by the quantity. α =2 -k (that is, divide by 2) k ) to calculate signals d2[n] The decimal value.

[0045] Optionally, the filter 100 includes a cutoff circuit 112 that receives signals. d2[n] It is then truncated (e.g., one or more bits starting from the least significant bit (LSB)) to reduce its bit length and produce the filter output signal. out[n] (For example, transferring from a 32-bit signal to a 16-bit signal). Therefore, the transfer function of the digital IIR DC tracking filter 100 can be written as follows:

[0046] Therefore, the filter circuit 100 implements an IIR (Infinite Impulse Response) structure based (only) on shift and addition / subtraction operations, thus saving a significant amount of area. For example, in one or more embodiments, when processing a 16-bit input signal, the area of ​​the filter 100 can be less than 1 kgate, with a clock frequency in the MHz range. The filter 100 can generate a cutoff frequency that varies with the signal... k The low-pass response decreases as the value of increases. In this regard, see [reference needed]. Figure 7 The graph shows the different values ​​from 0 to 14. k Value, based on normalized frequency f / ( f SThe magnitude of the transfer function of filter 100 (absolute value) is given by ( / 2) and is expressed in dB. The cutoff frequency can reach very low values; therefore, this filter can be used to calculate the DC value of the input signal.

[0047] It should be noted that, such as Figure 6 The IIR DC tracking filter 100 shown in the figure has an output out[n] The input signal was basically calculated at that point. x[n] The exponential average of the transfer function, which has a one-sample delay (see z in the numerator of the transfer function above). -1 (item), that is, in the input x[n] At a specific clock cycle, the i-th data sample is available; output... out[n] This represents the exponential mean calculated for the sample up to the (i-1)th sample.

[0048] It should also be noted that executable functions for calculating digital signals... x[n] exponential variance S[n] The operation sequence can be as follows Figure 8 The operation block diagram is shown below, which includes (only) a subtraction block, an addition block, and a memory block (which stores its input value in one clock cycle and releases its input value in the next clock cycle, and is represented as z). -1 ), shift block (corresponding to multiplying by 2 in the case of right shift) -k In the case of a left shift, this corresponds to multiplying by 2. k (and squared value blocks. The input signal is a digital data signal.) x [n] .

[0049] The first operation block includes a subtractor 202, an adder 204, a memory element 206, and a right shifter 208. It has two feedback loops: one from the output of memory element 206 to the input of adder 204, and the other from the output of right shifter 208 to the negative input of subtractor 202. The output values ​​of operations 202, 204, 206, and 208 are... μ[n-1] That is, it is equal to a signal with a delay of one sample. x[n] The exponential average. The second operation block uses... μ[n-1] As input, it includes a subtractor 210, a squarer 212, and a right shifter 214, which have a feedforward loop (from the input terminal to the positive input of the subtractor 210). The output values ​​of operations 210, 212, and 214 are... The third operation block uses As inputs, and including adder 216, subtractor 218, right shifter 220 in a feedforward loop from the output of adder 216 to the negative input of subtractor 218, and memory element 222 in a feedback loop from the output terminal to the input of adder 216. The output values ​​of operations 216, 218, 220, and 222 are signals. x[n] exponential variance S[n] .

[0050] It can be displayed. Figure 8 The operation sequence shown is equivalent to Figure 9 The operation sequence shown in the operation block diagram also includes (only) a subtraction block, an addition block, a memory block, a shift block, and a square value block, and also from the input digital signal. x[n] Start to generate exponential variance S[n] .

[0051] exist Figure 9 In the diagram, the input signal is a digital data signal. x[n] First operation block 21 and reference Figure 8 The first operation block discussed is identical and therefore includes subtractor 202, adder 204, memory element 206, and right shifter 208. The first operation block 21 has two feedback loops: one from the output of memory element 206 to the input of adder 204, and the other from the output of right shifter 208 to the negative input of subtractor 202. The output values ​​of operations 202, 204, 206, and 208 are... μ[n-1] That is, it is equal to the exponential average with a delay of one sample. The second operation block 22... μ[n-1] As input, and including subtractor 210 and squaring unit 212, the second operation block 22 has a feedforward loop (from the input terminal to the positive input of subtractor 210).

[0052] therefore, Figure 9 The second operation block 22 in the middle corresponds to Figure 8 The second operation block 22 is used, but it lacks a right shifter 214. Therefore, the output value of the second operation block 22 is ( x[n] - μ[n-1] ) 2 The third operation block 23 ( x[n] - μ[n-1] ) 2 As input, and including adder 224, memory element 226, right shifter 228, subtractor 230, and right shifter 232, as shown in the figure. Operation block 23 calculates the exponential average of the signal ( x[n] - μ[n-1] ) 2 The fourth operation block 24 calculates the exponential average of the signal (...). x[n] - μ[n-1] ) 2 As input, and including subtractor 234 and right shifter 236, right shifter 236 is in a feedforward loop from the output of right shifter 232 to the negative input of subtractor 234. Therefore, operation block 24 is equivalent to exponentially averaging the signal ( x[n] - μ[n-1] ) 2 Multiply by (1-2) k The output value of the fourth operation block 24 is a signal. x[n] exponential variance S[n] .

[0053] Since both operation blocks 21 and 23 are equivalent to calculating the exponential average of their respective input signals, one or more embodiments may rely on using a DC tracking filter 100 (e.g., as...). Figure 6 As shown, operations 21 and 23 are performed: In fact, it can be recalled that the DC tracking filter 100 calculates the exponential moving average (delayed by one sample). Since the IIR DC tracking filter 100 is used twice, the exponential variance... S[n] Relative to the input data signal x[n] It has a delay of one sample. Alternatively, one or more embodiments may rely on using a DC tracking filter 100 to perform operation block 21 (i.e., calculate the exponential average), and then perform... Figure 8 The remaining operations 210 to 222 are shown to calculate the exponential variance.

[0054] Therefore, one or more embodiments may depend on having Figure 10 The digital filter 300 shown in the circuit block diagram is used to calculate the signal. x[n] exponential variance S[n] The digital filter 300 includes a receiver for receiving data signals. x[n] The input terminal. In a first example 302 of the DC tracking filter circuit 100, the signal is received at the input. x[n] And generate a corresponding output signal. x1[n] to execute Figure 9 Operation block 21. Subtractor circuit 304 from signal x[n] Subtract signal x1[n] And generate a corresponding output signal (difference signal). x2[n] The square arithmetic circuit 306 receives signals at its input. x2[n] and generate signals x2[n] The corresponding output signal corresponding to the square value x3[n] It should be noted that circuits 304 and 306 perform... Figure 9 Operation block 22.

[0055] A second example 308 of the DC tracking filter circuit 100 receives a signal at the input. x3[n] And generate a corresponding output signal. x4[n] to execute Figure 9 Operation block 23. The right shifter circuit 310 receives signals at its input. x4[n] and will signal x4[n] Shift right by k bits (i.e., multiply by 2) -k To generate the corresponding output signal x5[n] The subtractor circuit 312 receives the signal... x4[n] Subtract signal x5[n] and generate signals x[n] exponential variance S[n] The corresponding output signal (difference signal). It should be noted that circuits 310 and 312 execute... Figure 9 Operation block 24. Optionally, the digital filter 300 may also include a right shifter circuit 314 that receives the exponential variance signal at its input. S[n] and will signal S[n] Shift right by M bits (i.e., multiply by 2) -M To generate an output signal This is an additional operation that exponentially increases the variance. S[n] Zoom 2 -M This allows the generation of output signals from hardware block 300 that can be represented with fewer bits.

[0056] Because the IIR DC tracking filter 100 is used twice (sequentially, in the exponential variance) S[n] (Two consecutive stages of computation), one or more embodiments may involve a folded architecture, such as Figure 11 The digital filter 300' shown in the circuit block diagram. The digital filter 300' includes a receiver for receiving data signals. x[n] The input terminal. Input signal x[n] It is passed to the first input of the multiplexer circuit 402, instead of like Figure 10 As in the embodiment, it is directly passed to the DC tracking filter circuit 100, the multiplexer circuit 402 being selected by the signal. sel_ph Control, and when sel_ph When ='0', a signal can be transmitted. x [n] The output of multiplexer circuit 402 is coupled to the input of (only) instance 302' of DC tracking filter circuit 100'.

[0057] The DC tracking filter circuit 100' is also relative to Figure 6 The DC tracking filter circuit 100 has been slightly improved, as will be referred to below. Figure 12As further described, but it performs essentially the same operation (i.e., calculates the exponential average of its input signal with a one-sample delay). The DC tracking filter circuit 100' receives the selection signal. sel_ph and two enable signals en_ff1 and en_ff2 Its operation will also refer to Figure 12 Describe it.

[0058] Signal sel_ph , en_ff1 and en_ff2 This can be generated by the control unit (CU) 404. The DC tracking filter circuit 100' generates a corresponding output signal, thereby performing the first stage. Figure 9 Operation block 21, therefore in this first stage, the output signal of DC tracking filter circuit 100' corresponds to Figure 10 signal x1[n] . Figure 11 The subtractor circuit 304 and the squarer circuit 306 in the architecture are as shown in the reference. Figure 10 The operation is performed as described in the embodiment. Note again that circuits 304 and 306 perform... Figure 9 Operation block 22. Signal from square arithmetic circuit 306. x3[n] It is passed to the second input of the multiplexer circuit 402, instead of as Figure 10 In the second instance 308 of the embodiment, the signal is passed to the DC tracking filter circuit 100 as in the previous embodiment. sel_ph When ='1', the multiplexer circuit 402 can then pass it to (only) instance 302' of the improved DC tracking filter circuit 100' for execution in the second stage. Figure 9 Operation block 23.

[0059] Therefore, in the second stage, the output signal of the DC tracking filter circuit 100' corresponds to Figure 10 signal x4[n] . Figure 11 The right shifter circuit 310, subtractor circuit 312, and optional right shifter circuit 314 in the architecture are as shown in the reference. Figure 10 The embodiments described herein operate to generate signals. x[n] The output signal corresponding to the exponential variance S[n] And optionally generate a scaling signal. Similarly, since the IIR DC tracking filter 100' is used twice, the exponential variance... S[n] Relative to the input data signal x[n] It has a delay of one sample.

[0060] Therefore, in Figure 11In the folded implementation, the IIR DC tracking filter circuit is used in both stages of each variance calculation. This filter uses 2... (N+1) bits, but for the first stage, N least significant bits are sufficient to calculate the result.

[0061] Figure 12 The diagram shows the applicability in Figure 11 Possible implementations of the improved IIRDC tracking filter circuit 100' operating in the folded architecture of the filter circuit 300' will now be described, primarily by emphasizing its similarity to... Figure 6 The differences in implementation are shown to avoid unnecessarily repeating much of this specification. Essentially, the improved IIR DC tracking filter circuit 100' includes two memory elements 108a and 108b (e.g., flip-flops) instead of a single memory element 108, and an additional multiplexer circuit 502 coupled between the memory elements 108a, 108b and the right shifter circuit 110. Both memory elements 108a, 108b receive their input signals from the output of the multiplexer 107 (or, in embodiments without a multiplexer, directly from the adder circuit 106).

[0062] Memory element 108a is enabled by an enable signal. en_ff1 Control and generate output signals d1a[n] The signal d1a [n] The first input of the multiplexer 502 is passed to the memory element 108b, and the memory element 108b is enabled by the information. en_ff2 Control and generate output signals d1b[n] The signal d1b[n] The signal is passed to the second input of multiplexer 502. Multiplexer 502 is powered by the signal. sel_ph Control, and send signals d1a[n] or signal d1b[n] As a signal d1[n] The signal is passed to the right shifter circuit 110. Therefore, in the first operating phase of the digital filter 300' (execution... Figure 9 In operation block 21), only the first memory element 108a is enabled (e.g., en_ff1 ='1', en_ff2 ='0'), and the multiplexer 502 is configured to convert the signal from its first input terminal into ... d1a[n] Passed to its output (e.g., sel_ph ='0'). Conversely, in the second operation phase of digital filter 300' (execution Figure 9 In operation block 23), only the second memory element 108b is enabled (e.g., en_ff1 ='0', en_ ff2 ='1'), and the multiplexer 502 is configured to convert the signal from its second input terminal into ... d1b[n] Passed to its output (e.g., sel_ph ='1').

[0063] Control unit 404 is configured to drive enable signal en_ff1 and en_ff2 and the selection signals for multiplexers 402 and 502 sel_ph To process the sequence of two computational stages. Enable signal. en_ff1 and en_ff2 It can also be used to access signals via multiplexer 107 init_stat To set the initial state of each memory element (note that, for ease of explanation, signals...) init exist Figure 12 It is not visible in the image, but can be operated in the improved IIR DC tracking filter circuit 100', such as... Figure 6 IIR DC trajectory filter circuit 100).

[0064] Figure 13 This is a circuit block diagram example of a possible integration of digital filter circuit 300 (or 300') in (reusable) IP block 600. Essentially, filter circuit 300 can provide a first output signal. S'[n] Second output signal μ[n] The first output signal S'[n] Signal indicating the output from right shifter circuit 314 x[n] The exponentially shifting variance (bit-scaled, with a one-sample delay) of the second output signal μ[n] Signal indicating the output of the first DC tracking filter 302 x[n] The exponential moving average (with a one-sample delay). IP block 600 may include additional circuitry, such as for storing the input signal. x[n] The memory element 602 (e.g., a flip-flop) stores the value of the input signal. x[n] Subtract the moving average signal from the stored value μ[n] The subtractor circuit 604 and the multiplexer circuit 606 are controlled by a user-selectable configuration register and configured to transmit signals from the output of the subtractor 210. x2[n] Or the signal output by subtractor 604.

[0065] Basically, signal x2[n] equal x[n] The difference between the output of the first instance of the IIR DC tracking filter 302 and the output of the filter 302. Since the output of filter 302 is cut off... x[n-1] All samples (i.e., in) x[n] The exponential average of all previous input samples, and therefore equivalent to the value at the cutoff point. x[n-1] The estimated DC value over all samples of the signal x2[n] This is equivalent to using the estimated DC value calculated on the previous input samples to adjust the signal. x[n] High-pass filtering is performed. On the other hand, the output of subtractor 604 is equivalent to being used in... x[n] The estimated DC value calculated on all input samples, including the signal x[n] High-pass filtering is performed (as long as the input signal is delayed by one sample by memory element 602). The output of multiplexer 606 is an indication signal. x[n] high-pass filtered signal hpf[n] In the calculation of the estimated DC value, it can be selected to include or exclude the last sample. x[n] .

[0066] In addition, IP block 600 may include a square root arithmetic unit circuit ( Figure 13 (Not visible in the image), this circuit receives the exponentially shifted variance at the input. S[n] And generate an indication signal. x[n] The signal of the exponential standard deviation is output. IP block 600 may include output multiplexer circuit 608, which outputs multiplexer circuit 608 according to the request of external circuitry and the selection signal. SEL Instructions, select signal S[n] , μ[n] and hpf[n] One of them (and possibly a signal indicating the standard deviation) is used as the output signal. y[n] .

[0067] Therefore, one or more embodiments may provide one or more of the following advantages: faster computation time for the exponential moving variance of a digital signal compared to known solutions based on firmware computation; lower silicon footprint compared to known hardware IP blocks dedicated to calculating the exponential moving variance; additional area savings even achieved through folding; reuse of proven IP blocks, namely the IIR DC tracking filter circuit 100; and provision of versatile hardware (e.g., IP block 600) capable of calculating various quantities associated with the input digital signal, such as the exponential moving average, exponential moving variance, high-pass function, and low-pass function.

[0068] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, from what has been described by example only, without departing from the scope of protection.

[0069] The scope of protection is determined by the appended claims.

Claims

1. A digital signal processing method, the method comprising: Receive digital input signals; A first infinite impulse response filtering operation is applied to the digital input signal to generate a first filtered signal; A mathematical transformation is performed on the combination of the digital input signal and the first filtered signal to generate a transformed signal; A second infinite impulse response filtering operation is applied to the transformed signal to generate a second filtered signal; A scaling operation is performed on the second filtered signal to generate a scaled signal; as well as The second filtered signal and the scaling signal are combined to produce a digital output signal that indicates the statistical characteristics of the digital input signal.

2. The method of claim 1, wherein applying the first infinite impulse response filtering operation comprises: A low-pass filter is applied to the digital input signal to generate a first filtered signal that indicates the exponential moving average of the digital input signal.

3. The method of claim 1, wherein performing the mathematical transformation comprises: The first filtered signal is subtracted from the digital input signal to generate the second intermediate signal; as well as The square of the second intermediate signal is calculated to generate the transformed signal.

4. The method of claim 1, wherein applying the second infinite impulse response filtering operation comprises: A low-pass filter is applied to the transformed signal to generate a second filtered signal that indicates the exponential moving average of the transformed signal.

5. The method of claim 1, wherein performing the scaling operation comprises: The second filtered signal is shifted to the right to generate the scaled signal.

6. The method of claim 1, wherein combining the second filtered signal and the scaled signal comprises: The scaling signal is subtracted from the second filtered signal to generate the digital output signal.

7. The method of claim 1, wherein applying the first infinite impulse response filtering operation comprises: The digital input signal is low-pass filtered to generate the first filtered signal; The mathematical transformation includes: subtracting the first filtered signal from the digital input signal to generate a second intermediate signal, and calculating the square of the second intermediate signal to generate the transformed signal; The application of the second infinite impulse response filtering operation includes: applying a low-pass filter to the transformed signal to generate a second filtered signal that indicates the exponential moving average of the transformed signal; Performing the scaling operation includes: right-shifting the second filtered signal to generate the scaling signal; and The combination of the second filtered signal and the scaling signal includes: subtracting the scaling signal from the second filtered signal to generate the digital output signal.

8. A digital filter circuit, comprising: The input terminal is configured to receive digital input signals; An output terminal is configured to provide a digital output signal that indicates the exponentially shifted variance of the digital input signal; A circuit is formed that constitutes a signal processing chain arranged between the input terminal and the output terminal, the signal processing chain being configured as follows: A low-pass filter is applied to the digital input signal to generate a first intermediate signal that indicates the exponential moving average of the digital input signal; The first intermediate signal is subtracted from the digital input signal to generate the second intermediate signal; Calculate the square of the second intermediate signal to generate the third intermediate signal; A low-pass filter is applied to the third intermediate signal to generate a fourth intermediate signal that indicates the exponential moving average of the third intermediate signal; Shift the fourth intermediate signal to the right to generate the fifth intermediate signal; as well as The fifth intermediate signal is subtracted from the fourth intermediate signal to generate the digital output signal.

9. The digital filter circuit of claim 8, wherein the signal processing chain is further configured to: right-shift the digital output signal to generate a bit-scaled digital output signal.

10. The digital filter circuit according to claim 8, wherein the signal processing chain further comprises: A multiplexer circuit having a first input configured to receive the digital input signal and a second input configured to receive the third intermediate signal, the multiplexer circuit being controlled by a selection signal to transmit the digital input signal in a first operation phase and to transmit the third intermediate signal in a second operation phase; An Infinite Impulse Response (IIR) filter block is coupled to the output of the multiplexer circuit and configured to: apply a low-pass filter to the digital input signal during the first operation phase to generate the first intermediate signal, and apply a low-pass filter to the third intermediate signal during the second operation phase to generate the fourth intermediate signal. A first subtractor circuit is coupled to the input terminal and the output of the IIR filter block, and is configured to subtract the first intermediate signal from the digital input signal to generate the second intermediate signal; A square operator circuit is coupled to the output of the first subtractor circuit and configured to: calculate the square value of the second intermediate signal to generate the third intermediate signal; A first right shifter circuit is coupled to the output of the IIR filter block and is configured to right-shift the fourth intermediate signal to generate the fifth intermediate signal. as well as The second subtractor circuit is coupled to the output of the IIR filter block and the output of the first right shifter circuit, and is configured to subtract the fifth intermediate signal from the fourth intermediate signal to generate the digital output signal.

11. The digital filter circuit of claim 10, further comprising a second right shifter circuit coupled to the output of the second subtractor circuit and configured to right-shift the digital output signal to produce a bit-scaled digital output signal.

12. The digital filter circuit according to claim 10, wherein the IIR filter block comprises: The subtractor circuit is configured to subtract an internal first feedback signal from the input signal of the IIR filter block to generate a first IIR intermediate signal; The adder circuit is configured to add the first IIR intermediate signal and the internal second feedback signal to generate a second IIR intermediate signal; A first memory element is configured to selectively receive the second IIR intermediate signal and, in response to a first enable signal being asserted, pass the second IIR intermediate signal to the output of the first memory element to generate a corresponding second feedback signal, the first enable signal being asserted during the first operation phase. The second memory element is configured to selectively receive the second IIR intermediate signal and, in response to a second enable signal being asserted, pass the second IIR intermediate signal to the output of the second memory element to generate a corresponding second feedback signal, the second enable signal being asserted during the second operation phase. Another multiplexer circuit is configured to receive the second feedback signal from the first memory element and the second memory element, the other multiplexer circuit being controlled by the selection signal to transmit the second feedback information from the first memory element during the first operation phase, and to transmit the second feedback information from the second memory element during the second operation phase. as well as The right shifter circuit is configured to right-shift the digital output signal from the other multiplexer circuit by the number of bits indicated by the shift control signal to generate the internal first feedback signal.

13. The digital filter circuit of claim 12, wherein the IIR filter block further comprises: A sign extension circuit is arranged between the corresponding input terminal and the subtractor circuit, and is configured to increase the number of bits of the corresponding input signal before passing the corresponding input signal to the subtractor circuit; as well as A cutoff circuit is arranged between the corresponding right shifter circuit and the corresponding output terminal, and is configured to cut off the number of bits of the internal first feedback signal before passing the internal first feedback signal to the corresponding output terminal.

14. The digital filter circuit according to claim 12, wherein the IIR filter block comprises: A third multiplexer circuit is arranged between the output of the adder circuit and the input of the first memory element and the input of the second memory element. The third multiplexer circuit is controlled by a control signal to transmit the second IIR intermediate signal or register initialization signal to the first memory element or the second memory element.

15. A system-on-a-chip, comprising: Analog-to-digital converter; According to claim 8, the input terminal of the digital filter circuit is coupled to the output of the analog-to-digital converter; as well as The ASK demodulator circuit has an input coupled to the output terminal of the digital filter circuit.

16. A digital filter circuit, comprising: The input terminal is configured to receive digital input signals; A first infinite impulse response (IIR) filter block is coupled to the input terminal and configured to apply a low-pass filter to the digital input signal to generate a first intermediate signal. A first subtractor circuit is coupled to the input terminal and the output of the first IIR filter block, and is configured to subtract the first intermediate signal from the digital input signal to generate a second intermediate signal. A square operator circuit is coupled to the output of the first subtractor circuit and configured to: calculate the square of the second intermediate signal to generate a third intermediate signal; The second IIR filter block is coupled to the output of the square arithmetic circuit and is configured to apply a low-pass filter to the third intermediate signal to generate a fourth intermediate signal. A first right shifter circuit is coupled to the output of the second IIR filter block and is configured to right shift the fourth intermediate signal to generate a fifth intermediate signal. as well as The second subtractor circuit, coupled to the output of the second IIR filter block and the output of the first right shifter circuit, is configured to subtract the fifth intermediate signal from the fourth intermediate signal to produce a digital output signal indicating the exponential shift variance of the digital input signal.

17. The digital filter circuit of claim 16, further comprising a second right shifter circuit coupled to the output of the second subtractor circuit and configured to right-shift the digital output signal to produce a bit-scaled digital output signal.

18. The digital filter circuit of claim 16, wherein the first IIR filter block and the second IIR filter block each comprise: The subtractor circuit is configured to subtract the corresponding internal first feedback signal from the corresponding input signal to generate the corresponding first IIR intermediate signal; The adder circuit is configured to add the corresponding first IIR intermediate signal and the corresponding internal second feedback signal to generate the corresponding second IIR intermediate signal; The memory element is configured to selectively receive a corresponding second IIR intermediate signal, and in response to an enable signal being asserted, to pass the corresponding second IIR intermediate signal to the output of the memory element to generate a corresponding second feedback signal; as well as The right shifter circuit is configured to shift the corresponding second feedback signal to the right by the number of bits indicated by the shift control signal to generate the corresponding internal first feedback signal.

19. The digital filter circuit of claim 18, wherein the first IIR filter block and the second IIR filter block each further include: A sign extension circuit is arranged between the corresponding input terminal and the subtractor circuit, and is configured to increase the number of bits of the corresponding input signal before passing the corresponding input signal to the subtractor circuit; as well as A cutoff circuit is arranged between the corresponding right shifter circuit and the corresponding output terminal, and is configured to cut off the number of bits of the corresponding internal first feedback signal before passing the corresponding internal first feedback signal to the corresponding output terminal.

20. The digital filter circuit of claim 18, wherein the first IIR filter block and the second IIR filter block each include a multiplexer circuit disposed between the output of the adder circuit and the input of the memory element, the multiplexer circuit being controlled by a control signal to pass a corresponding second IIR intermediate signal or register initialization signal to the memory element.

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