Ring oscillator

Abstract

The invention discloses a ring oscillator, which comprises a control unit used for responding to an external control voltage and generating a corresponding bias current; the output end of the oscillation unit of the last stage connected in series is connected with the input end of the oscillation unit of the first stage to form an annular structure; the oscillation unit is used for working in a current limited state under the action of the bias current and performing phase inversion and delay processing on an input signal to generate an oscillation signal; by continuously adjusting the external control voltage, the bias current and the time delay of the oscillation unit are changed, and then continuous adjustment of the frequency of the output oscillation signal is achieved. Provided is a ring oscillator capable of linearly and finely tuning an oscillation frequency with low power consumption and high stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a ring oscillator. Background Technology

[0002] Ring oscillators are widely used in clock generation circuits in integrated circuits due to their simple structure and ease of integration. Traditional ring oscillators typically consist of an odd number of inverters connected in series to form a closed loop, and oscillation is achieved through the delay of the inverter chain.

[0003] However, existing ring oscillators have the following drawbacks and problems: (1) The frequency stability is poor and it is easily affected by process deviations, power supply noise and temperature changes; (2) High power consumption, especially in high-frequency applications, which is not conducive to low-power design; (3) Poor linearity when adjusting frequency.

[0004] Therefore, it is necessary to improve the existing ring oscillator circuit. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a ring oscillator that can linearly tune the resonant oscillation frequency with low power consumption and high stability.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide a ring oscillator, comprising: The control unit is used to generate a corresponding bias current in response to an external control voltage; and An odd number of oscillating units are connected in series, and the output terminal of the last oscillating unit in the series connection is connected to the input terminal of the first oscillating unit to form a ring structure; the oscillating unit is used to operate in a current-limited state under the action of the bias current, and to perform inversion and transmission delay processing on the input signal to generate an oscillating signal; By continuously adjusting the external control voltage, the bias current and the propagation delay of the oscillation unit are changed, thereby achieving continuous tuning of the frequency of the output oscillation signal.

[0007] Furthermore, the oscillation unit includes: A bias circuit is used to receive the bias current and provide a current-starved operating point for the inverter. An inverter is used to invert and delay the input signal at the current-starved operating point.

[0008] Furthermore, the control unit includes a fifth MOSFET M5 and a sixth MOSFET M6; the gate of the fifth MOSFET M5 is connected to an external control voltage, the source of the fifth MOSFET M5 is grounded, the drain of the fifth MOSFET M5 is electrically connected to the drain of the sixth MOSFET M6, the gate of the sixth MOSFET M6 is electrically connected to the drain of the sixth MOSFET M6, and the source of the sixth MOSFET M6 is connected to the power supply VDD.

[0009] Furthermore, the bias circuit includes a first MOSFET M1 and a fourth MOSFET M4; the gate of the first MOSFET M1 is electrically connected to the gate of the fifth MOSFET M5, the source of the first MOSFET M1 is grounded, and the drain of the first MOSFET M1 is electrically connected to the first power supply terminal of the inverter; the gate of the fourth MOSFET M4 is electrically connected to the gate of the sixth MOSFET M6, the source of the fourth MOSFET M4 is connected to the power supply VDD, and the drain of the fourth MOSFET M4 is electrically connected to the second power supply terminal of the inverter.

[0010] Furthermore, the inverter includes a second MOSFET M2 and a third MOSFET M3; the source of the second MOSFET M2 serves as the first power supply terminal of the inverter and is electrically connected to the drain of the first MOSFET M1, and the drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3; the source of the third MOSFET M3 serves as the second power supply terminal of the inverter and is electrically connected to the drain of the fourth MOSFET M4; the gate of the second MOSFET M2 is electrically connected to the gate of the third MOSFET M3 as the input terminal of the inverter to receive the input signal; and the drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3 as the output terminal of the inverter to output the signal to the next stage inverter.

[0011] Furthermore, the first MOSFET M1, the second MOSFET M2, and the fifth MOSFET are all NMOS transistors; the third MOSFET M3, the fourth MOSFET M4, and the sixth MOSFET M6 are all PMOS transistors.

[0012] Furthermore, it also includes an output buffer, the input of which is electrically connected to the output of the last stage oscillation unit, for shaping and driving the output oscillation signal.

[0013] Furthermore, the MOSFETs in the ring oscillator are all fabricated using FinFET technology.

[0014] Furthermore, the number of oscillation units is five.

[0015] Furthermore, the method for continuously tuning the frequency of the output oscillation signal by adjusting the external control voltage to change the bias current and the propagation delay of the oscillation unit includes: when the external control voltage is increased, the bias current increases, the propagation delay of the oscillation unit decreases, and the frequency of the oscillation signal increases; when the external control voltage is decreased, the bias current decreases, the propagation delay of the oscillation unit increases, and the frequency of the oscillation signal decreases.

[0016] The ring oscillator of this invention has at least the following beneficial effects: This invention employs a current starvation mechanism, linearly adjusting the bias current through an external control voltage, thereby precisely controlling the propagation delay of each inverter stage, ultimately achieving continuous and fine-tuning of the output frequency. This fundamentally avoids the inherent contradiction of the discrete transistor dimensions in FinFET technology, which prevents precise frequency fine-tuning through geometric dimensions. FinFET's superior gate control capability and steep subthreshold slope make the external control voltage's control of the bias current extremely precise and sensitive, ensuring the linearity and resolution of frequency tuning. Furthermore, the current starvation mechanism actively limits the dynamic operating current, which, combined with the low static power consumption characteristics of FinFET, significantly reduces overall power consumption while achieving high-frequency oscillation, achieving a balance between high performance, low power consumption, and high stability. Simultaneously, the FinFET process enhances the ring oscillator's robustness to process fluctuations and temperature changes, resulting in a more stable output frequency. The clock frequency can be continuously adjusted over a wide range through a single analog voltage port, overcoming the limitations of traditional one-time design methods that involve changing the number of stages or dimensions. This allows the ring oscillator to dynamically adapt to different performance modes or application scenarios during operation, greatly improving flexibility. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram of one embodiment of the ring oscillator of the present invention. Detailed Implementation The invention will now be further described with reference to the accompanying drawings.

[0018] In this ring oscillator design, all MOSFETs are fabricated using FinFET technology, specifically a 12nm FinFET process. FinFET technology offers superior gate control, extremely low leakage current, and higher current drive efficiency. These characteristics make it an essential choice for realizing low-power, high-performance integrated circuits. However, FinFET technology also introduces new constraints to traditional ring oscillator design methods: in FinFET, the effective width of a transistor is determined by the number of fins and the number of fingers, and the layout generally requires that the number of fins not be less than 4. This means that the transistor width is a discrete value. For example, if the unit fin width is approximately 250nm, then the width achievable by adjusting the number of fingers could be 250nm, 500nm, 750nm, etc., but not an arbitrary value like 350nm. Therefore, some dimensions of MOSFETs in FinFET technology cannot be achieved through manual adjustment. If the theoretically optimal width is calculated to be 350nm, it cannot be precisely achieved in the actual layout; only nearby discrete values ​​(such as 250nm or 500nm) can be selected. This directly leads to the oscillation frequency deviating from the design target and makes fine-tuning impossible. Traditional ring oscillators require adjusting the size of the internal inverters (and transistors) or the number of internal inverter stages to regulate the frequency of the output oscillation signal. As discussed above, it is impossible to adjust the frequency by adjusting the size of the internal inverters in FinFET technology. Adjusting the frequency of the output oscillation signal by adjusting the number of internal inverter stages results in abrupt changes in chip area, power consumption, and phase noise characteristics, making smooth performance optimization impossible. Both existing adjustment methods are determined once during manufacturing and cannot be dynamically adjusted during chip operation. Therefore, this invention proposes a ring oscillator with linearly and finely tuned oscillation frequency in FinFET technology. Please see Figure 1 One embodiment of the ring oscillator of the present invention includes a control unit 100 and an odd number of oscillating units 200 connected in series, wherein the output terminal of the last oscillating unit 200 connected in series is connected to the input terminal of the first oscillating unit 200, forming a ring structure. In this embodiment, the number of oscillating units 200 is 5. It should be understood that the number of oscillating units 200 can be any odd number, for example, 3, 7, etc. The control unit 100 is used to respond to an external control voltage V. ctrlThe oscillation unit 200 generates a corresponding bias current. Under the influence of the bias current, the oscillation unit 200 operates in a current-limited state and performs inversion and propagation delay processing on the input signal to generate an oscillation signal. The oscillation unit 200 includes a bias circuit 210 and an inverter 220. The bias circuit 210 receives the bias current and provides a current-starved operating point for the inverter 220. The inverter 220 performs inversion and propagation delay processing on the input signal under the current-starved operating point. The current-limited state refers to the maximum current that the inverter 220 can obtain under normal operation being actively and forcibly limited by the bias circuit 210 to a value controlled by an external voltage V. ctrl Under controlled current values, by connecting the bias circuit 210 in series with the inverter 220, the bias circuit 210 acts as a current valve, thereby precisely clamping the current flowing through the inverter 220 according to the magnitude of the bias current, achieving current starvation.

[0019] The application of the current starvation mechanism has the following advantages: it enables fine and linear tuning of the oscillation frequency, since the propagation delay of the inverter 220 depends on its operating current; limiting the current to a low level can significantly reduce the dynamic power consumption of the system; stabilizing the current at a controlled value can reduce the impact of transistor process deviations and environmental fluctuations, and improve the frequency stability of the output oscillation signal and its immunity to power supply noise.

[0020] This invention achieves this by continuously adjusting the external control voltage V ctrl The magnitude of the bias current can be changed, thereby linearly adjusting the propagation delay of the oscillation unit 200, ultimately achieving continuous and fine tuning of the output oscillation signal frequency. Specifically, the adjustment method is as follows: when the external control voltage V is increased... ctrl When the bias current increases, the propagation delay of the oscillation unit 200 decreases, and the frequency of the oscillation signal increases; when the external control voltage V decreases... ctrl When the bias current decreases, the transmission delay of the oscillation unit 200 increases, and the frequency of the oscillation signal decreases.

[0021] The transmission delay mentioned in this embodiment refers to the delay time required for the signal to pass through the first-stage inverter 220. In this scheme, the external control voltage V ctrl By setting a bias current, the propagation delay is limited; a smaller bias current results in a longer delay, and a larger bias current results in a shorter delay. This successfully transforms the delay of each inverter stage 220 from an uncontrollable value determined by process and temperature into a value that can be controlled by an external voltage V. ctrl The variable is controlled linearly, precisely, and continuously. This is achieved by adjusting the external control voltage V. ctrlBy adjusting the generated bias current, the transmission delay of the oscillation unit 200 can be controlled linearly and precisely, thereby controlling the frequency of the oscillation signal. Specifically, the control unit 100 includes a fifth MOSFET M5 and a sixth MOSFET M6. The gate of the fifth MOSFET M5 is connected to an external control voltage V. ctrl The source of the fifth MOSFET M5 is grounded, the drain of the fifth MOSFET M5 is electrically connected to the drain of the sixth MOSFET M6, the gate of the sixth MOSFET M6 is electrically connected to the drain of the sixth MOSFET M6, and the source of the sixth MOSFET M6 is connected to the power supply VDD. The fifth MOSFET M5 is an NMOS transistor, and the sixth MOSFET M6 is a PMOS transistor.

[0022] The bias circuit 210 includes a first MOSFET M1 and a fourth MOSFET M4. The gate of the first MOSFET M1 is electrically connected to the gate of the fifth MOSFET M5, the source of the first MOSFET M1 is grounded, and the drain of the first MOSFET M1 is electrically connected to the first power supply terminal of the inverter 220. The gate of the fourth MOSFET M4 is electrically connected to the gate of the sixth MOSFET M6, the source of the fourth MOSFET M4 is connected to the power supply VDD, and the drain of the fourth MOSFET M4 is electrically connected to the second power supply terminal of the inverter 220. The first MOSFET M1 is an NMOS transistor, and the fourth MOSFET M4 is a PMOS transistor.

[0023] The inverter 220 includes a second MOSFET M2 and a third MOSFET M3. The source of the second MOSFET M2 serves as the first power supply terminal of the inverter 220 and is electrically connected to the drain of the first MOSFET M1. The drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3. The source of the third MOSFET M3 serves as the second power supply terminal of the inverter 220 and is electrically connected to the drain of the fourth MOSFET M4. The gates of the second MOSFET M2 and the third MOSFET M3 are electrically connected, serving as the input terminal of the inverter 220 to receive the input signal. The drains of the second MOSFET M2 and the third MOSFET M3 are electrically connected, serving as the output terminal of the inverter 220 to output the signal to the next stage inverter 220. The second MOSFET M2 is an NMOS transistor, and the third MOSFET M3 is a PMOS transistor.

[0024] In a preferred embodiment, an output buffer 300 is also provided. The input terminal of the output buffer 300 is electrically connected to the output terminal of the last stage oscillation unit 200, and is used to shape and drive the output oscillation signal.

[0025] This invention employs a current starvation mechanism, linearly adjusting the bias current through an external control voltage to precisely control the propagation delay of each inverter stage, ultimately achieving continuous and fine-tuning of the output frequency. This fundamentally avoids the inherent contradiction of FinFET technology, where discrete transistor dimensions prevent precise frequency fine-tuning through geometric dimensions. FinFET's superior gate control capability and steep subthreshold slope make the external control voltage's control of the bias current extremely precise and sensitive, ensuring the linearity and resolution of frequency tuning. Furthermore, the current starvation mechanism actively limits the dynamic operating current, which, combined with FinFET's low static power consumption, significantly reduces overall power consumption while achieving high-frequency oscillation, achieving a balance between high performance, low power consumption, and high stability. Simultaneously, FinFET technology enhances the ring oscillator's robustness to process fluctuations and temperature changes, resulting in a more stable output frequency. The clock frequency can be continuously adjusted over a wide range through a single analog voltage port, overcoming the limitations of traditional one-time design methods that involve changing the number of stages or dimensions. This allows the ring oscillator to dynamically adapt to different performance modes or application scenarios during operation, greatly improving flexibility.

[0026] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A ring oscillator, characterized in that, include: The control unit is used to generate a corresponding bias current in response to an external control voltage; as well as An odd number of oscillating units are connected in series, and the output terminal of the last oscillating unit in the series connection is connected to the input terminal of the first oscillating unit to form a ring structure; the oscillating unit is used to operate in a current-limited state under the action of the bias current, and to perform inversion and transmission delay processing on the input signal to generate an oscillating signal; By continuously adjusting the external control voltage, the bias current and the propagation delay of the oscillation unit are changed, thereby achieving continuous tuning of the frequency of the output oscillation signal.

2. The ring oscillator as described in claim 1, characterized in that, The oscillation unit includes: A bias circuit is used to receive the bias current and provide a current-starved operating point for the inverter. An inverter is used to invert and delay the input signal at the current-starved operating point.

3. The ring oscillator as described in claim 2, characterized in that: The control unit includes a fifth MOSFET M5 and a sixth MOSFET M6; the gate of the fifth MOSFET M5 is connected to an external control voltage, the source of the fifth MOSFET M5 is grounded, the drain of the fifth MOSFET M5 is electrically connected to the drain of the sixth MOSFET M6, the gate of the sixth MOSFET M6 is electrically connected to the drain of the sixth MOSFET M6, and the source of the sixth MOSFET M6 is connected to the power supply VDD.

4. The ring oscillator as described in claim 3, characterized in that: The bias circuit includes a first MOSFET M1 and a fourth MOSFET M4; the gate of the first MOSFET M1 is electrically connected to the gate of the fifth MOSFET M5, the source of the first MOSFET M1 is grounded, and the drain of the first MOSFET M1 is electrically connected to the first power supply terminal of the inverter; the gate of the fourth MOSFET M4 is electrically connected to the gate of the sixth MOSFET M6, the source of the fourth MOSFET M4 is connected to the power supply VDD, and the drain of the fourth MOSFET M4 is electrically connected to the second power supply terminal of the inverter.

5. The ring oscillator as described in claim 4, characterized in that: The inverter includes a second MOSFET M2 and a third MOSFET M3; the source of the second MOSFET M2 serves as the first power supply terminal of the inverter and is electrically connected to the drain of the first MOSFET M1, and the drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3; the source of the third MOSFET M3 serves as the second power supply terminal of the inverter and is electrically connected to the drain of the fourth MOSFET M4; the gate of the second MOSFET M2 is electrically connected to the gate of the third MOSFET M3 as the input terminal of the inverter to receive the input signal; and the drain of the second MOSFET M2 is electrically connected to the drain of the third MOSFET M3 as the output terminal of the inverter to output the signal to the next stage inverter.

6. The ring oscillator as described in claim 5, characterized in that: The first MOSFET M1, the second MOSFET M2, and the fifth MOSFET are all NMOS transistors; the third MOSFET M3, the fourth MOSFET M4, and the sixth MOSFET M6 are all PMOS transistors.

7. The ring oscillator as described in claim 1, characterized in that: It also includes an output buffer, the input of which is electrically connected to the output of the last stage oscillation unit, for shaping and driving the output oscillation signal.

8. The ring oscillator as claimed in claim 1, characterized in that: The MOSFETs in the ring oscillator are all fabricated using FinFET technology.

9. The ring oscillator as claimed in claim 1, characterized in that: The number of oscillation units is five.

10. The ring oscillator as claimed in claim 1, characterized in that, The method for continuously tuning the frequency of the output oscillation signal by continuously adjusting the external control voltage to change the bias current and the propagation delay of the oscillation unit includes: when the external control voltage is increased, the bias current increases, the propagation delay of the oscillation unit decreases, and the frequency of the oscillation signal increases; when the external control voltage is decreased, the bias current decreases, the propagation delay of the oscillation unit increases, and the frequency of the oscillation signal decreases.

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