Flip-flop with multiple data retention paths

Abstract

The invention relates to a flip-flop with multiple data retention paths. The disclosed D flip-flop includes a first stage and a second stage. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a transistor pair connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of the different transistors in the pair to provide feed-forward and feedback paths when the clock signal is static and the second intermediate node is floating to maintain the voltage level of the signal on the second intermediate node. Optionally, the second stage may also include a feedback loop (including an inverter and a multiphase clocked tri-state logic device connected in series from and back to the third intermediate node) to maintain a voltage level of the signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.

Description

Technical Field

[0001] This disclosure relates to trigger circuits, and more particularly to embodiments of area-reduced, low-power trigger circuits suitable for both high-frequency and low-frequency clock-controlled operations. Background Technology

[0002] Various types of circuit structures (e.g., memory circuits, counters, shift registers, etc.) employ data flip-flops. Data flip-flops are also known in the art as delay flip-flops, D-type flip-flops, or D flip-flops, and will be referred to as D flip-flops below. A D flip-flop is a circuit configured to receive a data input (D), temporarily store the data, and subsequently output a data output (Q) reflecting D and / or an inverted data output (Qb) relative to the inversion of D. D flip-flop processing is controlled by a clock input (CK) and is typically edge-triggered. For example, a D flip-flop can be configured such that Q switches only when CK transitions from low to high to reflect the current value of D. Therefore, when CK transitions from low to high, Q will switch to reflect the current value D. When CK transitions from high back to low, Q should hold the current value of D. D flip-flops are relatively large (e.g., including 24 transistors), consume a lot of power, and require the use of a constant frequency CK and multiple versions of CK (i.e., multiple phases of CK). Recently, D flip-flops have been developed that rely on a single-phase CK and are smaller, faster, and consume less power than conventional D flip-flops. However, these D flip-flops require CK to be dynamic (e.g., toggling at a constant frequency) to avoid data loss. That is, if CK remains static for an extended period, the stored data may be lost. Summary of the Invention

[0003] Embodiments of the disclosed trigger may include a first stage and a second stage. The first stage may have a first intermediate node. The second stage may be connected to the first stage and may include a second intermediate node and a third intermediate node. The second stage may also include a pair of node-controlled transistors connected in series between a voltage rail and the second intermediate node. The first intermediate node of the first stage and the third intermediate node of the second stage may be connected to the gates of different node-controlled transistors in the pair.

[0004] More specifically, in some embodiments disclosed herein, a trigger may include a first stage and a second stage. The first stage may include a first intermediate node. The second stage may be connected to the first stage and may include a second intermediate node and a third intermediate node. The second stage may also include a pair of node-controlled transistors (e.g., P-type field-effect transistors (PFETs)) connected in series between a positive voltage rail and the second intermediate node. The first intermediate node of the first stage and the third intermediate node of the second stage may be connected to the gates of different node-controlled transistors in the pair.

[0005] In other embodiments disclosed herein, a trigger may include a first stage and a second stage. The first stage may include a first intermediate node. The second stage may be connected to the first stage and may include a second intermediate node and a third intermediate node. The second stage may also include a pair of node-controlled transistors (e.g., N-type field-effect transistors (NFETs)) connected in series between the second intermediate node and a ground rail. The first intermediate node of the first stage and the third intermediate node of the second stage may be connected to the gates of different node-controlled transistors in the pair.

[0006] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the foregoing summary can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary section, can be combined to form embodiments not specifically described herein. Details of one or more embodiments are set forth in the drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0007] This disclosure will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0008] Figure 1 This is a schematic diagram illustrating an embodiment of the disclosed D flip-flop;

[0009] Figure 2 It is shown Figure 1 A table showing the different possible states of a node in a D flip-flop when energized;

[0010] Figure 3 This indicates when the clock signal (CKM) is low and then goes high. Figure 1 The table shows four example ADs of the possible states of the nodes in the D flip-flop, and also shows four additional example EHs of the possible states of these nodes when CKM is high and then goes low.

[0011] Figure 4 This shows the use of high-frequency CKM. Figure 1 Timing diagram of the operation of the D flip-flop;

[0012] Figure 5 This indicates the use of low-frequency CKM. Figure 1 The timing diagram of the operation of the D flip-flop; and

[0013] Figure 6 This is a schematic diagram illustrating another embodiment of the disclosed D flip-flop. Detailed Implementation

[0014] As described above, a D flip-flop is a circuit configured to receive a data input (D), temporarily store the data, and subsequently output a data output (Q) reflecting D and / or an inverted data output (Qb) relative to the inversion of D. The processing of a D flip-flop is controlled by a clock input (CK) and is typically edge-triggered. For example, a D flip-flop can be configured such that Q switches only when CK transitions from low to high to reflect the current value of D. Therefore, when CK transitions from low to high, Q will switch to reflect the current value D. When CK transitions back from high to low, Q should maintain the current value of D. D flip-flops are relatively large (e.g., including 24 transistors), consume a significant amount of power, and require the use of a constant frequency CK and multiple versions of CK (i.e., multiple phases of CK). Recently, D flip-flops have been developed that rely on a single-phase CK and are smaller, faster, and consume less power than conventional D flip-flops. However, these D flip-flops require CK to be dynamic (e.g., switching at a constant frequency) to avoid data loss. That is, if CK remains static for an extended period, the stored data may be lost.

[0015] In view of the above, this document discloses embodiments of D flip-flops that are smaller, faster, and consume less power than conventional D flip-flops, and are configured with a combination of data retention paths (including feedforward paths, feedback paths, and feedback loops) to prevent data loss when the clock signal controlling the operation of the flip-flop remains static for an extended period and the data input signal (D) changes state. More specifically, in the disclosed embodiments, the D flip-flop includes a first stage and a second stage. Among other components, the first stage may also include a first intermediate node (also referred to herein as a precharge node). The second stage may be connected to the first stage and, among other components, may also include a second intermediate node (also referred to herein as a data transfer node) and a third intermediate node (also referred to herein as a data retention node). The second stage may also include a pair of transistors connected in series between the second intermediate node and a positive voltage rail or ground rail (depending on the embodiment) and controlled by signal voltage levels on the first and third intermediate nodes. That is, the first and third intermediate nodes may be connected to the gates of different transistors in the pair to provide feedforward and feedback paths to maintain the voltage level of the signal on the second intermediate node when the clock signal controlling the operation of the flip-flop is static and the second intermediate node is floating.

[0016] Optionally, the second stage may further include a feedback loop (comprising an inverter and a multi-phase clocked tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of the signal on the third intermediate node when the clock signal is static and the third intermediate node is floating. It should be noted that in the disclosed embodiments, except in the feedback loop, the operation of the D flip-flop may be controlled by a single-phase clock signal, and in the feedback loop, the multi-phase clocked tri-state logic device may be controlled by both the clock signal and the inverted clock signal, as discussed in more detail below.

[0017] More specifically, Figure 1 This is a schematic diagram illustrating an embodiment of a D flip-flop 100. The D flip-flop 100 may include a first stage (S1) (also referred to herein as the input stage or primary stage) and a second stage (S2) connected to S1 (also referred herein as the output stage or secondary stage).

[0018] S1 may include a data input node 115, which is electrically connected to receive a data input (D). S1 may also include a first single-phase clocked tri-state logic device 110 (referred to herein as the first SPCTSL). For the purposes of this disclosure, a single-phase clocked tri-state logic device is a tri-state logic device that outputs a signal that is high (i.e., logic 1, e.g., at VDD), low (i.e., logic 0, preferably at ground or 0.0V), or floating, depending on the state of a single clock signal and the input signal. A multi-phase clocked tri-state logic device is a tri-state logic device that outputs a signal that is high (i.e., logic 1), low (i.e., logic 0), or floating, depending on the state of at least two clock signals (e.g., a clock signal and an inverted clock signal) and the input signal. The first SPCTSL 110 may include a stack of first transistors including a first P-type field-effect transistor (PFET) 111, an additional first PFET 112, and a first N-type field-effect transistor (NFET) 113 electrically connected in series between a positive voltage rail 199 at a positive supply voltage (VDD) level and a ground rail 198 (e.g., at 0.0 volts (V)). In some embodiments, VDD may be 0.8V. Alternatively, VDD may be at any other suitable positive supply voltage level (e.g., the processing technology node of a given design trigger). The gate 111g of the first PFET 111 and the gate 113g of the first NFET 113 may be electrically connected to the data input node 115 to receive D. The gate 112g of the additional first PFET 112 may be electrically connected to receive a clock signal (CKM) from a clock signal generator 101 (also referred to herein as a clock generation circuit), as discussed in more detail below. The first SPCTSL 110 may also include a first intermediate node 116 located at the junction between the additional first PFET 112 and the first NFET 113 (i.e., at the electrical connection between the additional first PFET 112 and the first NFET 113). A first intermediate signal (I1) may be output at the first intermediate node 116. The state of I1 may be high, low, or floating, depending on the states of D and CKM.

[0019] S2 may include a second single-phase clocked tri-state logic device 120 (hereinafter referred to as the second SPCTSL). The second SPCTSL 120 may include a stack of second transistors, the stack including a second PFET 121, a second NFET 123, and an additional second NFET 124 electrically connected in series between a positive voltage rail 199 and a ground rail 198. The gate 121g of the second PFET 121 and the gate 124g of the additional second NFET 124 may be electrically connected to receive CKM. The gate 123g of the second NFET 123 may be electrically connected to a first intermediate node 116 to receive I1. The second SPCTSL 120 may also include a second intermediate node 126 located at the junction between the second PFET 121 and the second NFET 123 (i.e., at the electrical connection between the second PFET 121 and the second NFET 123). A second intermediate signal (I2) may be output at the second intermediate node 126, and the state of I2 may be high, low, or floating, depending on the states of I1 and CKM.

[0020] S2 may also include a third single-phase clocked tri-state logic device 130 (hereinafter referred to as the third SPCTSL). The third SPCTSL 130 may include a third PFET 131, a third NFET 133, and an additional third NFET 134 connected in series between the positive voltage rail 199 and the ground rail 198. The gate 131g of the third PFET 131 and the gate 134g of the additional third NFET 134 may be electrically connected to the second intermediate node 126 to receive I2. The gate 133g of the third NFET 133 may be electrically connected to receive CKM. The third SPCTSL 130 may also include a third intermediate node 136 located at the junction between the third PFET 131 and the third NFET 133 (i.e., at the electrical connection between the third PFET 131 and the third NFET 133). A third intermediate signal (I3) may be output at the third intermediate node 136, and the state of I3 may be high, low, or floating, depending on the states of I2 and CKM.

[0021] S2 may also include a stack 140 of fourth transistors. The stack 140 may include a fourth PFET 141 and an additional fourth PFET 142 electrically connected in series between the positive voltage rail 199 and the second intermediate node 126. The gate 141g of the fourth PFET 141 may be electrically connected to the third intermediate node 136 to receive I3, thereby creating a feedback path 192 from the third intermediate node 136 to the fourth PFET 141 to help maintain a high voltage level on the second intermediate node 126 if necessary. Furthermore, the gate 142g of the additional fourth PFET 142 may be electrically connected to the first intermediate node 116 to receive I1, thereby creating a feedforward path 191 from the first intermediate node 116 to the additional fourth PFET 142 to further help maintain a high voltage level on the second intermediate node 126 if necessary. For example, given the above feedback path 192 and feedforward path 191, when both I1 and I3 are at low voltage levels, if the second intermediate node 126 is floating, the fourth PFET 141 and the additional fourth PFET 142 will both be turned on (i.e., conduct) to keep the voltage level on I2 high, as discussed in more detail below.

[0022] S2 may also include an inverter 150 and a multiphase clocked tri-state logic device 160 (hereinafter referred to as MPCTSL), which are electrically connected in series with the third intermediate node 136 and further arranged to loop back to the third intermediate node 136 (discussed in more detail below) and / or an additional inverter 170, which is also electrically connected in series with the third intermediate node 136.

[0023] Specifically, S2 may include an inverter 150. Inverter 150 may include a fifth PFET 151 and a fifth NFET 153 electrically connected in series between a positive voltage rail 199 and a ground rail 198. The gates 151g of the fifth PFET 151 and 153g of the fifth NFET 153 may both be electrically connected to a third intermediate node 136 to receive I3. Inverter 150 may also include a node 156 (which is a data output node or a fourth intermediate node) located at the junction between the fifth PFET 151 and the fifth NFET 153 (i.e., at the electrical connection between the fifth PFET 151 and the fifth NFET 153). Without the additional inverter 170, the output signal of the inverter 150 at node 156 can be the data output signal (Q) of the D flip-flop 100, or, when the additional inverter 170 is included in the D flip-flop 100 to generate Q (as described below), the output signal of the inverter 150 at node 156 can be a fourth intermediate signal (I4). In either case, when I3 is high, Q (or I4, which has the same state as Q) will be low, and vice versa. MPCTSL 160 may include a stack of sixth transistors comprising a sixth PFET 161, an additional sixth PFET 162, a sixth NFET 163, and an additional sixth NFET 164 electrically connected in series between the positive voltage rail 199 and the ground rail 198. The gate 161g of the sixth PFET 161 and the gate 164g of the additional sixth NFET 164 may be electrically connected to node 156 to receive Q (or I4). Furthermore, the gate 162g of the additional sixth PFET 162 can be electrically connected to receive CKM, and the gate 163g of the sixth NFET 163 can be electrically connected to receive the inverted clock signal (CKN). CKN can be inverted relative to CKM, and in particular, can have the same characteristics in terms of frequency, but have the opposite polarity relative to CKM. MPCTSL 160 may also include a sixth intermediate node 166 located at the junction between the additional sixth PFET 162 and the sixth NFET 163 (i.e., at the electrical connection between the additional sixth PFET 162 and the sixth NFET 163). A feedback signal (Ifb) can be output at the sixth intermediate node 166, and the state of Ifb can be high, low, or floating, depending on the states of Q (or I4), CKM, and CKN. The sixth intermediate node 166 can be electrically connected back to the third intermediate node 136, thereby forming a feedback loop 193 to maintain I3 high or low when CKM is low and CKN is high.

[0024] The additional inverter 170 may include a seventh PFET 171 and a seventh NFET 173 electrically connected in series between the positive voltage rail 199 and the ground rail 198. The gates 171g of the seventh PFET 171 and 173g of the seventh NFET 173 may both be electrically connected to a third intermediate node 136 to receive I3. The additional inverter 170 may also include a data output node 176 located at the junction between the seventh PFET 171 and the seventh NFET 173 (i.e., at the electrical connection between the seventh PFET 171 and the seventh NFET 173). A data output signal (Q) may be output at the data output node 176, and the state of Q will be the same as I4. Specifically, Q will depend on the state of I3 (i.e., when I3 is high, Q will be low, and vice versa).

[0025] Therefore, in the above and Figure 1 In the D flip-flop 100 shown, operation is primarily controlled by a single clock signal (i.e., CKM), except for the operation of feedback loop 193, which is controlled by two clock signals (i.e., CKM and CKN). CKM and CKN can be generated by clock signal generator 101. Clock signal generator 101 may, for example, include a pair of inverters 102 and 103 connected in series. Inverter 102 can be connected to receive the system clock signal (CK) and can invert CK to output CKN. Inverter 103 can be connected to receive CKN and can invert CKN to output CKM. Thus, CKN is inverted relative to both CK and CKM. Since the D flip-flop 100 only requires CKM and CKN to operate, clock signal generator 101 is relatively small. That is, it has fewer inverters and / or delay buffers than clock signal generators used for other D flip-flops that require more than two different clock phases to operate. Furthermore, since the number of transistors controlled by these clock signals in the D flip-flop 100 is relatively small (e.g., only one transistor controlled by CKN and only five transistors controlled by CKM), the size of the clock driver can be reduced.

[0026] Figure 2 This is a table showing the different possible states of the nodes in the D flip-flop 100 when energized. Combined with... Figure 2 refer to Figure 1If both CKM and D are low when powered on, the first PFET 111 will turn on, the first NFET 113 will turn off, and the additional first PFET 112 will turn on. Therefore, I1 at the first intermediate node 116 will be pulled up. When I1 is high, the second NFET 123 will turn on. However, since CKM is low, the additional second NFET 124 will turn off, preventing the voltage level at the second intermediate node 126 from being pulled down. Furthermore, the second PFET 121 will turn on and pull up the voltage level at the second intermediate node 126, thus I2 will be high. When I2 is high, the third PFET 131 will turn off, preventing the voltage level I3 at the third intermediate node from being pulled up. Furthermore, when I2 is high, the additional third NFET 134 will turn on. However, since CKM is low, the third NFET 133 will turn off, preventing the voltage level at the third intermediate node 136 from being pulled down. Therefore, the voltage level at the third intermediate node 136 will be floating, and I3 should maintain the same state as when it was de-energized, such as... Figure 2 As indicated by "x" in the table. Since I3 remains in the same state as it was when the power was off, Q(I4) will also remain so.

[0027] If CKM is low and D is high when power is applied, the first PFET 112 will be turned on, but the first PFET 111 will be turned off, preventing the voltage level on the first intermediate node 116 from being pulled up. Additionally, the first NFET 113 will be turned on, thereby pulling down the voltage level on the first intermediate node 116. Therefore, I1 will be low. When I1 is low and CKM is also low, the second PFET 121 will be turned on and pull up the voltage level on the second intermediate node 126. When I2 is high and CKM is low, the third intermediate node 136 will be floating. Therefore, as described above, I3 and Q (I4) should maintain their states (high or low) before power-off.

[0028] If CKM is high and D is low when power is applied, the first PFET 111 will be turned on, but the additional first PFET 112 will be turned off, preventing the voltage level on the first intermediate node 116 from being pulled up. Furthermore, the first NFET 113 will be turned off, preventing the voltage level on the first intermediate node 116 from being pulled down. Therefore, the first intermediate node 116, the second intermediate node 126, and the third intermediate node 136 will all be floating, and I1, I2, I3, and Q (I4) will retain their states (high or low) before power-off.

[0029] If CKM is high and D is also high when power is applied, both the first PFET 111 and the additional first PFET 112 will be turned off, preventing the voltage level on the first intermediate node 116 from being pulled up. The first NFET 113 will be turned on, pulling the voltage level on the first intermediate node 116 down to ground. When CKM is high and I1 is low, the second PFET 121 will be turned off, preventing the voltage level on the second intermediate node 126 from being pulled up. Furthermore, since CKM is high, the additional second NFET 124 will be turned on. However, since I1 is low, the second NFET 123 will be turned off, preventing the voltage level on the second intermediate node 126 from being pulled down. Therefore, the second intermediate node 126 will float, and I2, I3, and Q (I4) will retain their states (high or low) before power-off.

[0030] Figure 3 This is a table that shows four example ADs of multiple possible states of D and I1-Q when CKM is low, and how these states change when CKM transitions from low to high. It also shows four additional example EHs of possible states of D and I1-Q when CKM is high, and how these states change when CKM transitions from high to low.

[0031] As shown in Example AD, during any transition of CKM from low to high, Q(I4) will either remain unchanged or change to be the same as D. For example, in Example A, if CKM and D are currently low, and I1 is high, I2 is high, I3 is low, and Q is high, then a transition of CKM from low to high (i.e., the rising edge of CKM) will cause I1 to remain high, I2 to go low, I3 to go high, and Q to go low. Therefore, Q changes to reflect the same state as D. In Example B, if CKM and D are currently low, I1 is high, I2 is high, I3 is high, and Q is low, then a transition of CKM from low to high will cause I1 to remain high, I2 to go low, I3 to remain high, and Q to remain low. Therefore, Q remains unchanged to reflect the same state as D. In example C, if CKM is currently low, D is currently high, and if I1 is low, I2 is high, I3 is low, and Q is high, then the transition of CKM from low to high will cause I1 to remain low, I2 to remain high, I3 to remain low, and Q to remain high. Therefore, Q remains unchanged to reflect the same state as in D. In example D, if CKM is currently low and D is high, and if I1 is low, I2 is high, I3 is high, and Q is low, then the transition of CKM from low to high will cause I1 to remain low, I2 to remain high, I3 to become low, and Q to become high. Therefore, Q changes to reflect the same state as in D.

[0032] As shown in Example EH, when CKM transitions from high to low, Q(I4) remains unchanged regardless of the state of D. In Example E, if CKM is currently high, D is currently low, I1, I2, and I3 are high, and Q is low, then the transition of CKM from high to low (i.e., the falling edge of CKM) will not cause any of these nodes to change (i.e., I1, I2, and I3 will remain high, and Q will remain low). Therefore, Q remains unchanged. In Example F, if CKM is currently high, D is currently low, I1 and I2 are high, I3 is low, and Q is high, then the transition of CKM from high to low will again not cause any of these nodes to change (i.e., I1 and I2 remain high, I3 remains low, and Q remains high). Therefore, Q remains unchanged. In example G, if CKM and D are currently both high, and if I1 is low, I2 and I3 are high, and Q is low, then a transition of CKM from high to low will again not cause any of these nodes to change (i.e., I1 remains low, I2 and I3 remain high, and Q remains low). Therefore, Q remains unchanged. In example H, if CKM and D are currently both high, and if I1 is low, I2 is high, I3 is low, and Q is high, then a transition of CKM from high to low will again not cause any of these nodes to change (i.e., I1 remains low, I2 remains high, I3 remains low, and Q remains high). Therefore, Q remains unchanged.

[0033] Figure 4 It is a timing diagram, which shows the relationship between the timing diagram and the timing of the timing diagram. Figure 1 The change in Q of the D flip-flop 100 only reflects the change in D at the rising edge of the high-frequency CKM (e.g., 100MHz CKM). Figure 5 It is a timing diagram, which shows the relationship between the timing diagram and the timing of the timing diagram. Figure 1 The change in Q of the D flip-flop 100 similarly reflects the change in D at the rising edge of a low-frequency CKM (e.g., 1kHz CKM). It should be noted that... Figure 1 In the D flip-flop 100, by ensuring that I2 and I3 maintain their current state when the second intermediate nodes 126 and / or 136 are floating respectively, the combination of feedforward path 191, feedback path 192, and feedback loop 193 effectively prevents data loss when CKM remains static for an extended period (i.e., a long period without clock edges). Therefore, the combination of feedforward path 191, feedback path 192, and feedback loop 193 ensures... Figure 5 Q in the code toggles only on the rising edge of CKM.

[0034] For example, as described above, the third intermediate node 136 is also referred to herein as a data holding node. Feedback loop 193 ensures that I3 does not change state when the third intermediate node 136 is floating. Specifically, when D goes high or is high and CKM is low, I1 on the first intermediate node 116 will be low. When I1 is low and CKM is low, the second PFET 121 will be turned on, and the second NFET 123 and the additional second NFET 124 will both be turned off. Therefore, I2 on the second intermediate node 126 will go high. If I2 on the second intermediate node 126 is high and CKM is low, the third intermediate node 136 is floating, and I3 is held in its current state via feedback loop 193. For example, if I3 is high, it will remain high. This is because when Q(I4) is low and within MPCTSL 160, when Q(I4) is low, CKM is low, and CKN is high, both the additional sixth PFET 162 and the sixth PFET 161 will be turned on, and the additional sixth NFET 164 will be turned off. Therefore, Ifb on the sixth intermediate node 166 will be pulled up through the additional sixth PFET 162 and the sixth PFET 161, thereby pulling up I3 on ​​the third intermediate node 136. Conversely, if I3 is low, it will remain low. This is because when Q(I4) is high and within MPCTSL 160, when Q(I4) is high, CKM is low, and CKN is high, the sixth PFET 161 will be turned off, and the sixth NFET 163 and the additional sixth NFET 164 will be turned on. Therefore, Ifb on the sixth intermediate node 166 will be pulled down through the sixth NFET 163 and the additional sixth NFET 164, thereby pulling down I3 on ​​the third intermediate node 136.

[0035] When D goes low or is low and CKM is low, the first PFET 111 and the additional first PFET 112 will be turned on, and the first NFET 113 will be turned off. Therefore, I1 on the first intermediate node 116 will go high. If I1 is high and CKM is low, both the second PFET 121 and the second NFET 123 will be turned on, but the additional second NFET 124 will be turned off. Therefore, the second PFET 121 can pull up the voltage level on the second intermediate node 126, and the additional second NFET 124 will prevent the voltage level on it from being pulled down. Therefore, regardless of whether I1 is high or low, when CKM is low, I2 on the second intermediate node 126 will be high. As described above, if I2 on the second intermediate node 126 is high and CKM is low, the third intermediate node 136 will be floating, and I3 will be held in its current state (high or low) through the feedback loop 193 in the same manner as described above. It should be noted that when CKM is high and CKN is low, feedback loop 193 will be turned off (i.e., the sixth intermediate node 166 will be floating).

[0036] Furthermore, as described above, the second intermediate node 126 is also referred to herein as a data transmission node. Feedforward path 191 and feedback path 192 ensure that I2 does not change state under certain conditions (particularly when CKM transitions from low to high and D is high). For example, as described above, when CKM is low, I2 on the second intermediate node 126 will be high regardless of the state of I1, and the third intermediate node 136 will be floating, therefore I3 can be low and Q can be the same as D (e.g., ...). Figure 3 (Example C in the table), or, I3 can be high and Q can be different from D (e.g., ... Figure 3 (Example D in the table). If CKM goes high when D is high, the first NFET 113 will remain on and continue to pull down the voltage level on the first intermediate node 116. Therefore, I1 on the first intermediate node 116 will be low. As a result, the second PFET 121 and the second NFET 123 will both be off, so the second intermediate node 126 will float. Therefore, to ensure that I2 remains high when I3 is low to prevent I3 from changing state, and more specifically, to ensure that Q remains high to reflect D, the fourth PFET 141 and the additional fourth PFET 142 of the feedforward path 191 and the feedback path 192 will both be on, pulling up the voltage level on the second intermediate node 126 and ensuring that I2 remains high.

[0037] Figure 6 This is a schematic diagram illustrating an alternative embodiment of the D flip-flop 600. The D flip-flop 600 is similar to the D flip-flop 100, but with minor variations, including, but not limited to, the stack 640 of the fourth transistor being an NFET instead of a PFET. Specifically, refer to... Figure 6 The D flip-flop 600 may include a first stage (S1) (also referred to herein as the input stage or primary stage) and a second stage (S2) connected to S1 (also referred herein as the output stage or secondary stage).

[0038] S1 may include a data input node 615, which is electrically connected to receive data input (D). S1 may also include a first single-phase clocked tri-state logic device 610 (hereinafter referred to as the first SPCTSL). As described above, a single-phase clocked tri-state logic device is a tri-state logic device that outputs a signal that is high (i.e., logic 1, for example, at VDD), low (i.e., logic 0, for example, at ground or 0.0V), or floating and depends on the state of a single clock signal and the input signal. A multi-phase clocked tri-state logic device is a tri-state logic device that outputs a signal that is high (i.e., logic 1), low (i.e., logic 0), or floating and depends on the state of at least two clock signals (e.g., a clock signal and an inverted clock signal) and the input signal. The first SPCTSL 610 may include a stack of first transistors including a first PFET 611, a first NFET 613, and an additional first NFET 614 electrically connected in series between a positive voltage rail 699 at a positive supply voltage (VDD) level and a ground rail 698 (e.g., at 0.0 volts (V)). In some embodiments, VDD may be 0.8V. Alternatively, VDD may be at any other suitable positive supply voltage level (e.g., the processing technology node of a given design trigger). The gate 611g of the first PFET 611 and the gate 614g of the additional first NFET 614 may be electrically connected to a data input node 615 to receive D. The gate 613g of the first NFET 613 may be electrically connected to receive a clock signal (CKN) from a clock signal generator 601 (also referred to herein as a clock generation circuit), as discussed in more detail below. The first SPCTSL 610 may further include a first intermediate node 616 located at the junction between the first PFET 611 and the first NFET 613 (i.e., at the electrical connection between the first PFET 611 and the first NFET 613). A first intermediate signal (I1) may be output at the first intermediate node 616. The state of I1 may be high, low, or floating, depending on the states of D and CKN.

[0039] S2 may include a second single-phase clocked tri-state logic device 620 (hereinafter referred to as the second SPCTSL). The second SPCTSL 620 may include a stack of second transistors, the stack including a second PFET 621, an additional second PFET 622, and a second NFET 623 electrically connected in series between a positive voltage rail 699 and a ground rail 698. The gate 621g of the second PFET 621 and the gate 623g of the second NFET 623 may be electrically connected to receive CKN. The gate 622g of the additional second PFET 622 may be electrically connected to a first intermediate node 616 to receive I1. The second SPCTSL 620 may also include a second intermediate node 626 located at the junction between the additional second PFET 622 and the second NFET 623 (i.e., at the electrical connection between the additional second PFET 622 and the second NFET 623). A second intermediate signal (I2) may be output at the second intermediate node 626, and the state of I2 may be high, low, or floating, depending on the states of I1 and CKN.

[0040] S2 may also include a third single-phase clocked tri-state logic device 630 (hereinafter referred to as the third SPCTSL). The third SPCTSL 630 may include a third PFET 631, an additional third PFET 632, and a third NFET 633 connected in series between the positive voltage rail 699 and the ground rail 698. The gate 631g of the third PFET 631 and the gate 633g of the third NFET 633 may be electrically connected to the second intermediate node 626 to receive I2. The gate 632g of the additional third PFET 632 may be electrically connected to receive CKN. The third SPCTSL 630 may also include a third intermediate node 636 located at the junction between the additional third PFET 632 and the third NFET 633 (i.e., at the electrical connection between the additional third PFET 632 and the third NFET 633). A third intermediate signal (I3) may be output at the third intermediate node 636, and the state of I3 may be high, low, or floating, depending on the states of I2 and CKN.

[0041] S2 may also include a stack 640 of fourth transistors. The stack 640 may include a fourth NFET 643 and an additional fourth NFET 644 electrically connected in series between the second intermediate node 626 and the ground rail 698. The gate 644g of the additional fourth NFET 644 may be electrically connected to the third intermediate node 636 to receive I3, thereby creating a feedback path 692 from the third intermediate node 636 to the additional fourth NFET 644 to help maintain a low voltage level on the second intermediate node 626 if necessary. Furthermore, the gate 643g of the fourth NFET 643 may be electrically connected to the first intermediate node 616 to receive I1, thereby creating a feedforward path 691 from the first intermediate node 616 to the fourth NFET 643 to further help maintain a low voltage level on the second intermediate node 626 if necessary. For example, given the above feedback path 692 and feedforward path 691, when both I1 and I3 are at high voltage levels, if the second intermediate node 626 is floating, the fourth NFET 643 and the additional fourth NFET 644 will both be turned on (i.e., conduct) to keep the voltage level on I2 low.

[0042] S2 may also include an inverter 650 and a multiphase clocked tri-state logic device 660 (hereinafter referred to as MPCTSL), which are electrically connected in series with the third intermediate node 636 and arranged to loop back to the third intermediate node 636 (discussed in more detail below) and / or an additional inverter 670, which is also electrically connected in series with the third intermediate node 636. Specifically, S2 may include an inverter 650. The inverter 650 may include a fifth PFET 651 and a fifth NFET 653 electrically connected in series between the positive voltage rail 699 and the ground rail 698. The gate 651g of the fifth PFET 651 and the gate 653g of the fifth NFET 653 may both be electrically connected to the third intermediate node 636 to receive I3. Inverter 650 may also include node 656 located at the junction between the fifth PFET 651 and the fifth NFET 653 (i.e., at the electrical connection between the fifth PFET 651 and the fifth NFET 653). Without the additional inverter 670, the output signal of inverter 650 at node 656 may be the data output signal (Q) of the D flip-flop 600, or, when the additional inverter 670 is included in the D flip-flop 600 to generate Q (as described below), the output signal of inverter 650 at node 656 may be a fourth intermediate signal (I4). In any case, when I3 is high, Q (or I4, which has the same state as Q) will be low, and vice versa. MPCTSL 660 may include a stack of sixth transistors comprising a sixth PFET 661, an additional sixth PFET 662, a sixth NFET 663, and an additional sixth NFET 664 electrically connected in series between a positive voltage rail 699 and a ground rail 698. The gate 661g of the sixth PFET 661 and the gate 664g of the additional sixth NFET 664 can be electrically connected to node 656 to receive Q (or I4). Furthermore, the gate 662g of the additional sixth PFET 662 can be electrically connected to receive CK, while the gate 663g of the sixth NFET 663 can be electrically connected to receive another clock signal (CK). CKN can be inverted relative to CK; specifically, they can have the same characteristics in terms of frequency, but with opposite polarity relative to CK. MPCTSL 660 may also include a sixth intermediate node 666 located at the junction between the additional sixth PFET 662 and the sixth NFET 663 (i.e., at the electrical connection between the additional sixth PFET 662 and the sixth NFET 663). A feedback signal (Ifb) can be output at the sixth intermediate node 666, and the state of Ifb can be high, low, or floating, depending on the states of Q (or I4), CK, and CKN. The sixth intermediate node 666 can be electrically connected back to the third intermediate node 636, thereby forming a feedback loop 693, which is used to keep I3 high or low when CK is low and CKN is high.

[0043] The additional inverter 670 may include a seventh PFET 671 and a seventh NFET 673 electrically connected in series between a positive voltage rail 699 and a ground rail 698. The gates 671g of the seventh PFET 671 and 673g of the seventh NFET 673 may both be electrically connected to a third intermediate node 636 to receive I3. The additional inverter 670 may also include a data output node 676 located at the junction between the seventh PFET 671 and the seventh NFET 673 (i.e., at the electrical connection between the seventh PFET 671 and the seventh NFET 673). A data output signal (Q) may be output at the data output node 676, and the state of Q will be the same as I4. Specifically, it will depend on the state of I3 (i.e., when I3 is high, Q is low, and vice versa).

[0044] Therefore, in the above and Figure 6 In the D flip-flop 600 shown, operation is primarily controlled by a single clock signal (i.e., CKN), with only the operation of feedback loop 693 controlled by two clock signals (i.e., CK and CKN). CKN can be generated by a clock signal generator 601. For example, clock signal generator 601 may include a single inverter 602. Inverter 602 can be connected to receive CK (e.g., the system clock signal) and can invert CK to output CKN. Since the D flip-flop 600 only requires CK and CKN to operate, clock signal generator 601 is relatively small. That is, it does not require as many inverters and / or delay buffers as clock signal generators used for other D flip-flops that require more than two different clock phases to operate. Furthermore, since the number of transistors controlled by these clock signals in the D flip-flop 600 is relatively small (e.g., only one transistor controlled by CK and only five transistors controlled by CKN), the clock driver size can be reduced.

[0045] It should be understood that the D flip-flop 600 and Figure 1 The D flip-flop 100 operates similarly. That is, when CKN transitions from low to high, Q(I4) will change or remain unchanged to reflect D. However, when CKN transitions from high to low, Q will remain in the same state regardless of the state of D. Furthermore, in Figure 6 In the D flip-flop 600, by ensuring that I2 and I3 maintain their current state when the second intermediate nodes 626 and / or 636 are floating respectively, the combination of feedforward path 691, feedback path 692, and feedback loop 693 effectively prevents data loss when CKN remains static for an extended period (i.e., a long period without clock edges). Therefore, the combination of feedforward path 691, feedback path 692, and feedback loop 693 ensures that Q switches only on the rising edge of CKN.

[0046] It should be understood that in the above embodiments, a field-effect transistor (FET) is a semiconductor device comprising: a channel region located between a source region and a drain region; a main gate (also referred to in the art as a front gate) adjacent to the channel region; and optionally, an auxiliary gate (also referred to in the art as a back gate) adjacent to the channel region and opposite to the main gate. A P-type FET (PFET) may include a channel region and a P-type source / drain region at a relatively high conductivity level (e.g., a P+ source / drain region), the channel region being an intrinsic (i.e., undoped) channel region or an N-type channel region at a relatively low conductivity level (e.g., an N- channel region). An N-type FET (NFET) may include a channel region and an N-type source / drain region at a relatively high conductivity level (e.g., an N+ source / drain region), the channel region being an intrinsic (i.e., undoped) channel region or a P-type channel region at a relatively low conductivity level (e.g., a P- channel region). Various types of FET structures are well known in the art and can be incorporated into the disclosed circuit structures. For example, the FET described above can be a bulk semiconductor device or a semiconductor-on-insulator device, a planar semiconductor device or a non-planar semiconductor device, a single-gate device or a dual-gate device, a single-gate finger device or a multi-gate finger device, etc.

[0047] In some embodiments, the disclosed Figure 1 D flip-flop 100 or Figure 6 The FETs of the D flip-flop 600 can be formed using an advanced semiconductor-on-insulator (SOS) technology processing platform, such that they are either fully depleted SOS FETs (e.g., fully depleted SOI (FDSOI) FETs) or partially depleted SOS FETs (e.g., partially depleted SOI (PDSOI) FETs). Those skilled in the art will recognize that one advantage of the advanced SOS technology processing platform is that FETs can be formed on an insulating layer over a specific type of well region (e.g., an N-type well region (N-well) or a P-type well region (P-well)) to achieve different types of NFETs or PFETs with different threshold voltages (VT). For example, for ultra-low threshold voltage (SLVT) or low threshold voltage (LVT) FETs, an NFET can be formed over an N-well, and a PFET can be formed over a P-well. For conventional threshold voltage (RVT) or high threshold voltage (HVT) FETs, an NFET can be formed over a P-well, and a PFET can be formed over an N-well. Whether the FET is an SLVT FET or an LVT FET, or whether the FET is an RVT FET or an HVT FET, will depend on the design (e.g., device size, etc.) and process specifications (e.g., dopant concentration, etc.). In some embodiments, Figure 1 D flip-flop 100 or Figure 6The FETs within the D flip-flop 600 can all be RVT FETs or HVT FETs. That is to say, for D flip-flops 100 and 600, the PFET can be located above the N-well, and the NFET can be located above the P-well.

[0048] It should be understood that in the above methods and structures, semiconductor materials refer to materials whose conductivity properties can be altered by doping with impurities. Exemplary semiconductor materials include, but are not limited to, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon carbide germanium, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements such as aluminum (Al), gallium (Ga), or indium (In) with group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials that are doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different types of conductivity (e.g., P-type and N-type conductivity) can be achieved using different impurities (i.e., different dopants), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different levels of conductivity depend on the relative concentration levels of one or more dopants in a given semiconductor region.

[0049] It should be understood that the terminology used herein is for describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Moreover, as used herein, when oriented and shown in figures, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “under,” “above,” “overlapping,” “parallel,” “vertical,” etc., are intended to describe relative positions (unless otherwise stated), and terms such as “touches,” “directly contacts,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when elements are oriented and shown in a figure, to indicate that one element is located to the side of another element, rather than above or below it. For example, an element laterally adjacent to another element will be beside the other element, an element laterally directly adjacent to another element will be directly beside the other element, and an element laterally surrounding another element will be adjacent to and bound to the outer wall of the other element. All corresponding structures, materials, actions, and equivalents of the means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions used to perform a function in combination with other elements of the specific claims.

[0050] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with either surface-mount or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0051] The descriptions of various disclosed embodiments are given for illustrative purposes and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of techniques found in the market, or improvements to techniques, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A trigger, comprising: The first level has a first intermediate node; as well as The second level, which is connected to the first level, includes: Second intermediate node; The third intermediate node; and A pair of node-controlled transistors, connected in series between a voltage rail and a second intermediate node, wherein the first intermediate node and the third intermediate node are connected to the gates of different node-controlled transistors in the pair.

2. The trigger according to claim 1, wherein, The second level also includes: Inverter; and A multiphase clock-controlled tri-state logic device, wherein the inverter is connected in series between the third intermediate node and the multiphase clock-controlled tri-state logic device, and the multiphase clock-controlled tri-state logic device is connected in series between the inverter and the third intermediate node.

3. The trigger according to claim 2, in, The multiphase clock-controlled tri-state logic device includes a P-type field-effect transistor (PFET), an additional PFET, an N-type field-effect transistor (NFET), and an additional NFET connected in series between the positive voltage rail and the ground rail. The gates of the PFET and the additional NFET are connected to the inverter, and The gates of the additional PFET and the NFET are connected to receive the clock signal and the inverted clock signal, respectively.

4. The trigger according to claim 3, in, The inverter includes a data output node, and The data output node is connected to the gate of the PFET and the additional NFET of the multi-phase clocked tri-state logic device.

5. The trigger according to claim 3, in, The inverter includes a fourth intermediate node. The fourth intermediate node is connected to the gate of the PFET and the additional NFET of the multi-phase clocked tri-state logic device, and The trigger also includes an additional inverter connected to the third intermediate node and having a data output node.

6. A trigger, comprising: The first level has a first intermediate node; as well as The second level, which is connected to the first level, includes: Second intermediate node; The third intermediate node; and A pair of node-controlled transistors are connected in series between a positive voltage rail and a second intermediate node, wherein the first intermediate node and the third intermediate node are connected to the gates of different node-controlled transistors in the pair.

7. The trigger according to claim 6, in, The first stage includes a first P-type field-effect transistor (PFET), an additional first PFET, and a first N-type field-effect transistor (NFET) connected in series between the positive voltage rail and the ground rail. The first intermediate node is located at the junction between the additional first PFET and the first NFET. The gates of the first PFET and the first NFET are connected to the data input node, and The gate of the additional first PFET is connected to receive a clock signal.

8. The trigger according to claim 7, in, The second level includes: A second PFET, a second NFET, and an additional second NFET are connected in series between the positive voltage rail and the ground rail. The second intermediate node is located at the junction between the second PFET and the second NFET. Wherein, the gate of the second NFET is connected to the first intermediate node, and The gates of the second PFET and the additional second NFET are connected to receive the clock signal; and A third PFET, a third NFET, and an additional third NFET are connected in series between the positive voltage rail and the ground rail. The third intermediate node is located at the junction between the third PFET and the third NFET. The gates of the third PFET and the additional third NFET are connected to the second intermediate node, and The gate of the third NFET is connected to receive the clock signal, and The transistors controlled by the nodes in the pair include a fourth PFET and an additional fourth PFET.

9. The trigger according to claim 8, wherein, The second level also includes: Inverter; and A multiphase clock-controlled tri-state logic device, wherein the inverter is connected in series between the third intermediate node and the multiphase clock-controlled tri-state logic device, and the multiphase clock-controlled tri-state logic device is connected in series between the inverter and the third intermediate node.

10. The trigger according to claim 9, in, The inverter includes a fifth PFET and a fifth NFET connected in series between the positive voltage rail and the ground rail. The gates of the fifth PFET and the fifth NFET are connected to the third intermediate node. The multiphase clock-controlled tri-state logic device includes a sixth PFET, an additional sixth PFET, a sixth NFET, and an additional sixth NFET connected in series between the positive voltage rail and the ground rail. Wherein, the gates of the sixth PFET and the additional sixth NFET are connected to the node at the junction between the fifth PFET and the fifth NFET, and The gates of the additional sixth PFET and the sixth NFET are connected to receive the clock signal and the inverted clock signal, respectively.

11. The trigger of claim 10, wherein, The node between the fifth PFET and the fifth NFET is a data output node.

12. The trigger according to claim 10, in, The node between the fifth PFET and the fifth NFET is another intermediate node, and The trigger also includes an additional inverter connected to the third intermediate node and having a data output node.

13. The trigger of claim 10, further comprising a clock signal generator, wherein, The clock signal generator includes a first inverter and a second inverter connected in series, wherein the first inverter receives the system clock signal and outputs the inverted clock signal, and wherein the second inverter receives the inverted clock signal and outputs the clock signal.

14. A trigger, comprising: The first level has a first intermediate node; as well as The second level, which is connected to the first level, includes: Second intermediate node; The third intermediate node; and A pair of node-controlled transistors connected in series between the second intermediate node and the ground rail, wherein the first intermediate node and the third intermediate node are connected to the gates of different node-controlled transistors in the pair.

15. The trigger according to claim 14, in, The first stage includes a first P-type field-effect transistor (PFET), a first N-type field-effect transistor (NFET), and an additional first NFET connected in series between the positive voltage rail and the ground rail. The first intermediate node is located at the junction between the first PFET and the first NFET. Wherein, the gates of the first PFET and the additional first NFET are connected to the data input node, and In this configuration, the gate of the first NFET is connected to receive an inverted clock signal.

16. The trigger according to claim 15, in, The second level includes: A second PFET, an additional second PFET, and a second NFET are connected in series between the positive voltage rail and the ground rail. The second intermediate node is located at the junction between the additional second PFET and the second NFET. Wherein, the gate of the additional second PFET is connected to the first intermediate node, and The gates of the second PFET and the second NFET are connected to receive the inverted clock signal; and A third PFET, an additional third PFET, and a third NFET are connected in series between the positive voltage rail and the ground rail. The third intermediate node is located at the junction between the additional third PFET and the third NFET. Wherein, the gates of the third PFET and the third NFET are connected to the second intermediate node, and The gate of the additional third PFET is connected to receive the inverted clock signal, and The transistors controlled by the nodes in the pair include a fourth NFET and an additional fourth NFET.

17. The trigger of claim 16, wherein, The second level also includes: Inverter; and Multiphase clock-controlled tri-state logic devices, The inverter is connected in series between the third intermediate node and the multi-phase clock-controlled tri-state logic device, and the multi-phase clock-controlled tri-state logic device is connected in series between the inverter and the third intermediate node. The inverter includes a fifth PFET and a fifth NFET connected in series between the positive voltage rail and the ground rail. The gates of the fifth PFET and the fifth NFET are connected to the third intermediate node. The multiphase clock-controlled tri-state logic device includes a sixth PFET, an additional sixth PFET, a sixth NFET, and an additional sixth NFET connected in series between the positive voltage rail and the ground rail. Wherein, the gates of the sixth PFET and the additional sixth NFET are connected to the node at the junction between the fifth PFET and the fifth NFET, and The gates of the additional sixth PFET and the sixth NFET are connected to receive the clock signal and the inverted clock signal, respectively.

18. The trigger of claim 17, wherein, The node between the fifth PFET and the fifth NFET is a data output node.

19. The trigger according to claim 17, in, The node between the fifth PFET and the fifth NFET is another intermediate node, and The trigger also includes an additional inverter connected to the third intermediate node and having a data output node.

20. The trigger of claim 17, further comprising a clock signal generator, wherein, The clock signal generator receives the clock information and outputs the inverted clock signal.

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