Generation method of check matrix and communication device

Abstract

A method for generating a check matrix and a communication device, the method comprising: acquiring a basis matrix, the basis matrix comprising a first matrix, the first matrix being a matrix formed by a first column to a tenth column and a first row to a fourth row of the basis matrix, elements included in the first column of the basis matrix being non-zero elements, and the first column being a punched column; and according to the basis matrix, obtaining a check matrix of the multivariate low density parity check LDPC code, the check matrix being used for LDPC coding or LDPC decoding. Elements included in a first column in the basis matrix are all non-zero elements, and the first column is a punching column, so that the code rate of the LDPC code corresponding to the basis matrix provided by the method can reach 2 / 3, and compared with the prior art, the code rate of the multivariate LDPC code is improved, and the coding and decoding performance of the multivariate LDPC code is improved.

Description

Technical Field

[0001] This application relates to the field of coding, and more specifically, to a method for generating a parity check matrix and a communication device. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Currently, researchers are applying multi-dimensional LDPC codes to fields such as satellite communications, and how to improve the code rate of multi-dimensional LDPC codes suitable for wireless communications has become a research hotspot in this field. Summary of the Invention

[0003] The embodiments of this application provide a method for generating a parity check matrix and a communication device, with the aim of improving the code rate of multivariate LDPC codes and enhancing the encoding and decoding performance of multivariate LDPC codes.

[0004] In a first aspect, a method for generating a parity check matrix is ​​provided. The communication device can be a communication equipment, such as a network device or a terminal device, or a component configured in the communication equipment, such as a circuit or chip inside the communication equipment (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core or a system-in-package (SIP) chip, etc.), or a logic module or software capable of implementing some or all of the functions of the communication device, etc. This application does not limit the scope of the application.

[0005] The method includes: obtaining a base matrix, the base matrix comprising a first matrix, the first matrix being a matrix composed of columns 1 to 10 and rows 1 to 4 of the base matrix; the first matrix comprising a second matrix, the second matrix being a matrix composed of columns 7 to 10 and rows 1 to 4 of the first matrix; the first column of the second matrix having a column weight of 3; the other columns of the second matrix having a column weight of 2; all elements in the first column of the base matrix being non-zero elements; and the first column being a punched column; and obtaining a parity check matrix for a multivariate low-density parity-check (LDPC) code based on the base matrix, the parity check matrix being used for LDPC encoding or LDPC decoding.

[0006] Furthermore, the method may also include:

[0007] The aforementioned parity-check matrix is ​​used for LDPC encoding or LDPC decoding.

[0008] It should be understood that the method for generating the parity check matrix provided in this application can be applied during the encoding process on the encoding side and / or the decoding process on the decoding side.

[0009] It should also be understood that the elements in the basis matrix can be 0 or 1, or the non-zero elements in the basis matrix can have different values, and the specific values ​​of the non-zero elements can come from the set of values ​​corresponding to the multivariate Galois field.

[0010] It should also be understood that the first column in the base matrix is ​​the punched column, meaning that the encoded codewords corresponding to the first column in the base matrix need to be punched.

[0011] According to the method provided in this application, a communication device can obtain the parity check matrix of a multi-dimensional LDPC code based on the basis matrix, and then perform LDPC encoding or decoding. Since the first matrix in the basis matrix is ​​4 rows and 10 columns, and all elements in the first column are non-zero, and this first column is a punched column, the code rate of the LDPC code corresponding to the basis matrix provided in this application can reach (10⁻⁴) / (10⁻¹) = 2 / 3, which improves the code rate of the multi-dimensional LDPC code compared to existing technologies, further enhancing the encoding and decoding performance of the multi-dimensional LDPC code. Furthermore, the increased code rate of the multi-dimensional LDPC code makes it more suitable for changing wireless channel environments.

[0012] In conjunction with the first aspect, in some possible implementations, the first row of the first matrix corresponds to a first sequence, which is {1,0,1,0,1,0,1,1,0,0}, and is the sequence corresponding to replacing non-zero elements in the first row with 1; the second row of the first matrix corresponds to a second sequence, which is {1,1,0,1,0,1,0,1,1,0}, and is the sequence corresponding to replacing non-zero elements in the second row with 1; the third row of the first matrix corresponds to a third sequence, which is {1,0,0,1,1,0,1,0,1,1}, and is the sequence corresponding to replacing non-zero elements in the third row with 1; the fourth row of the first matrix corresponds to a fourth sequence, which is {1,1,1,0,1,1,1,0,0,1}, and is the sequence corresponding to replacing non-zero elements in the fourth row with 1.

[0013] It should be understood that the position of 1 in the first sequence corresponds to the position of the non-zero element in the first row of the first matrix. The position of 1 in the second sequence corresponds to the position of the non-zero element in the second row of the first matrix. The position of 1 in the third sequence corresponds to the position of the non-zero element in the third row of the first matrix. The position of 1 in the fourth sequence corresponds to the position of the non-zero element in the fourth row of the first matrix. The above sequences are only to illustrate the positions of the non-zero elements in each row from the first to the fourth row of the first matrix.

[0014] It should also be understood that, assuming the elements in the basis matrix take values ​​of 0 and 1, the first matrix can be represented as:

[0015]

[0016] In conjunction with the first aspect, in some possible implementations, the code rate R of the multivariate LDPC code satisfies:

[0017]

[0018] Where m = 6, 7, ..., 26, 27.

[0019] It should be understood that the highest code rate R of this multivariate LDPC code can reach 2 / 3.

[0020] In conjunction with the first aspect, in some possible implementations, the code rate of the multivariate LDPC code is R = 0.67.

[0021] In conjunction with the first aspect, in some possible implementations, the base matrix comprises 25 rows and 31 columns, and the average column weight of the first matrix is ​​2.4.

[0022] The above content defines the size of the base matrix and the average column weight of the first matrix.

[0023] In conjunction with the first aspect, in some possible implementations, the values ​​of the non-zero elements in the i-th row of the basis matrix are determined based on the elements in the first set, which is the set of optimal tuples in the multivariate Galois field GF(q), and the row weight of the i-th row is equal to the number of elements included in the first set, where q is a power of 2 and q is an integer greater than 2.

[0024] It should be understood that the value of q in the multivariate galo domain GF(q) can be predefined or preconfigured by the protocol / system, or the value of q can be indicated by indication information.

[0025] Based on the above technical solution, the values ​​of the non-zero elements in each row of the basis matrix can be selected from the optimal tuple set of GF(q) and include a set whose number of elements is equal to the row weight (e.g., a first set). The specific values ​​of the non-zero elements in the row are determined based on the elements in the first set. For example, the values ​​of the non-zero elements in the i-th row of the basis matrix can correspond one-to-one with the values ​​of the elements in the first set, or the values ​​of the non-zero elements in the i-th row of the basis matrix are obtained by mathematical operations on the values ​​of the elements in the first set.

[0026] In conjunction with the first aspect, in some possible implementations, the elements in the basis matrix take values ​​of 0 or 1. The parity check matrix of the multivariate LDPC code is obtained based on the basis matrix, including: selecting a second set corresponding to the i-th row from the set of optimal tuples in the multivariate Galois field GF(q) based on the row weight of the i-th row in the basis matrix, where the row weight of the i-th row is equal to the number of elements in the second set, q is a power of 2, and q is an integer greater than 2; replacing the non-zero elements in the i-th row of the basis matrix with elements related to the elements in the second set to obtain the i-th row of a third matrix; and obtaining the parity check matrix of the multivariate LDPC code based on the third matrix.

[0027] Based on the above technical solution, the elements in the basis matrix take values ​​of 0 or 1, meaning the basis matrix can be viewed as a basis matrix of a binary field. When obtaining the parity-check matrix of the multivariate LDPC code from this basis matrix, a third matrix needs to be obtained based on it, and then the parity-check matrix of the multivariate LDPC code needs to be obtained from the third matrix. The non-zero elements in the i-th row of this third matrix correspond one-to-one with the 1 elements in the i-th row of the basis matrix. The specific values ​​of the non-zero elements in the i-th row of the third matrix can be determined based on the row weight of the i-th row in the basis matrix. This is achieved by selecting a set from the optimal tuple set of GF(q) whose number of elements is equal to the row weight of the i-th row (e.g., the second set). The specific values ​​of the non-zero elements in the i-th row of the third matrix are then determined based on the elements in the second set.

[0028] In conjunction with the first aspect, in some possible implementations, the values ​​of the non-zero elements in the j-th row of the basis matrix are determined based on the elements in the third set. The third set is selected from the element value mapping relationship of the multivariate Galois field GF(q) according to the row index. The row weight of the j-th row is equal to the number of elements included in the third set, where q is a power of 2 and q is an integer greater than 2.

[0029] It should be understood that the element value mapping relationship of this multi-GF(q) can be a diagram, text, or other representation. This mapping relationship can be predefined by the system / protocol or preconfigured.

[0030] Based on the above technical solution, the values ​​of the non-zero elements in each row of the base matrix can be determined from the set (e.g., the third set) corresponding to the row index in the element value mapping relationship of GF(q). The specific values ​​of the non-zero elements in the row corresponding to the row index are determined based on the elements in the third set. For example, if the row index of the i-th row in the base matrix is ​​i, the set corresponding to the row index i (e.g., the third set) is selected from the element value mapping relationship of GF(q) according to the row index i. The values ​​of the non-zero elements included in the third set can correspond one-to-one with the values ​​of the non-zero elements in row i.

[0031] In conjunction with the first aspect, in some possible implementations, the elements in the base matrix take values ​​of 0 or 1. The parity check matrix of the multivariate LDPC code is obtained based on the base matrix, including: selecting a fourth set corresponding to the row index from the element value mapping relationship of the multivariate Galois field GF(q) based on the row index of the j-th row in the base matrix, where the row weight of the j-th row is equal to the number of elements included in the fourth set, q is a power of 2, and q is an integer greater than 2; replacing the non-zero elements of the j-th row in the base matrix with elements from the fourth set to obtain the j-th row of the fourth matrix; and obtaining the parity check matrix of the multivariate LDPC code based on the fourth matrix.

[0032] Based on the above technical solution, the elements in the basis matrix take values ​​of 0 or 1, meaning the basis matrix can be viewed as a basis matrix of a binary field. When obtaining the parity-check matrix of the multivariate LDPC code from this basis matrix, a fourth matrix needs to be obtained based on this basis matrix, and then the parity-check matrix of the multivariate LDPC code is obtained from the fourth matrix. The non-zero elements in the i-th row of this fourth matrix correspond one-to-one with the elements 1 in the i-th row of the basis matrix. The specific values ​​of the non-zero elements in the i-th row of the fourth matrix can be determined from the set corresponding to row index i in the element value mapping relationship of GF(q) (e.g., the third set).

[0033] In conjunction with the first aspect, in some possible implementations, the method further includes:

[0034] Receive first indication information, which indicates the value of q corresponding to the multivariate Galois domain GF(q).

[0035] It should be understood that this first instruction information can be carried in radio resource control signaling.

[0036] In conjunction with the first aspect, in some possible implementations, when the code rates of the multivariate LDPC codes are different, the offset values ​​corresponding to at least one non-zero element in the base matrix corresponding to the multivariate LDPC codes are different; and / or, when the spread factors of the multivariate LDPC codes are different, the offset values ​​corresponding to at least one non-zero element in the base matrix corresponding to the multivariate LDPC codes are different.

[0037] Based on the above technical solution, in this application, the code rate and / or spread factor of the multivariate LDPC code are different, and the offset value corresponding to at least one non-zero element in the basis matrix is ​​different. Compared with the existing schemes where all non-zero elements in the basis matrix use the same offset value, this method can specifically design the parity check matrix in the encoding and decoding process of LDPC codes, thereby obtaining higher encoding and decoding performance of LDPC codes.

[0038] Secondly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0039] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, or an input / output interface, or a communication interface, or an interface unit; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0040] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0041] Thirdly, a communication device is provided, comprising: at least one processor coupled to a memory for storing a program, the processor for executing a computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0042] In one implementation, the device is either a transmitting device or a receiving device.

[0043] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0044] Fourthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the above aspects or their implementations. The communication interface may be implemented in hardware or software.

[0045] In one implementation, the device further includes the memory.

[0046] Fifthly, a processor is provided for executing the methods provided in the above aspects.

[0047] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0048] In a sixth aspect, a computer-readable storage medium is provided, on which a computer program or instructions are stored, which, when executed on a computer, cause the computer to perform the methods provided in any of the foregoing aspects or their implementations.

[0049] In a seventh aspect, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0050] Eighthly, a chip or chip system is provided, the chip or chip system including a processor, which causes a communication device on which the chip or chip system is installed to perform the method provided in any of the above aspects or implementations thereof by running a computer program or instructions stored in a memory.

[0051] Optionally, the chip or chip system further includes a communication interface through which the processor can execute computer programs or instructions stored in memory. This communication interface can be implemented in hardware or software.

[0052] Alternatively, as one implementation, the chip may also include a memory for storing computer programs or instructions.

[0053] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0054] Ninthly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above.

[0055] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of a network architecture applicable to embodiments of this application.

[0057] Figure 2 This is a schematic diagram of a communication scenario applicable to embodiments of this application.

[0058] Figure 3 This is a schematic diagram of the signal processing procedure of the physical layer applicable to embodiments of this application.

[0059] Figure 4 This is a schematic block diagram of a device used to implement physical layer processing.

[0060] Figure 5 This is a schematic diagram of the LDPC verification matrix H provided in the embodiments of this application.

[0061] Figure 6 This is a Tanner diagram of the parity-check matrix H of LDPC provided in the embodiments of this application.

[0062] Figure 7 This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application.

[0063] Figure 8 These are two different dimensions of Raptor-like structures provided in the embodiments of this application.

[0064] Figure 9 This is a schematic diagram illustrating the relationship between base graph (BG) selection, transport block size (TBS), and rate provided in the embodiments of this application.

[0065] Figure 10 This is a schematic flowchart illustrating a method for generating a verification matrix provided in this application.

[0066] Figure 11 This is a schematic diagram of a basis matrix provided in an embodiment of this application.

[0067] Figure 12 This is a simulation comparison diagram provided in an embodiment of this application.

[0068] Figure 13 This is a schematic block diagram of a communication device provided in an embodiment of this application.

[0069] Figure 14 This is another schematic block diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0070] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0071] "For indication" or "indication" can include both direct and indirect indication, or it can be explicit and / or implicit indication.

[0072] The various numerical designations, such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments in this application, such as distinguishing different messages or different information.

[0073] "Predefined" can be achieved by pre-storing the corresponding code, table or other means that can be used to indicate relevant information in the device. This application does not limit the specific implementation method.

[0074] The “protocol” involved can refer to standard protocols in the field of communications, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems. This application does not limit this.

[0075] The words “example,” “for example,” “exemplary,” “as another example,” etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as an “example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs.

[0076] The terms “including,” “comprising,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

[0077] "At least one" means one or more, while "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple.

[0078] The phrases "when," "if," "under certain circumstances," and "if" all indicate that the network element will take corresponding actions under certain objective conditions, not that they limit the time, nor do they require the network element to perform a judgment action, nor do they imply any other limitations. Furthermore, in this application, the descriptions of conditions such as "when," "if," "under certain circumstances," and "if" can be understood as necessary conditions, without limiting whether the condition is a sufficient condition or a necessary and sufficient condition. For example, "under the condition of A, execute B" can be understood as "if at least A is satisfied, execute B."

[0079] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0080] The following describes a communication system to which embodiments of this application can be applied.

[0081] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0082] In a communication system, a device can send signals to or receive signals from another device. These signals can include information, signaling, or data. The device can also be replaced by an entity, network entity, communication equipment, communication module, node, communication node, etc.; this application uses a device as an example. For instance, a communication system can include at least one terminal device and at least one network device. The network device can send downlink signals to the terminal device, and / or the terminal device can send uplink signals to the network device. It is understood that the terminal device in this application can be replaced by a first communication device, and the network device can be replaced by a second communication device, both performing the corresponding communication methods described in this application.

[0083] The radio access network (RAN) device in this application is a device with wireless transceiver capabilities. The RAN device can provide wireless communication services, enabling terminal devices to access the wireless network. The RAN can also be called an access network device or a network device. In the embodiments of this application, the network device can refer to a radio access network (RAN) node (or device) used in a cellular network (or mobile network) to connect terminal devices to the wireless network. It can also be a Zigbee base station, a Bluetooth master (BTmaster), a Bluetooth Low Energy (BLE) master, a long-range radio (Lora) base station, or a Wi-Fi access point.

[0084] Network equipment can be a base station. The term "base station" can broadly encompass, or be interchangeable with, various names including: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or similar entities, or combinations thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device that performs base station functions in D2D, V2X, and M2M communications, or a device that performs base station functions in future communication systems. A base station can support networks with the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or equipment form used in the network equipment. In some deployments, the network equipment mentioned in the embodiments of this application can be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network equipment can include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0085] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0086] RAN nodes can support one or more types of fronthaul interfaces, each corresponding to a DU and RU with different functions. If the fronthaul interface between the DU and RU is a Common Public Radio Interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and RU is another type of interface, relative to CPRI, some downlink and / or uplink baseband functions, such as, for downlink, one or more of precoding, beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP), are moved from the DU to the RU; and for uplink, one or more of beamforming (BF), or fast Fourier transform (FFT) / removing CP, are moved from the DU to the RU. In one possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the segmentation between DU and RU differs, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, and F.

[0087] Taking eCPRI Cat A as an example, for downlink transmission, layer mapping is used as the dividing line. The DU is configured to implement one or more functions preceding layer mapping (i.e., coding, rate matching, scrambling, modulation, and layer mapping itself), while other functions following layer mapping (e.g., resource element (RE) mapping, digital BF, or IFFT / CP addition) are implemented in the RU. For uplink transmission, de-RE mapping is used as the dividing line. The DU is configured to implement one or more functions preceding de-mapping (i.e., decoding, rate matching de-matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping itself), while other functions following de-mapping (e.g., digital BF or FFT / CP removal) are implemented in the RU. It is understood that descriptions of the functions of the DU and RU corresponding to various types of eCPRI can be found in the eCPRI protocol and will not be elaborated upon here.

[0088] In one possible design, the processing unit in the BBU used to implement baseband functions is called the baseband high (BBH) unit, and the processing unit in the RRU / AAU / RRH used to implement baseband functions is called the baseband low (BBL) unit.

[0089] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open-RAN (O-RAN or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules. The network device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, general-purpose hardware can be a server, such as a cloud server.

[0090] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuit, software module, or a hardware circuit plus a software module. This apparatus can be installed in the network device or used in conjunction with the network device. In this embodiment, the example of a network device being used to implement the functions of a network device is provided only and does not constitute a limitation on the solutions described in this embodiment.

[0091] The terminal equipment in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0092] Terminal devices can be devices that provide voice / data, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or future public land mobile communication networks. Terminal devices in a network (PLMN), devices in a Zigbee network, devices in a LoRa network, Bluetooth slaves, Bluetooth Low Energy slaves, Wi-Fi stations (STAs), etc. This application does not limit the scope of the embodiments.

[0093] Terminal devices can also be terminal devices in an IoT system, also known as IoT nodes. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network that enables human-machine interconnection and machine-to-machine interconnection. Connectivity can be achieved through broadband or narrowband technologies. IoT technology, for example, can achieve massive connectivity, deep coverage, and low terminal power consumption through narrowband (NB) technology. IoT technologies include reflective communication technology, spread spectrum technology, and ultra-wideband (UWB), which will not be elaborated further.

[0094] In addition, terminal devices may also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0095] By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0096] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or it can be any device capable of supporting the terminal device in implementing those functions, such as a chip system. This device can be installed in or used in conjunction with the terminal device. In this embodiment, the chip system can be composed of chips or may include chips and other discrete components. This embodiment only uses the terminal device as an example to illustrate the device for implementing the functions of the terminal device, and does not constitute a limitation on the solution of this embodiment.

[0097] The terminal device in this application can be a hardware device, a software function running on dedicated hardware, or a software function running on general-purpose hardware. It can also be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, the general-purpose hardware can be a server, such as a cloud server.

[0098] Network devices and / or terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located.

[0099] For example, Figure 1 A schematic diagram of a network architecture applicable to embodiments of this application is shown.

[0100] Figure 1 This is a schematic diagram of the architecture of the communication system 10 used in the embodiments of this application. Figure 1 A schematic diagram of a possible, non-limiting system architecture is shown. (e.g.) Figure 1 As shown, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 also includes an Internet 300. The RAN 100 may include at least one RAN node (e.g., Figure 1 110a and 110b in the above), may also include at least one terminal device (such as Figure 1 (120a-120j in the original text). Terminal devices can connect to radio access network (RAN) devices wirelessly. Terminal devices can connect to each other, and RAN devices can connect to each other via wired or wireless means. RAN node 110 connects to core network 200 wirelessly or via wired means. The core network devices in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and RAN logical functions.

[0101] Figure 1 This is just an illustration; the communication system 10 may also include other network devices, such as wireless repeaters and wireless backhaul devices. Figure 1 It is not shown in the middle.

[0102] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be ORAN, cloud radio access network (CRAN), Zigbee network systems, or wireless fidelity (Wi-Fi) systems. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0103] The RAN node can be an airborne base station, such as satellite base station 110a; or an indoor base station, such as a micro base station or indoor station 110b. It should be understood that this application does not limit the specific technology or device form used in the wireless access network equipment. For ease of description, the following description uses a base station as an example of a wireless access network device.

[0104] The terminal device can be a terminal device deployed in the air, such as... Figure 1 The 120i can be a helicopter or drone; it can also be a terminal device deployed on the ground, such as... Figure 1Among them are mobile phones 120a, 120e, 120f and 120j, vehicles 120b, computers 120g, printers 120h, gas stations 120c, smart home devices 120d, etc.

[0105] Alternatively, the terminal device can also be used as a RAN node. For example, the UE can act as a scheduling entity, providing sidelink signaling between terminal devices in vehicle-to-everything (V2X), device-to-device (D2D), or peer-to-peer (P2P) scenarios.

[0106] RAN nodes and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the RAN nodes and terminal devices.

[0107] The roles of RAN nodes and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a RAN node. For terminal devices 120j that access RAN 100 via 120i, terminal device 120i is a RAN node; however, for RAN node 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Alternatively, 110a and 120i can also communicate via an interface protocol between RAN nodes; in this case, 120i is also a RAN node relative to 110a. Therefore, both RAN nodes and terminal devices can be collectively referred to as communication devices. Figure 1 110a, 110b, and 120a-120j can be referred to as communication devices with their respective corresponding functions, such as communication devices with RAN node functions or communication devices with terminal functions.

[0108] In the embodiments of this application, the functions of the RAN node can be executed by modules (such as chips) within the RAN node, or by a control subsystem that includes RAN node functions. This control subsystem, including RAN node functions, can be a control center in the aforementioned terminal application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be executed by modules (such as chips) within the terminal device, or by a device that includes terminal device functions. This application does not limit the scope of these limitations.

[0109] Figure 2These are schematic diagrams illustrating several different communication scenarios applicable to the communication methods provided in the embodiments of this application. For example, point-to-point transmission between RAN nodes and terminals or between terminals (such as...). Figure 2 (a) in the text refers to point-to-point transmission between RAN nodes and terminals, and multi-hop transmission between RAN nodes and terminals (e.g., ...). Figure 2 (b) Figure 2 (c) Transmission, dual connectivity (DC) of multiple RAN nodes and terminals (e.g.) Figure 2 (d) or multiple connections, etc. It should be noted that the specific communication application scenarios mentioned above are merely examples and do not constitute limitations. In particular, from a business perspective, the embodiments of this application are applicable to many business scenarios, such as data encoding scenarios and high-capacity uplink scenarios in extended reality (XR) services. Furthermore, Figure 2 This application does not impose any restrictions on the network architecture applicable to this application, and it does not restrict uplink, downlink, access link, backhaul link, sidelink (SL) and other transmissions.

[0110] Figure 3 This is a schematic diagram of the signal processing process of the physical layer applicable to embodiments of this application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0111] Downlink processing is the process of transmitting information data from higher layers after physical layer processing. For example, downlink processing includes: performing channel coding (or simply coding) on ​​the layer 2 (L2) information data, modulation, layer mapping, precoding, framing, IFFT, and processing it into an air interface signal to be transmitted through intermediate radio frequency (IRF).

[0112] More specifically, the transmitting end can divide the information data from Layer 2 into multiple TBs based on the system-supported transport block (TB) size (TBS), and add a cyclic redundancy check (CRC) code to each TB. If the TB size after adding the CRC code exceeds the maximum code block length, the TB can be segmented to obtain multiple code blocks (CBs). Each segmented CB can be further CRC-coded to obtain the input to be encoded corresponding to each CB. This input to be encoded is a sequence of bits to be encoded, specifically including the information bits and check bits (i.e., the CRC code) in its corresponding CB. The transmitting end can perform channel coding on this input to be encoded, such as LDCP coding, to obtain the corresponding coded code blocks. Rate matching is performed on the coded code blocks, and the rate-matched coded code blocks are concatenated to form codewords (CWs). The transmitting end can scramble the codewords to generate scrambled bits. The scrambled bits are modulated to obtain modulation symbols. After being mapped by resource elements (REs), the modulation symbols are mapped onto multiple REs, thus obtaining the value carried on each RE. Based on the values ​​carried on these REs, the transmitter can generate a baseband signal. The baseband signal can then be transmitted by the antenna after undergoing IFR processing and other operations.

[0113] Uplink processing is the process of physical layer processing of signals received through the air interface. For example, uplink processing includes: performing IRF processing on the received signal to obtain the baseband signal, and then completing physical layer signal processing through FFT, deframing, demodulation, and decoding, and then handing the obtained information data to layer 2.

[0114] More specifically, the signal receiver performs IRF processing on the signal received from the antenna to obtain the baseband signal. Subsequently, the receiver's physical layer can sequentially perform RE mapping, demodulation, descrambling, rate matching de-matching, and channel decoding on the signal to obtain the bit sequence before encoding, which may specifically include information bits and parity bits.

[0115] Optionally, after completing RE mapping and before demodulation, the receiver can perform channel equalization. Channel equalization is based on the channel estimated by the channel, and the influence of the channel is removed by using an equalization algorithm, thereby ensuring correct signal demodulation.

[0116] Optionally, after modulation but before RE mapping, the transmitting end can perform layer mapping and precoding. For example, the transmitting end can map the modulation symbols to multiple layers, and the layer-mapped modulation symbols are then precoded to obtain a precoded signal. The precoded signal is then mapped to multiple REs via RE mapping. Correspondingly, after performing de-layer mapping, the receiving end performs channel equalization and then demodulation; or, the receiving end can perform de-layer mapping and then demodulation after completing channel equalization; or it can perform de-layer mapping and then channel equalization after completing deframe.

[0117] because Figure 3 The specific implementation methods for each step can be achieved using existing technologies. For details, please refer to the relevant chapters in the 3rd Generation Partnership Project (3GPP) technical specification (TS) 38.211, which will not be elaborated here.

[0118] The apparatus for implementing the above-described physical layer processing can be a communication device, such as a network device or terminal, or a mobile communication chip; this application does not limit this. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, Figure 4 This is a schematic block diagram of a device used to implement physical layer processing. Figure 4 (a) and (b) show apparatus 400A and apparatus 400B, respectively. Apparatus 400A can be used to implement uplink processing, and apparatus 400B can be used to implement downlink processing.

[0119] like Figure 4 As shown in (a) and (b), devices 400A and 400B respectively include a computing unit, a control unit, and a storage unit. The computing unit is responsible for processing the logical operations of the device, specifically including encoding and / or decoding logical operations. The storage unit is responsible for storing data during the computing process, and can also be used to store information related to encoding and decoding, such as base maps. The control unit is responsible for scheduling and controlling the computing unit and storage resources.

[0120] For example, such as Figure 4 As shown in (a), the computing unit of device 400A can be used to perform operations such as TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding, and code block concatenation. The BG selection can be made from the BGs stored in the storage unit.

[0121] For example, such as Figure 4As shown in (b), the computing unit of device 400B can be used to perform operations such as rate matching, HARQ merging, LDPC decoding, CB CRC check, and TB CRC check.

[0122] In another possible implementation, the module in device 400A used for LDPC encoding is an encoder. In yet another possible implementation, the encoder can not only implement LDPC encoding but also perform LDPC encoding preprocessing and / or post-processing. LDPC encoding preprocessing includes, for example, one or more of the following: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. LDPC encoding post-processing includes, for example, code block concatenation. For example, device 400A is an encoder. Of course, the encoder can also implement other functions besides LDPC encoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0123] In one possible implementation, the module in device 400B used for LDPC decoding is a decoder. In another possible implementation, the decoder can not only perform LDPC decoding, but also perform LDPC decoding preprocessing and / or post-processing. LDPC decoding preprocessing includes, for example, one or more of the following: rate matching or HARQ merging. LDPC post-processing includes, for example, one or more of the following: CB CRC or TB CRC. For example, device 400B is a decoder. Of course, the decoder can also perform other functions besides LDPC decoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0124] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0125] 1. LDPC code

[0126] LDPC codes are linear block codes, and their parity-check matrix is ​​a sparse matrix. The number of zero elements in the LDPC parity-check matrix is ​​far greater than the number of non-zero elements; in other words, the row weight and column weight of the parity-check matrix are very small compared to the code length of the LDPC.

[0127] For an LDPC code with a bit sequence of length K and a code length of N, it can be uniquely determined by its parity-check matrix H, which has a dimension of (NK)×N. The corresponding codeword c can be defined by the parity-check matrix H as follows:

[0128] c = {c|Hc} T =0, c∈{0,1} N}

[0129] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and each parity-check equation corresponds to a check node (CN). NK parity-check equations correspond to NK check nodes of the LDPC code. Each column corresponds to a symbol (or codeword bit) of the LDPC code, and each codeword bit corresponds to a variable node. N symbol bits correspond to N variable nodes (VN) of the LDPC code. The non-zero elements h in matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. A regular LDPC check matrix H with a code length of 10 and a code rate of 1 / 2 is shown below. Figure 5 As shown, v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0130] Figure 5 This is a schematic diagram of the parity check matrix H of an LDPC. Figure 5 In this diagram, there are 10 variable nodes and 5 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain a Tanner diagram.

[0131] LDPC codes can be represented using graphical models, such as Tanner graphs, factor graphs, and tree graphs. Tanner graphs offer the most concise and intuitive representation. Tanner first described LDPC codewords graphically in 1981; this type of graph is now called a Tanner graph. Tanner graphs correspond one-to-one with parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity-check nodes, representing parity-check constraints. Each parity-check node represents a parity-check constraint. The following section will discuss this in conjunction with... Figure 6 Please provide an explanation. Figure 6 In a matrix description, the degree of a node can be defined as the number of edges connected to it, corresponding to the definition of degree in the matrix description.

[0132] Figure 6 The Tanner plot of the parity-check matrix H of an LDPC.

[0133] like Figure 6 As shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle uses one vertex from this group of vertices as both the start and end point, and traverses each node only once. The length of the cycle is defined as the number of connections it contains, while the circumference of the graph, also known as the size of the graph, is defined as the minimum cycle length in the graph, such as... Figure 3 In the middle, the circumference is 4, such as Figure 3 The diagram shows the black lines connecting the variable nodes in the Tanner graph. Variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. Parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connection between two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between a variable node and a parity node can also be called an edge. A connection between a parity node and a variable node can also be described as: the parity node and the variable node have a connection or an edge. The edge relationship between a parity node and a variable node can include either the presence of an edge or the absence of an edge.

[0134] As mentioned above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0135] 2. Column weight and row weight

[0136] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. Column weight can also be called column degree or column count.

[0137] For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. Row weight can also be called row degree or row count.

[0138] For example, such as Figure 5 As shown, the column weight of the first column of the verification matrix H is 2, and the row weight of the first row is 4.

[0139] 3. QC-LDPC code

[0140] Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes. When the code length is long, the parity-check matrix H of an LDPC code can become very large; therefore, H is usually represented in blocks: the complete parity-check matrix H is considered as consisting of multiple Z... c ×Z c The submatrix is ​​generated. Specifically, the complete parity check matrix H can be generated from a basis matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The base matrix H is a submatrix, and each submatrix can be represented by a number of cyclically shifted bits. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. b The elements in it can also be called quasi-cyclic (QC) blocks.

[0141] Based on the basis matrix H b And the boost value Z c (lifting size) can be used to transform the basis matrix H b Expanded into a complete parity-check matrix for encoding or decoding. Z c It can also be called expansion factor, boosting factor, expansion value, expansion coefficient, or boosting size, etc.

[0142] Specifically, for a (N,K) QC-LDPC code, the number of parity bits is M = NK, and the parity check matrix H can be represented as:

[0143]

[0144] Where M = m b ×Z, N=n b ×Z, P i,j Representing a Z×Z cyclic shift matrix or a Z×Z all-zero matrix, a cyclic shift matrix can be represented by its corresponding cyclic shift coefficient V. i,j To simplify the representation, for example, the cyclic shift matrix can be defined as a cyclic right shift matrix of an identity matrix, where each element "1" in the identity matrix can be based on the cyclic shift coefficient V. i,j Perform a circular shift to the right. Where V...i,j When P = -1, i,j V is a Z×Z matrix containing all zeros; i,j When P = 0, i,j V is a Z×Z identity matrix, which is obtained by cyclically shifting each "1" in the identity matrix to the right by 0 bits (or, in other words, without shifting); i,j ∈[-1, Z max When P = -1], i,j Circularly shift each element "1" in a Z×Z identity matrix to the right by V. i,j The matrix obtained by Z max It is the maximum value of Z, Z≤Z max .

[0145] The element P in the verification matrix H i,j The process of converting a matrix into a cyclic shift matrix or a zero matrix can be achieved using the conversion function g(V). i,j Z) represents the following:

[0146]

[0147] Where % represents the modulo operation; V i,j The value can be predefined, for example, through a protocol, such as in Tables 5.3.2-2 and 5.3.2-3 of the 3rd Generation Partnership Project (3GPP) technical specification (TS) 38.212.

[0148] With Z=4, Z max For example, if the value is 8, the element P in the check matrix... i,j The correspondence between these matrices and cyclic shift matrices or all-zero matrices is as follows:

[0149] The matrix corresponding to the element "-1" That is, an all-zero matrix; elements "0" to "7" correspond to a cyclic shift matrix, where elements "0" and "4" correspond to a matrix The matrix corresponding to elements "1" and "5" The matrix corresponding to elements "2" and "6" The matrix corresponding to elements "3" and "7"

[0150] 4. Base graph (BG) and base matrix

[0151] In some implementations, the base graph can be simplified as a table indicating the row and column positions of non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0152] A base graph can be represented as a graph of dimension m. b ×n b The basis matrix is ​​m. The basis matrix can be used to construct the parity-check matrix of a QC-LDPC code. b ×n b The corresponding check matrix has a dimension of (m) b ×Z)×(n b As can be seen, each element in the basis matrix can be replaced with a matrix of dimension Z×Z, becoming a submatrix of dimension Z×Z in the parity matrix.

[0153] It should be noted that the terms "Z×Z matrix" and "Z×Z submatrix" mentioned above refer to different objects. A single element in the base matrix can replace a Z×Z matrix, which is only a part of the parity check matrix; therefore, it is called a submatrix of the parity check matrix.

[0154] A basis matrix can include zero elements and non-zero elements. Zero elements in a basis matrix can be replaced with a Z×Z matrix of all zeros; non-zero elements in a basis matrix can be a Z×Z cyclic parity check matrix P. i,j Let i and j represent the row and column positions of the non-zero elements in the basis matrix, respectively, and P i,j The specific cyclic shift matrix to be replaced can be determined by the transformation function g(V) mentioned above. i,j The determination is made by Z, which will not be elaborated here.

[0155] In the basis matrix, zero elements can be represented by 0, and non-zero elements can be represented by 1. The number of bits for cyclic shift can be determined according to the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, zero elements can be represented by -1, non-zero elements by 0, and the number of bits for the circular shift can be determined by the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, a zero element can be represented by -1, a non-zero element can be represented by a value greater than or equal to 0, and the number of digits in a cycle can be indicated by the value of the non-zero element. This application does not limit this.

[0156] Currently, the NR protocol defines two base maps: BG 1 and BG 2. BG 1 defines a base matrix with a dimension of 46×68 and a core matrix with a dimension of 4×26, and is mainly used for scenarios with high throughput requirements, high bit rate, and long code length. BG 2 defines a base matrix with a dimension of 42×52 and a core matrix with a dimension of 4×14, and is mainly used for scenarios with low throughput requirements, low bit rate, and short code length.

[0157] Figure 7This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application. Figure 7 The structure of the verification matrix shown is a Raptor-like structure, which is quite common in 5G. For example... Figure 7 As shown, the parity check matrix of the Raptor-like LDPC structure includes the following five parts:

[0158] Part A: Information bits of the core array;

[0159] Part B: The parity bit portion of the core array, which has a double diagonal structure;

[0160] Part C: All-zero matrix;

[0161] Part D: The information bit portion of the extended array;

[0162] Part E: The parity bit portion of the extended matrix, which has a single diagonal structure.

[0163] It should be understood that the descriptions of the core matrix, all-zero matrix, and extended matrix mentioned above are all relative to their respective parts. In the parity check matrix, the core matrix can be called the core submatrix, the all-zero matrix can be called the all-zero submatrix (or simply, the all-zero submatrix), and the extended matrix can be called the extended submatrix.

[0164] The verification matrix includes the core matrix H core and extended array H ext Among them, the core array H core include Figure 7 Parts A and B (shown in thick black boxes in the diagram) constitute a high-bitrate parity-check matrix, which can be represented as [AB]. Its dimension is M. core ×N core M core ≤M, N core ≤N, and also satisfies: N core =M core +K. Based on the core array H core Scalable generation of extended matrix H ext , can correspond to Figure 7 The D and E parts. Extended array H ext Each additional row adds one column to the parity check matrix H. It should be understood that the names of the various parts above are for ease of distinction only and should not constitute any limitation on this application. For example, part A can also be called the high-bitrate information column region, part B can also be called the high-bitrate core parity check region, and parts D and E can also be called incremental redundancy regions.

[0165] It should be noted that since the parity-check matrix can be generated based on the basis matrix, and each element in the basis matrix can be converted into a Z×Z matrix, the dimension M of the core matrix is... core ×Ncore It can also correspond to a basis matrix with dimension (M) core / Z)×(N core The parity-check matrix is ​​a submatrix of ( / Z). Since part C of the parity-check matrix is ​​an all-zero submatrix and part E is a diagonal submatrix, both having relatively regular structures, the description of the parity-check matrix or basis matrix can primarily focus on parts A, B, and D. For ease of explanation and understanding, parts C and E will not be described in detail later, but those skilled in the art will understand that once the core matrix and extended matrix are determined, the other parts can be obtained based on the aforementioned structure, thus yielding the complete parity-check matrix.

[0166] It should also be noted that in some implementations, the core matrix may include rows and / or columns other than parts A and B. For example, the number of rows in the core matrix is ​​the number of rows in matrix [AB] + 1, and the number of columns in the core matrix is ​​the number of columns in matrix [AB] + 1. The core matrix is ​​defined exemplarily for the convenience of understanding the embodiments of this application and should not constitute any limitation on this application. This application does not limit the dimensions of the core matrix. Unless otherwise specified, the core matrix will still be understood as [AB] below.

[0167] For example, Figure 8 These are two different dimensions of Raptor-like structures provided in the embodiments of this application. The 5G protocol defines two different BGs: BG 1 and BG 2, as follows: Figure 8 As shown in (a) and (b) in the figure. Figure 8 In the structure shown in (a), BG 1 has a size of 46×68, and the core array H core Its size is 4×26, and it is mainly used in scenarios with high throughput requirements, high bit rate, and long bit length. Figure 8 In the structure shown in (b), BG2 has a size of 42×52, and the core array H... core The size is 4×14, and it is mainly used in scenarios with low throughput requirements, low bit rate, and short bit length.

[0168] In practical applications, the choice of which block size (BG) to use to generate the parity check matrix for LDPC encoding and decoding can be determined based on the transport block size (TBS) and the code rate. Figure 9An example of the relationship between BG selection, TBS, and bitrate is shown. As illustrated, if A ≤ 292; or A ≤ 3824 and R ≤ 0.67; or R ≤ 0.25, BG 2 is selected; otherwise, BG 1 is selected. Here, the message block length A is the TBS excluding CRC, and R is the bitrate indicated by the MCS index, which can be understood as the desired bitrate, referred to as the target bitrate, rather than the actual bitrate.

[0169] Multivariate LDPC codes (or non-binary LDPC codes) are an extension of LDPC codes. Their key feature is that the elements in the parity-check matrix are no longer limited to the binary field GF(2), but extended to the multivariate field GF(q), where q is a power of 2, i.e., q = 2^p, and p is a positive integer. Suppose we construct LDPC codes in the binary field GF(2) and the multivariate field GF(q), respectively. The corresponding parity-check matrices can be represented as H2 and Hq. H2 consists of elements 0 and 1, while Hq consists of elements 0, 1, 2, ..., q-1. Each element in Hq is a composite of p elements in H2. Suppose a value 'a' in the multivariate field GF(q) of q = 2p is associated with a 1*p binary vector. Substituting this vector into Hq yields the binary representation of Hq. The main characteristic of multivariate LDPC codes is that the elements in the parity-check matrix are no longer limited to the binary field GF(2), but extended to the multivariate field GF(q). This extension brings higher transmission efficiency and stronger error correction capabilities, making it particularly suitable for complex channel environments that require efficient transmission and multi-level modulation.

[0170] Multi-level LDPC codes, due to their superior performance, have broad application prospects in wireless communication, fiber optic communication, satellite communication, data storage, and other fields. They are particularly effective in complex channel environments requiring high-efficiency transmission and multi-level modulation. Furthermore, with the continuous development of communication technologies, research on multi-level LDPC codes is deepening, and they are expected to be applied and promoted in even more fields in the future.

[0171] In existing multi-dimensional LDPC code matrix schemes, the parity-check matrices are all independently optimized and are unrelated to the binary matrix of the NR encoding and decoding standard. Furthermore, the base map size of the core matrix of the multi-dimensional LDPC code is a 2x4 matrix of all 1s, indicating that the highest code rate supported by this LDPC code is only 0.5. If a higher code rate is needed, it must be achieved through puncturing, which may result in some performance loss in LDPC encoding and decoding.

[0172] In view of the problems existing in the prior art, this application provides a method for generating a parity check matrix, which can optimize the encoding and decoding performance of multivariate LDPC codes by designing the positions of non-zero elements in the base matrix.

[0173] Figure 10 This is a schematic flowchart illustrating a method for generating a verification matrix provided in an embodiment of this application. Figure 10 The method shown can be executed by a communication device, which can be a communication equipment, such as a network device or a terminal device, or a component configured in the communication equipment, such as a circuit or chip inside the communication equipment (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software that can implement some or all of the functions of the communication device, etc. This application does not limit it in this regard.

[0174] It should be understood that the parity-check matrix generated based on this method can be used for both LDPC encoding and LDPC decoding. Therefore, Figure 10 The method shown can be applied to the encoding end, for example, it can be used by... Figure 4 The device shown, 400A, performs this action; it can also be applied to a decoding end, for example, it can be executed by... Figure 4 The device 400B shown is used to perform this action.

[0175] Figure 10 The method 1000 for generating the parity check matrix shown may include steps 1010 to 1020. The following describes... Figure 10 Each step in the method 1000 shown is described in detail.

[0176] 1001, obtain the basis matrix.

[0177] It should be understood that the base matrix includes a first matrix, which is a matrix composed of rows 1 to 4 and columns 1 to 10 of the base matrix; that is, the first matrix is ​​a 4x10 matrix, and it is located in the top left corner of the base matrix. The first matrix includes a second matrix, which is a 4x4 double-diagonal matrix with the first column having a weight of 3, and all columns except the first column having a weight of 2. The second matrix is ​​located in rows 1 to 4 and columns 7 to 10 of the first matrix, meaning it is located to the right of the first matrix.

[0178] In this base matrix, the first column contains non-zero elements, and this first column is a punched column.

[0179] Optionally, the average column weight of the first matrix is ​​2.4. Optionally, the average column weight is determined based on the threshold calculation of multivariate PRXIT commonly used in encoding matrix design. For example, the average number of non-zero elements in each column of the first matrix is ​​2.4.

[0180] It should be understood that the non-zero elements in the basis matrix in the embodiments of this application can be represented by 1, or by numerical values ​​in the value set corresponding to other multi-element fields. Assume that the value set of the non-zero elements corresponding to the 8-element field GF(8) is {1,2,3,4,5,6,7}, and the specific values ​​of the non-zero elements in the basis matrix come from the set {1,2,3,4,5,6,7}.

[0181] In one possible implementation, the first row of the first matrix corresponds to a first sequence, which is the sequence corresponding to replacing the non-zero elements in the first row with 1, and the first sequence is {1,0,1,0,1,0,1,1,0,0}; the second row of the first matrix corresponds to a second sequence, which is the sequence corresponding to replacing the non-zero elements in the second row with 1, and the second sequence is {1,1,0,1,0,1,0,1,1,0}; the third row of the first matrix corresponds to a third sequence, which is the sequence corresponding to replacing the non-zero elements in the third row with 1, and the third sequence is {1,0,0,1,1,0,1,0,1,1}; the fourth row of the first matrix corresponds to a fourth sequence, which is the sequence corresponding to replacing the non-zero elements in the fourth row with 1, and the fourth sequence is {1,0,0,1,1,0,1,0,1,1}.

[0182] Assuming that all non-zero elements in the basis matrix are 1, the first matrix in the basis matrix can be represented as:

[0183]

[0184] Furthermore, assume that the non-zero elements in this basis matrix take values ​​from the set of values ​​corresponding to the multivariate field. Taking an 8-tuple field as an example, the set of values ​​corresponding to GF(8) is {1,2,3,4,5,6,7}, and the first matrix in this basis matrix can be represented as:

[0185]

[0186] It should be understood that the above is merely an example of the first matrix, and no specific representation of the first matrix is ​​limited.

[0187] In another possible implementation, the size of the base matrix can be a 25-row, 31-column matrix. For example... Figure 11 As shown, Figure 11 This diagram illustrates a matrix obtained by replacing all non-zero elements in a base matrix with 1. The base matrix consists of 25 rows and 31 columns. The first column of this base matrix contains only non-zero elements.

[0188] Optionally, the code rate R corresponding to the multivariate LDPC code determined based on this basis matrix can satisfy: Where m = 6, 7, ..., 26, 27. It can be seen that when m = 6, the code rate R corresponding to this multi-element LDPC code can reach 2 / 3 (approximately 0.67).

[0189] It should be understood that the first column of the basis matrix is ​​the punctured column; correspondingly, the codewords in the first column of the basis matrix in the encoded codewords of this multi-element LDPC code need to be punctured. Therefore, the basis matrix designed by the method of this application enables the highest code rate obtained by the multi-element LDPC code to be...

[0190] 1002, the parity check matrix of the multivariate LDPC code is obtained from the basis matrix.

[0191] In one possible implementation, the value of the non-zero element in the i-th row of the basis matrix obtained in step 1001 is determined based on elements in a first set, which is the set of optimal tuples of GF(q), and the row weight of the i-th row is equal to the number of elements included in the first set. Here, q is a power of 2 and is an integer greater than 2.

[0192] The specific value of q in GF(q) can be predefined by the protocol, preconfigured by the system, or indicated by indication information; this application does not impose any limitations on this. Assuming the specific value of q is indicated by indication information, this indication information can be carried in RRC signaling and semi-statically indicated to the communication device.

[0193] The following is a brief introduction to the optimal tuple in a multivariate field.

[0194] The values ​​of the multivariate field can be represented as a submatrix of the binary field. The optimal tuple is the combination of non-zero elements in each row of the multivariate matrix. This tuple can be replaced by a binary submatrix to obtain a matrix that can serve as a binary linear block code. The tuple with the largest minimum code distance and the smallest number of minimum weight codewords is selected as the optimal tuple. A detailed description of the optimal tuple can be found in existing schemes and will not be repeated here.

[0195] Taking GF(8) as an example, suppose that the primitive polynomial of GF(8) and x can be expressed as: p(x) = x 3 +x+1, then its binary submatrix can be represented as:

[0196]

[0197] Among them, the seven values ​​of the non-zero elements corresponding to GF(8) correspond to different powers of the matrix A mentioned above: {A k :k=1,…,7}.

[0198] Suppose that the set of optimal tuples corresponding to GF(8) is shown in Table 1:

[0199] Table 1: GF(8) optimal tuples

[0200] Tuple size tuple values 3 0，3，6 4 0，2，4，5 5 0，1，2，4，5 6 0，1，2，3，4，5 7 0，1，2，3，4，5，6

[0201] It should be understood that the values ​​in Table 1 above are in the form of powers of primitive elements. When filling the non-zero elements in the base matrix with the values ​​from Table 1, it is necessary to increment each value in the set by 1. That is, the values ​​of the elements raised to the power of 0 of the primitive elements are filled into the positions corresponding to the non-zero elements in the matrix. For example, taking the first row of the first matrix in the above base matrix as an example, assuming the row weight of the first row is 5, then based on this row weight of 5, the first set corresponding to tuples of size 5 is selected from Table 1. This first set of tuples of size 5 contains 5 elements. The tuple values ​​{0,1,2,4,5} corresponding to the size 5 of the tuple represent the powers of the primitive elements. Then, performing mathematical operations on each value in the tuple values ​​{0,1,2,4,5} (e.g., incrementing each value by 1) yields the values ​​of the non-zero elements in the first row. The first row can be represented as {1,0,2,0,6,0,3,5,0,0} or {3,0,5,0,1,0,2,6,0,0}. The order of the non-zero elements in the first row and the tuple values ​​in the optimal tuple can be arbitrary, and this application does not impose any restrictions on this.

[0202] It should also be understood that the values ​​of the non-zero elements in the other rows of the basis matrix are similar to those of the non-zero elements in the first row of the first matrix, and will not be described in detail here.

[0203] Furthermore, assume that the set of optimal tuples corresponding to GF(8) is shown in Table 2:

[0204] Table 2: GF(8) optimal tuples

[0205] Tuple size tuple values 3 1，4，7 4 1，3，5，6 5 1，2，3，5，6 6 1，2，3，4，5，6 7 1，2，3，4，5，6，7

[0206] It should be understood that the values ​​in Table 2 above are tuple values ​​of the primitive element raised to the power of 0. These values ​​can be directly filled into the non-zero element positions in the basis matrix. For example, taking the third row of the first matrix in the above basis matrix as an example, assuming the row weight of the third row in the first matrix is ​​6, then based on this row weight of 6, the first set corresponding to the tuple size of 6 is selected from Table 2 above. The first set corresponding to the tuple size of 6 includes 6 elements. The tuple values ​​{1,2,3,4,5,6} corresponding to the tuple size of 6 are tuple values ​​of the primitive element raised to the power of 0. Therefore, the values ​​of the tuple values ​​{1,2,3,4,5,6} are directly filled into the non-zero element values ​​in the third row. The third row can be represented as {1,0,0,2,3,0,4,0,5,6} or {2,0,0,3,1,0,4,0,6,5}. The order of the non-zero elements in the third row and the tuple values ​​in the optimal tuple can be arbitrary, and this application does not impose any restrictions on this.

[0207] It should also be understood that the values ​​of the non-zero elements in the other rows of the basis matrix are similar to those of the non-zero elements in the third row of the first matrix mentioned above, and will not be described in detail here.

[0208] It should also be understood that the above method of replacing the values ​​of non-zero elements in the corresponding rows based on the values ​​of tuples in the optimal tuple can be applied to the entire parity check matrix of the multivariate LDCP code, or it can be applied only to the first matrix in the basis matrix.

[0209] Similar to GF(8) above, the set of optimal tuples corresponding to GF(4) can be represented as shown in Table 3 and Representation 4 below:

[0210] Table 3

[0211]

[0212]

[0213] It should be understood that the values ​​in Table 3 above are the powers of the primitive elements corresponding to GF(4). Similar to Table 1 above, when filling the non-zero elements in the base matrix with the values ​​in Table 3, it is necessary to increment each value in the set by 1, that is, to fill the non-zero elements in the matrix with the zero power of the primitive element. Based on the row weight of each row in the base matrix, select the tuple size that is equal to the row weight from Table 3, perform mathematical operations on the elements in the set corresponding to the tuple size that is equal to the row weight (e.g., increment each value by 1), and fill them into the non-zero elements in the row corresponding to that row weight. The order of the elements included in the optimal tuple set and the order of the non-zero elements in that row are not restricted.

[0214] Table 4

[0215] Tuple size tuple values 3 1，2，3 4 1，1，2，3 5 1，1，2，2，3 6 1，1，2，2，3，3

[0216] It should be understood that the values ​​in Table 4 above are the tuple values ​​of the primitive element corresponding to GF(4) raised to the power of 0. Similar to Table 2 above, the values ​​in Table 4 can be directly filled into the positions of non-zero elements in the basis matrix. Based on the row weight of each row in the basis matrix, a tuple size equal to the row weight is selected from Table 4, and the elements in the set corresponding to the tuple size equal to the row weight are directly filled into the positions of non-zero elements in the row corresponding to that row weight. The order of the elements included in the optimal tuple set and the order of the non-zero elements in that row are not restricted.

[0217] It should also be understood that the above method of replacing the values ​​of non-zero elements in the corresponding rows based on the values ​​of tuples in the optimal tuple can be applied to the entire parity check matrix of the multivariate LDCP code, or it can be applied only to the first matrix in the basis matrix.

[0218] In another possible implementation, if all non-zero elements in the i-th row of the basis matrix obtained in step 1001 are 1, then the elements in the basis matrix are either 0 or 1. The communication device obtains the parity check matrix of the multi-dimensional LDPC code based on the basis matrix, including: the communication device obtains the parity check matrix of the multi-dimensional LDPC code based on a third matrix, which is determined based on the basis matrix. For example, the process of determining the third matrix may include the following steps 1 and 2:

[0219] Step 1: Based on the row weight of the i-th row in the basis matrix, select a second set corresponding to the i-th row from the set of the optimal tuples of GF(q), where the row weight of the i-th row is equal to the number of elements in the second set.

[0220] Assuming q = 8, the row weight of the i-th row in the basis matrix is ​​5. Based on the row weight of 5 in the i-th row, the communication device selects a second set corresponding to the row weight of 5 from the set of the optimal tuples in GF(8). The second set contains 5 elements. Combining the example of the optimal tuples corresponding to GF(8) introduced in step 1001 above, the row with a row weight of 5 in the basis matrix can be the first row, which can be represented as {1,0,1,0,1,0,1,1,0,0}. Based on the optimal tuples in GF(8), the tuple values ​​corresponding to the tuple size of 5 can be selected from Table 1 above, that is, the second set can be represented as {0,1,2,4,5}. Based on the optimal tuples in GF(8), the tuple values ​​corresponding to the tuple size of 5 can be selected from Table 2 above, that is, the second set can be represented as {1,2,3,5,6}.

[0221] It should be understood that the i-th row in the basis matrix can be any row in the basis matrix.

[0222] Step 2: Replace the non-zero elements in the i-th row of the base matrix with elements related to the elements in the second set to obtain the i-th row of the third matrix.

[0223] As an example, taking the optimal tuple corresponding to GF(8), the row with a row weight of 5 in the basis matrix can be the first row, which can be represented as {1,0,1,0,1,0,1,1,0,0}. According to the optimal tuple of GF(8), the tuple values ​​corresponding to the tuple size of 5 are selected from Table 1 above, that is, the second set can be represented as {0,1,2,4,5}. The communication device adds 1 to each element in the second set and replaces the 1 on the non-zero elements in the first row to obtain the first row of the third matrix. Then the first row of the third matrix can be represented as {1,0,2,0,3,0,5,6,0,0} or {3,0,5,0,1,0,2,6,0,0}, etc. The values ​​of each element in the second set correspond one-to-one with the values ​​of the non-zero elements in the first row, and the order of correspondence is not limited.

[0224] As another example, taking the optimal tuple corresponding to GF(8) as an example, the row with a row weight of 5 in the basis matrix can be the first row, which can be represented as {1,0,1,0,1,0,1,1,0,0}. According to the optimal tuple of GF(8), the tuple values ​​corresponding to the tuple size of 5 are selected from Table 1 above, that is, the second set can be represented as {1,2,3,5,6}. The communication device can directly replace the 1s on the non-zero elements in the first row with the elements in the second set to obtain the first row of the third matrix. Then the first row of the third matrix can be represented as {1,0,2,0,3,0,5,6,0,0} or {3,0,5,0,1,0,2,6,0,0}, etc. The values ​​of each element in the second set correspond one-to-one with the values ​​of the non-zero elements in the first row, and the order of correspondence is not limited.

[0225] Taking the first matrix in the basis matrix as an example, the elements of this first matrix are either 0 or 1. This first matrix can be represented as:

[0226]

[0227] Assuming q = 8, then the new matrix corresponding to the first matrix obtained from the optimal tuple of GF(8) can be represented as:

[0228]

[0229] Similarly, the non-zero elements in each row of the base matrix are replaced with elements related to the elements in the second set corresponding to that row, resulting in a third matrix. That is, the positions of the non-zero elements in this third matrix are the same as those in the base matrix. The communication device then uses this third matrix to obtain the parity check matrix of the multivariate LDPC code. Specifically, the communication device can determine the parity check matrix of the multivariate LDPC code based on the spread factor and the offset values ​​corresponding to each element.

[0230] In another possible implementation, the values ​​of the non-zero elements in the j-th row of the basis matrix obtained in step 1001 are determined based on the elements in the third set. The third set is selected from the element value mapping relationship of the multivariate Galois field GF(q) according to the row index. The row weight of the j-th row is equal to the number of elements included in the third set, where q is a power of 2 and q is an integer greater than 2.

[0231] It should be understood that the element value mapping relationship of GF(q) can be predefined by the protocol or preconfigured by the system, and this application does not limit this. The following will use GF(8) as an example, and provide an exemplary table of element value mapping relationships for GF(8) in conjunction with Table 5:

[0232] Table 5

[0233]

[0234]

[0235] It should be understood that Table 5 shows the optimal set of element values ​​for the multivariate fields corresponding to different row indices. Each element in this set of multivariate values ​​corresponds one-to-one with the position of the non-zero element in the row corresponding to the row index.

[0236] It should be understood that the mapping relationship table shown in Table 5 above can also be represented in other forms (e.g., text or relationship diagrams), etc.

[0237] For example, the base matrix comprises 25 rows and 31 columns, and Table 5 above shows the multivariate value sets corresponding to the 25 row indices. The number of elements in the multivariate value set corresponding to each row index is equal to the row weight of the row corresponding to that index. For example, the row weight of the first row in the base matrix shown above (i.e., the first row of the first matrix) is 5, and the multivariate value set corresponding to row index 1 is {2,1,6,4,7}. The communication device directly fills the values ​​from {2,1,6,4,7} into the non-zero element values ​​of the first row of the base matrix according to Table 5. The order of the non-zero element values ​​in the first row and the tuple values ​​in the multivariate value sets can be arbitrary, and this application does not impose any restrictions on this.

[0238] In another possible implementation, if all non-zero elements in the j-th row of the basis matrix obtained in step 1001 are 1, that is, if the elements in the basis matrix are 0 or 1, then the communication device obtains the parity check matrix of the multi-dimensional LDPC code based on the basis matrix, including: the communication device obtains the parity check matrix of the multi-dimensional LDPC code based on a fourth matrix, which is determined based on the basis matrix.

[0239] For example, the process of determining the fourth matrix may include the following steps 3 and 4:

[0240] Step 3: Based on the row index of the j-th row in the base matrix, select the fourth set corresponding to the row index from the element value mapping relationship of GF(q). The row weight of the j-th row is equal to the number of elements included in the fourth set.

[0241] Assuming q = 8 and j = 1, the row index of the first row in the base matrix is ​​1. Based on the row index 1 of the first row, the communication device selects the fourth set corresponding to row index 1 from the element value mapping relationship of GF(8). This fourth set is {2, 1, 6, 4, 7}. Here, based on the above description of the row weight of the first row of the base matrix corresponding to GF(8), which is 5, equal to the number of elements (5) included in the fourth set corresponding to row index 1. Referring to the example of the base matrix corresponding to GF(8) described in step 1001 above, the first row can be represented as {2, 0, 1, 0, 6, 0, 4, 7, 0, 0}, or {6, 0, 7, 0, 2, 0, 4, 1, 0, 0}, etc. This application does not limit the order of the values ​​of the non-zero elements included in the i-th row and the values ​​of the elements in the fourth set.

[0242] It should be understood that the j-th row in the basis matrix can be any row in the basis matrix, and the values ​​of the non-zero elements in the other rows of the basis matrix are similar to those in the first row above.

[0243] Step 4: Replace the non-zero elements in the j-th row of the base matrix with elements from the fourth set to obtain the j-th row of the fourth matrix.

[0244] As an example, combining the element value mapping table of GF(8) (Table 5) above, the communication device selects the fourth set corresponding to the row index of the j-th row from Table 5 according to the row index of the j-th row in the base matrix and Table 5 above, and replaces the non-zero elements of the j-th row in the base matrix with the elements included in the fourth set to obtain the j-th row of the fourth matrix. Each element included in the fourth set corresponds one-to-one with the non-zero element of the j-th row, and the order of correspondence is not limited.

[0245] Taking the first matrix in the basis matrix as an example, the elements of this first matrix are either 0 or 1. This first matrix can be represented as:

[0246]

[0247] Assuming q = 8, then according to Table 5 above, the new matrix corresponding to the first matrix can be represented as:

[0248]

[0249] Similarly, each non-zero element in each row of the base matrix is ​​replaced with an element from the fourth set corresponding to that row, resulting in a fourth matrix. That is, the positions of the non-zero elements in this fourth matrix are the same as those in the base matrix. The communication device then obtains the parity-check matrix of the multivariate LDPC code based on this fourth matrix. Specifically, the communication device can determine the parity-check matrix of the multivariate LDPC code based on the spread factor and the offset values ​​corresponding to each element.

[0250] It should be understood that the detailed explanation of how the communication device determines the parity check matrix of the multivariate LDPC code based on the fourth matrix, the expansion factor, and the offset value is similar to that of existing schemes for determining the parity check matrix, and will not be elaborated here.

[0251] In this application, when the code rates of the multivariate LDPC codes are different, the offset values ​​corresponding to at least one non-zero element in the basis matrix of the multivariate LDPC codes are different; and / or, when the spread factors of the multivariate LDPC codes are different, the offset values ​​of at least one non-zero element in the basis matrix of the multivariate LDPC codes are different.

[0252] The following example, using an expansion factor Z=23, illustrates the values ​​of the offset corresponding to at least one non-zero element in the base matrix under different code rates.

[0253] Example 1: Assume the code rate of the multivariate LDPC code is 0.67. Taking the first matrix in the basis matrix as an example, the offset values ​​corresponding to each element in the first matrix are shown in Table 6. "-1" indicates that there is no value, that is, the position of the element "-1" corresponds to the weight 0 matrix.

[0254] Table 6

[0255] 22 -1 8 -1 1 -1 5 11 -1 -1 19 21 -1 10 -1 8 -1 4 22 -1 2 -1 -1 8 14 -1 5 -1 1 11 16 8 4 -1 2 22 7 -1 -1 14

[0256] Example 2: Assuming the code rate of the multivariate LDPC code is 0.5, taking the matrix consisting of rows 1 to 7 and columns 1 to 13 of the base matrix as an example, the offset values ​​corresponding to each element in this matrix are shown in Table 7. Empty positions in the matrix indicate that no value has been taken:

[0257] Table 7

[0258] 19 3 1 1 14 13 4 0 11 3 9 2 8 5 11 18 9 16 10 14 7 4 14 21 21 5 21 4 8 14 14 3 8 22 22 4

[0259] Example 3: Assuming the code rate of the multivariate LDPC code is 0.4, taking the matrix consisting of rows 1 to 10 and columns 1 to 16 of the base matrix as an example, the offset values ​​corresponding to each element in this matrix are shown in Table 8. Empty positions in the matrix indicate that no value has been taken:

[0260] Table 8

[0261] 10 5 3 14 12 8 7 3 18 8 12 8 14 18 16 1 3 19 17 0 4 22 11 5 17 15 9 8 14 0 8 8 21 17 12 15 3 19 10 5 21 22 17 15 10 0

[0262] Example 4: Assuming the code rate of the multivariate LDPC code is 0.33, taking the matrix consisting of rows 1 to 13 and columns 1 to 19 of the base matrix as an example, the offset values ​​corresponding to each element in this matrix are shown in Table 9. Empty positions in the matrix indicate that no value has been taken:

[0263] Table 9

[0264] 8 18 7 12 2 8 9 10 4 10 22 13 21 9 7 11 11 21 7 6 3 5 5 3 22 20 22 20 9 21 3 2 21 10 12 11 3 20 19 19 1 5 21 7 10 16 8 22 14 10 22 18 6 20 15 20 13

[0265] Example 5: Assuming the code rate of the multivariate LDPC code is 0.25, taking the matrix consisting of rows 1 to 19 and columns 1 to 25 of the base matrix as an example, the offset values ​​corresponding to each element in this matrix are shown in Table 10. Empty positions in the matrix indicate that no value is taken:

[0266] Table 10

[0267] 8 22 0 1 6 0 2 1 1 3 14 0 8 8 0 0 19 8 7 12 10 8 16 9 17 4 2 10 22 14 19 20 21 15 12 3 9 5 14 21 6 16 15 16 20 7 4 10 2 17 11 10 12 19 15 1 21 3 17 20 12 22 0 5 21 1 22 12 17 19 3 1 6 10 5 16

[0268] Example 6: Assuming the code rate of the multivariate LDPC code is 0.2, taking the matrix consisting of rows 1 to 25 and columns 1 to 31 of the base matrix as an example, the offset values ​​corresponding to each element in this matrix are shown in Table 11. Empty positions in the matrix indicate that no value has been taken:

[0269] Table 11

[0270]

[0271]

[0272] Optionally, the method further includes step 1003: performing LDPC encoding or LDPC decoding based on the parity check matrix.

[0273] As mentioned earlier, this parity check matrix can be used for LDPC encoding or LDPC decoding. If the communication device needs to send data, it can perform LDPC encoding based on this parity check matrix; if the communication device receives data, it can perform LDPC decoding based on this parity check matrix. The process will be briefly described below using LDPC encoding and LDPC decoding as examples.

[0274] LDPC encoding:

[0275] If a communication device needs to send data, it can encode the data before sending it. For example, the communication device can preprocess data obtained from a higher layer to obtain information bits to be encoded, and then perform LDPC encoding on the information bits based on a parity check matrix.

[0276] As mentioned earlier, the parity check matrix H satisfies:

[0277]

[0278] Where c represents the information bits to be encoded, including K information bits, for example denoted as c0, ..., c K－1 w represents (N+D-K) parity bits, for example, denoted as c K c N+D－K－1 .

[0279] The process of LDPC encoding based on the parity-check matrix H is as follows: K information bits c0, ..., c K－1 As input, given the parity check matrix H, the (N+D-K) parity bits c can be calculated. K c N+D－K－1 Therefore, the output can be obtained, which consists of (N+D) encoded bits: c0, ..., c K－1 c K c N+D－K－1 .

[0280] The encoded bits obtained can be transmitted after undergoing operations such as modulation, layer mapping, precoding, framing, IFFT, and IRF.

[0281] For a more detailed explanation of the steps before and after encoding, please refer to the preceding text. Figure 3 The relevant descriptions will not be repeated here.

[0282] LDPC decoding:

[0283] If the communication device receives data, it can decode the data and then send it to a higher layer. For example, the communication device can preprocess the signal received from the air interface, such as IRF, FFT, deframing, de-mapping, channel equalization, demodulation, etc., to obtain the encoded bits to be decoded, and then perform LDPC decoding on the encoded bits to be decoded based on the parity check matrix.

[0284] For example, the communication device can use the sum-product algorithm (SPA) and its simplified min-sum algorithm for decoding. For ease of distinction and explanation, the log-likelihood ratio (LLR) of the (N+D) coded bits obtained after demodulation of the signal received by the communication device is denoted as: q0,…,q N+D-1 These are also the initial values ​​of the posterior information for each variable node. The SPA algorithm uses the connection relationships between the variable nodes and check nodes in the check matrix H to iteratively update the posterior information q0,…,q for each variable node (corresponding to the received bit). N+D-1 Finally, the decision result for each variable node (i.e., the received encoded bits) is obtained based on the posterior information. For a more detailed explanation of the steps before and after decoding, please refer to the preceding text. Figure 3 The relevant descriptions will not be repeated here.

[0285] For ease of understanding, the data transmission process will be described here using the data interaction between this communication device and another communication device as an example. In the following text, for ease of distinction and explanation, this communication device will be referred to as communication device #1, and the other communication device with which it communicates will be referred to as communication device #2.

[0286] Communication device #1 preprocesses the information data received from higher layers to obtain a bit sequence to be encoded. Based on a parity-check matrix, it performs LDPC encoding on this bit sequence. The encoded bits are then transmitted after operations such as modulation, layer mapping, precoding, framing, IFFT, and IRF. Communication device #2 receives a signal over the air interface and performs preprocessing on the received signal, including IRF, FFT, deframing, de-layer mapping, channel equalization, and demodulation, to obtain encoded bits to be decoded. It then performs LDPC decoding on these encoded bits and transmits them to higher layers. Both the parity-check matrix used for LDPC encoding and the parity-check matrix used for LDPC decoding can be parity-check matrices obtained using the methods described above; that is, parity-check matrices obtained based on the first basis matrix.

[0287] It is understandable that communication device #1 and communication device #2 mentioned above can be interchanged; that is, communication device #2 sends data and performs LDPC encoding, while communication device #1 receives data and performs LDPC decoding. For the sake of brevity, further details will not be provided.

[0288] It should be understood that the above Figure 10 The method for generating the parity-check matrix shown increases the code rate range of the multivariate LDPC code obtained by designing the base matrix. At the same time, the code rate supported by the multivariate LDPC code can reach 0.67, thus improving the compilation performance of the multivariate LDPC code.

[0289] In addition, the method provided in this application is designed to obtain the multivariate field values ​​corresponding to the non-zero elements in the basis matrix. One method is to select a tuple size equal to the row weight from the optimal tuple of the corresponding GF(q) based on the row weight of each row in the basis matrix, and then select the position of the non-zero element in that row according to the set corresponding to the tuple size. The other method is to select the multivariate value set corresponding to the row index from the tuple value mapping relationship of the corresponding GF(q) based on the row index of each row in the basis matrix, and then select the position of the non-zero element in that row according to the set of multivariate values.

[0290] Based on the method provided in this application, assuming the information bit length K = 400 and the code rate R = 0.4, Figure 12 A simulation comparison diagram is shown. According to... Figure 12 As can be seen from the simulation comparison diagram, under low signal-to-noise ratio conditions, the method provided in this application ( Figure 12 The normalized new basemap in the middle) and the existing scheme #1 ( Figure 12 In the case of a medium-rate new base map (within a balanced state) and high signal-to-noise ratio, the method provided in this application is significantly superior to existing solutions. Specifically, existing solution #1 can only adapt to each bit rate interval within a medium-rate range, while the base matrix provided in this application can be compatible with all bit rates below 0.67. Compared to existing solution #1, the solution provided in this application achieves better performance when the frame error rate is 10... -6 When the above conditions are met, the method provided in this application performs comparably to the existing solution #1; when the frame error rate is 10... -6 The method provided in this application has a gain of approximately 0.1 dB.

[0291] The method provided in this application is different from the existing solution #2. Figure 12 A performance comparison between 5G LDPC codes shows that when the frame error rate is 10... -4 At that time, the gain was 0.15dB with a maximum of 20 iterations; when the frame error rate was 10... -7 At the maximum number of iterations (20), the gain is 0.95 dB. Table 12 shows the performance gain of the method provided in this application at different bit rates:

[0292] Table 12

[0293]

[0294] The above text combined Figures 7 to 12 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figures 13 to 14 This describes an embodiment of the apparatus described in this application.

[0295] It is understandable that, in order to achieve the functions described in the above embodiments, Figures 13 to 14 The apparatus includes hardware structures and / or software modules that perform various functions. Those skilled in the art will readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0296] As an example, Figure 13 and Figure 14 These are schematic block diagrams illustrating possible apparatuses provided in embodiments of this application. These apparatuses can be used to implement the functions of the communication apparatus in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0297] Figure 13 A schematic block diagram of a communication device provided in an embodiment of this application. Figure 13 The device 1300 shown may include a processing module 1310 and a communication module 1320.

[0298] In one possible design, device 1300 can be used to implement Figure 10 The embodiment shown illustrates a communication method implemented by a communication device. For example, processing module 1310 is used to implement processing-related steps such as acquisition and encoding / decoding performed by the communication device in steps 1001 to 1003 of method 1000, and communication module 1320 can be used to implement steps such as sending and / or receiving performed by the communication device in method 1000.

[0299] For example, the processing module 1310 can be used to: obtain a base matrix; obtain a parity check matrix of a multivariate LDPC code based on the base matrix; and perform LDPC encoding or LDPC decoding based on the parity check matrix.

[0300] For a more detailed description of the processing module 1310 and the communication module 1320 mentioned above, please refer to [link / reference]. Figure 10 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0301] It should be noted that the communication module can also be called a transceiver module, transceiver unit, transceiver, transceiver device, or transceiver apparatus, etc. The processing module can also be called a processor, processing board, processing unit, or processing apparatus, etc. Optionally, the communication module is used to execute the sending and receiving operations of the first or second communication device in the above method. The device in the communication module that implements the receiving function can be considered as the receiving module, and the device in the communication module that implements the sending function can be considered as the sending module; that is, the communication module can include both a receiving module and a sending module.

[0302] It should also be noted that, in one possible design, the aforementioned processing module and / or communication module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. In another possible design, the processing module or communication module can also be implemented through physical devices. For example, if the device is implemented using a chip / chip circuit, the communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module can be an integrated processor, a microprocessor, or an integrated circuit.

[0303] The module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional modules in the various examples of this embodiment can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0304] Figure 14 This is a schematic diagram of the structure of a communication device provided in yet another embodiment of this application. (See attached diagram.) Figure 14 As shown, the device 1400 includes a processing circuit 1410 and a communication circuit 1420. The processing circuit 1410 and the communication circuit 1420 are coupled to each other.

[0305] It is understood that the processing circuit 1410 can be one or more processors, or it can be all or part of the processing functions of one or more processors.

[0306] Understandably, the communication circuit 1420 can be a transceiver or an input / output interface.

[0307] Optionally, the device 1400 may further include a memory 1430 for storing instructions executed by the processing circuit 1410, or storing input data required for the running instructions of the processing circuit 1410, or storing data generated after the running instructions of the processing circuit 1410.

[0308] It is understood that the memory 1430 may be located outside the processing circuit 1410, or inside the processing circuit 1410.

[0309] As an example, the processing circuit 1410 is used to implement the functions of the processing module 1310, and the communication circuit 1420 is used to implement the functions of the communication module 1320.

[0310] As an example, device 1400 can be a communication device or a chip used in a communication device.

[0311] When device 1400 is a communication device, the communication circuit can be a transceiver; when device 1400 is a chip, the communication circuit can be an input / output circuit, a bus, pins, or other types of communication interfaces. The input circuit in the input / output circuit can be used for receiving, and the output interface can be used for transmitting.

[0312] In some embodiments of this application, a computer program product is also provided, which, when run on a processor, can implement the method for obtaining a verification matrix implemented by a communication device in the above method embodiments.

[0313] In some embodiments of this application, a computer-readable storage medium is also provided, which contains computer instructions that, when executed on a processor, can implement the method for obtaining a parity check matrix implemented by a communication device in the above-described method embodiments.

[0314] In some embodiments of this application, a communication system is also provided, including the aforementioned communication device, which can be used to implement the method for obtaining a parity check matrix implemented by the communication device in the above method embodiments.

[0315] It is understood that the processor in the embodiments of this application may be any of the following devices or all or part of the circuitry used for processing functions: a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0316] The terms “unit”, “module”, etc., used in this specification may be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution.

[0317] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0318] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0319] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0320] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0321] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0322] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. This computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0323] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0324] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for generating a parity check matrix, characterized in that, The method includes: Obtain a base matrix, wherein the base matrix includes a first matrix, which is a matrix composed of columns 1 to 10 and rows 1 to 4 of the base matrix; the first matrix includes a second matrix, which is a matrix composed of columns 7 to 10 and rows 1 to 4 of the first matrix; the first column of the second matrix has a column weight of 3; the other columns of the second matrix have a column weight of 2; all elements in the first column of the base matrix are non-zero elements; and the first column is a punched column. Based on the basis matrix, the parity check matrix of the multivariate low-density parity-check LDPC code is obtained, and the parity check matrix is ​​used for LDPC encoding or LDPC decoding.

2. The method according to claim 1, characterized in that, The first row of the first matrix corresponds to the first sequence, which is {1,0,1,0,1,0,1,0,1,1,0,0}. The first sequence is the sequence corresponding to replacing the non-zero elements in the first row with 1. The second row of the first matrix corresponds to the second sequence, which is {1,1,0,1,0,1,0,1,0,1,1,0}. The second sequence is the sequence corresponding to replacing the non-zero elements in the second row with 1. The third row of the first matrix corresponds to the third sequence, which is {1,0,0,1,1,0,1,0,1,1}. The third sequence is the sequence corresponding to replacing the non-zero elements in the third row with 1. The fourth row of the first matrix corresponds to the fourth sequence, which is {1,1,1,0,1,1,1,0,0,1}. The fourth sequence is the sequence corresponding to replacing the non-zero elements in the fourth row with 1.

3. The method according to claim 1 or 2, characterized in that, The code rate R of the multivariate LDPC code satisfies: Where m = 6, 7, ..., 26, 27.

4. The method according to any one of claims 1 to 3, characterized in that, The code rate of the multivariate LDPC code is R = 0.

67.

5. The method according to any one of claims 1 to 4, characterized in that, The base matrix comprises 25 rows and 31 columns, and the average column weight of the first matrix is ​​2.

4.

6. The method according to any one of claims 1 to 5, characterized in that, The values ​​of the non-zero elements in the i-th row of the basis matrix are determined based on the elements in the first set, which is the set of optimal tuples in the multivariate Galois field GF(q). The row weight of the i-th row is equal to the number of elements included in the first set, where q is a power of 2 and q is an integer greater than 2.

7. The method according to any one of claims 1 to 5, characterized in that, The elements in the basis matrix can take the value 0 or 1. Based on the basis matrix, the parity-check matrix of the multivariate LDPC code is obtained, including: Based on the row weight of the i-th row in the basis matrix, select a second set corresponding to the i-th row from the set of optimal tuples in the multivariate Galois field GF(q). The row weight of the i-th row is equal to the number of elements included in the second set, q is a power of 2, and q is an integer greater than 2. The non-zero elements in the i-th row of the base matrix are replaced with elements related to the elements in the second set to obtain the i-th row of the third matrix; Based on the third matrix, the check matrix of the multivariate LDPC code is obtained.

8. The method according to any one of claims 1 to 5, characterized in that, The values ​​of the non-zero elements in the j-th row of the basis matrix are determined based on the elements in the third set. The third set is selected from the element value mapping relationship of the multivariate Galois field GF(q) according to the row index. The row weight of the j-th row is equal to the number of elements included in the third set, where q is a power of 2 and q is an integer greater than 2.

9. The method according to any one of claims 1 to 5, characterized in that, The elements in the basis matrix can take the value 0 or 1. Based on the basis matrix, the parity-check matrix of the multivariate LDPC code is obtained, including: Based on the row index of the j-th row in the basis matrix, a fourth set corresponding to the row index is selected from the element value mapping relationship of the multivariate Galois field GF(q). The row weight of the j-th row is equal to the number of elements included in the fourth set, q is a power of 2, and q is an integer greater than 2. Replace the non-zero element in the j-th row of the base matrix with an element from the fourth set to obtain the j-th row of the fourth matrix; Based on the fourth matrix, the parity check matrix of the multivariate LDPC code is obtained.

10. The method according to claim 6 or 7, characterized in that, The method further includes: Receive first indication information, which indicates the value of q corresponding to the multivariate Galois domain GF(q).

11. The method according to any one of claims 1 to 10, characterized in that, When the code rates of the multivariate LDPC codes are different, the offset values ​​corresponding to at least one non-zero element in the basis matrix of the multivariate LDPC codes are different; and / or, When the expansion factors of the multivariate LDPC codes are different, the offset values ​​corresponding to at least one non-zero element in the basis matrix of the multivariate LDPC codes are different.

12. A communication device, characterized in that, It includes functional modules for implementing the method as described in any one of claims 1 to 11.

13. A communication device, characterized in that, include: One or more processors and communication circuitry, the communication circuitry being used by the communication device to perform at least one of signal input or output; the one or more processors being used to implement the method as described in any one of claims 1 to 11.

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