Audio signal amplification and noise reduction system of satellite handheld terminal docking station

Abstract

The invention belongs to the technical field of satellite communication, and particularly relates to an audio signal amplification and noise reduction system of a satellite handheld terminal docking station. Comprising a differential input port used for receiving an original audio signal output by a satellite hand-held terminal; the instrument amplifier is used for performing common-mode rejection and differential-mode amplification on the original audio signal to output a primary amplified audio signal; and the analog adaptive notch module is used for processing the primary amplified audio signal and outputting a notch output audio signal, and the analog adaptive notch module comprises an interference frequency detection unit, a bias current generation unit and a transconductance-capacitance notch filtering unit. According to the invention, common-mode interference and periodic interference can be effectively suppressed in a complex electromagnetic environment, dynamic change of interference frequency is automatically adapted, stability and consistency of output volume are kept, and satellite communication call quality is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of satellite communication, and particularly relates to an audio signal amplification and noise reduction system of a satellite handheld terminal docking station. BACKGROUND

[0002] As a communication device directly used by users, a satellite handheld terminal undertakes multiple functions such as voice communication, short message sending and receiving, and positioning. However, the satellite handheld terminal is limited by strict constraints on volume, weight and power consumption, and the size and output power of the loudspeaker are often small, which is difficult to meet the use requirements in noisy environments or occasions requiring multiple people to listen. In order to solve this problem, the docking station as a supporting peripheral of the satellite handheld terminal emerges as the times require, and the audio output capability is enhanced through external voice handles or high-power loudspeakers to improve the communication experience.

[0003] The docking station needs to obtain the audio signal from the satellite handheld terminal and amplify it to drive the external loudspeaker. This audio signal transmission and processing process faces many technical challenges. First, the satellite handheld terminal will generate strong radio frequency radiation in the working state, and the transmit power of the S-band is usually about 2 watts. The radio frequency energy will enter the audio circuit through space coupling or conductive coupling, introducing interference in the audio channel. Secondly, the satellite mobile communication system generally adopts a time division multiple access system, and the radio frequency power amplifier is periodically turned on and off according to a specific frame structure. This periodic radio frequency transmission will induce a periodic interference signal related to the frame period in the audio circuit, which is manifested as a regular buzzing or beeping sound. In addition, the switching power supply, digital circuit clock and other electronic devices inside the docking station will also generate various electromagnetic interferences, which will superimpose on the audio signal and affect the communication quality. In view of the anti-interference problem in the audio signal transmission, the existing technology usually adopts a scheme combining differential transmission and differential reception. Differential transmission uses a shielded twisted pair as the transmission medium, and transmits the audio signal in the form of differential mode on two wires, while external interference acts on the two wires in the form of common mode. The receiving end uses an instrument amplifier or a differential amplifier to extract the differential mode signal and suppress the common mode interference, which can obtain a high common mode rejection ratio. This scheme has good suppression effect on the common mode interference coupled in space, but for the interference directly superimposed on the signal source or the residual interference that cannot be completely eliminated due to insufficient common mode rejection ratio, further signal processing means is still needed. SUMMARY

[0004] The main purpose of the present application is to provide an audio signal amplification and noise reduction system of a satellite handheld terminal docking station, which can effectively suppress common mode interference and periodic interference in a complex electromagnetic environment, automatically adapt to the dynamic changes of interference frequency, maintain the stability of the output volume, and significantly improve the communication quality of satellite communication.

[0005] To solve the above technical problems, the application provides an audio signal amplification and noise reduction system of a satellite handheld terminal docking station, which comprises: a differential input port configured to receive an original audio signal output by a satellite handheld terminal; an instrumentation amplifier connected to the differential input port and configured to perform common-mode rejection and differential-mode amplification on the original audio signal to output a primary amplified audio signal; an analog adaptive notch filter module connected to the instrumentation amplifier and configured to process the primary amplified audio signal and output a notch output audio signal, the analog adaptive notch filter module comprising an interference frequency detection unit, a bias current generation unit and a transconductance-capacitance notch filter unit, the interference frequency detection unit outputs an interference frequency count value, the bias current generation unit generates a transconductance control current based on the interference frequency count value, and the transconductance-capacitance notch filter unit receives the transconductance control current and performs notch processing on the primary amplified audio signal to output the notch output audio signal; a programmable gain amplifier configured to perform gain adjustment on the notch output audio signal and output a gain-adjusted audio signal; an amplitude detection unit connected to an output end of the programmable gain amplifier and configured to perform rectification and integration on the gain-adjusted audio signal to output an amplitude detection value; a microcontroller connected to the amplitude detection unit and the programmable gain amplifier and configured to collect the amplitude detection value and set a gain level based on the amplitude detection value; and a power amplifier configured to receive the gain-adjusted audio signal and drive a speaker unit of a voice handle to produce sound.

[0006] Further, the differential input port is connected to the satellite handheld terminal via a shielded twisted pair cable, two cores of the shielded twisted pair cable are connected to positive and negative ends of the differential input port respectively, and a shielding layer of the shielded twisted pair cable is connected to a shell ground of the docking station.

[0007] Further, the interference frequency detection unit comprises a zero-crossing comparator, an edge counter, a timing window generator and a frequency latch; a non-inverting input end of the zero-crossing comparator receives the primary amplified audio signal, an inverting input end of the zero-crossing comparator is connected to an analog ground potential, and the zero-crossing comparator outputs a rectangular pulse sequence corresponding to zero-crossing time points of the primary amplified audio signal.

[0008] Further, the timing window generator is composed of an oscillator and a frequency divider, the oscillator generates a clock signal, the frequency divider outputs a periodic window enable signal and a window end signal after frequency division of the clock signal; the edge counter accumulatively counts rising edges of the rectangular pulse sequence during the window enable signal is valid, and outputs the count value to the frequency latch and performs a clear reset when the window end signal arrives; and the frequency latch keeps the count value as an interference frequency count value before the next window end signal arrives.

[0009] Further, the bias current generation unit comprises a digital-to-analog converter, a voltage-to-current converter and a current mirror; the digital-to-analog converter receives the interference frequency count value and converts the interference frequency count value into a frequency indication voltage according to a frequency-to-voltage mapping table pre-stored in a read-only memory, the frequency-to-voltage mapping table stores a one-to-one correspondence between discrete count values and corresponding voltage values, and the digital-to-analog converter outputs the frequency indication voltage corresponding to the interference frequency count value by looking up the frequency-to-voltage mapping table.

[0010] Further, the voltage-to-current converter is composed of an operational amplifier and a reference resistor, the non-inverting input terminal of the operational amplifier receives the frequency indication voltage, the output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier through the reference resistor, and the current flowing through the reference resistor forms a reference bias current and is output from the output terminal of the operational amplifier.

[0011] Further, the current mirror is composed of a first PMOS transistor and a second PMOS transistor, the sources of the first PMOS transistor and the second PMOS transistor are commonly connected to a positive power supply terminal, the gate of the first PMOS transistor is short-circuited with the drain and receives the reference bias current, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the second PMOS transistor outputs a transconductance control current in a mirror proportional relationship with the reference bias current.

[0012] Further, the transconductance-capacitance notch filter unit adopts a double second-order notch topology structure and comprises a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, a first on-chip capacitor, a second on-chip capacitor and an output summing node; the first transconductance amplifier, the second transconductance amplifier, the third transconductance amplifier and the fourth transconductance amplifier all adopt a differential input single-ended output structure and have a bias current terminal, the bias current terminal receives the transconductance control current; the non-inverting input terminal of the first transconductance amplifier receives a primary amplified audio signal, the inverting input terminal of the first transconductance amplifier is connected to the upper plate of the second on-chip capacitor, and the output terminal of the first transconductance amplifier is connected to the upper plate of the first on-chip capacitor; the non-inverting input terminal of the second transconductance amplifier is connected to the upper plate of the first on-chip capacitor, the inverting input terminal of the second transconductance amplifier is connected to an analog ground potential, and the output terminal of the second transconductance amplifier is connected to the upper plate of the second on-chip capacitor; the non-inverting input terminal of the third transconductance amplifier is connected to the upper plate of the first on-chip capacitor, the inverting input terminal of the third transconductance amplifier is connected to the analog ground potential, and the output terminal of the third transconductance amplifier is connected to the output summing node; the non-inverting input terminal of the fourth transconductance amplifier receives the primary amplified audio signal, the inverting input terminal of the fourth transconductance amplifier is connected to the analog ground potential, and the output terminal of the fourth transconductance amplifier is connected to the output summing node; the lower plate of the first on-chip capacitor and the lower plate of the second on-chip capacitor are both connected to the analog ground potential, and the output summing node outputs a notch output audio signal.

[0013] Further, the trap center frequency of the transconductance-capacitance trap filter unit is determined by the ratio of the transconductance value of the first transconductance amplifier and the capacitance value of the first on-chip capacitance, the transconductance values of the first transconductance amplifier, the second transconductance amplifier, the third transconductance amplifier and the fourth transconductance amplifier increase synchronously to make the trap center frequency move to high frequency when the transconductance control current increases, and the trap center frequency moves to low frequency when the transconductance control current decreases; the interference component with the frequency equal to the trap center frequency in the primary amplified audio signal forms a trap attenuation channel through the transconductance-capacitance trap filter unit, and the speech component with the frequency deviating from the trap center frequency in the primary amplified audio signal forms a passband channel through the transconductance-capacitance trap filter unit.

[0014] Further, the program-controlled gain amplifier comprises a gain selection switch network and a gain latching register, and the control end of the microcontroller is connected to the gain latching register to write the gain gear; the amplitude detection unit comprises a rectifier circuit and an integration circuit, the rectifier circuit and the integration circuit are connected to the output end of the program-controlled gain amplifier and output an amplitude detection value, the microcontroller collects the amplitude detection value and updates the gain gear; the input end of the power amplifier is connected to the output end of the program-controlled gain amplifier, and the output end of the power amplifier is connected to the loudspeaker unit of the voice handle.

[0015] The satellite handheld terminal expansion dock audio signal amplification and noise reduction system has the following beneficial effects: The satellite handheld terminal expansion dock audio signal amplification and noise reduction system provided by the application effectively solves the technical problems of poor audio signal transmission quality, difficult-to-eliminate periodic interference and unstable output volume in a satellite communication environment, and significantly improves the audio processing performance of the expansion dock and the user call experience.

[0016] The satellite handheld terminal expansion dock audio signal amplification and noise reduction system provided by the application effectively solves the technical problems of poor audio signal transmission quality, difficult-to-eliminate periodic interference and unstable output volume in a satellite communication environment, and significantly improves the audio processing performance of the expansion dock and the user call experience.

[0017] The interference frequency detection unit used in the analog adaptive notch technology of the application accurately extracts the frequency information of the periodic interference component by real-time statistics of the zero-crossing points of the audio signal; the bias current generation unit converts the frequency information into a transconductance control current; the notch center frequency of the transconductance-capacitance notch filter unit is dynamically adjusted by the transconductance control current, so that the notch filter is always aligned with the interference frequency. This closed-loop adaptive mechanism does not require the participation of a digital signal processor, and completes frequency tracking and notch filtering completely in the analog domain, avoiding the delay and distortion caused by analog-to-digital conversion and digital-to-analog conversion, reducing system power consumption and cost, while being able to automatically adapt to the interference frequency changes caused by factors such as time division multiple access frame rate drift and mode switching, ensuring stable and reliable interference suppression effect under various working conditions.

[0018] The program-controlled gain amplification and amplitude detection closed-loop control mechanism of the application effectively solves the problem of unstable volume caused by signal amplitude fluctuation of the satellite communication link. The amplitude detection unit extracts the envelope information of the output signal in real time, and the microcontroller automatically adjusts the gain level according to the comparison result of the amplitude detection value and the preset threshold, so that the output signal amplitude is always maintained within the appropriate dynamic range, avoiding the situation that the signal is too weak to be heard or the signal is too strong to produce clipping distortion, providing users with a smooth, clear and comfortable call experience.

[0019] In summary, through the synergistic effect of the three technical means of differential reception to suppress common-mode interference, analog adaptive notch to eliminate periodic interference, and program-controlled gain amplification to stabilize output volume, the audio signal processing capability of the satellite handheld terminal expansion dock is comprehensively improved, which has the advantages of strong anti-interference ability, good adaptability, fast response speed, low implementation cost, etc., and can meet the demand for high-quality voice communication of satellite mobile communication in various application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The circuit principle structure schematic diagram of the transconductance-capacitance notch filter unit provided for the embodiments of the application; Figure 2 The amplitude variation characteristic schematic diagram of the notch output audio signal received by the program-controlled gain amplifier provided for the embodiments of the application over time.

[0021] Figure 3 The gain level dynamic adjustment process schematic diagram of the program-controlled gain amplifier provided for the embodiments of the application over time.

[0022] Figure 4 The amplitude variation relationship schematic diagram of the output signal of the program-controlled gain amplifier and the amplitude detection value output by the amplitude detection unit over time. DETAILED DESCRIPTION

[0023] The method of the present application will be further described in detail below in combination with the accompanying drawings and embodiments of the present application.

[0024] The audio signal amplification and noise reduction system of the satellite handheld terminal docking station comprises: a differential input port for receiving the original audio signal output by the satellite handheld terminal; an instrument amplifier connected to the differential input port for performing common-mode rejection and differential-mode amplification on the original audio signal to output a primary amplified audio signal; an analog adaptive notch filter module connected to the instrument amplifier for processing the primary amplified audio signal and outputting a notch output audio signal; the analog adaptive notch filter module comprises an interference frequency detection unit, a bias current generation unit and a transconductance-capacitance notch filter unit, the interference frequency detection unit outputs an interference frequency count value, the bias current generation unit generates a transconductance control current based on the interference frequency count value, and the transconductance-capacitance notch filter unit receives the transconductance control current and performs notch processing on the primary amplified audio signal to output the notch output audio signal; a programmable gain amplifier for performing gain adjustment on the notch output audio signal and outputting a gain-adjusted audio signal; an amplitude detection unit connected to the output end of the programmable gain amplifier for performing rectification and integration on the gain-adjusted audio signal to output an amplitude detection value; a microcontroller connected to the amplitude detection unit and the programmable gain amplifier for collecting the amplitude detection value and setting a gain level accordingly; and a power amplifier for receiving the gain-adjusted audio signal and driving the speaker unit of the voice handle to produce sound.

[0025] In the working state of the satellite handheld terminal, the radio frequency power amplifier, the baseband processor and the switching power supply inside the satellite handheld terminal will generate strong electromagnetic radiation, which will induce common-mode interference voltage on the audio transmission line. At the same time, there is a certain physical distance between the docking station and the satellite handheld terminal, and the audio signal is easily affected by the power frequency electric field, radio frequency signals and electromagnetic interference from other electronic devices in the external environment. In order to obtain high-quality audio signals in such a complex electromagnetic environment, the present embodiment adopts a combination of differential transmission and differential reception, receives the original audio signal output by the satellite handheld terminal through the differential input port, and uses the instrument amplifier to perform common-mode rejection and differential-mode amplification processing on the original audio signal.

[0026] The differential input port is provided on the shell of the docking station and comprises three independent electrical connection points, namely a positive end, a negative end and a shielded ground end. The positive end and the negative end are respectively used for receiving the positive component and the inverted component of the original audio signal, and the shielded ground end is used for connecting the shielding layer of the transmission cable. In a specific embodiment, the differential input port adopts a 3-pin aviation socket, wherein pin No. 1 is defined as the positive end, pin No. 2 is defined as the negative end, and pin No. 3 is defined as the shielded ground end. The aviation socket has good mechanical locking structure and electromagnetic shielding performance, and can adapt to the use requirements of satellite communication equipment in the field environment.

[0027] The satellite handset and the docking station are connected by a shielded twisted pair cable. A shielded twisted pair cable is composed of two insulated wires twisted together and a metal braid shield wrapped around the outside. The two insulated wires are connected to the positive and negative terminals of the differential input port respectively, and the metal braid shield is connected to the chassis ground of the docking station. The twisted structure causes the two wires to be tightly intertwined in space, so when an external electromagnetic field acts on the transmission line, the interference voltages induced on the two wires have similar amplitudes and the same phase, forming a common-mode interference signal; while the useful audio signal exists in the form of differential mode between the two wires, showing voltages with equal amplitudes but opposite phases. This transmission method distinguishes the useful signal from the interference signal in signal form, laying the foundation for subsequent common-mode rejection processing.

[0028] The positive and negative terminals of the differential input port are connected to the two input terminals of the instrumentation amplifier after being connected in series with a resistor. The resistance values of the two series resistors are equal, both being 100 ohms. The role of the series resistors is to limit the surge current that may occur, and together with the parasitic capacitance of the input terminal, they form a low-pass filter network to preliminarily attenuate high-frequency interference beyond the audio frequency band. A transient suppression diode is connected in parallel between the positive terminal of the differential input port and the chassis ground, and between the negative terminal and the chassis ground. The reverse breakdown voltage of the transient suppression diode is set to a level slightly higher than the normal operating voltage, which is 6.8 volts in this embodiment. When a transient overvoltage event such as electrostatic discharge or lightning induction occurs, the transient suppression diode quickly conducts to discharge the overvoltage energy to the chassis ground, thereby protecting the instrumentation amplifier in the later stage from damage.

[0029] In this embodiment, the instrumentation amplifier adopts a classic three-op-amp structure, including a first input stage operational amplifier, a second input stage operational amplifier, and an output stage operational amplifier. The input impedance of the instrumentation amplifier has an important influence on the quality of signal transmission. The input impedance of the three-op-amp structure instrumentation amplifier is presented by the non-inverting input terminal of the input stage operational amplifier, which can usually reach several hundred megohms or even gigohms. The extremely high input impedance means that the instrumentation amplifier hardly draws current from the signal source, and the change in the internal resistance of the signal source will not cause the amplitude of the input signal to attenuate. The audio output port of the satellite handset usually has an output impedance of several tens of ohms to several hundred ohms, which cooperates with the high input impedance of the instrumentation amplifier to achieve good impedance matching, avoiding signal reflection and frequency response distortion.

[0030] The bandwidth of the instrumentation amplifier should cover the frequency range of the speech signal with an appropriate margin. The main energy of the speech signal is concentrated in the 300 Hz to 3400 Hz frequency band. Considering the transition characteristics at the band edges, the small-signal bandwidth of the instrumentation amplifier is set to DC to 20 kHz. The gain-bandwidth product is an important parameter of the operational amplifier, defined as the product of the closed-loop gain and the corresponding bandwidth. In this embodiment, the gain-bandwidth product of the input stage operational amplifier is not less than 10 MHz to ensure that it can still provide a bandwidth of over 200 kHz at a closed-loop gain of 50 times, meeting the transmission requirements of the audio signal.

[0031] The equivalent input noise of the instrumentation amplifier directly determines the minimum signal level that the system can resolve. Equivalent input noise is typically expressed as noise voltage density, measured in nanovolts per radian hertz (NV / HHz). In this embodiment, a low-noise operational amplifier is selected for the input stage, with an equivalent input noise voltage density not exceeding 10 NV / HHz at a frequency of 1 kHz. Within the speech frequency band of 300 Hz to 3400 Hz, the total integrated noise is approximately 550 NV RMS. In contrast, the audio signal amplitude output by a satellite handheld terminal is typically in the peak-to-peak range of 10 mV to 100 mV, with a signal-to-noise ratio exceeding 65 dB, ensuring clear call quality.

[0032] The instrumentation amplifier uses a bipolar power supply, with a positive voltage of +5V and a negative voltage of -5V. This bipolar supply allows the output signal to swing bidirectionally near zero potential, enabling the processing of AC audio signals without DC bias and simplifying the DC-coupled design of subsequent circuits. Decoupling capacitors are connected in parallel at the power supply ports, including 10µF electrolytic capacitors and 100nm ceramic capacitors. The electrolytic capacitors provide low-frequency power filtering, while the ceramic capacitors provide high-frequency power decoupling. Together, they effectively suppress the impact of power line ripple and high-frequency noise on the instrumentation amplifier's performance.

[0033] A first-order low-pass filter is installed at the output of the instrumentation amplifier to suppress potential high-frequency residual interference. This low-pass filter consists of a series resistor (1 kΩ) and a parallel capacitor (47 nanofarads). The cutoff frequency of the low-pass filter is... Determined by the following formula: ;in This indicates the cutoff frequency, measured in Hertz (Hz). This indicates the resistance value of the series resistor, expressed in ohms. The capacitance value of the parallel capacitor is expressed in farads. Substituting the parameter values ​​in this embodiment, the cutoff frequency is calculated to be 3386 Hz, slightly lower than the upper limit frequency of the voice signal of 3400 Hz. The signal attenuation at the cutoff frequency is 3 dB, which is within an acceptable range for the high-frequency components of the voice signal, while providing effective attenuation for high-frequency interference above the cutoff frequency. After the instrumentation amplifier passes through the aforementioned low-pass filter, it outputs a primary amplified audio signal, which is then sent to a subsequent analog adaptive notch filter module for further processing.

[0034] Satellite communication systems operate under a specific time-division multiple access (TDMA) architecture. The radio frequency (RF) power amplifier periodically transmits signal pulses with a fixed frame structure. This periodic RF transmission induces periodic interference in the audio circuitry, which is related to the frame rate. Taking the Tiantong-1 satellite communication system as an example, its TDMA frame period is approximately 4.615 milliseconds, corresponding to a fundamental frequency interference frequency of approximately 217 Hz, along with integer multiples of harmonics at that frequency. Furthermore, the switching power supply inside the expansion dock operates at switching frequencies ranging from tens to hundreds of kilohertz, and its fundamental and lower harmonic frequencies also couple into the audio channel, creating interference. While the frequencies of these periodic interferences are relatively stable, they are not absolutely constant and drift within a certain range depending on system operating conditions, temperature changes, and power supply voltage fluctuations. Traditional fixed-frequency notch filters cannot track this frequency drift, resulting in a decrease in notch filtering effectiveness. This embodiment employs a simulated adaptive notch filter technique. By real-time detection of the interference frequency and dynamic adjustment of the notch filter's center frequency, the notch filter is always aligned with the interference components, achieving a stable and reliable interference suppression effect.

[0035] After the primary amplified audio signal is output from the instrumentation amplifier, it first enters the interference frequency detection unit. The core task of the interference frequency detection unit is to extract the frequency information of periodic interference from the composite signal that mixes speech components and interference components. Periodic interference signals have a stable repetition period, and their zero-crossing points exhibit a regular distribution on the time axis, while the zero-crossing point distribution of speech signals is random and time-varying. Utilizing this difference in characteristics, the frequency of the dominant periodic component can be estimated by statistically analyzing the number of zero-crossings within a certain time window. When the amplitude of the interference signal is significantly higher than that of the speech signal, the number of zero-crossings is mainly determined by the interference signal, and the statistical results can accurately reflect the interference frequency.

[0036] The zero-crossing comparator is the front-end circuit of the interference frequency detection unit. Its function is to convert continuously changing analog signals into rectangular pulse sequences that are easy for digital circuits to process. The non-inverting input of the zero-crossing comparator receives the primary amplified audio signal, and the inverting input is connected to the analog ground potential, which serves as the reference threshold for zero-crossing decision. When the instantaneous voltage of the primary amplified audio signal is higher than the analog ground potential, the output of the zero-crossing comparator jumps to a high level; when the instantaneous voltage of the primary amplified audio signal is lower than the analog ground potential, the output of the zero-crossing comparator jumps to a low level. Thus, each time the primary amplified audio signal completes a zero-crossing crossing from negative to positive or from positive to negative, the output of the zero-crossing comparator generates a level transition. The rectangular pulse sequence output by the zero-crossing comparator corresponds one-to-one with the zero-crossing moments of the primary amplified audio signal.

[0037] The timing window generator provides a precise time reference for the edge counter, determining the update rate and resolution of the frequency detection. The timing window generator consists of an oscillator and a frequency divider. The oscillator generates a stable clock signal, and its frequency accuracy directly affects the final frequency measurement accuracy. This embodiment uses a quartz crystal oscillator as the clock source, with an oscillation frequency of 32.768 kHz and a frequency stability better than ±50 ppm. This frequency was chosen because 32.768 kHz is 2 to the power of 15, facilitating the acquisition of low-frequency signals with various integer division ratios through a binary frequency divider. Furthermore, crystal oscillators at this frequency are inexpensive and compact, widely used in portable electronic devices.

[0038] The frequency divider divides the clock signal output from the oscillator, generating a window enable signal and a window end signal. The frequency divider employs a synchronous counter structure, composed of multiple cascaded flip-flops. Let the division ratio be... ,in The division factor of the frequency divider is a dimensionless positive integer. The clock period of the oscillator is... ,in This represents the period of the clock signal, in microseconds. The duration of the timing window is then determined. for: ;in This indicates the duration of the timing window, in milliseconds. In this embodiment, the frequency division ratio is set to 1024, and the clock period is 30.518 microseconds, resulting in a calculated timing window duration of 31.25 milliseconds. This window length is approximately 6.8 times the period of the 217 Hz interference signal, allowing for the collection of a sufficient number of zero-crossing events within a single window to ensure statistical accuracy. Simultaneously, the window update rate reaches 32 times per second, enabling timely tracking of the slow drift of the interference frequency.

[0039] The edge counter counts the rising edges of the rectangular pulse sequence output by the zero-crossing comparator during the timing window. The edge counter uses an asynchronous counter structure; the clock input of the first-stage flip-flop is connected to the output of the zero-crossing comparator, and the clock inputs of subsequent flip-flops are connected to the inverted outputs of the preceding flip-flops. Each time the zero-crossing comparator output generates a rising edge, the first-stage flip-flop toggles once, triggering subsequent flip-flops to count according to a binary rule. The bit width of the edge counter determines the maximum countable value; this embodiment uses an 8-bit counter with a maximum count of 255. Within a 31.25 millisecond timing window, if the interference frequency is 217 Hz, the number of zero-crossings is approximately 217 multiplied by 0.03125 multiplied by 2, which equals 13.6 times, rounded down to 14 times. The count value is much smaller than the maximum counter value, preventing overflow. Even if the interference frequency is as high as 4 kHz, the number of zero-crossings is only 250, still within the range of an 8-bit counter.

[0040] The edge counter has an enable control terminal and an asynchronous reset terminal. The enable control terminal is connected to the window enable signal output by the timing window generator. The edge counter only counts the input pulses when the window enable signal is high; otherwise, the counter retains its current value. The asynchronous reset terminal is connected to the window end signal. When the rising edge of the window end signal arrives, the edge counter immediately resets to zero, preparing for counting in the next timing window. The asynchronous reset operation has higher priority than the counting enable, ensuring that the counter starts counting from zero at the beginning of each timing window.

[0041] The frequency latch samples and holds the current count value of the edge counter at the end of each timing window, outputting it as the interference frequency count value to the subsequent bias current generation unit. The frequency latch employs an 8-bit parallel latch structure, containing eight D flip-flops. The data input of each D flip-flop is connected to the 8-bit parallel output of the edge counter, and the clock input of each D flip-flop is connected to the window end signal. When the rising edge of the window end signal arrives, the current count value of the edge counter is synchronously latched to the output of the frequency latch, and this output value remains unchanged until the next window end signal arrives. The output of the frequency latch is the interference frequency count value, represented as an 8-bit binary number.

[0042] There is a definite conversion relationship between the interference frequency count value and the actual interference frequency. Let the interference frequency count value be... ,in This represents the number of zero-crossings detected within the timing window, and is a dimensionless positive integer. Since the signal generates two zero-crossings (one positive and one negative) for each complete cycle, the formula for calculating the interference frequency is: ;in Indicates the interference frequency, measured in Hertz; This indicates the duration of the timing window, in seconds. Taking the parameters of this embodiment as an example, if the count value is 14 and the timing window is 0.03125 seconds, the calculated interference frequency is 224 Hz, which deviates from the theoretical value of 217 Hz by approximately 3 percent. This deviation stems from the quantization error caused by the non-integer multiple relationship between the timing window and the interference signal period. For notch filters, the notch bandwidth is typically designed to be in the tens of hertz range, and a frequency deviation of 3 Hz is still within the notch bandwidth range and does not affect the notch filtering effect.

[0043] The function of the bias current generation unit is to convert the digital interference frequency count value output by the interference frequency detection unit into an analog transconductance control current. This transconductance control current is used to adjust the notch center frequency of the transconductance-capacitor notch filter unit. The conversion process consists of two stages: first, the digital quantity is converted into a voltage quantity by a digital-to-analog converter, and then the voltage quantity is converted into a current quantity by a voltage-to-current converter and a current mirror.

[0044] The design of a frequency-voltage mapping table needs to consider the correspondence between the interference frequency count and the notch filter center frequency, as well as the correspondence between the notch filter center frequency and the transconductance amplifier bias current. The center frequency of the transconductance-capacitance filter... The transconductance value of the transconductance amplifier And the capacitance value of the integrating capacitor They jointly decide to satisfy the following relationship: ;in This indicates the center frequency of the filter, measured in Hertz. This indicates the transconductance value of the transconductance amplifier, in Siemens units. This indicates the capacitance value of the integrating capacitor, measured in farads. The transconductance of the transconductance amplifier is related to its bias current. Proportional, for transconductance amplifiers using differential pair structures, the relationship between the two can be expressed as: ;in This represents the tail current of the transconductance amplifier, i.e., the bias current, and is measured in amperes. This represents the thermal voltage, which is approximately 26 millivolts at room temperature (25 degrees Celsius). Substituting the above formula into the center frequency formula, we get: Therefore, it can be seen that the center frequency of the notch filter is linearly proportional to the bias current. If it is desired that the center frequency of the notch filter tracks the change of the interference frequency, the bias current only needs to change synchronously with the interference frequency. The frequency-voltage mapping table is designed based on this linear relationship, making the frequency indication voltage proportional to the interference frequency count value, and thus making the final transconductance control current proportional to the interference frequency.

[0045] The specific content of the frequency-voltage mapping table is determined based on the target notch filter frequency range and circuit parameters. Assuming the target notch filter frequency range is 50 Hz to 500 Hz, covering power frequency interference and its low-order harmonics, as well as time-division multiple access frame rate interference, the corresponding interference frequency count value range is 3 to 31. The frequency indication voltage is designed to range from 0.1 V to 1.0 V, linearly mapped to the count value. For a count value of 3, the mapped frequency indication voltage is 0.1 V; for a count value of 31, the mapped frequency indication voltage is 1.0 V; intermediate count values ​​are determined by linear interpolation. For count values ​​outside the range, the frequency indication voltage is clamped to the boundary value, i.e., 0.1 V is output when the count value is less than 3, and 1.0 V is output when the count value is greater than 31. This clamping process prevents abnormal count values ​​from causing the circuit to operate in an abnormal state.

[0046] A voltage-to-current converter converts the frequency indication voltage output from a digital-to-analog converter into a proportional reference bias current. The voltage-to-current converter consists of two core components: an operational amplifier and a reference resistor, operating in a classic voltage follower-current output configuration. The non-inverting input of the operational amplifier receives the frequency indication voltage, while the inverting input is connected to the output of the operational amplifier via the reference resistor. Due to the operational amplifier's deep negative feedback, its virtual short characteristic ensures that the voltage at the inverting input is equal to the voltage at the non-inverting input; that is, the voltage at the inverting input equals the frequency indication voltage. The reference resistor is connected between the output of the operational amplifier and the inverting input, with its lower end (inverting input side) having a potential equal to the frequency indication voltage. If the upper end (output side) of the reference resistor is connected to a fixed reference potential, the current flowing through the reference resistor can be accurately calculated. In this embodiment, the reference resistor is chosen to be 100 kiloohms. When the frequency indication voltage is 0.1 volts, the reference bias current is 1 microamp; when the frequency indication voltage is 1.0 volt, the reference bias current is 10 microamps. The reference bias current varies from 1 microamp to 10 microamps, and is linearly proportional to the frequency indication voltage, and thus linearly proportional to the interference frequency count value.

[0047] The function of a current mirror is to replicate the reference bias current output from the voltage-to-current converter as a transconductance control current, while simultaneously achieving electrical isolation between the current source and the current sink. A current mirror consists of two devices: a first PMOS transistor and a second PMOS transistor, forming a basic current mirror topology. The sources of both the first and second PMOS transistors are connected to the positive power supply, ensuring that the source potentials of the two transistors are the same. The gate and drain of the first PMOS transistor are shorted, forming a diode connection, allowing the reference bias current to flow from the voltage-to-current converter into the drain of the first PMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, sharing the same gate voltage. The drain of the second PMOS transistor serves as the output terminal of the transconductance control current, connected to the bias current input terminal of the transconductance-capacitance notch filter unit.

[0048] The current mirror operates based on the square-law characteristic of a field-effect transistor. For a PMOS transistor operating in the saturation region, its drain current... With gate-source voltage The following relationship exists between them: ;in This represents the drain current, measured in amperes. This represents hole mobility, expressed in square centimeters per volt-second. This represents the capacitance per unit area of ​​the gate oxide layer, expressed in farads per square centimeter. This indicates the transistor channel width, measured in micrometers. This indicates the channel length of a transistor, measured in micrometers. This represents the gate-source voltage, measured in volts. This represents the threshold voltage, measured in volts.

[0049] Since the gate and drain of the first PMOS transistor are shorted, its drain current is equal to the reference bias current. The gate-source voltage is determined by the square-law equation described above. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, therefore the two transistors have the same gate-source voltage. If the two transistors have the same process parameters and the same aspect ratio, then the drain current of the second PMOS transistor is equal to the drain current of the first PMOS transistor, that is, the transconductance control current is equal to the reference bias current. If the two transistors have different aspect ratios, let the aspect ratio of the first PMOS transistor be... The aspect ratio of the second PMOS transistor is Then the transconductance control current With reference bias current The relationship between them is: ;in This represents the transconductance control current, measured in microamps. and These represent the width-to-length ratio of the first PMOS transistor and the second PMOS transistor, respectively, and are dimensionless. By designing different width-to-length ratios, current scaling can be achieved. In this embodiment, the width-to-length ratios of the two transistors are designed to be the same, achieving a 1:1 current mirror relationship, with the transconductance control current equal to the reference bias current, varying from 1 microamp to 10 microamps.

[0050] The accuracy of a current mirror is affected by transistor matching. In integrated circuit manufacturing, adjacent transistors placed on the same chip can achieve good matching, and the current mirror error can be controlled within 1 inch. For current mirrors implemented with discrete components, specially designed matching transistor pairs can be used, or a Wilson current mirror composed of transistors can be used to improve matching accuracy. In this embodiment, the current mirror is implemented using matching transistor pairs within the integrated circuit, and the current mirror error is less than 2 inches, meeting the notch filter frequency accuracy requirements.

[0051] The transconductance-capacitor notch filter unit is the core circuit of the analog adaptive notch filter. Its function is to deeply attenuate interference components at specific frequencies in the primary amplified audio signal, while allowing other frequency components to pass through with essentially unchanged characteristics. This filter unit adopts a dual second-order notch topology, consisting of four transconductance amplifiers and two on-chip capacitors connected in a specific manner to form a notch response with second-order transfer function characteristics.

[0052] The choice of a dual second-order notch filter topology is based on the following considerations. First-order filters cannot achieve notch characteristics because notch filtering requires generating transmission zeros at specific frequencies, but the poles and zeros of a first-order system are located on the real axis, making it impossible to achieve deep attenuation at specific positions on the frequency axis. Second-order filters can have conjugate complex poles and conjugate complex zeros. When the zeros are located on the imaginary axis (i.e., the zero quality factor is infinite) and the poles are located in the left half-plane close to the imaginary axis, a notch response can be formed. The dual second-order structure is the standard form for implementing a second-order transfer function, and the positions of its poles and zeros can be independently adjusted through circuit parameters, offering high design flexibility.

[0053] The transconductance-capacitor notch filter unit comprises six core components: a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, a first on-chip capacitor, and a second on-chip capacitor, as well as one circuit node for output summation. All four transconductance amplifiers employ a differential input, single-ended output configuration. The differential input structure suppresses the effects of power supply noise and common-mode interference on signal processing, while the single-ended output structure simplifies inter-stage connections and signal summation. Each transconductance amplifier has four ports: a non-inverting input, an inverting input, an output, and a bias current terminal. The bias current terminal receives the transconductance control current to adjust the transconductance value of the transconductance amplifier.

[0054] refer to Figure 1 , Figure 1 A schematic diagram of the circuit structure of a transconductance-capacitor notch filter unit according to an exemplary embodiment of this application is shown. This circuit topology is based on a dual second-order active filter architecture, and through the coordinated operation of four operational transconductance amplifiers and two on-chip capacitors, it achieves a high-Q notch filter function for interference signals at specific frequencies. Figure 1 As shown, the notch filter unit mainly consists of a first operational transconductance amplifier, a second operational transconductance amplifier, a third operational transconductance amplifier, a fourth operational transconductance amplifier, a first capacitor, a second capacitor, and an output load resistor. For ease of description, the four operational transconductance amplifiers are represented by OTA1, OTA2, OTA3, and OTA4 in the figure, respectively. However, it should be noted that in actual layout design or circuit implementation, they may use the exact same differential pair transistor structure to ensure good matching. The signal input terminal of the circuit is used to receive the primary amplified audio signal from the preamplifier. This signal is transmitted simultaneously to the non-inverting input terminals of the first and fourth operational transconductance amplifiers via the input bus, thus forming two parallel signal processing paths within the circuit. The first path is a direct-through path, where the fourth operational transconductance amplifier directly converts the input voltage into a current signal and transmits it to the output node. The second path is an integral feedback path, consisting of a second-order resonant loop formed by cascading the first and second operational transconductance amplifiers.

[0055] Specifically, the output of the first operational transconductance amplifier is connected to the upper plate of the first capacitor, and the lower plate of the first capacitor is connected to the simulated ground potential. This allows the first capacitor to be charged and discharged by the output current of the first operational transconductance amplifier, forming a first-stage integrator. The output node of this first-stage integrator, i.e., the upper plate of the first capacitor, is further connected to the non-inverting input of the second operational transconductance amplifier. The output of the second operational transconductance amplifier is connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is also connected to the simulated ground potential, forming a second-stage integrator. To form a resonant circuit capable of generating oscillations or specific frequency selectivity, the output of the second-stage integrator, i.e., the upper plate of the second capacitor, is connected back to the inverting input of the first operational transconductance amplifier via a feedback circuit, thus forming a closed-loop negative feedback system. The natural resonant frequency of this second-order closed-loop system is determined by the transconductance values ​​of the first and second operational transconductance amplifiers, as well as the capacitance values ​​of the first and second capacitors. Simultaneously, the non-inverting input of the third operational transconductance amplifier is connected to the upper plate of the first capacitor to acquire the output signal of the first-stage integrator.

[0056] In the signal output stage, the outputs of the third and fourth operational transconductance amplifiers are superimposed in the current domain and connected together to the output summing node. The output summing node is further connected to one end of a load resistor, the other end of which is grounded. Due to the voltage-controlled current source characteristic of the transconductance amplifiers, the in-phase current component output by the fourth operational transconductance amplifier is vector-synthesized with the integrated current component output by the third operational transconductance amplifier across the output load resistor. At the designed notch filter center frequency, the signal processed by the first-stage integrator undergoes a specific phase shift, causing the current injected into the output node by the third and fourth operational transconductance amplifiers to have equal amplitudes but opposite phases at that frequency. This results in destructive interference, causing this frequency component to be significantly attenuated in the output voltage, forming a notch characteristic. In frequency bands far from the center frequency, since the phase condition no longer satisfies the destructive requirement, the input signal can be transmitted to the output through a direct path or a synthesized path, forming a passband.

[0057] also, Figure 1 The diagram also shows a transconductance control current bus connected to the bias terminals of all operational transconductance amplifiers. This bus carries the transconductance control current from the preceding bias current generation unit, the specific value of which is dynamically set by the interference frequency detection unit based on the real-time detected interference frequency. The internal bias circuits of the first to fourth operational transconductance amplifiers are all coupled to this bus, allowing the transconductance parameters of the four amplifiers to be synchronously and linearly adjusted with changes in the control current. When the control current increases, the transconductance values ​​of each transconductance amplifier increase synchronously, reducing the time constant formed by the integrator, thereby driving the center frequency of the notch filter to shift towards higher frequencies; conversely, when the control current decreases, the notch filter center frequency shifts towards lower frequencies. This structure ensures that the filtering characteristics of the hardware circuit can track the periodic interference frequency changes in the external electromagnetic environment in real time, achieving adaptive noise reduction in the pure analog domain and avoiding the quantization noise and delay problems that may be introduced by digital filtering. Figure 1 The illustrated embodiment achieves high-performance audio purification within a very small chip area through fully integrated on-chip capacitors and well-matched transconductance units.

[0058] A transconductance amplifier is a controlled source device that converts input voltage into output current; its core characteristic parameter is its transconductance value. Let the voltage at the non-inverting input of the transconductance amplifier be... The voltage at the inverting input terminal is The output current is Transconductance value ,in This indicates the voltage at the non-inverting input terminal, in volts. This indicates the voltage at the inverting input terminal, measured in volts. This indicates the output current, measured in amperes. This represents the transconductance value, measured in amperes per volt (Siemens). The input-output relationship of the transconductance amplifier is then: A typical implementation of a transconductance amplifier is a differential pair circuit, consisting of two transistors connected at their sources, with a tail current source providing bias current to the differential pair. The transconductance of the differential pair is proportional to the tail current; the transconductance value can be changed by adjusting the tail current. In this embodiment, the transconductance control current is simultaneously fed into the bias current terminals of all four transconductance amplifiers, ensuring that the transconductance values ​​of the four amplifiers remain consistent and change synchronously.

[0059] The first and second on-chip capacitors are integrators in the transconductance-capacitance filter. The on-chip capacitors are fabricated inside the integrated circuit using a metal-insulator-metal structure or a polysilicon-insulator-polysilicon structure, exhibiting good linearity and temperature stability. The upper and lower plates of the on-chip capacitors serve as two electrical connection ports. The lower plate typically has a large parasitic capacitance to ground; therefore, in circuit design, the lower plate is connected to a low-impedance node (such as simulated ground potential) to reduce the impact of parasitic effects. In this embodiment, the capacitance values ​​of both the first and second on-chip capacitors are designed to be 10 picofarads. This capacitance value matches the transconductance range of the transconductance amplifier, enabling coverage of the target notch filter frequency range.

[0060] The signal connections of the transconductance-capacitor notch filter unit are as follows: The non-inverting input of the first transconductance amplifier receives the primary amplified audio signal, serving as the signal input to the filter unit; the inverting input of the first transconductance amplifier is connected to the upper plate of the second on-chip capacitor, introducing the feedback signal from the second integrator; the output of the first transconductance amplifier is connected to the upper plate of the first on-chip capacitor, and the output current charges and discharges the first on-chip capacitor to form an integration effect. The non-inverting input of the second transconductance amplifier is connected to the upper plate of the first on-chip capacitor, sampling the output voltage of the first integrator; the inverting input of the second transconductance amplifier is connected to the analog ground potential, serving as a reference level; the output of the second transconductance amplifier is connected to the upper plate of the second on-chip capacitor, and the output current charges and discharges the second on-chip capacitor to form a second-stage integration effect. The lower plates of both the first and second on-chip capacitors are connected to the analog ground potential.

[0061] The third and fourth transconductance amplifiers together form the output summing network. The non-inverting input of the third transconductance amplifier is connected to the upper plate of the first on-chip capacitor, sampling the output voltage of the first integrator; the inverting input of the third transconductance amplifier is connected to the analog ground potential; the output of the third transconductance amplifier is connected to the output summing node. The non-inverting input of the fourth transconductance amplifier receives the primary amplified audio signal, sharing the same input signal as the first transconductance amplifier; the inverting input of the fourth transconductance amplifier is connected to the analog ground potential; the output of the fourth transconductance amplifier is connected to the output summing node. At the output summing node, the output currents of the third and fourth transconductance amplifiers are superimposed, and the total current is converted into an output voltage through the output load resistor. This output voltage is the notch-filtered output audio signal.

[0062] The mechanism by which this topology forms notch characteristics can be understood from the perspective of signal flow. The primary amplified audio signal is directly transmitted to the output summing node through the fourth transconductance amplifier, forming a direct path. Simultaneously, the primary amplified audio signal passes through the first integrator composed of the first transconductance amplifier and the first on-chip capacitor, and then through the second integrator composed of the second transconductance amplifier and the second on-chip capacitor, forming a second-order integrated signal that is fed back to the inverting input of the first transconductance amplifier. The output signal of the first integrator is also transmitted to the output summing node through the third transconductance amplifier, forming a bypass path after first-order integration.

[0063] At the notch filter center frequency, the feedback signal, after two stages of integration, is 180 degrees out of phase with the input signal (each stage of integration introduces a 90-degree phase shift). The feedback signal and the input signal are subtracted at the differential input of the first transconductance amplifier, causing the output amplitude of the first integrator to reach its maximum. At this point, the output currents of the third and fourth transconductance amplifiers have equal amplitudes but opposite phases at the output summation node, canceling each other out and causing the output signal amplitude to approach zero, thus forming the notch filter effect. At frequencies far from the notch filter center frequency, the phase relationship between the feedback signal and the input signal does not satisfy the cancellation condition. The output amplitude of the first integrator is smaller, and the output current of the third transconductance amplifier cannot cancel the output current of the fourth transconductance amplifier, allowing the input signal to be transmitted to the output.

[0064] The notch center frequency of the transconductance-capacitor notch filter unit is determined by the transconductance of the transconductance amplifiers and the capacitance of the on-chip capacitors. Let the transconductance of each of the four transconductance amplifiers be... The capacitance values ​​of the capacitors on the first and second chips are both... The center frequency of the notch filter is... The expression is: ;in This represents the center frequency of the notch filter, measured in Hertz. When the transconductance control current changes, the transconductance values ​​of the four transconductance amplifiers change synchronously, and the center frequency of the notch filter changes accordingly. The relationship between the transconductance value and the bias current has been given earlier; substituting it into the above equation yields: ;in This represents the transconductance control current, measured in amperes. This represents the thermal voltage, approximately 26 millivolts. This indicates the capacitance value of the on-chip capacitor, in farads. In this embodiment, the on-chip capacitor has a capacitance value of 10 picofarads. When the transconductance control current is 1 microamp, the notch filter center frequency is calculated as follows: When the transconductance control current is 10 microamps, the notch filter center frequency is calculated as follows: Therefore, when the transconductance control current varies from 1 μA to 10 μA, the notch filter center frequency varies from approximately 306 Hz to 3060 Hz, covering the frequency range of common periodic interference. In actual circuits, due to the discreteness of transistor process parameters and the influence of temperature, there will be a certain deviation between the calculated and measured values. This deviation can be compensated by adjusting the contents of the frequency-voltage mapping table.

[0065] Notch depth is a key indicator of a notch filter's ability to suppress interference, defined as the attenuation at the notch's center frequency. Ideally, the notch depth is infinite; however, in practical circuits, due to device mismatch and parasitic effects, the notch depth is a finite value. The main factors affecting notch depth include the transconductance matching accuracy between the third and fourth transconductance amplifiers, the capacitance matching accuracy between the first and second on-chip capacitors, and the finite output impedance of each transconductance amplifier. In integrated circuit implementation, layout design techniques such as common-centroid placement and virtual device addition can improve device matching accuracy, achieving notch depths exceeding 40 dB.

[0066] The quality factor of a notch filter determines the frequency selectivity of the notch characteristic. A higher quality factor results in a narrower notch bandwidth and less impact on adjacent frequency speech components. The quality factor of a dual second-order notch filter topology can be changed by adjusting the feedback coefficient at the inverting input of the first transconductance amplifier. In the topology of this embodiment, the quality factor is determined by the integrating loop formed by the first and second transconductance amplifiers. The designed quality factor is approximately 10, corresponding to a 3dB notch bandwidth of approximately one-tenth of the notch center frequency. For a notch center frequency of 217 Hz, a 3dB bandwidth is approximately 22 Hz, which is sufficient to effectively suppress interference signals while keeping the impact on the speech signal within an acceptable range.

[0067] The signal from the output summing node is passed through the output buffer to form a notch output audio signal. The output buffer adopts a unity-gain voltage follower structure, providing low-impedance driving capability to ensure that the notch output audio signal can drive the subsequent programmable gain amplifier without signal attenuation. The bandwidth of the output buffer is designed to be no less than 100 kHz, and the phase margin is no less than 60 degrees to ensure stable operation throughout the entire audio frequency band.

[0068] In one optional implementation, the transconductance-capacitor notch filter unit is implemented using a fully differential structure to further improve the suppression of common-mode interference and power supply noise. In the fully differential structure, each transconductance amplifier has two outputs (a non-inverting output and an inverting output), with two on-chip capacitors connected to the non-inverting signal path and the inverting signal path, respectively. The common-mode feedback circuit of the fully differential structure is used to stabilize the output common-mode level, ensuring the symmetry of the differential output signal.

[0069] In another alternative implementation, to simultaneously suppress interference components at multiple frequencies, the transconductance-capacitor notch filter unit is designed in a cascaded configuration, consisting of two or more independent dual second-order notch stages connected in series. Each notch stage has an independent transconductance control current input, allowing for the setting of different notch center frequencies. The first notch stage is set to track the detected main interference frequency, and the second notch stage is set to the second harmonic frequency of the main interference frequency. The second harmonic frequency can be achieved by amplifying the transconductance control current corresponding to the main frequency through a 2x current mirror and feeding it into the bias terminal of the second notch stage, eliminating the need for additional frequency detection circuitry.

[0070] The signal quality of satellite communication links is affected by various factors such as atmospheric attenuation, multipath effects, and terminal transmit power adjustments, causing the amplitude of the audio signal output by satellite handheld terminals to fluctuate within a wide range. Directly feeding an unstable signal into a power amplifier to drive the speaker will result in inconsistent call volume, severely impacting the user experience. A programmable gain amplifier (PGA) stabilizes the output signal amplitude within a suitable range by adjusting the amplification factor in real time, ensuring consistent volume output from the handset.

[0071] The programmable gain amplifier (PGA) receives the notch output audio signal from the transconductance-capacitor notch filter unit as input, and outputs a gain-adjusted audio signal after variable gain amplification. The core structure of the PGA consists of a gain selection switch network and a gain latch register. The gain selection switch network comprises an operational amplifier, a feedback resistor array, and an analog switch array. The operational amplifier is configured as an inverting amplifier; its non-inverting input is connected to analog ground to provide a stable reference level, and its inverting input receives the notch output audio signal through an input resistor. The feedback resistor array contains multiple precision resistors of different values. One end of each resistor is connected to the output of the operational amplifier, and the other end is connected to the inverting input of the operational amplifier through a corresponding analog switch.

[0072] Figure 2 This diagram illustrates the amplitude variation over time of the notch-filtered audio signal received by a programmable gain amplifier. The horizontal axis represents time in milliseconds, ranging from 0 to 2500 milliseconds, with 500-millisecond intervals as the primary scale. The vertical axis represents signal amplitude in millivolts, ranging from 0 to 1000 millivolts, with 200-millivolt intervals as the primary scale. The curve shows that the amplitude of the notch-filtered audio signal exhibits a segmented variation throughout the entire observation time window. During the time interval from 0 to 500 milliseconds, the signal amplitude remains at a low level of approximately 30 millivolts, corresponding to operating scenarios with poor satellite communication link signal quality or low terminal transmit power, resulting in weak received audio signal energy.

[0073] The curve exhibits relatively stable low-amplitude fluctuations during this time period, with the signal envelope represented by the light blue filled area, reflecting the actual energy distribution of the signal. When the time enters the 500-1000 ms interval, the signal amplitude rises significantly to approximately 200 mV, an increase of about 6.7 times. This change corresponds to an improvement in communication link quality or an increase in terminal transmit power. The area of ​​the blue envelope region of the curve expands accordingly, indicating an increase in signal energy. In the 1000-1500 ms interval, the signal amplitude further jumps to approximately 800 mV, reaching the peak level during the observation period. At this point, the signal envelope almost occupies most of the usable area of ​​the vertical axis. This high amplitude state may correspond to the terminal being in an optimal communication environment, with minimal link attenuation and optimal received signal strength. Subsequently, in the 1500-2000 ms time window, the signal amplitude drops back to approximately 100 mV, a decrease of about 8 times compared to the previous stage, reflecting a further deterioration in the communication environment or link quality fluctuations caused by terminal relocation.

[0074] In the final stage of the observation period, from 2000 to 2500 milliseconds, the signal amplitude stabilized at approximately 500 millivolts, a moderately high level, indicating that the link quality had recovered to a relatively good state. The entire curve exhibits a stepped change pattern, with each step lasting approximately 500 milliseconds. The transitions between steps are relatively rapid, with transition times on the order of tens of milliseconds. A high-frequency modulation component, represented by a dark blue solid line, is superimposed on the curve. This modulation component reflects the carrier characteristics of the audio signal itself, with a frequency of approximately 120 Hz, consistent with the typical spectral characteristics of speech signals. The filled area of ​​the signal envelope is displayed in semi-transparent blue, making the energy change trend of the signal readily apparent. Observing this graph, it is clear that the amplitude variation range of the notch filter output audio signal spans a wide range from 30 millivolts to 800 millivolts, with a dynamic range exceeding 28 dB. This wide range of amplitude fluctuations is the fundamental reason why a programmable gain amplifier is needed for adaptive adjustment.

[0075] The voltage gain of an inverting amplifier is determined by the ratio of the feedback resistor to the input resistor. Let the input resistor be... ,in This indicates the input resistance value, in kiloohms; the feedback resistance value of the gate is... ,in This indicates the currently effective feedback resistor value, in kiloohms. Then the voltage gain... The calculation formula is: ;in The voltage gain is indicated by a negative sign, signifying inverse phase. This embodiment features four gain levels. The input resistance is fixed at 10 kΩ, and the feedback resistor array includes four resistors of 10 kΩ, 31.6 kΩ, 100 kΩ, and 316 kΩ, corresponding to absolute gain values ​​of 1x, 3.16x, 10x, and 31.6x, respectively, equivalent to 0 dB, 10 dB, 20 dB, and 30 dB. The gain difference between adjacent levels is 10 dB. This step size can accommodate a wide range of signal amplitude changes without causing noticeable volume jumps due to excessively large single adjustments.

[0076] Figure 3 This demonstrates the dynamic adjustment of the gain level of a programmable gain amplifier over time. The horizontal axis represents time in milliseconds, with a scale range from 0 milliseconds to 2500 milliseconds. Figure 2A consistent time base is maintained for comparative analysis. The vertical axis represents the gain level in decibels (dB), ranging from -2 dB to 35 dB, with 10 dB increments, including four gain levels: 0 dB, 10 dB, 20 dB, and 30 dB. The curve is drawn with a thick black line, 3.5 units wide, using a stepped plot to fully represent the discrete switching characteristics of the gain levels. During the time interval from 0 milliseconds to 500 milliseconds, the gain level is set to 30 dB, which is the highest gain level provided by the system, corresponding to a voltage amplification factor of approximately 31.6 times.

[0077] This high gain setting and Figure 2 During this time period, the amplitude of a low 30mV input signal is matched, and the weak energy of the input signal is compensated for by high gain to ensure that the output reaches a usable level. The gain range during this time period is filled with red semi-transparent material, and a "30dB" label with a white background and red border is marked in the middle of the curve. When the time enters the 500ms to 1000ms range, the gain level is reduced to 20dB, corresponding to a voltage amplification factor of approximately 10 times. This adjustment responds to... Figure 2 When the input signal amplitude increases to 200 mV, the microcontroller detects the increased amplitude and automatically reduces the gain level to prevent output saturation. This time period is filled with orange and labeled "20dB". Within a 1000-1500 ms time window, the gain level is further reduced to 10 dB, the lowest gain level, with a voltage amplification factor of approximately 3.16. At this point, the input signal amplitude reaches a peak of 800 mV, and the system uses the minimum gain to prevent the output from exceeding the dynamic range; this area is filled with green and labeled "10dB". Subsequently, between 1500-2000 ms, the input signal amplitude drops back to 100 mV, and the gain level is correspondingly increased back to 20 dB, again filled with orange and labeled "20dB".

[0078] During the final 2000-2500 milliseconds, the input amplitude stabilizes at 500 millivolts, and the gain level remains at a low 10 dB, indicated by a green area marked "10 dB". The entire gain adjustment process exhibits an inverse relationship with the input signal amplitude; the gain decreases as the input amplitude increases and increases as the input amplitude decreases, demonstrating the negative feedback adjustment mechanism of automatic gain control. The switching of gain levels is represented by a vertical jump on the time axis, with the switching moment precisely corresponding to the moment of input signal amplitude change, indicating that the microcontroller's gain decision response is rapid. Each gain level is spaced 10 dB apart; this proportional step design results in a voltage amplification factor of approximately 3.16 times between adjacent levels, effectively adapting to a wide range of input signal variations. Observing this figure verifies that the programmable gain amplifier has four discrete gain levels: 0 dB, 10 dB, 20 dB, and 30 dB, which can be adjusted in real time according to the input signal amplitude, with the adjustment period synchronized with the input signal variation period.

[0079] The gain latch register stores the currently selected gain level and drives the analog switch array. It is a 2-bit parallel register; its data input is connected to the microcontroller's general purpose input / output port, and its clock input is connected to the latch pulse signal output by the microcontroller. The microcontroller selects one of four gain levels by writing a 2-bit binary code to the gain latch register: code 00 corresponds to 0 dB, code 01 to 10 dB, code 10 to 20 dB, and code 11 to 30 dB. The two outputs of the gain latch register are decoded into four independent switch control signals. Each control signal drives a corresponding analog switch in the feedback resistor array, ensuring that only one analog switch is active at any given time.

[0080] Figure 4This diagram illustrates the relationship between the amplitude of the output signal from the programmable gain amplifier and the amplitude detection value output by the amplitude detection unit over time, with the upper and lower thresholds of the automatic gain control system clearly marked. The horizontal axis represents time in milliseconds, ranging from 0 to 2500 milliseconds. The vertical axis represents amplitude in millivolts, ranging from 0 to 3500 millivolts, marked with 500 millivolt increments. First, the output signal envelope is represented by a light green semi-transparent filled area; the upper boundary of this area reflects the instantaneous amplitude change of the audio signal after gain adjustment. Within the time interval of 0 to 500 milliseconds, the output signal amplitude is approximately 950 millivolts, corresponding to a 30 millivolt input signal amplified by a 30 dB gain. Between 500 and 1000 milliseconds, the output amplitude is approximately 2000 millivolts, corresponding to a 200 millivolt input signal amplified by a 20 dB gain. Between 1000 and 1500 milliseconds, the output amplitude is approximately 2530 millivolts, close to the upper threshold level, which is obtained by amplifying an 800 millivolt input by 10 dB.

[0081] During the 1500-2000 ms period, the output amplitude is approximately 1000 mV, generated by amplifying a 100 mV input with a 20 dB gain. In the final 2000-2500 ms period, the output amplitude is approximately 1580 mV, corresponding to a 500 mV input amplified with a 10 dB gain. Superimposed on the output signal envelope is the amplitude detection curve, plotted as a thick red line with a width of 3.5 units. This curve represents the smoothed envelope obtained after the output signal has been processed by the rectifier and integrator circuits, reflecting the average amplitude level of the output signal. Due to the smoothing effect of the integrator circuit, the amplitude detection curve is flatter than the output signal envelope, lacking high-frequency modulation components and exhibiting smooth, segmented DC characteristics. Within each time period, the amplitude detection values ​​stabilize around approximately 950 mV, 2000 mV, 2530 mV, 1000 mV, and 1580 mV, respectively, closely matching the average amplitude of the output signal.

[0082] The upper threshold, marked with a thick purple dashed line at the 2500 mV vertical axis, is the threshold at which the microcontroller determines the output amplitude is too high. When the detected amplitude exceeds the upper threshold, the microcontroller lowers the gain level to prevent output saturation. The lower threshold, marked with a thick orange dashed line at the 500 mV vertical axis, is the threshold at which the output amplitude is too low. When the detected amplitude is below the lower threshold, the microcontroller raises the gain level to increase the output level. The area between the upper and lower thresholds, i.e., 500 mV to 2500 mV, is filled with light gray semi-transparent material and marked as the target range. This target range is the output amplitude range that the system expects to maintain, ensuring that neither excessively low amplitude leads to a decrease in the signal-to-noise ratio, nor excessively high amplitude causes signal clipping distortion.

[0083] The effectiveness of automatic gain control can be verified by observing the relationship between the amplitude detection value curve and the threshold. In the 1000-1500 ms timeframe, the amplitude detection value is approximately 2530 mV, slightly exceeding the upper threshold of 2500 mV. At this point, the system has already adopted the lowest gain setting of 10 dB and cannot further reduce the gain, thus allowing for a brief, slight overshoot. In all other timeframes, the amplitude detection value remains within the target range of 500 mV to 2500 mV, indicating that the automatic gain control system successfully stabilizes the output amplitude within the set dynamic range.

[0084] The amplitude detection unit extracts the amplitude envelope information of the gain-adjusted audio signal, providing a basis for the microcontroller's gain adjustment decision. The amplitude detection unit comprises two cascaded sub-circuits: a rectifier circuit and an integrator circuit. The rectifier circuit converts the bipolar AC audio signal into a unipolar signal, while the integrator circuit smooths and filters the rectified signal, outputting a DC voltage that reflects the average amplitude of the signal.

[0085] The rectifier circuit employs a precision full-wave rectifier structure, consisting of two operational amplifiers and four diodes connected in a specific topology. Compared to simple diode rectification, the precision rectifier utilizes the high open-loop gain of the operational amplifiers to overcome the forward voltage drop of the diodes, enabling accurate rectification of small signals in the millivolt range and avoiding rectification dead zones caused by signal amplitudes below the diode threshold voltage. The output of the rectifier circuit is the absolute value of the gain-adjusted audio signal, with a waveform of pulsating DC after full-wave rectification.

[0086] The integrator circuit employs a first-order low-pass filter structure, consisting of resistors and capacitors connected in series and parallel. Let the resistance of the filter resistor be... The capacitance of the filter capacitor is ,in This indicates the resistance value of the integrating resistor, in kiloohms. This represents the capacitance value of the integrating capacitor, in microfarads (µF). It also represents the time constant of the integrating circuit. for: ;in The time constant, expressed in milliseconds, determines the response speed of amplitude detection to signal changes. In this embodiment, an integrating resistor of 100 kiloohms and an integrating capacitor of 1 microfarad are selected, resulting in a time constant of 100 milliseconds. This time constant is approximately half the duration of a typical syllable in a speech signal, effectively smoothing amplitude fluctuations within a syllable to reflect the average level, and promptly tracking level changes between different syllables to achieve dynamic gain adjustment. The output of the integrating circuit is the amplitude detection value, expressed as a DC voltage representing the average amplitude of the gain-adjusted audio signal.

[0087] The microcontroller handles the digital processing tasks of amplitude detection value acquisition and gain level decision-making. The microcontroller has a built-in analog-to-digital converter (ADC), whose analog input channel is connected to the output of the amplitude detection unit, digitally sampling the amplitude detection values ​​at a fixed sampling period. In this embodiment, the sampling period is set to 10 milliseconds, corresponding to 100 samples per second, which is sufficient to capture the dynamic changes in the amplitude of the speech signal. The ADC has a resolution of 10 bits, a range of 0 volts to 3.3 volts, and a minimum resolution voltage of approximately 3.2 millivolts.

[0088] The microcontroller compares the acquired amplitude detection value with a preset threshold value to determine whether to adjust the gain level and the direction of adjustment. In this embodiment, the upper threshold is set to 2.5 volts, the lower threshold to 0.5 volts, and the target amplitude range is 0.5 volts to 2.5 volts. When the amplitude detection value is higher than the upper threshold, it indicates that the current gain is too high, causing the output to approach saturation, and the microcontroller lowers the gain level by one step. When the amplitude detection value is lower than the lower threshold, it indicates that the current gain is insufficient, causing the output level to be too low, and the microcontroller raises the gain level by one step. When the amplitude detection value is between the upper and lower thresholds, the current gain level remains unchanged. The minimum hold time for gain adjustment is set to 200 milliseconds, meaning there must be at least a 200-millisecond interval between two consecutive adjustments to avoid frequent gain switching caused by transient signal fluctuations.

[0089] The power amplifier amplifies the gain-adjusted audio signal from the programmable gain amplifier to a power level sufficient to drive the speaker. The input of the power amplifier connects to the output of the programmable gain amplifier, and the output connects to the speaker unit inside the microphone handle via a cable. The speaker unit has a nominal impedance of 8 ohms, a rated power of 0.5 watts, and a corresponding rated driving voltage of approximately 2 volts.

[0090] The power amplifier employs a bridge push-pull output structure, consisting of two complementary push-pull output stages. The speaker is connected between the two outputs to form a bridge load. Compared to single-ended output, the bridge output achieves four times the output power at the same supply voltage, which is beneficial for meeting the speaker's power requirements under low-voltage supply conditions. The power amplifier's voltage gain is set to 6 dB, amplifying the maximum 1-volt peak signal from the programmable gain amplifier to a 2-volt peak, meeting the speaker's driving requirements. An output filter is installed at the power amplifier's output to remove switching noise and high-frequency interference components; the filter cutoff frequency is set to 10 kHz.

[0091] In one alternative implementation, the programmable gain amplifier uses a continuously adjustable gain structure instead of a step-by-step switching structure, achieving stepless gain adjustment by adjusting the feedback resistor via a digital potentiometer. The tap position of the digital potentiometer is controlled by a microcontroller through a serial interface, with an adjustment resolution of up to 256 levels or even higher, resulting in smoother gain adjustment and avoiding the slight volume jumps that may occur during step-by-step switching.

[0092] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of the present invention. Therefore, the scope of the present invention is defined only by the appended claims.

Claims

1. An audio signal amplification and noise reduction system for a satellite handheld terminal expansion dock, characterized in that, include: Differential input port, used to receive the raw audio signal output from the satellite handheld terminal; An instrumentation amplifier, connected to a differential input port, is used to perform common-mode rejection and differential-mode amplification on the raw audio signal to output a primary amplified audio signal; The analog adaptive notch filter module is connected to the instrumentation amplifier and is used to process the primary amplified audio signal and output a notch output audio signal. The analog adaptive notch filter module includes an interference frequency detection unit, a bias current generation unit, and a transconductance-capacitance notch filter unit. The interference frequency detection unit outputs an interference frequency count value, the bias current generation unit generates a transconductance control current based on the interference frequency count value, and the transconductance-capacitance notch filter unit receives the transconductance control current and performs notch processing on the primary amplified audio signal to output a notch output audio signal. A programmable gain amplifier is used to perform gain adjustment on the notch-filtered audio signal and output the gain-adjusted audio signal. The amplitude detection unit is connected to the output of the programmable gain amplifier and is used to rectify and integrate the audio signal after gain adjustment to output the amplitude detection value. The microcontroller connects the amplitude detection unit and the programmable gain amplifier to acquire amplitude detection values ​​and set the gain level accordingly; the power amplifier receives the gain-adjusted audio signal and drives the speaker unit of the microphone handset to produce sound.

2. The system as described in claim 1, characterized in that, The differential input port is connected to the satellite handheld terminal via a shielded twisted pair cable. The two cores of the shielded twisted pair cable are connected to the positive and negative terminals of the differential input port, respectively, and the shielding layer of the shielded twisted pair cable is connected to the ground of the docking station's chassis.

3. The system as described in claim 1, characterized in that, The interference frequency detection unit includes a zero-crossing comparator, an edge counter, a timing window generator, and a frequency latch. The non-inverting input of the zero-crossing comparator receives the primary amplified audio signal, the inverting input of the zero-crossing comparator is connected to the analog ground potential, and the zero-crossing comparator outputs a rectangular pulse sequence corresponding to the zero-crossing time of the primary amplified audio signal.

4. The system as described in claim 3, characterized in that, The timing window generator consists of an oscillator and a frequency divider. The oscillator generates a clock signal, and the frequency divider divides the clock signal to output periodic window enable and window end signals. The edge counter accumulates the count of the rising edges of the rectangular pulse sequence during the window enable signal's validity period, and outputs the count value to the frequency latch and performs a clear reset when the window end signal arrives. The frequency latch holds the count value as the interference frequency count value until the next window end signal arrives.

5. The system as described in claim 1, characterized in that, The bias current generation unit includes a digital-to-analog converter, a voltage-to-current converter, and a current mirror; The digital-to-analog converter receives the interference frequency count value and converts it into a frequency indication voltage according to the frequency-voltage mapping table pre-stored in the read-only memory. The frequency-voltage mapping table stores a one-to-one correspondence between discrete count values ​​and corresponding voltage values. The digital-to-analog converter outputs the frequency indication voltage corresponding to the interference frequency count value by looking up the frequency-voltage mapping table.

6. The system as described in claim 5, characterized in that, The voltage-to-current converter consists of an operational amplifier and a reference resistor. The non-inverting input of the operational amplifier receives the frequency indication voltage, and the output of the operational amplifier is connected to the inverting input of the operational amplifier through the reference resistor. The current flowing through the reference resistor forms the reference bias current and is output from the output of the operational amplifier.

7. The system as described in claim 5, characterized in that, The current mirror is composed of a first PMOS transistor and a second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the positive power supply terminal. The gate and drain of the first PMOS transistor are shorted and receive the reference bias current. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor. The drain of the second PMOS transistor outputs a transconductance control current that is mirror-proportional to the reference bias current.

8. The system as described in claim 1, characterized in that, The transconductance-capacitor notch filter unit adopts a dual second-order notch topology, including a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, a first on-chip capacitor, a second on-chip capacitor, and an output summing node. The first, second, third, and fourth transconductance amplifiers all employ a differential input single-ended output structure and have a bias current terminal, which receives the transconductance control current. The non-inverting input of the first transconductance amplifier receives the primary amplified audio signal, the inverting input is connected to the upper plate of the second on-chip capacitor, and the output is connected to the first on-chip capacitor. The upper plate of the first capacitor is connected to the first transconductance amplifier; the non-inverting input of the second transconductance amplifier is connected to the upper plate of the first capacitor, the inverting input of the second transconductance amplifier is connected to the analog ground potential, and the output of the second transconductance amplifier is connected to the upper plate of the second capacitor; the non-inverting input of the third transconductance amplifier is connected to the upper plate of the first capacitor, the inverting input of the third transconductance amplifier is connected to the analog ground potential, and the output of the third transconductance amplifier is connected to the output summing node; the non-inverting input of the fourth transconductance amplifier receives the primary amplified audio signal, the inverting input of the fourth transconductance amplifier is connected to the analog ground potential, and the output of the fourth transconductance amplifier is connected to the output summing node. The lower plates of the first and second capacitors are both connected to simulated ground potential, and the output summation node outputs a notch filter to output an audio signal.

9. The system as described in claim 8, characterized in that, The notch center frequency of the transconductance-capacitor notch filter unit is determined by the ratio of the transconductance value of the first transconductance amplifier to the capacitance value of the first on-chip capacitor. When the transconductance control current increases, the transconductance values ​​of the first, second, third, and fourth transconductance amplifiers increase synchronously to shift the notch center frequency towards higher frequencies. When the transconductance control current decreases, the notch center frequency shifts towards lower frequencies. Interference components in the primary amplified audio signal with frequencies equal to the notch center frequency form a notch attenuation channel through the transconductance-capacitor notch filter unit, while speech components in the primary amplified audio signal with frequencies deviating from the notch center frequency form a passband channel through the transconductance-capacitor notch filter unit.

10. The system as claimed in claim 1, characterized in that, The programmable gain amplifier includes a gain selection switch network and a gain latch register. The control terminal of the microcontroller is connected to the gain latch register to write the gain level. The amplitude detection unit includes a rectifier circuit and an integrator circuit. The rectifier circuit and the integrator circuit are connected to the output terminal of the programmable gain amplifier and output the amplitude detection value. The microcontroller collects the amplitude detection value and updates the gain level. The input terminal of the power amplifier is connected to the output terminal of the programmable gain amplifier. The output terminal of the power amplifier is connected to the speaker unit of the microphone handset.

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