Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the same are provided. The semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked; the channel structure extends into the gate stack structure; a plurality of first semiconductor patterns at one end of the channel structure, each of the plurality of first semiconductor patterns including a P-doped region and an undoped region; an N-doped region between adjacent ones of the first semiconductor patterns; a blocking pattern between the P-doped region and the N-doped region; and a common source electrode on each of the plurality of first semiconductor patterns and a respective surface of the N-doped region.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0131034, filed on September 26, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device and an electronic system including the same. BACKGROUND

[0003] An electronic system requiring data storage can require a semiconductor device capable of storing a large amount of data. Accordingly, methods for increasing the data storage capacity of a semiconductor device are being researched. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally rather than two-dimensionally is proposed. SUMMARY

[0004] The present disclosure attempts to provide a semiconductor element and an electronic system including the same that ensure improved reliability and reduced misalignment during a manufacturing process.

[0005] According to some embodiments, a semiconductor device includes a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked; a channel structure extending into the gate stack structure; a plurality of first semiconductor patterns at one end of the channel structure, each of the plurality of first semiconductor patterns including a P-doped region and an undoped region; an N-doped region between adjacent ones of the first semiconductor patterns; a barrier pattern between the P-doped region and the N-doped region; and a common source electrode on a respective surface of each of the plurality of first semiconductor patterns and the N-doped region.

[0006] According to some embodiments, a method for manufacturing a semiconductor device includes forming an N-doped region on a substrate; forming an etch stopper by etching a portion of the N-doped region; forming a gate stack structure on the N-doped region and the etch stopper; forming a channel hole extending into the gate stack structure and overlapping the etch stopper; removing the etch stopper; forming a gate dielectric layer and a channel layer in the channel hole and a region where the etch stopper is removed; forming a trench by removing a material filling the substrate and the etch stopper; forming a barrier pattern on a side surface of the trench; and forming an undoped region and a P-doped region in the trench.

[0007] According to some embodiments, there is provided a semiconductor device including: a substrate including an N-doped region and a plurality of first semiconductor patterns in the N-doped region; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; and a channel structure extending into the gate stack structure and superposed with the first semiconductor patterns. The first semiconductor patterns include a P-doped region and an undoped region, and the first semiconductor patterns include a barrier pattern between the P-doped region and the N-doped region.

[0008] According to some embodiments, there is provided an electronic system including: a main substrate; a semiconductor device on the main substrate; and a controller on the main substrate and electrically connected to the semiconductor device, wherein the semiconductor device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked; a channel structure extending into the gate stack structure; a plurality of first semiconductor patterns at one end of the channel structure, each of the plurality of first semiconductor patterns including a P-doped region and an undoped region; an N-doped region between adjacent first semiconductor patterns of the plurality of first semiconductor patterns; a barrier pattern between the P-doped region and the N-doped region; and a common source electrode on respective surfaces of the plurality of first semiconductor patterns and the N-doped region.

[0009] The embodiments set forth above can provide semiconductor elements and electronic systems including semiconductor elements that ensure improved reliability and reduced misalignment during a manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic plan view of a semiconductor element according to some embodiments.

[0011] Figure 2 is a cross-sectional view taken along line A-A' in Figure 1 .

[0012] Figure 3 is an enlarged cross-sectional view of region A in Figure 2 .

[0013] Figure 4 shows the direction of flow of hole current for erasing and the direction of flow of electron current in channel inversion during a read operation in the same region as Figure 3 .

[0014] Figures 5 to 25 shows a manufacturing process according to some embodiments of the present disclosure.

[0015] Figure 26 is a view schematically showing an electronic system including a semiconductor device according to some embodiments.

[0016] Figure 27 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to some embodiments.

[0017] Figure 28 Conceptually shown Figure 27 The area cut along line I-I' of the semiconductor package. Detailed Implementation

[0018] In the following detailed description, embodiments of the present disclosure are given with reference to the accompanying drawings, enabling those skilled in the art to readily practice the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments provided herein.

[0019] To clearly represent multiple layers and regions, the thicknesses of these layers and regions are exaggerated in the accompanying drawings. Throughout the specification, the same reference numerals designate the same elements. It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element may be directly on the other element or may have another element placed between it. On the other hand, when an element is referred to as being "directly on" another element, there is no third element placed between them.

[0020] In the following, semiconductor devices and electronic systems according to embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Here, terms indicating sequence (such as first, second, etc.) are used to distinguish elements having the same / similar functions, and ordinal numbers may be interchanged according to the order in which the terms are mentioned. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] The following description refers to Figures 1 to 5 A semiconductor device is described according to some embodiments.

[0022] Figure 1 This is a schematic plan view of a semiconductor element according to some embodiments. Figure 2 It is along Figure 1 The sectional view taken by line A-A' in the middle. Figure 3 yes Figure 2 An enlarged sectional view of region A in the diagram. For ease of description, Figure 3 By flipping Figure 2 To show the top and bottom of region A. Figure 2 Region A in the middle.

[0023] Reference Figures 1 to 3A semiconductor device according to some embodiments may include a cell region 100 having a memory cell structure and a circuit region 200 having a peripheral circuit structure, the peripheral circuit structure controlling the operation of the memory cell structure. As an example, the circuit region 200 and the cell region 100 may be respectively connected to the memory cell structure... Figure 26 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 in the electronic system 1000 are shown as corresponding portions. In some embodiments, the circuit region 200 and the cell region 100 may each include... Figure 28 The semiconductor chip 2200 shown in the figure has a first structure 4100 and a second structure 4200.

[0024] Here, circuit region 200 may include peripheral circuit structures formed on the first substrate 210, and cell region 100 may include a gate stack structure 120 and a channel structure CH as a memory cell structure. In some embodiments, cell region 100 may be disposed on circuit region 200. Therefore, the region corresponding to circuit region 200 does not need to be ensured separately from cell region 100, thus reducing the area of ​​the semiconductor device. However, some embodiments are not limited to this, and circuit region 200 may be disposed adjacent to cell region 100. Some embodiments may be modified in various other ways.

[0025] The circuit region 200 may include a first substrate 210, circuit elements 220 formed on the first substrate 210, and a first wiring portion 230.

[0026] The first substrate 210 may be a semiconductor substrate comprising a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or it may be a semiconductor substrate in which a semiconductor layer is formed on a substrate. As an example, the first substrate 210 may include monocrystalline silicon or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).

[0027] The circuit element 220 formed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structure disposed in the cell region 100. As an example, the circuit element 220 may be configured with peripheral circuit structures (such as decoder circuitry 1110). Figure 26 (in the middle), page buffer 1120 (in Figure 26 (in the middle), logic circuit 1130 (in Figure 26 medium).

[0028] Circuit element 220 may include, for example, transistors, but is not limited thereto. For example, circuit element 220 may include not only active elements (such as transistors) but also passive elements (such as capacitors, resistors, or inductors).

[0029] A first wiring portion 230 disposed on a first substrate 210 may be electrically connected to a circuit element 220. In some embodiments, the first wiring portion 230 may include a plurality of wiring layers 234 spaced apart from each other while having a wiring insulating layer 232 therebetween, and connected to each other via contact vias 236 to form a desired path. The wiring layers 234 or contact vias 236 may include various conductive materials, and the wiring insulating layer 232 may include various insulating materials.

[0030] Circuit region 200 may include a second insulating layer IL2 disposed on the first wiring portion 230 and a second pad CP2 disposed in the second insulating layer IL2. The second pad CP2 may be disposed from the surface of the second insulating layer IL2 (e.g., Figure 2 The upper surface of the second pad CP2 is exposed. The second pad CP2 and the wiring layer 234 can be connected to each other via a via VIA. The via VIA can penetrate the second insulating layer IL2 and the wiring insulating layer 232 to connect the second pad CP2 to the wiring layer 234. The second pad CP2 may include copper, but is not limited thereto.

[0031] Cell region 100 may include a gate stack structure 120 and a channel structure CH. Cell region 100 may include a structure for connecting the gate stack structure 120 and / or the channel structure CH formed in cell region 100 to circuit region 200 or external circuitry.

[0032] Cell region 100 may include a first insulating layer IL1 disposed in the portion contacting circuit region 200 and a first pad CP1 disposed in the first insulating layer IL1. The first pad CP1 may be disposed from the surface of the first insulating layer IL1 (e.g., Figure 2 The lower surface of the first pad CP1 is exposed. The first pad CP1 and bit line 181 can be connected to each other via a via VIA. The via VIA penetrates the first insulating layer IL1 to connect the first pad CP1 to the bit line 181. The first pad CP1 may include, but is not limited to, copper. Figure 2 As shown, the first pad CP1 and the second pad CP2 can be in direct contact with each other. That is, the cell region 100 and the circuit region 200 can be connected to each other through the first pad CP1 and the second pad CP2. Each of the first pad CP1 and the second pad CP2 may include copper, but is not limited thereto.

[0033] Cell region 100 may include gate stack structure 120 and channel structure CH. Gate stack structure 120 includes alternately stacked cell insulating layers 132 and gate electrodes 130. Channel structure CH extends in a third direction (Z direction) by extending into or through gate stack structure 120.

[0034] The unit insulating layer 132 may include an interlayer insulating layer 132m disposed between two adjacent gate electrodes 130 in each of the plurality of gate stack structures 120a and 120b, and an interface insulating layer 132a or 132b disposed on one surface of each of the plurality of gate stack structures 120a and 120b. In some embodiments, the thicknesses of the plurality of unit insulating layers 132 may not all be the same. For example, the thickness of the interface insulating layer 132a or 132b may be greater than the thickness of the interlayer insulating layer 132m.

[0035] The gate electrode 130 may comprise various conductive materials. For example, the gate electrode 130 may comprise a metallic material (e.g., tungsten (W), copper (Cu), aluminum (Al), or molybdenum (Mo)), polycrystalline silicon, a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a combination thereof. The unit insulating layer 132 may comprise various insulating materials. For example, the unit insulating layer 132 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0036] In some embodiments, the channel structure CH can be formed by passing through the gate stack structure 120 and extending in a direction intersecting with the first substrate 210 (e.g., a direction perpendicular to the first substrate 210; i.e., the Z-axis direction in the figures).

[0037] Simultaneously refer to Figure 2 and Figure 3 The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 disposed on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may also include a core insulating layer 142 disposed in the channel layer 140, or in another example, the channel structure CH may not include a core insulating layer 142. The channel structure CH may include a first semiconductor pattern 146 and a second semiconductor pattern 147, each disposed at one end of the channel structure CH. The gate dielectric layer 150 disposed between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156 sequentially formed on the channel layer 140.

[0038] Each channel structure CH can form a string of memory cells, and multiple channel structures CH can be arranged in rows and columns on a plane while being spaced apart from each other. For example, multiple channel structures CH can be arranged in any shape on a plane, such as a grid shape, a zigzag shape, etc. The channel structure CH can have a columnar shape. However, some embodiments are not limited to this, and the arrangement, shape, etc., of the channel structures CH can be modified in various ways.

[0039] The channel layer 140 may include a semiconductor material (e.g., monocrystalline silicon or polycrystalline silicon). The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0040] The tunneling layer 152 may include an insulating material (e.g., silicon oxide or silicon oxynitride) that allows charge tunneling. The charge storage layer 154 may serve as a data storage region and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material that prevents unwanted charge from flowing into the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0041] However, the materials, stacking structures, etc. of each of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 can be modified in various ways, and some embodiments are not limited thereto.

[0042] like Figure 2 As shown, the first semiconductor pattern 146 and the second semiconductor pattern 147 may be disposed at both ends of the channel structure CH to be electrically connected to the channel layer 140.

[0043] The second semiconductor pattern 147 may be disposed in the region where the core insulating layer 142 has been removed and may be in contact with the channel layer 140. The second semiconductor pattern 147 may comprise epitaxial silicon, epitaxial germanium, polycrystalline silicon, monocrystalline silicon, polycrystalline germanium, or monocrystalline germanium, whether doped or undoped. For example, the second semiconductor pattern 147 may comprise N+ doped polycrystalline silicon, and as described below, the second semiconductor pattern 147 may be connected to the bit line 181, and the first semiconductor pattern 146 may be connected to the common source electrode 112.

[0044] Reference Figure 3 The first semiconductor pattern 146 may include a P-doped region 1461 and an undoped region 1462. As described separately below, the P-doped region 1461 may be a region that is P-doped and electrically connected to the common source electrode 112, and the undoped region 1462 may be a region provided with undoped crystalline silicon. Figure 3 A common source electrode-interface layer 113 disposed on the common source electrode 112 is shown; this is merely an example, and the common source electrode-interface layer 113 may be omitted in some embodiments. The common source electrode-interface layer 113 may include TiN, but is not limited thereto. The common source electrode 112 may include, for example, tungsten, but is not limited thereto.

[0045] like Figure 3As shown, the P-doped region 1461 can be disposed between the undoped region 1462 and the common source electrode 112. This structure can be obtained by forming the P-doped region 1461 in a self-aligned manner, which is described separately below. Figure 2 and Figure 3 As shown, the semiconductor device according to this embodiment may have a P-doped region 1461 disposed below each channel structure CH. Furthermore, as described separately below, an N-doped region 149 may be disposed between the respective P-doped regions 1461, and a blocking pattern 148 may be disposed between the N-doped regions 149 and the P-doped regions 1461. Therefore, the semiconductor device according to this embodiment can effectively perform a bulk erase operation. See below for reference... Figure 3 and Figure 4 Describe the specific effects of the operation.

[0046] Refer again Figure 2 In some embodiments, the gate stack structure 120 may include a plurality of gate stack structures 120a and 120b stacked sequentially. The number of stacked gate electrodes 130 can thus be increased, thereby increasing the number of memory cells in a stable structure. The figures illustrate a gate stack structure 120 including a first gate stack structure 120a and a second gate stack structure 120b. However, some embodiments are not limited thereto. The gate stack structure 120 may include one gate stack structure, or it may include three or more gate stack structures.

[0047] As described above, when multiple gate stack structures 120a and 120b are configured, the channel structure CH may have multiple channel structures CHa and CHb extending into or through the multiple gate stack structures 120a and 120b, respectively. The multiple channel structures CHa and CHb may be connected to each other. Each of the multiple channel structures CHa and CHb may have a sloping side surface that narrows as the structure approaches the common source electrode 112 based on its aspect ratio when viewed in cross-section, and due to the width difference, a bent portion may be formed at the connection portion between the multiple channel structures CHa and the multiple channel structures CHb. As another example, each of the multiple channel structures CHa and CHb may have a continuously connected sloping side surface without a bent portion. Figure 2The diagram illustrates that the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of each of the plurality of channel structures CHa and CHb extend to form an integral structure. However, some embodiments are not limited to this, and the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of each of the plurality of channel structures CHa and CHb may be formed separately from each other and then electrically connected to each other. Furthermore, separate channel pads may be further disposed on the connection portions between the plurality of channel structures CHa and CHb. In this way, some embodiments are not limited to the form of the plurality of channel structures CHa and CHb.

[0048] In some embodiments, the gate stack structure 120 can be planarly divided into multiple portions by extending in a direction intersecting the first substrate 210 (e.g., a direction perpendicular to the first substrate 210; i.e., the Z-axis direction in the figures) through a separation structure 160 of the gate stack structure 120. Furthermore, a separation pattern 170 may be formed on one side of the gate stack structure 120. (See also...) Figure 1 Multiple separation structures 160 and / or separation patterns 170 may be arranged on a plane and extend in a second direction (the Y-axis direction in the figures) to be spaced apart from each other at a predetermined distance in a first direction (the X-axis direction in the figures) that intersects with the second direction.

[0049] Through the separation structure 160, multiple gate stack structures 120 can each extend in a plane in a second direction (the Y-axis direction in the figures) to be spaced apart from each other at a predetermined distance in a first direction (the X-axis direction in the figures). The gate stack structures 120 separated by the separation structure 160 can be configured into a memory cell block. However, some embodiments are not limited to this, and the scope of the memory cell block is not limited to this.

[0050] For example, the separation structure 160 may extend through the gate stack structure 120, and the separation pattern 170 may separate only one or some of the plurality of gate electrodes 130 from each other.

[0051] Separation patterns 170 may be disposed between separation structures 160. Each of the plurality of separation patterns 170 may be disposed between adjacent separation structures 160. Here, the gate electrode 130 separated by the separation pattern 170 may be referred to as the select gate electrode 130g. Here, the select gate electrode 130g may be a string select gate electrode for selecting strings, and the separation pattern 170 may be a string separation pattern for separating strings. In some embodiments, the select gate electrode 130g may also include gate electrodes other than the string select gate electrode for selecting strings.

[0052] As an example, the separation structure 160 is shown as having a sloping side that, when viewed in cross-section, has a width that gradually decreases as the structure approaches the common source electrode 112 due to a high aspect ratio, and some embodiments are not limited to this. Furthermore, this embodiment shows the separation structure 160 including a bent portion at the connection between the plurality of gate stack structures 120a and the plurality of gate stack structures 120b. However, the separation structure 160 may not include a bent portion at the connection between the plurality of gate stack structures 120a and the plurality of gate stack structures 120b.

[0053] The separation structure 160 or separation pattern 170 may be partially or completely filled with various insulating materials. For example, the separation structure 160 or separation pattern 170 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Figure 2 and Figure 3 The diagram shows a discrete structure 160 partially or completely filled with a first layer 161, a second layer 162, a third layer 163, a first semiconductor pattern 146, and a second semiconductor pattern 147, but is not limited thereto. In some embodiments, the first layer 161 of the discrete structure 160 may comprise silicon oxide, the second layer 162 may comprise silicon nitride, and the third layer 163 may comprise silicon oxide; these are merely examples, and the disclosure is not limited thereto.

[0054] In addition, such as Figure 2 As shown, a contact via 182 can be disposed between the channel structure CH and the bit line 181. (Refer to...) Figure 1 Bit line 181 may extend in a first direction (X-axis direction in the figure) that intersects with the second direction along which gate electrode 130 extends. Bit line 181 may be electrically connected to channel structure CH via contact via 182.

[0055] Reference Figure 2 The common source electrode 112 may be disposed on another surface of the gate stack structure 120 (e.g., Figure 2 On the upper surface of the channel structure CH. The common source electrode 112 can be connected to the first semiconductor pattern 146 of the channel structure CH. The common source electrode 112 can be configured as the common source line of a non-volatile memory device (e.g., Figure 26 (CSL in the text). The common source electrode 112 may include, for example, doped polysilicon, a metal, or a combination thereof, and is not limited thereto. Figure 2 As shown, a common source electrode-interface layer 113 may be disposed between the common source electrode 112 and the channel structure CH. The common source electrode 112 may include tungsten, and the common source electrode-interface layer 113 may include TiN. In some embodiments, the common source electrode-interface layer 113 may be omitted.

[0056] Although Figure 2Not shown, but another semiconductor structure including the unit region can be stacked on the common source electrode 112. In this case, Figure 2 The common source electrode 112 of the semiconductor structure shown and the additionally stacked common source electrodes of the semiconductor structures can be stacked facing each other, and the common source electrodes 112 of the respective semiconductor structures can be connected to each other. This connection can be made using copper pads. This connection configuration is an example, and a schematic connection configuration is shown as follows. Figure 28 The 2-1 structure 4200a and the 2-2 structure 4200b are included, but are not limited to these.

[0057] The following description is referenced below. Figure 3 The connection configuration between the common source electrode 112 and the channel structure CH is described. For ease of description, Figure 3 This is shown by flipping the top and bottom of region A. Figure 2 Region A in the middle.

[0058] Reference Figure 3 The N-doped region 149 and the first semiconductor pattern 146 may be disposed on one surface of the common source electrode 112. The first semiconductor pattern 146 may include a P-doped region 1461 and an undoped region 1462. The P-doped region 1461 may be a region that is P-doped and electrically connected to the common source electrode 112, and the undoped region 1462 may be a region disposed of with undoped crystalline silicon.

[0059] Simultaneously refer to Figure 1 and Figure 3 , Figure 1 The remaining region of the un-channeled CH and P-doped region 1461 can be an N-doped region 149. That is, the channeled CH can be disposed in the N-doped region 149, and the P-doped region 1461 can be superimposed on the channeled CH. For example, the P-doped region 1461 can be superimposed on the channeled CH in a direction perpendicular to the substrate including the N-doped region 149 and the first semiconductor pattern 146 (e.g., the Z-axis direction in the figure).

[0060] Reference Figures 1 to 3 The planar dimension or diameter of the P-doped region 1461 may be less than (i.e., less than) or equal to the planar dimension or diameter of the widest portion of the channel structure. Furthermore, the planar dimension or diameter of the P-doped region 1461 may be greater than (i.e., more than) the planar dimension or diameter of the portion of the channel structure that contacts the first semiconductor pattern 146. For example, the planar dimension or diameter of the P-doped region 1461 may be greater than the planar dimension or diameter of the narrowest portion of the channel structure. Figure 1 This shows a cross-section of the widest part of the channel structure CH. (Example) Figure 1As shown, the planar dimension or planar diameter of the P-doped region 1461 may be smaller than the planar dimension or planar diameter of the widest part of the channel structure CH.

[0061] like Figure 3 As shown, the barrier pattern 148 may be disposed between the P-doped region 1461 and the N-doped region 149. Therefore, the P-doped region 1461 and the N-doped region 149 may not be in direct contact with each other. The barrier pattern 148 may include silicon oxide, but is not limited thereto. The barrier pattern 148 may include an insulating material.

[0062] However, refer to Figure 3 The blocking pattern 148 may not completely electrically insulate the first semiconductor pattern 146 and the N-doped region 149 from each other. For example... Figure 3 As shown, the barrier pattern 148 may be spaced apart from the gate dielectric layer 150 and may not be in direct contact with the gate dielectric layer 150. The channel layer 140 may be disposed between the barrier pattern 148 and the gate dielectric layer 150. The barrier pattern 148 may be in contact with the first semiconductor pattern 146, which serves as a conductive layer, the channel layer 140, and the N-doped region 149.

[0063] like Figure 3 As shown, the first semiconductor pattern 146 and the N-doped region 149 are electrically connected to each other at one end of the barrier pattern 148. Figure 3 As shown, the first semiconductor pattern 146 and the channel layer 140 may be in contact with each other, and the channel layer 140 and the N-doped region 149 may be in contact with each other. Therefore, the first semiconductor pattern 146, the channel layer 140, and the N-doped region 149 may be electrically connected to each other. Thus, as described separately below, the electronic current applied to the channel structure CH may flow to the N-doped region 149, the channel layer 140, and the undoped region 1462 of the first semiconductor pattern 146, and the hole current for the erase operation transmitted through the common source electrode 112 may be applied to the P-doped region 1461 and the undoped region 1462 of the first semiconductor pattern 146, as well as the channel layer 140.

[0064] Figure 4 Showing with Figure 3 The direction of hole current flow for erasure in the same region and the direction of electron current flow during channel reversal during read operation. For example... Figure 4 As shown in the central portion, hole current can flow to the P-doped region 1461 and the undoped region 1462 of the first semiconductor pattern 146, as well as the channel layer 140. Figure 4As shown on the right, the electron current for the read operation can flow in reverse through the undoped region 1462 of the first semiconductor pattern 146 and the channel of the channel layer 140 to the N-doped region 149. The flow of the hole current for the erase operation and the movement path of the electron current for the read operation can be independent of each other and do not affect each other.

[0065] In other words, the semiconductor device according to some embodiments can perform erasure by allowing hole current to flow directly from the P-doped region 1461 to the channel. Therefore, the semiconductor device according to these embodiments can perform fast erasure. Erasure methods that operate by charging the channel capacitance are limited in their efficiency due to the increased charging time and the increased erasure time resulting from the increased charging time. However, the semiconductor device according to these embodiments can perform erasure by applying hole current directly from the P-doped region 1461 to the channel, thus achieving fast erasure. However, the erasure method performed by applying hole current directly to the channel can have a complex structure because it requires separating the hole current path (hole path) for erasure and the electron current path (electron path) for read operations. Furthermore, the electron path and hole path can be disconnected due to misalignment during the process of forming the P-doped and N-doped regions. However, in the semiconductor device according to this embodiment, the P-doped region 1461 can be disposed below each channel structure CH, and the N-doped region 149 can be disposed between the P-doped regions 1461. A blocking pattern 148 may be disposed between the P-doped region 1461 and the N-doped region 149, thereby separating the P-doped region 1461 and the N-doped region 149 from each other. Here, as... Figure 3 and Figure 4 As shown, electron paths and hole paths can be independent of each other without affecting each other. Furthermore, in the method for manufacturing the semiconductor device according to these embodiments, the P-doped region 1461 can be formed in a self-aligned manner, thereby solving the problem of electron paths and hole paths being disconnected due to misalignment during the processes of forming the P-doped region 1461 and the N-doped region 149, respectively.

[0066] The following description describes a method for manufacturing a semiconductor device according to this embodiment.

[0067] Figures 5 to 25 The present disclosure illustrates manufacturing processes according to some embodiments of the present disclosure. For ease of description, reference is made to... Figures 5 to 25 Description for manufacturing Figure 2 The method for region A in the middle.

[0068] First, refer to Figure 5An auxiliary substrate 310 can be prepared, and the auxiliary substrate 310 can be N-doped to form an N-doped region 149. Then, an etch stop 311 can be formed on the auxiliary substrate 310. Here, the N-doped material can be phosphorus (P) or arsenic (As), and is not limited thereto.

[0069] The etch stop 311 can be formed by forming a groove H1 in the auxiliary substrate 310 and filling the groove H1 of the auxiliary substrate 310. For example... Figure 5 As shown, the etch stop 311 may include a first layer 312 and a second layer 313. The first layer 312 may be disposed along the surface of the groove H1 of the auxiliary substrate 310, and the second layer 313 may partially or completely fill the interior of the groove H1. However, this configuration is exemplary, and the present disclosure is not limited thereto. The etch stop 311 may also be formed as a single layer. The etch stop 311 may include one or more of polysilicon, tungsten, TiN, and / or carbon. If the second layer 313 of the etch stop 311 includes tungsten, then the first layer 312 may include TiN. In this case, the first layer 312 including TiN can prevent the diffusion of tungsten in the second layer 313. However, if the etch stop 311 includes polysilicon, TiN, or carbon, the etch stop 311 may be formed as a single layer.

[0070] In addition, such as Figure 5 As shown, an interface layer 315 may be provided between the etch stop member 311 and the auxiliary substrate 310. The interface layer 315 may include silicon oxide, but is not limited thereto. In some embodiments, the interface layer 315 may be omitted.

[0071] Next, refer to Figure 6 Multiple interlayer insulating layers 132m and multiple sacrificial insulating layers 130s can be alternately stacked on an auxiliary substrate 310 to form a first stacked structure 120d. The interlayer insulating layer 132m may include silicon oxide, silicon nitride, silicon oxynitride, low-k materials, etc.; and the sacrificial insulating layer 130s may include at least one of silicon, silicon oxide, silicon carbide, and / or silicon nitride, and may be made of a material different from that of the interlayer insulating layer 132m. For example, the interlayer insulating layer 132m may include silicon oxide, and the sacrificial insulating layer 130s may include silicon nitride. The sacrificial insulating layer 130s may be fabricated in a subsequent process with a gate electrode 130 (see [link to relevant documentation]). Figure 2 The sacrificial insulating layer 130s can be formed to correspond to the formation of the gate electrode 130 (see [link to relevant documentation]). Figure 2 ( ) part.

[0072] Next, refer to Figure 7The first stacked structure 120d can be patterned to form a first sub-via CHS1 and a second sub-via CHS2 that overlap with each of the etch stop members 311 through the first stacked structure 120d. The first sub-via CHS1 may be the region where the channel structure CH will be formed, and the second sub-via CHS2 may be the region where the separation structure 160 will be formed. Figure 11 The cross-sections of the first sub-hole CHS1 and the second sub-hole CHS2 are shown. The planar shape of the first sub-hole CHS1 can be similar to... Figure 1 The channel structure CH shown is similar to a circular shape, and the planar shape of the second sub-hole CHS2 can be as follows: Figure 1 The shape of the separation structure 160 shown extends in the second direction (Y direction).

[0073] The first sub-hole CHS1 and the second sub-hole CHS2 can be formed by stacking them with an etch stop element 311, and a portion of the etch stop element 311 can be etched due to the formation of the first sub-hole CHS1 and the second sub-hole CHS2. In this step, each of the first sub-hole CHS1 and the second sub-hole CHS2 can be partially or completely filled with a sacrificial film CHP. The sacrificial film CHP filling each of the first sub-hole CHS1 and the second sub-hole CHS2 can comprise polycrystalline silicon or a carbon-based material. However, the material of the sacrificial film CHP is not limited to these and can be changed in various ways.

[0074] Next, refer to Figure 8 The sacrificial film CHP and etch stop 311 that fill the interior of the first sub-hole CHS1 can be removed. Here, the interface layer 315 may not need to be removed.

[0075] Next, refer to Figure 9 The gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 can be formed in the first sub-hole CHS1 after the sacrificial film CHP and the etch stop element 311 have been removed.

[0076] The gate dielectric layer 150 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156. The tunneling layer 152 may include an insulating material (e.g., silicon oxide or silicon oxynitride) that allows charge tunneling. The charge storage layer 154 may serve as a data storage region and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material that prevents unwanted charge from flowing into the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a combination thereof. As an example, the tunneling layer 152 may include silicon oxide, the charge storage layer 154 may include silicon nitride, and the barrier layer 156 may include silicon oxide. However, this configuration is merely an example, and the present disclosure is not limited thereto. If the barrier layer 156 includes silicon oxide and the interface layer 315 also includes silicon oxide, the boundary between the barrier layer 156 and the interface layer 315 may not be identified. That is, as... Figure 9 As shown, the boundary between the interface layer 315 and the barrier layer 156 can be indistinguishable, and the interface layer 315 and the barrier layer 156 can be identified as one layer.

[0077] The channel layer 140 may include a semiconductor material (e.g., monocrystalline silicon or polycrystalline silicon). The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The core insulating layer 142 may partially or completely fill the space in the first sub-via CHS1. In the trench H1 where the etch stop has been removed, the core insulating layer 142 may not completely fill the trench H1, and voids may be formed.

[0078] Next, refer to Figure 10 The sacrificial film CHP and etch stop 311 filling the interior of the second sub-hole CHS2 can be removed, and the sacrificial insulating layer 130s can be selectively removed through the space formed by the removal, thereby forming the gate electrode 130. Specifically, the sacrificial insulating layer 130s can be removed first, and the gate electrode 130 can be formed in the space where the sacrificial insulating layer 130s has been removed. That is, the sacrificial insulating layer 130s can be removed using an etching process, and then a metallic material (such as tungsten (W), copper (Cu), aluminum (Al), or molybdenum (Mo)) can be deposited to form the gate electrode 130.

[0079] Next, a first layer 161, a second layer 162, and a third layer 163 may be formed in the second sub-via CHS2. The first layer 161 may comprise silicon oxide, the second layer 162 may comprise silicon nitride, and the third layer 163 may comprise silicon oxide; this is merely an example, and the disclosure is not limited thereto. The first layer 161 filling the second sub-via CHS2 may comprise the same material as the barrier layer 156 filling the first sub-via CHS1, the second layer 162 filling the second sub-via CHS2 may comprise the same material as the charge storage layer 154 filling the first sub-via CHS1, and the third layer 163 filling the second sub-via CHS2 may comprise the same material as the tunneling layer 152 filling the first sub-via CHS1. However, this configuration is exemplary, and the disclosure is not limited thereto.

[0080] The third layer 163 may partially or completely fill the space in the second sub-hole CHS2. In the groove H1 where the etch stop has been removed, the third layer 163 may not completely fill the groove H1, and voids may be formed.

[0081] Next, as Figure 11 As shown, the stacked structure is flipped so that the auxiliary substrate 310 is set as the upper surface of the stacked structure.

[0082] Next, refer to Figure 12 The auxiliary substrate 310 and a portion of the N-doped region 149 can be removed. The auxiliary substrate 310 can be removed by grinding the upper surface of the auxiliary substrate 310 and then removing it by wet etching. However, this configuration is exemplary, and this disclosure is not limited thereto. The auxiliary substrate 310 can be removed using various methods. After removing the auxiliary substrate 310, the N-doped region (e.g., a portion of the N-doped region) can be removed using a chemical mechanical polishing (CMP) process. During this process, the upper surface of the trench H1 connecting the first sub-hole CHS1 and the second sub-hole CHS2 can be exposed. That is, as... Figure 12 As shown, the upper surfaces of the barrier layer 156 and the first layer 161, which fill the first sub-hole CHS1 and the second sub-hole CHS2, can be exposed. The barrier layer 156 and the first layer 161 may each comprise silicon oxide.

[0083] Next, refer to Figure 13 The exposed barrier layer 156 and the upper surface of the first layer 161 can be removed. The barrier layer 156 and the first layer 161 may comprise the same material and can therefore be removed using a single process. During this process, the upper surfaces of the second layer 162 and the charge storage layer 154 may be exposed.

[0084] Next, refer to Figure 14A portion of the second layer 162 and the charge storage layer 154 can be removed. The second layer 162 and the charge storage layer 154 may each comprise silicon nitride. The second layer 162 and the charge storage layer 154 may comprise the same material, and therefore can be removed using a single process.

[0085] Next, refer to Figure 15 A portion of the third layer 163 and the tunneling layer 152 can be removed. The third layer 163 and the tunneling layer 152 may comprise the same material and can therefore be removed using a single process. The third layer 163 and the tunneling layer 152 may each comprise silicon oxide. In this process, the thickness of the third layer 163 filling the trench H1 on the upper surface of the second sub-via CHS2 can be reduced, and the tunneling layer 152 disposed in the trench H1 on the upper surface of the first sub-via CHS1 can be removed. Therefore, the channel layer 140 can be exposed in the trench H1 on the upper surface of the first sub-via CHS1.

[0086] Furthermore, the first layer 161, the second layer 162, the tunneling layer 152, the charge storage layer 154, and the barrier layer 156 can be removed in the previous steps, and void spaces can thus be formed between the N-doped region 149 and the channel layer 140, and between the N-doped region 149 and the third layer 163.

[0087] Reference Figure 16 A first undoped silicon layer 143 can be formed in the space between the N-doped region 149 and the channel layer 140. The first undoped silicon layer 143 can be formed over the entire upper portion of the structure, and then a CMP process can be performed to thus form the first undoped silicon layer 143 in the space between the N-doped region 149 and the channel layer 140, and in the space between the N-doped region 149 and the third layer 163.

[0088] Next, refer to Figure 17 The silicon can be partially etched. Here, the exposed channel layer 140, the N-doped region 149, and the first undoped silicon layer 143 can all comprise silicon and therefore can be etched simultaneously. Figure 17 As shown, the upper surface of the channel layer 140 can be partially etched, and the N-doped region 149 and the first undoped silicon layer 143 can be partially etched to reduce their thickness. Therefore, as... Figure 17 As shown, the third layer 163 and the core insulation layer 142 of the filling groove H1 can protrude.

[0089] Next, refer to Figure 18 A capping layer 144 can be formed. The capping layer 144 may include, but is not limited to, silicon nitride. For example... Figure 18As shown, the capping layer 144 can fill the space between the protruding core insulation layer 142 and the third layer 163. The capping layer 144 having this shape or structure can be formed by depositing the capping layer 144 on the entire surface of the structure and then performing a CMP process.

[0090] Next, refer to Figure 19 The third layer 163 and the core insulating layer 142 of the filled trench H1 can be removed. Here, the third layer 163 and the core insulating layer 142 may comprise the same material, and therefore can be removed using a single process. Specifically, the third layer 163 and the core insulating layer 142 may each comprise silicon oxide. Through this process, the trench H1 where the etch stop is set can be exposed to an empty space. This space may be the area where the first semiconductor pattern is formed, as described below.

[0091] Next, refer to Figure 20 A barrier pattern 148 can be formed on the sidewall of the tank H1. The barrier pattern 148 may include silicon oxide or silicon nitride. Figure 20 As shown, a barrier pattern 148 can be formed on the sidewall of the groove H1. The barrier pattern 148 can be formed by performing an etching process after forming the barrier pattern 148 on the entire surface of the structure. In this process, a third layer 163 and a core insulating layer 142, comprising the same material as the barrier pattern (e.g., silicon oxide), can be partially etched. Therefore, as... Figure 20 As shown, the third layer 163 and the core insulating layer 142 can be etched at the bottom surface of the groove H1 to create a height difference.

[0092] Next, refer to Figure 21 This can form a second undoped silicon layer 171. For example... Figure 21 As shown, a second undoped silicon layer 171 can be disposed on the entire surface of the structure and fill the trench H1. Here, the second undoped silicon layer 171 formed in the trench H1 may not have a flat upper surface due to the height difference of the trench H1. The second undoped silicon layer 171 formed in this step may be amorphous.

[0093] Next, refer to Figure 22 The second undoped silicon layer 171 and the first undoped silicon layer 143 formed in the previous step can be irradiated with a laser to crystallize the second undoped silicon layer 171 and the first undoped silicon layer 143. In this step, the second undoped silicon layer 171 can crystallize to form an undoped region 1462.

[0094] In this step, laser irradiation can be performed at a temperature between 1100 and 1300 degrees Celsius. This temperature falls within the range where amorphous silicon can crystallize. Amorphous silicon can be transformed into a crystal and acquire semiconductor characteristics through laser irradiation.

[0095] In the laser irradiation process, the first undoped silicon layer 143 can contact the N-doped region 149, thus causing the diffusion of the N-doped region 149. Furthermore, the channel layer 140 disposed on the side of the N-doped region 149 may also include silicon, thus causing the diffusion of the N-doped region 149. Therefore, a portion of the channel layer 140 and the first undoped silicon layer 143 can also be N-doped through diffusion, thus forming an N-doped region 149. That is, as... Figure 22 As shown, the N-doped region 149 can be extended in this step.

[0096] However, the blocking pattern 148 can be disposed between the first undoped silicon layer 143 and the undoped region 1462, thus preventing N dopant from diffusing into the undoped region 1462.

[0097] like Figure 22 As shown, due to the expansion of the N-doped region 149 caused by the diffusion of the N dopant, the N-doped region 149 and the channel layer 140 can contact each other, and the channel layer 140 and the undoped region 1462 can contact each other. This contact can cause electron movement paths. Figure 22 The channel layer 140 and the undoped region 1462 are shown separately. However, if both the channel layer 140 and the undoped region 1462 comprise silicon, the boundary between the channel layer 140 and the undoped region 1462 may not be distinguishable. Therefore, it is understood that the N-doped region 149 and the undoped region 1462 are in direct contact with each other, which can cause electron movement paths. Even if the channel layer 140 is individually identified as distinct from the undoped region 1462 and the N-doped region 149, the channel layer 140 may still possess conductive properties, which can therefore cause electron movement paths.

[0098] Next, refer to Figure 23 P-doping can be performed on the undoped region 1462. Here, the P-doping material can be boron, but is not limited to this. In this process, a capping layer 144 can be disposed on top of the N-doped region 149, thus preventing doping into the N-doped region 149. (Refer to...) Figure 23 A P-doped region 1461 can be formed on the upper surface of the undoped region 1462 by P doping. Due to the height difference in the trench H1, the undoped region 1462 can be formed non-uniformly (uniformly) on the upper part of the trench H1. Therefore, as Figure 23 As shown, the P-doped region 1461 in the trench H1 may also be formed to include or have a curved surface.

[0099] Following p-doping, a laser annealing process can be performed. This laser annealing process can be performed at temperatures ranging from 700°C to 900°C. The temperature of the laser annealing process in this step can be lower than the temperature mentioned above. Figure 22 The laser irradiation temperature during the crystallization step. (Above)Figure 22 Laser irradiation in this process can be performed to melt amorphous silicon and then crystallize it, thus requiring high temperatures. However, a laser annealing process in this step can be performed to activate p-doped silicon, thus eliminating the need for such high temperatures.

[0100] Next, refer to Figure 24 The upper surface of the structure can be etched using a CMP process. In this process, the capping layer 144 can be removed. Figure 24 As shown, the upper surface of the N-doped region 149 can be exposed by an etching process. Furthermore, the upper surface of the P-doped region 1461 in the trench can also be exposed. A barrier pattern 148 can be disposed between the N-doped region 149 and the P-doped region 1461. The undoped region 1462 and the channel layer 140 can be disposed below the P-doped region 1461 and can contact the N-doped region 149 below the barrier pattern 148 as described above. Therefore, movement paths for electron and hole currents can be formed.

[0101] Next, refer to Figure 25 This can form a common source electrode 112. For example... Figure 25 As shown, a common source electrode-interface layer 113 may be formed first, followed by the formation of a common source electrode 112. However, the construction of the common source electrode-interface layer 113 is optional and may be omitted in some embodiments.

[0102] This manufacturing method can be used to manufacture a semiconductor device in which P-doped regions 1461 are disposed at the bottom of each channel structure CH, N-doped regions 149 are disposed between the respective P-doped regions 1461, and a blocking pattern 148 is disposed between the P-doped regions 1461 and the N-doped regions 149. The semiconductor device having this shape or configuration can efficiently perform a volume erase operation, and the hole path for erasure and the electron current path for readout operations can be independent of each other without affecting each other. Furthermore, each of the P-doped regions 1461 and N-doped regions 149 can be formed in a self-aligned manner, thereby solving the problem of broken electron and hole paths due to misalignment during the process of forming the P-doped and N-doped regions.

[0103] The following description provides a detailed example of an electronic system that includes the aforementioned semiconductor device.

[0104] Figure 26 This is a schematic view of an electronic system including semiconductor devices according to some embodiments.

[0105] Reference Figure 26According to some embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device that includes one or more semiconductor devices 1100.

[0106] Semiconductor device 1100 may be a non-volatile memory device (e.g., the aforementioned NAND flash memory device). Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed next to or on the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including bit line BL, common source line CSL, word line WL, first gate upper line UL1, second gate upper line UL2, first gate lower line LL1, second gate lower line LL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0107] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways in some embodiments.

[0108] In some embodiments, lower transistors LT1 and LT2 may include ground select transistors, and upper transistors UT1 and UT2 may include string select transistors. A first lower gate line LL1 and a second lower gate line LL2 may be the gate lines of lower transistors LT1 and LT2, respectively. A word line WL may be the gate line of a memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate lines of upper transistors UT1 and UT2, respectively.

[0109] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 can each be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the interior of the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the interior of the first structure 1100F to the second structure 1100S.

[0110] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one memory cell transistor selected from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 extending from the interior of the first structure 1100F to the second structure 1100S.

[0111] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, in which case the controller 1200 may control the plurality of semiconductor devices 1100.

[0112] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 operates based on predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface (I / F) 1221 for handling communication between NAND controller 1220 and semiconductor device 1100. Through NAND interface 1221, NAND controller 1220 can send control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs) of semiconductor device 1100, etc. Host interface 1230 can be used to provide communication between electronic system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0113] Figure 27 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to some embodiments. Figure 28 Show Figure 27Some embodiments of the semiconductor package 2003 are shown conceptually. Figure 27 The area cut along line I-I' of the semiconductor package 2003.

[0114] Reference Figure 27 According to some embodiments, the electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the main substrate 2001.

[0115] The main substrate 2001 may include a connector 2006 comprising a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host based on any of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI-Fast), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In some embodiments, the electronic system 2000 may be operated by power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0116] The controller 2002 can write data to or read data from the semiconductor package 2003 and improve the operating speed of the electronic system 2000.

[0117] DRAM 2004 can be a buffer memory to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in electronic system 2000 can also operate as a type of cache memory and can provide space for temporary data storage during the operation of the semiconductor package 2003. If electronic system 2000 includes DRAM 2004, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to the NAND controller for controlling semiconductor package 2003.

[0118] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 disposed on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 disposed on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structure 2400.

[0119] The package substrate 2100 may be a printed circuit board including package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. Input / output pads 2210 may correspond to... Figure 26 The input / output pad 1101 is included. Each semiconductor chip 2200 may include a gate stack structure 4210 and a channel structure 4220. The semiconductor chip 2200 may include the semiconductor device described above with reference to the accompanying drawings.

[0120] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the package pads 2130 to each other. Therefore, the semiconductor chips 2200 of each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other via a bonding wire method and may be electrically connected to the package pads 2130 of the package substrate 2100. According to some embodiments, the semiconductor chips 2200 of each of the first semiconductor package 2003a and the second semiconductor package 2003b may also be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire type connection structure 2400.

[0121] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected by wiring formed on the intermediate substrate.

[0122] Reference Figure 28In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, an upper package pad 2130 disposed on an upper surface of the package substrate body portion 2120, a lower package pad 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120, and internal wiring 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 to each other within the package substrate body portion 2120. The upper package pad 2130 may be electrically connected to a connection structure 2400. The lower package pad 2125 may be connected via a conductive connector 2800 to a wiring pattern 2005 (e.g., PCB) included in the main substrate 2001 of the electronic system 2000. Figure 27 (as shown in the image).

[0123] Reference Figure 28 In the semiconductor package 2003, each semiconductor chip 2200 may include a semiconductor substrate 4010, a first structure 4100 disposed on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding method.

[0124] The first structure 4100 may include a peripheral circuit region comprising peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 disposed between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 passing through the gate stack structure 4210, and a second bonding structure 4250 electrically connected to each word line of the gate stack structure 4210 and the channel structure 4220. For example, the second bonding structure 4250 may be electrically connected to each of the channel structure 4220 and the word line WL via bit lines electrically connected to the channel structure 4220 and gate connection wiring electrically connected to the word line WL.

[0125] like Figure 28 As shown, the second structure 4200 may include a 2-1 structure 4200a and a 2-2 structure 4200b that are joined to each other. The 2-1 structures 4200a and 2-2 structures 4200b may be joined to each other while in contact with each other. The portions of the 2-1 structures 4200a and 2-2 structures 4200b that are joined to each other may be made of, for example, copper (Cu).

[0126] The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 can join each other while in contact with each other. The parts of the first joining structure 4150 and the second joining structure 4250 that join each other can be made of, for example, copper (Cu).

[0127] According to some embodiments, a semiconductor device can be manufactured in such a manner that, in the semiconductor chip 2200 or semiconductor device, a P-doped region 1461 is disposed at the bottom of each channel structure CH, an N-doped region 149 is disposed between each P-doped region 1461, and a blocking pattern 148 is disposed between the P-doped region 1461 and the N-doped region 149. A semiconductor device having this shape or configuration can effectively perform a volume erase operation, and the movement paths of the hole current for erasure and the movement paths of the electron current for readout operations can be independent of each other and do not affect each other.

[0128] Each semiconductor chip 2200 may also include an input / output pad 2210 and input / output connection wiring 4265 disposed beneath the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0129] According to some embodiments, in a semiconductor package 2003, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 in the form of bonding wires. As another example, a plurality of semiconductor chips 2200, or a plurality of portions included in a plurality of semiconductor chips 2200, may be electrically connected to each other via a connection structure including through electrodes.

[0130] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A gate stack structure comprising alternating stacked interlayer insulating layers and multiple gate electrodes; The channel structure extends into the gate stack structure; A plurality of first semiconductor patterns, at one end of a channel structure, each of the plurality of first semiconductor patterns including a P-doped region and an undoped region; N-doped regions are located between adjacent first semiconductor patterns in the plurality of first semiconductor patterns; Barrier pattern between P-doped and N-doped regions; as well as Common source electrodes are located on the respective surfaces of the plurality of first semiconductor patterns and N-doped regions.

2. The semiconductor device according to claim 1, wherein, The undoped region lies between the p-doped region and the channel structure, and The undoped region is in contact with the channel structure.

3. The semiconductor device according to claim 1, wherein, The profile of the P-doped region includes a curved surface.

4. The semiconductor device according to claim 1, wherein, The P-doped region has a planar size that is smaller than or equal to the planar size of the widest part of the channel structure.

5. The semiconductor device according to claim 1, wherein, The P-doped region has a planar size larger than the planar size of the region of the channel structure that contacts the corresponding first semiconductor pattern among the plurality of first semiconductor patterns.

6. The semiconductor device according to claim 1, wherein, The blocking pattern includes silicon oxide or silicon nitride.

7. The semiconductor device according to claim 1, wherein, The channel structure includes a channel layer and a gate dielectric layer, and In this design, the gate dielectric layer and the barrier pattern are spaced apart from each other.

8. The semiconductor device according to claim 7, wherein, The N-doped region and the channel layer are in contact with each other, and In this structure, the channel layer and the undoped region are in contact with each other.

9. The semiconductor device according to claim 1, wherein, The P-doped and N-doped regions are spaced apart from each other.

10. The semiconductor device according to any one of claims 1 to 9, further comprising: The separated structure extends into the gate stack structure; as well as An additional first semiconductor pattern is located at one end of the discrete structure and includes an additional P-doped region and an additional undoped region.

11. A semiconductor device, comprising: The substrate includes an N-doped region and a plurality of first semiconductor patterns in the N-doped region; A gate stack structure includes multiple interlayer insulating layers and multiple gate electrodes alternately stacked on a substrate; as well as The channel structure extends into the gate stack structure and is stacked with the first semiconductor pattern in a direction perpendicular to the substrate. The first semiconductor pattern includes a P-doped region and an undoped region, and The semiconductor device further includes a barrier pattern between the P-doped region and the N-doped region.

12. The semiconductor device according to claim 11, wherein, The undoped region lies between the p-doped region and the channel structure, and The undoped region is in contact with the channel structure.

13. The semiconductor device according to claim 11, wherein, The profile of the P-doped region includes a curved surface.

14. The semiconductor device according to claim 11, wherein, The P-doped region has a planar size that is smaller than or equal to the planar size of the widest portion of the channel structure, and The planar dimension of the P-doped region is larger than the planar dimension of the narrowest part of the channel structure.

15. The semiconductor device according to claim 11, wherein, The blocking pattern includes silicon oxide or silicon nitride.

16. The semiconductor device according to any one of claims 11 to 15, wherein, The channel structure includes a channel layer and a gate dielectric layer, and In this design, the gate dielectric layer and the barrier pattern are spaced apart from each other.

17. The semiconductor device according to claim 16, wherein, The N-doped region and the channel layer are in contact with each other, and In this structure, the channel layer and the undoped region are in contact with each other.

18. An electronic system comprising: Primary base; Semiconductor devices, on the main substrate; as well as The controller is located on the main substrate and is electrically connected to the semiconductor device. The semiconductor device includes: A gate stack structure comprising alternating stacked interlayer insulating layers and multiple gate electrodes; The channel structure extends into the gate stack structure; A plurality of first semiconductor patterns, at one end of a channel structure, each of the plurality of first semiconductor patterns including a P-doped region and an undoped region; N-doped regions are located between adjacent first semiconductor patterns in the plurality of first semiconductor patterns; Barrier patterns are formed between the P-doped and N-doped regions; and Common source electrodes are located on the respective surfaces of the plurality of first semiconductor patterns and N-doped regions.

19. The electronic system according to claim 18, wherein, The P-doped region has a planar size that is smaller than or equal to the planar size of the widest portion of the channel structure, and The planar dimension of the P-doped region is larger than the planar dimension of the region of the channel structure that contacts the corresponding first semiconductor pattern among the plurality of first semiconductor patterns.

20. The electronic system according to claim 18 or 19, wherein, The channel structure includes a channel layer and a gate dielectric layer. In this context, the N-doped region and the channel layer are in contact with each other, and In this structure, the channel layer and the undoped region are in contact with each other.

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