Memory cell and semiconductor device

Abstract

The invention provides a memory cell and a semiconductor device. The memory cell includes an active region, a stack structure on the active region, and a gate electrode on the stack structure. The stack structure includes a tunneling layer on the active region, a stack structure on the tunneling layer, and a barrier layer on the stack structure. The stacked structure comprises a charge trapping layer and a ferroelectric layer, and the stacking direction of the charge trapping layer and the ferroelectric layer is perpendicular to the stacking direction of the stacked structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of non-volatile memory, and in particular to a memory cell and a semiconductor device. BACKGROUND

[0002] Compared with two-dimensional memory, three-dimensional memory improves the storage density of the device by vertically stacking multiple memory cells, so that more storage capacity can be achieved on the same chip, thereby improving the storage efficiency of the memory cells. SUMMARY

[0003] In view of the above problems, the present disclosure provides a memory cell and a semiconductor device.

[0004] According to a first aspect of the present disclosure, a memory cell is provided, comprising an active region, a stack structure on the active region, and a gate electrode on the stack structure. The stack structure comprises a tunneling layer on the active region, a layer structure on the tunneling layer, and a blocking layer on the layer structure. The layer structure comprises a charge trapping layer and a ferroelectric layer, and the stacking direction of the charge trapping layer and the ferroelectric layer is perpendicular to the stacking direction of the stack structure.

[0005] According to an embodiment of the present disclosure, the active region comprises indium gallium zinc oxide.

[0006] According to an embodiment of the present disclosure, the active region comprises a semiconductor interlayer with P-type doping.

[0007] According to an embodiment of the present disclosure, the memory cell is configured to perform a programming operation in response to a programming voltage applied to the gate electrode, wherein the programming voltage causes the ferroelectric layer to have a polarization direction towards the active region, and the polarization electric field generated by the ferroelectric layer accelerates electron tunneling of the active region to the charge trapping layer.

[0008] According to an embodiment of the present disclosure, the programming voltage comprises a first pulse voltage and a second pulse voltage, the storage state of the ferroelectric layer is determined based on the pulse amplitude of the first pulse voltage, and the number of electrons trapped by the charge trapping layer is determined based on the pulse duration of the second pulse voltage, wherein the pulse amplitude of the first pulse voltage is greater than or equal to the pulse amplitude of the second pulse voltage, and the pulse duration of the first pulse voltage is less than the pulse duration of the second pulse voltage.

[0009] According to an embodiment of the present disclosure, the memory cell is configured to perform an erasing operation in response to an erasing voltage applied to the gate electrode, wherein the erasing voltage causes the polarization direction of the ferroelectric layer to flip, and the polarization electric field generated by the ferroelectric layer accelerates the release of electrons from the charge trapping layer.

[0010] According to an embodiment of the present disclosure, the thickness and doping concentration of the ferroelectric layer and the defect density of the charge trapping layer are determined based on reducing the reverse effect of the electric field formed by the trapped charges of the charge trapping layer on the polarization electric field of the ferroelectric layer.

[0011] According to an embodiment of the present disclosure, the ferroelectric layer comprises hafnium oxide or hafnium zirconium oxide, and the charge trapping layer comprises silicon nitride.

[0012] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising a plurality of memory cells arranged in layers.

[0013] According to an embodiment of the present disclosure, the active region of the semiconductor device is a vertical columnar active region, and the gate electrodes of the memory cells are arranged in layers in the vertical direction, and the memory cells are isolated by an isolation layer.

[0014] According to an embodiment of the present disclosure, a memory cell is provided. The memory cell comprises an active region, a stack structure, and a gate electrode, the stack structure comprising a stack structure of a charge trapping layer and a ferroelectric layer, and the stacking direction of the charge trapping layer and the ferroelectric layer is perpendicular to the stacking direction of the stack structure. By utilizing the characteristic that the polarization switching speed of the ferroelectric layer is greater than the trapping speed of the charge trapping layer for carriers, the multi-value storage capability of the memory cell is enhanced, and the storage efficiency of the memory cell is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A structure schematic diagram of a memory cell according to an embodiment of the present disclosure is shown;

[0017] Figure 2 A structure schematic diagram of a memory cell according to another embodiment of the present disclosure is shown;

[0018] Figure 3 A schematic diagram of a programming operation of a memory cell according to an embodiment of the present disclosure is shown;

[0019] Figure 4 And Figure 5 Schematic diagrams of a programming operation of a memory cell according to an embodiment of the present disclosure under a first pulse voltage and a second pulse voltage are shown, respectively;

[0020] Figure 6 A schematic diagram of an erasing operation of a memory cell according to an embodiment of the present disclosure is shown;

[0021] Figure 7 A structure schematic diagram of a semiconductor device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to specific embodiments and with reference to the drawings.

[0023] The endpoints of the ranges and any values disclosed herein are not limited to the precise values stated. The ranges or values should be construed to be approximations that allow for significant variation. Various ranges of values are stated in terms of being wider than the ranges themselves. For example, a range of 1 to 6 should be interpreted to include not only the precise ranges of 1-6 and 2-5, but also other ranges such as 1.5-4.5, 3-4.5, etc. and individual values within the example ranges.

[0024] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "including" "comprising" and the like are specifically intended to be construed to be inclusive of other features, steps, operations, and / or components, etc. that are in addition to those specifically recited.

[0025] All terms used herein including technical and scientific terms have the meanings commonly understood by one of ordinary skill in the art unless otherwise specified. It should be noted that the use of any terms herein should not be interpreted to limit the disclosure in any way.

[0026] In the description of the present disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "back", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the indicated subsystem or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be understood as limiting the present disclosure.

[0027] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present disclosure. The illustrative description in the specification does not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any appropriate manner in one or more embodiments or examples.

[0028] Three-dimensional memory technology, as one of the important technologies in the field of data storage, provides a solid foundation for data processing with its unique architecture design and high-efficiency storage mechanism. The core of three-dimensional memory is to vertically stack multiple storage units, rather than arranging them in only one plane as in two-dimensional memory. The structure of three-dimensional memory allows it to integrate more storage capacity on the same chip, thereby improving the storage density. The multi-value storage capability and storage efficiency of the storage unit are important directions for the development of three-dimensional memory.

[0029] Therefore, embodiments of the present disclosure provide a storage unit and a semiconductor device. The storage unit is provided with a stack structure perpendicular to the overall stacking direction of the unit between the tunneling layer and the blocking layer, and the stack structure includes a ferroelectric layer and a charge trapping layer. By utilizing the characteristic that the polarization flipping speed of the ferroelectric layer is greater than the trapping speed of the charge trapping layer to the carriers, the multi-value storage capability of the storage unit is enhanced, and the storage efficiency is improved.

[0030] Figure 1 A structural schematic diagram of a storage unit according to an embodiment of the present disclosure is shown.

[0031] As shown in Figure 1 , the storage unit of the embodiment of the present disclosure can include an active region 1, a stack structure 2 on the active region, and a gate electrode 3 on the stack structure. The stack structure 2 can include a tunneling layer 21 on the active region 1, a stack structure 22 on the tunneling layer 21, and a blocking layer 23 on the stack structure 22. The stack structure 22 can include a charge trapping layer 221 and a ferroelectric layer 222, and the stacking direction of the charge trapping layer 221 and the ferroelectric layer 222 (in the vertical direction in the plane of the paper in the example) is perpendicular to the stacking direction of the stack structure (in the horizontal direction in the plane of the paper in the example). Figure 1 Figure 1

[0032] According to an embodiment of the present disclosure, a storage unit is provided. The storage unit includes an active region, a stack structure, and a gate electrode, the stack structure including a stack structure of a charge trapping layer and a ferroelectric layer, and the stacking direction of the charge trapping layer and the ferroelectric layer is perpendicular to the stacking direction of the stack structure. By utilizing the characteristic that the polarization flipping speed of the ferroelectric layer is greater than the trapping speed of the charge trapping layer to the carriers, the multi-value storage capability of the storage unit is enhanced, and the storage efficiency of the storage unit is improved.

[0033] In some embodiments, the active region 1 can include a channel that provides a carrier (e.g., electron) transmission channel, and source / drain electrodes on the opposite sides of the channel, etc. The active region 1 can include indium gallium zinc oxide (IGZO). IGZO is an N-type oxide semiconductor material containing four elements of indium, gallium, zinc, and oxygen, and is usually amorphous, such as InGaZnO4, etc.

[0034] ​​In the related art, polycrystalline silicon material is usually used as the active region material. The polycrystalline silicon material has many defects due to the grain boundary problem, which leads to problems such as increased leakage current of the memory device and threshold voltage drift. According to an embodiment of the present disclosure, the amorphous IGZO material has a relatively uniform disordered structure inside, which can maintain good consistency in a large-area preparation process, reduce the defects caused by the grain boundary problem of the polycrystalline silicon material, and thus improve the electrical performance and stability of the memory cell.

[0035] In addition, the low-temperature (lower than 200°C) preparation characteristics of IGZO make it an ideal channel material for three-dimensional memory cells. Meanwhile, IGZO has a wide band gap, high electron mobility, high on-off ratio, and low off-state current, which can reduce the static power consumption of the memory cell, provide a good basis for clearly distinguishing multiple intermediate-state currents, and further improve the performance of the memory cell.

[0036] Figure 2 A structure diagram of a memory cell according to another embodiment of the present disclosure is shown.

[0037] As shown in Figure 2 , the active region 1 can also include a semiconductor interlayer 11 with P-type doping. The semiconductor interlayer 11 can be located at the interface between the active region 1 and the tunneling layer 21. The semiconductor interlayer 11 can be a P-type semiconductor material that provides holes.

[0038] According to an embodiment of the present disclosure, IGZO is an N-type semiconductor material, and the electron mobility inside IGZO is much higher than the hole mobility, which can reduce the erasing efficiency of the memory cell. By forming a semiconductor interlayer 11 with P-type doping in the active region 1, the difficulty of releasing charges from the charge trapping layer 221 can be reduced, thereby improving the erasing speed of the memory cell.

[0039] Continuing to refer to Figure 1 and Figure 2 , the tunneling layer 21 in the stack structure 2 is located on the active region 1, and electrons can enter or exit the charge trapping layer 221 from the active region 1 by the tunneling effect through the application of voltage, realizing the writing and erasing of data. The tunneling layer 21 can include silicon oxide, etc. The blocking layer 23 is located between the stack structure 22 and the gate electrode 3, which can be used to block the escape of electrons in the charge trapping layer 221, improving the stability of the stored charges. The blocking layer 23 can include silicon oxide, etc. In some embodiments, the charge trapping layer 221 can be used to store electrons to change the threshold voltage of the memory cell. The charge trapping layer 221 can include silicon nitride, etc. The ferroelectric layer 222 can include hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO4), etc. x Zr 1-xHafnium zirconium oxide (Hf, abbreviated as HZO) is a solid solution oxide composed of Hf and Zr. For example, it can be Hf... 0.5 Zr 0.5 O2, etc.

[0040] Figure 3 A schematic diagram illustrating the programming operation of a storage unit according to an embodiment of the present disclosure is shown.

[0041] like Figure 3 As shown, the memory cell in this embodiment of the present disclosure can be configured to respond to a programming voltage applied to the gate electrode 3. Figure 3 China and Israel "V" g The programming operation is performed by indicating that the ferroelectric layer 222 has a polarization direction toward the active region 1. The polarization electric field generated by the polarization charge in the ferroelectric layer 222 can accelerate the electron tunneling from the active region 1 to the charge trapping layer 221.

[0042] According to an embodiment of this disclosure, a programming voltage is applied to the gate electrode 3, such that the electric field generated by the polarization charge in the ferroelectric layer 222 can assist electrons from the active region 1 to be injected into the charge trapping layer 221 through the tunneling layer 21. This process is equivalent to lowering the potential barrier for electron injection into the charge trapping layer 221, reducing the programming voltage of the memory cell, and improving programming efficiency.

[0043] Figure 4 and Figure 5 The diagrams show the memory cell of this disclosure performing programming operations under the first pulse voltage and the second pulse voltage, respectively.

[0044] like Figure 4 and Figure 5 As shown, the programming voltage may include a first pulse voltage ( Figure 4 China and Israel "V" g1 (Illustration) and second pulse voltage ( Figure 5 China and Israel "V" g2 (Illustration). The storage state of ferroelectric layer 222 can be based on the first pulse voltage V. g1 The pulse amplitude is determined. The number of electrons captured by the charge trapping layer 221 can be based on the second pulse voltage V. g2 The pulse duration is determined. The first pulse voltage V... g1 The pulse amplitude is greater than or equal to the second pulse voltage V g2 The pulse amplitude, the first pulse voltage V g1 The pulse duration is less than the second pulse voltage V g2 The pulse duration.

[0045] Continue to refer to Figure 4 A first pulse voltage V can be applied to the gate electrode 3. g1 First pulse voltage Vg1 The first pulse voltage V g1 may be set as a short and strong voltage (i.e. a voltage with a short pulse length and a high pulse amplitude). The polarization state of the ferroelectric layer 222, such as a full polarization state, a partial polarization state, etc., can be adjusted by controlling the amplitude of the first pulse voltage V

[0046] With reference to Figure 5 , a second pulse voltage V g2 may be applied on the gate electrode 3. The second pulse voltage V g2 may be set as a long and small voltage (i.e. a voltage with a pulse amplitude smaller than the first pulse voltage V g1 and a pulse length greater than or equal to the first pulse voltage V g1 . In the case that the first pulse voltage V g2 has already generated an auxiliary polarization electric field in the ferroelectric layer 222, the auxiliary electric field can accelerate the injection of electrons into the charge trapping layer 221, and the number of electrons injected into the charge trapping layer 221 can be controlled by adjusting the pulse length of the second pulse voltage V g .

[0047] According to embodiments of the present disclosure, the electron injection process of the programming operation is controlled by the first pulse voltage and the second pulse voltage, taking advantage of the characteristic that the polarization flipping speed of the ferroelectric layer is greater than the carrier capture speed of the charge trapping layer, which enhances the multi-value storage capability of the storage unit, improves the storage rate and the stability of the storage.

[0048] Figure 6 A schematic diagram of the storage unit of embodiments of the present disclosure performing an erase operation is shown.

[0049] As shown in Figure 6 , the storage unit of embodiments of the present disclosure can be configured to perform an erase operation in response to an erase voltage (V Figure 6 ) applied to the gate electrode 3. The erase voltage can cause the polarization direction of the ferroelectric layer 222 to flip, and the polarization electric field generated by the ferroelectric layer 222 can accelerate the release of electrons from the charge trapping layer 221.

[0050] According to embodiments of the present disclosure, the erase voltage is applied on the gate electrode 3, and the erase voltage causes the polarization state of the ferroelectric layer 222 to flip. The polarization electric field generated by the polarization charge of the ferroelectric layer 222 after the polarization state flips can assist the release process of the electrons from the charge trapping layer 221, thereby improving the speed of erasing.

[0051] In some embodiments, the thickness and doping concentration of the ferroelectric layer 222 and the defect density of the charge trapping layer 221 of the embodiments of the present disclosure can be determined based on reducing the reverse effect of the electric field formed by the trapped charges of the charge trapping layer on the polarization electric field of the ferroelectric layer.

[0052] According to the embodiments of the present disclosure, the trapped charges in the charge trapping layer 221 can generate an electric field opposite to the direction of the polarization electric field of the ferroelectric layer 222. This electric field can have a negative effect on the polarization electric field of the ferroelectric layer 222, that is, a charge shielding effect. The embodiments of the present disclosure can reduce this reverse effect by regulating the thickness and doping concentration of the ferroelectric layer 222 and the defect density of the charge trapping layer 221, thereby improving the performance of the memory cell.

[0053] Figure 7 A structural schematic diagram of a semiconductor device of the embodiments of the present disclosure is shown.

[0054] As shown in Figure 7 , the semiconductor device of the embodiments of the present disclosure can include a plurality of the above-mentioned memory cells arranged in layers in a vertical direction. The active region 1 of the semiconductor device can be a vertical columnar active region. The columnar active region can include IGZO or the like. The gate electrodes 3 of the memory cells can be arranged in layers in the vertical direction. The memory cells can be isolated by the isolation layer 4. In Figure 6 , the active region 1 is in the shape of a hollow column, which is filled with a dielectric (for example, the same dielectric as the isolation layer 4).

[0055] According to the embodiments of the present disclosure, the semiconductor device is designed in a "sandwich" structure of the ferroelectric layer and the charge trapping layer, which takes advantage of the characteristic that the polarization flipping speed of the ferroelectric layer is greater than the speed of trapping carriers of the charge trapping layer, to realize the performance of multi-value storage of the device. The columnar IGZO channel is combined to replace the channel of the traditional polysilicon material, further improving the electrical performance of the device.

[0056] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0057] The embodiments of the present disclosure are described above. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A storage unit, characterized in that, include: Active region; The stacked structure on the active region includes a tunneling layer on the active region, a stacked structure on the tunneling layer, and a blocking layer on the stacked structure. The stacked structure includes a charge trapping layer and a ferroelectric layer, and the stacking direction of the charge trapping layer and the ferroelectric layer is perpendicular to the stacking direction of the stacked structure. as well as The gate electrode on the stacked structure.

2. The storage unit according to claim 1, characterized in that, The active region includes indium gallium zinc oxide.

3. The storage unit according to claim 2, characterized in that, The active region includes a semiconductor intercalation layer with P-type doping.

4. The storage unit according to any one of claims 1 to 3, characterized in that, The memory cell is configured to perform a programming operation in response to a programming voltage applied to the gate electrode, wherein the programming voltage causes the ferroelectric layer to have a polarization direction toward the active region, and the polarization electric field generated by the ferroelectric layer accelerates electron tunneling from the active region to the charge trapping layer.

5. The storage unit according to claim 4, characterized in that, The programming voltage includes a first pulse voltage and a second pulse voltage. The storage state of the ferroelectric layer is determined based on the pulse amplitude of the first pulse voltage. The number of electrons captured by the charge trapping layer is determined based on the pulse duration of the second pulse voltage. The pulse amplitude of the first pulse voltage is greater than or equal to the pulse amplitude of the second pulse voltage, and the pulse duration of the first pulse voltage is less than the pulse duration of the second pulse voltage.

6. The storage unit according to any one of claims 1 to 3, characterized in that, The memory cell is configured to perform an erase operation in response to an erase voltage applied to the gate electrode, wherein the erase voltage causes the polarization direction of the ferroelectric layer to reverse, and the polarization electric field generated by the ferroelectric layer accelerates the release of electrons from the charge-trapping layer.

7. The storage unit according to claim 1, characterized in that, The thickness and doping concentration of the ferroelectric layer and the defect density of the charge-trapping layer are determined based on reducing the reverse effect of the electric field formed by the trapped charge of the charge-trapping layer on the polarization electric field of the ferroelectric layer.

8. The storage unit according to claim 1, characterized in that, The ferroelectric layer comprises hafnium oxide or hafnium zirconium oxide, and the charge trapping layer comprises silicon nitride.

9. A semiconductor device, characterized in that, The storage unit includes a multi-layered, spaced arrangement as described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, wherein the active region of the semiconductor device is a vertical columnar active region, the gate electrodes of the memory cells are arranged in layers at intervals in the vertical direction, and the memory cells are isolated from each other by an isolation layer.

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