Semiconductor structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a semiconductor layer; the source region and the drain region are located in the semiconductor layer and are arranged at intervals; the gate structure is located on the semiconductor layer and comprises a gate dielectric layer and a gate which are stacked, the gate dielectric layer comprises a first region close to the drain region and a second region close to the source region, and the equivalent oxide layer thickness of the second region is equal to that of the first region; wherein the first region comprises a first dielectric layer and a second dielectric layer which are stacked; at least part of the first dielectric layer has a first dielectric constant; the second dielectric layer has a second dielectric constant which is greater than the first dielectric constant; the second region has a first dielectric constant. According to the semiconductor structure, the dielectric layer with the high dielectric constant is inserted into the gate dielectric layer close to the drain region, so that an asymmetric gate structure is formed under the condition that an EOT value is not changed, the overhigh longitudinal electric field intensity when high voltage is applied to the drain can be reduced, and the carrier tunneling probability is reduced.

Description

TECHNICAL FIELD

[0001] The application relates to a semiconductor structure, in particular to a MOS structure, and more particularly to a high-voltage MOS structure, and belongs to the technical field of high-voltage semiconductors. BACKGROUND

[0002] Gate-Induced Drain Leakage (GIDL) is a band-to-band tunneling phenomenon induced by the gate electric field in the drain depletion region. In high-voltage CMOS (HV CMOS), since a high voltage often needs to be applied to the drain, the energy band in the drain depletion region is easily bent sharply, so that the top of the valence band is higher than the bottom of the conduction band, and electrons can jump from the valence band to the conduction band through quantum tunneling, forming electron-hole pairs, with the electrons entering the drain or the gate oxide under the action of a strong electric field, and the holes being collected by the substrate, forming a substrate leakage current I GIDL .

[0003] Gate-induced drain leakage easily leads to a decrease in the quality of the gate oxide and adversely affects the reliability of the device, reducing the service life of the device. Taking a chip for display driving as an example, gate-induced drain leakage also has the following hazards: first, excessive leakage current can cause a sharp increase in the static power consumption of the chip; and second, the voltage drop caused by the leakage of the pixel circuit can cause display abnormal phenomena such as flickering, residual image, and uneven brightness.

[0004] To solve this problem, the industry often uses an improved ion implantation process or an optimized device structure. Studies have shown that by adjusting the tilt angle during ion implantation, a doping profile with a gradually changing concentration can be formed in the channel region, which can reduce the electric field at the drain end. In terms of device structure, the longitudinal electric field strength in the gate oxide layer can be reduced by pushing the drain region away from the gate, thereby reducing the GIDL leakage current. However, the improvement ability of the above methods is limited, and at the same time, they may cause side effects such as a decrease in device switching speed and an increase in device size. SUMMARY

[0005] Based on the above status, the application provides a semiconductor structure to effectively reduce the excessively high longitudinal electric field strength when a high voltage is applied to the drain, reduce the tunneling probability of carriers, and reduce the GIDL leakage current.

[0006] To achieve the above objectives, the present invention provides a semiconductor structure comprising: a semiconductor layer; a source region and a drain region disposed in the semiconductor layer and spaced apart; a gate structure disposed on the semiconductor layer, comprising a gate dielectric layer and a gate disposed in layers, the gate dielectric layer comprising a first region near the drain region and a second region near the source region, the second region having an equivalent oxide layer thickness equal to that of the first region; wherein, the first region comprises a first dielectric layer and a second dielectric layer disposed in layers; at least a portion of the first dielectric layer has a first dielectric constant; the second dielectric layer has a second dielectric constant, the second dielectric constant being greater than the first dielectric constant; and the second region has a first dielectric constant.

[0007] In one implementation, the first dielectric layer as a whole has a first dielectric constant; in another implementation, the first dielectric layer includes alternating first and second sub-regions, wherein the first sub-region has a first dielectric constant and the second sub-region has a second dielectric constant, that is, the dielectric constant of the second sub-region is equal to that of the second dielectric layer; furthermore, the second sub-region and the second dielectric layer are made of the same material.

[0008] Furthermore, the first dielectric layer includes a first sub-region and a second sub-region alternately disposed along a first direction or a second direction, wherein the first direction is parallel to the direction from the source region to the drain region, and the second direction is parallel to the surface of the semiconductor layer and perpendicular to the first direction.

[0009] Furthermore, along the second direction, the first dielectric layer includes a first sub-region located in the middle and second sub-regions located at both ends of the first sub-region.

[0010] Furthermore, for the aforementioned semiconductor structure, the first region also includes a third dielectric layer stacked on the second dielectric layer, the dielectric constant of the third dielectric layer being different from that of the second dielectric layer.

[0011] Furthermore, the semiconductor layer is a silicon-containing semiconductor material, the first dielectric layer of the second region and at least a portion thereof is a silicon dioxide layer, and the second dielectric layer is a high-k dielectric layer.

[0012] Furthermore, the aforementioned semiconductor layer includes a well region, and both the source and drain regions are located within the well region; the well region located below the gate structure is a doped region of the same doping type.

[0013] Furthermore, for the aforementioned semiconductor structure, sidewalls are provided on both sides of the gate structure, including a first sidewall near the drain region and a second sidewall near the source region; a portion or all of the second dielectric layer on the side near the first sidewall extends into the first sidewall to form an embedding portion, which is in direct contact with the surface of the semiconductor layer below it.

[0014] In one implementation, the embedded part is strip-shaped and extends along the shape of the first sidewall; in another implementation, there are multiple embedded parts, and the multiple embedded parts are spaced apart along the extension direction of the first sidewall; in yet another implementation, the embedded part is embedded at both ends of the first sidewall along its extension direction.

[0015] Furthermore, the aforementioned semiconductor structure also includes a lightly doped drain region located in the semiconductor layer.

[0016] The semiconductor structure provided by this invention inserts a dielectric material with a higher dielectric constant of a certain thickness into the dielectric layer near the drain region. While ensuring that the equivalent oxide thickness (EOT) remains unchanged or almost unchanged, an asymmetric gate dielectric layer structure and an asymmetric gate structure are formed. This can reduce the excessively high longitudinal electric field strength when a high voltage is applied to the drain, reduce the carrier tunneling probability, and reduce the GIDL leakage level of the semiconductor structure.

[0017] Based on this, by extending the dielectric material with a higher dielectric constant into the sidewall near the drain region as part of the sidewall, the electric field strength at the edge of the gate near the drain region can be further reduced. This region is also the region where the GIDL effect is most concentrated, thereby further reducing the carrier band tunneling probability and the GIDL leakage level. Attached Figure Description

[0018] Figure 1 A schematic diagram of the semiconductor structure provided in Embodiment 1 of the present invention is shown;

[0019] Figure 2 A schematic diagram of the semiconductor structure provided in Embodiment 2 of the present invention is shown;

[0020] Figure 3 A schematic diagram of the semiconductor structure provided in Embodiment 3 of the present invention is shown;

[0021] Figure 4 A schematic cross-sectional view of the semiconductor structure provided in an embodiment of the present invention is shown. Figure 1 ;

[0022] Figure 5 A schematic diagram of the semiconductor structure provided in Embodiment 4 of the present invention is shown;

[0023] Figure 6 A schematic cross-sectional view of the semiconductor structure provided in an embodiment of the present invention is shown. Figure 2 ;

[0024] Figures 7a to 7i A schematic diagram of key steps in the preparation of the semiconductor structure in Embodiment 2 of the present invention is shown. Detailed Implementation

[0025] The technical solutions of various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same structures or areas are represented by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, the technical features in the following embodiments can be combined with each other unless otherwise specified.

[0026] In the description of this invention, terms such as "first" and "second" are used only for distinction and do not represent priority or quantity. For ease of structural description, this invention uses spatial relationship terms such as "above," "on," "located above," and "below" to describe the relationship between one structure and another, as shown in the accompanying drawings. However, if the semiconductor structure in the drawings is flipped, the structure described as being "above" another structure will subsequently be "below" another structure.

[0027] Figures 1 to 3 Schematic diagrams of the semiconductor structures provided in different embodiments of the present invention are shown. For example... Figures 1 to 3 As shown, the semiconductor structure provided in this embodiment of the invention is actually a MOS device, and more specifically a high-voltage MOS device. The semiconductor structure specifically includes a semiconductor layer 10, in which a drain region 21 and a source region 22 are provided, and a channel is located between the source region 22 and the drain region 21; a gate structure is provided on the semiconductor layer 10, which includes a stacked gate dielectric layer and a gate 40; sidewalls may also be provided on both sides of the gate structure.

[0028] In this embodiment of the invention, the semiconductor layer 10 is, for example, a semiconductor substrate, specifically referring to the semiconductor substrate itself or an epitaxial layer formed on the semiconductor substrate; alternatively, the semiconductor layer 10 may refer to a well region located in the semiconductor substrate, which is a locally doped region formed by ion implantation or diffusion, and its core function is to provide a bulk environment for device operation, achieve electrical isolation, and regulate threshold voltage, etc. Of course, in some cases, the epitaxial layer located on the semiconductor substrate may also serve as a well region. The material of the semiconductor layer 10 is, for example, a silicon-containing semiconductor material, such as silicon or silicon carbide, and the doping type of the semiconductor layer 10 is, for example, P-type. An isolation structure 60 may be provided in the semiconductor layer 10 to isolate the active region, and the aforementioned drain region 21 and source region 22 are both located in the active region.

[0029] The gate dielectric layer located on the semiconductor layer 10 specifically includes a first region 31 and a second region 32, wherein the first region 31 is close to the drain region 21, and the second region 32 is close to the source region 22. For ease of distinction, the first region 31 and the second region 32 are shown with dashed boxes in the figure. The first region 31 adopts a multilayer structure. Figure 1As shown, in Embodiment 1, the first region 31 includes a two-layer structure stacked together, including a first dielectric layer 311 and a second dielectric layer 312, wherein the first dielectric layer 311 is located between the semiconductor layer 10 and the second dielectric layer 312; as Figure 2 and Figure 3 As shown, in Embodiment 2, the first region 31 includes a three-layer structure stacked together, namely a first dielectric layer 311, a second dielectric layer 312 and a third dielectric layer 313.

[0030] Figure 4 Figure (a) in the middle is along Figure 1 or Figure 2 A schematic cross-sectional view of the first dielectric layer 311 through the yellow dashed line, (a) where the vertical dashed line represents the dividing line between the first region 31 and the second region 32. Figure 1 , Figure 2 as well as Figure 4 As shown in (a), in Embodiment 1 and Embodiment 2, the first dielectric layer 311 has a uniform material and a first dielectric constant K1. The second dielectric layer 312 has a second dielectric constant K2, and the dielectric constant of the second dielectric layer 312 is greater than that of the first dielectric layer 311, i.e., K2 > K1.

[0031] The specific material selection of the first dielectric layer 311 can depend on the material of the semiconductor layer 10. For example, if the semiconductor layer 10 is a silicon substrate, a silicon carbide substrate, or a silicon epitaxial layer, then the first dielectric layer 311 can be a silicon dioxide layer to ensure the interface quality between the first region 31 and the semiconductor layer 10.

[0032] The dielectric constant of the second dielectric layer 312 is greater than that of the first dielectric layer 311. For example, if the first dielectric layer 311 is made of silicon dioxide, then the second dielectric layer 312 can be a high-k dielectric material, such as alumina, which is commonly used in the semiconductor field. High-K dielectric material. Of course, if the second dielectric layer 312 is in direct contact with the gate 40, then the second dielectric layer 312 is preferably selected from dielectric materials that have good interface quality with the gate 40.

[0033] In Embodiment 2, a third dielectric layer 313 is further provided on the second dielectric layer 312, which has a third dielectric constant, denoted as K3, which is different from the second dielectric constant (K3 ≠ K2). That is, in Embodiment 2, the dielectric constant of the middle second dielectric layer 312 is greater than that of the first dielectric layer 311 on one side, and different from that of the third dielectric layer 313 on the other side. In a more preferred embodiment, the third dielectric constant K3 is greater than or equal to the first dielectric constant K1.

[0034] The specific material of the third dielectric layer 313 mainly depends on the material of the gate 40. For example, if the gate 40 is a metal gate, then the third dielectric layer 313 is a high-k dielectric material; or if the gate 40 is a polysilicon gate, then the third dielectric layer 313 can be silicon dioxide. By adapting the third dielectric layer 313 to the gate 40, good interface quality between the first region 31 and the gate 40 can be ensured.

[0035] In one feasible embodiment, the semiconductor layer 10 is a silicon substrate or a silicon epitaxial layer, the gate 40 is a polysilicon gate, and the three dielectric layers of the first region 31 are a silicon dioxide layer, a high-k dielectric layer, and a silicon dioxide layer, respectively. In another feasible embodiment, the semiconductor layer 10 is a silicon substrate or a silicon epitaxial layer, the gate 40 is a metal gate, and the three dielectric layers of the first region 31 are a silicon dioxide layer, a high-k dielectric layer, and another high-k dielectric layer, respectively.

[0036] Since both the second region 22 near the source region 22 and the first dielectric layer 311 near the drain region 21 have a first dielectric constant K1, the second dielectric layer 312 has a higher dielectric constant than the second region 22 and the first dielectric layer 311. In the above embodiment, a second dielectric layer 312 of a certain thickness is inserted into a portion of the gate dielectric layer near the drain region 21. While ensuring that the equivalent oxide layer thickness EOT is equal or substantially equal, this means that the total physical thickness of the first region 31 is greater than the physical thickness of the second region 32. As can be seen from the electric field strength E=V / d, increasing the physical thickness d of the dielectric layer can reduce the electric field strength E, and also increases the path length that carriers need to traverse during tunneling, thereby reducing the carrier tunneling probability and consequently reducing the GIDL leakage current level of the semiconductor structure.

[0037] Figure 4 Figure (b) is along Figure 3 A schematic cross-sectional view of the first dielectric layer 311 is shown in Figure (b). The dashed line in Figure (b) represents the dividing line between the first region 31 and the second region 32. Figure 3 and Figure 4 As shown in (b), in Embodiment 3, the first region 31 also includes a first dielectric layer to a third dielectric layer stacked sequentially. However, unlike Embodiment 2, the first dielectric layer 311 includes an alternately arranged first sub-region 311a and a second sub-region 311b. The first sub-region 311a has a first dielectric constant K1, and the second sub-region 311b has a second dielectric constant K2. That is, the dielectric constant of the second sub-region 311b is equal to the dielectric constant of the second dielectric layer 312. Considering the processing difficulty, the second sub-region 311b is made of the same material as the second dielectric layer 312. The second sub-region 311b can be regarded as the region where the second dielectric layer 312 extends into the first dielectric layer 311.

[0038] The material of the first sub-region 311a can be, for example, silicon dioxide, while the material of the second sub-region 311b is a high-k dielectric material.

[0039] Specifically, in Embodiment 3, both the first sub-region 311a and the second sub-region 311b are elongated and extend along the width direction of the channel (referred to as the second direction), and multiple first sub-regions 311a and multiple second sub-regions 311b are alternately arranged along the length direction of the channel (i.e., parallel to the direction from the source region to the drain region, referred to as the first direction).

[0040] It should be noted that in Embodiment 3, there are multiple first sub-regions 311a and second sub-regions 311b, but this is not a limitation. In other embodiments, there can be one or more first sub-regions 311a and one or more second sub-regions 311b. Preferably, one of the second sub-regions 311b is located at the edge of the first dielectric layer 311 near the drain region 21; for example, the first dielectric layer 311 includes one first sub-region 311a and two second sub-regions 311b, wherein the two second sub-regions 311b are located on both sides of the first sub-region 311a.

[0041] Compared with Example 2, in Example 3, the high-K dielectric layer and the silicon dioxide layer are arranged alternately, which can further increase the range of the high-K dielectric. The potential line density in the high-K dielectric is low, which can further reduce the electric field strength at the interface near the drain region 21.

[0042] Unlike Embodiment 3, in other embodiments, the first dielectric layer 311 includes a plurality of first sub-regions and a plurality of second sub-regions, and the plurality of first sub-regions and the plurality of second sub-regions are alternately arranged along a second direction.

[0043] Due to the characteristics of high-voltage CMOS processes, the actual physical thickness of the gate dielectric layer at both ends along the channel width direction (second direction) may be smaller than the designed value, resulting in a more severe GIDL leakage effect at these two ends. Therefore, as... Figure 4 As shown in Figure (c), in one embodiment, the first dielectric layer includes two second sub-regions 311b spaced apart along a second direction, and a first sub-region 311a located between the two second sub-regions 311b, wherein the first sub-region 311a has a first dielectric constant K1, and the second sub-regions 311b have a second dielectric constant K2, and K2 > K1. That is, in the channel width direction, the dielectric constant of the regions at both ends of the first dielectric layer is greater than the dielectric constant of the middle region.

[0044] In one feasible implementation, the first sub-region 311a in the middle is made of silicon dioxide, the second sub-regions 311b at both ends are made of a high-k dielectric material; the second dielectric layer 312 is also made of a high-k dielectric material, and the third dielectric layer 313 is made of silicon dioxide. Furthermore, the second sub-region 311b is made of the same material as the second dielectric layer 312. That is, for the first region, the middle region is made of... The sandwich structure, with both ends being The dual-layer structure allows for the determination of the thickness of each layer and region based on the principle of equal EOT. This enables targeted reinforcement of the weakest areas of the GIDL effect (i.e., the two end regions), effectively reducing the leakage current level of the device. Furthermore, since the high-k dielectric material has a relatively small distribution area, its impact on the overall equivalent oxide thickness (EOT) of the first dielectric layer can be ignored, maximizing the interface quality between the gate dielectric layer and the semiconductor layer.

[0045] In the above embodiments, the equivalent oxide thickness (EOT) of the first region 31 and the second region 32 is equal, which ensures good device performance and stable threshold voltage. In practice, the above requirements can be achieved by adjusting the physical thicknesses of the first region 31 and the second region 32, wherein the total physical thickness of the first region 31 must be greater than the physical thickness of the second region 32. Taking the second region 32, the first dielectric layer 311, and the third dielectric layer 313 as silicon dioxide layers, and the second dielectric layer 312 as a high-k dielectric layer, the physical thickness of the second dielectric layer 312 is... The total physical thickness T of the first dielectric layer 311 and the third dielectric layer ox1 The physical thickness T of the second region 323 ox2 The dielectric constant K of the second dielectric layer 312 high-k The relationship between them is: T ox1 +(K SiO2 / K high-k )*T k =T ox2 K SiO2 is the dielectric constant of silicon dioxide. Based on this formula, the thickness of each layer in the gate dielectric layer can be roughly determined, and it can be adjusted according to the actual situation in actual production.

[0046] It should be noted that in practice, due to fluctuations in process parameters during film formation, photolithography, and etching, it is difficult to guarantee absolute precision. Therefore, the equivalent oxide layer thicknesses of the first region 31 and the second region 32 are unlikely to be absolutely consistent. For this reason, in this invention, as long as the relative error between the equivalent oxide layer thicknesses EOT of the first region 31 and the second region 32 is within ±5%, for example, the equivalent oxide layer thicknesses of the first region and the second region (denoted as EOT1 and EOT2, respectively) are related as follows: 95%*EOT2≤EOT1≤105%*EOT2, or 95%*EOT1≤EOT2≤105%*EOT1, they are considered to have the same or equal equivalent oxide layer thicknesses, and are within the protection scope of this invention.

[0047] Figure 5 A schematic diagram of the semiconductor structure provided in Embodiment 4 of the present invention is shown. Figure 5 As shown, the sidewalls on both sides of the gate structure include a first sidewall 51 near the drain region 21 and a second sidewall 52 near the source region 22. Unlike the aforementioned embodiment 2, in embodiment 4, the first sidewall 51 is further provided with an embedded portion 511, one side of which is connected to the second dielectric layer 312. That is, the embedded portion 511 can be regarded as a partial or complete extension of the second dielectric layer 312 near the first sidewall 51 into the first sidewall 51, and the embedded portion 511 is in direct contact with the surface of the semiconductor layer 10 below it.

[0048] Considering that the lateral electric field strength is strongest and the GIDL effect is most concentrated at the edge of the gate near the drain region in high-voltage MOS devices, in Embodiment 4, by adding a portion of the first sidewall 51 near the drain region 21 with a high dielectric constant such as a high-K dielectric material, and the embedded portion 511 is in direct contact with the semiconductor layer 10 below it, the electric field lines can pass through the embedded portion 511, where the potential line density is low, which can reduce the electric field strength in the aforementioned region where the GIDL effect is most concentrated, thereby comprehensively reducing the carrier band tunneling probability and reducing the GIDL leakage level.

[0049] Figure 6 Figures (a) to (c) show the passage through... Figure 5 A cross-sectional view of the second medium layer 312 and the embedded part 511 with yellow dashed lines. In Figures (a) to (c), the two dashed lines represent the dividing line between the first region and the second region, and the dividing line between the second region and the first sidewall, respectively.

[0050] Combination Figure 5 and Figure 6As shown in (a), in the first implementation, the embedded part 511 is strip-shaped and extends along the second direction (i.e., the channel width direction), that is, the embedded part 511 extends in the same shape as the first sidewall 51; more specifically, the length of the embedded part 511 is the same as the length of the first sidewall 51 and the two ends are aligned.

[0051] Combination Figure 5 and Figure 6 As shown in (b), in the second implementation, there are multiple embedded portions 511, which are arranged at intervals along the extension direction (i.e., the second direction) of the first sidewall 51. Taking the embedded portion 511 as an example, and the other areas of the first sidewall 51 as silicon dioxide, it is equivalent to alternating between high-K dielectric material and silicon dioxide, which can further improve the switching speed of the device while reducing the transverse electric field.

[0052] Since the strong electric field between the gate and drain is more pronounced at both ends of the device channel width, the high-k dielectric in the sidewalls can be retained only at both ends of the channel width. Figure 5 and Figure 6 As shown in (c), in the third implementation, the embedding portion 511 is provided only at both ends of the first sidewall 51 along the second direction. In this implementation, since the overlap area between the embedding portion 511 and the drain region 21 is very small, the influence on the device gate-drain capacitance Cgd can be ignored, thus maximizing the preservation of the original performance of the semiconductor structure.

[0053] The above embodiment four is based on embodiment two, further adding an embedding part and providing multiple implementation methods. However, it is not limited to this; an embedding part can also be added to other embodiments, which will not be elaborated here.

[0054] Furthermore, the semiconductor structure in the above embodiments can belong to high-voltage MOS devices, and may also include commonly used structures in high-voltage MOS devices, see reference. Figure 2 The semiconductor structure may further include, for example, an isolation structure 60 for defining the active region, such as a Shallow Trench Isolation (STI) structure. Additionally, the semiconductor structure may include a lightly doped drain region 70, which forms a lightly doped extended region below the boundary of the gate 40 and between the source / drain regions. This extended region creates an impurity concentration gradient between the source / drain regions and the channel, thereby reducing the peak electric field near the drain region 21 and improving the hot carrier HCl effect and device reliability. Furthermore, the semiconductor structure may also include a heavily doped contact region 80 for easy electrode lead-out.

[0055] Furthermore, in the semiconductor structure of the above embodiments, the semiconductor layer may also be a well region, or the semiconductor layer may be a semiconductor substrate, in which a doped region is provided to serve as a well region; or the semiconductor layer may include a substrate and an epitaxial layer, wherein the epitaxial layer as a whole serves as a well region. The aforementioned source region 22 and drain region 21, as well as the aforementioned possible lightly doped drain region 70 and contact region 80, are all located in the well region.

[0056] In a more preferred embodiment, the well regions located below the gate structure are of the same doping type. In other words, the portion of the well region located below the gate structure consists of well regions of the same doping type (i.e., all N-type or all P-type). That is, the semiconductor structure does not include cases where the portion of the well region below the gate structure, such as LDMOS, contains doped regions of two different doping types.

[0057] In addition to high-voltage MOS devices, the semiconductor structure can also be a CMOS integrated circuit; or a product of the BCD (Bipolar-CMOS-DMOS) process platform, in which at least one of the NMOS or PMOS adopts the above structure.

[0058] The following describes the process flow of the semiconductor structure in Example 4. The semiconductor structures of other examples can be improved and modified based on this.

[0059] like Figure 7a As shown, taking a silicon substrate as an example, the semiconductor layer 10 first forms a first dielectric material layer 91, such as a silicon dioxide layer, on the surface of the silicon substrate on which the isolation structure 60 is pre-formed. Then, a photoresist layer 92 is formed on the surface of the first dielectric material layer 91 by photolithography. The photoresist layer 92 covers the area corresponding to the first region.

[0060] like Figure 7b As shown, the first dielectric material layer 91, excluding the first region, is etched clean to expose the silicon substrate surface, resulting in the first dielectric layer 311. Subsequently, the photoresist layer 92 is removed.

[0061] like Figure 7c As shown, an atomic layer deposition (ALD) or physical vapor deposition (PVD) process is used to deposit a high-k dielectric material layer 93 on the surface of a silicon substrate, which covers the exposed surface of the silicon substrate, the first dielectric layer 311, and the surface of the isolation structure.

[0062] like Figure 7d As shown, a photoresist layer 94 is formed on the surface of the high-k dielectric material layer 93 using photolithography. This defines the high-k dielectric material layer 93 that needs to be retained in the first region and the first sidewall portion. The high-k dielectric material layer 93 in other regions is removed by dry or wet etching, exposing the silicon substrate surface. Figure 7eAs shown, a second dielectric layer 312 is covered on the surface of the first dielectric layer 311, and one side of the second dielectric layer 312 extends beyond the first dielectric layer 311 and directly contacts the silicon substrate. This part is part of the first sidewall, namely the embedded part 511.

[0063] like Figure 7f As shown, silicon dioxide is grown using the ISSG process. This process forms a high-quality silicon dioxide layer 95 on the exposed silicon substrate surface, while silicon dioxide cannot grow on the portion covered by the high-k dielectric layer, i.e., the second dielectric layer 312. Subsequently, another silicon dioxide layer 96 is deposited using a CVD process, as shown... Figure 7g As shown, the function of this silicon dioxide layer is to avoid the Fermi level pinning effect caused by direct contact between the high-k dielectric and polycrystalline silicon, and to integrate with the existing process flow to the greatest extent.

[0064] In this embodiment, the silicon dioxide layer is formed in two steps; in other embodiments, other processes can also be used to form the silicon dioxide layer. The appropriate film formation process can be selected according to the thickness and quality requirements of the actual product.

[0065] like Figure 7h and 7i As shown, a photoresist layer 97 is formed on the surface of the silicon dioxide layer 96 by photolithography, which covers the areas corresponding to the first and second regions. The silicon dioxide layer 96 in other regions is removed by dry or wet etching to expose the surface of the silicon substrate. The embedded portion 511 of the first sidewall can be fully preserved by adjusting the etching selectivity.

[0066] In addition to the steps described above, the process also includes steps such as fabricating the gate, forming the source / drain regions, forming other parts of the sidewalls, lightly doped drain regions, and isolation structures. These are all existing technologies and will not be described in detail here. Furthermore, the above process route is illustrated using the semiconductor structure in Example 4 as an example. Adjustments can be made to this process for semiconductor structures in other examples.

[0067] The technical solution of the present invention has been described in conjunction with the specific embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor layer; Source and drain regions located and spaced apart within a semiconductor layer; A gate structure located on a semiconductor layer includes a gate dielectric layer and a gate stacked thereon. The gate dielectric layer includes a first region near the drain region and a second region near the source region. The second region has the same equivalent oxide layer thickness as the first region. The first region includes a first dielectric layer and a second dielectric layer stacked together; at least a portion of the first dielectric layer has a first dielectric constant; the second dielectric layer has a second dielectric constant, and the second dielectric constant is greater than the first dielectric constant; the second region has a first dielectric constant, and the equivalent oxide layer thickness of the second region is equal to that of the first region.

2. The semiconductor structure according to claim 1, characterized in that, The first dielectric layer as a whole has a first dielectric constant; Alternatively, the first dielectric layer may include alternating first and second sub-regions, wherein the first sub-region has a first dielectric constant and the second sub-region has a second dielectric constant.

3. The semiconductor structure according to claim 2, characterized in that, The first dielectric layer includes a first sub-region and a second sub-region alternately arranged along a first direction or a second direction. Wherein, the first direction is parallel to the direction from the source region to the drain region, and the second direction is parallel to the surface of the semiconductor layer and perpendicular to the first direction.

4. The semiconductor structure according to claim 2, characterized in that, Along the second direction, the first dielectric layer includes a first sub-region located in the middle and second sub-regions located at both ends of the first sub-region.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The first region further includes a third dielectric layer stacked on the second dielectric layer, wherein the dielectric constant of the third dielectric layer is different from that of the second dielectric layer.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor layer is a silicon-containing semiconductor material, the first dielectric layer of the second region and at least a portion thereof is a silicon dioxide layer, and the second dielectric layer is a high-k dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor layer includes a well region, and the source region and the drain region are both located in the well region; The well region located below the gate structure is a doped region of the same doping type.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, The gate structure has sidewalls on both sides, including a first sidewall near the drain region and a second sidewall near the source region; The second dielectric layer extends partially or entirely into the first sidewall on the side closest to the first sidewall to form an embedded portion, which is in direct contact with the surface of the semiconductor layer below it.

9. The semiconductor structure according to claim 8, characterized in that, The embedded part is strip-shaped and extends in accordance with the shape of the first sidewall; Alternatively, there may be multiple embedded portions, and the multiple embedded portions may be spaced apart along the extension direction of the first sidewall; Alternatively, the embedding portion may be embedded at both ends of the first sidewall along its extension direction.

10. The semiconductor structure according to any one of claims 1-4, characterized in that, The semiconductor structure also includes a lightly doped drain region located in the semiconductor layer.

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