FDSOI integrated device and manufacturing method thereof

Abstract

The invention provides an FDSOI integrated device and a manufacturing method thereof. The FDSOI integrated device and the manufacturing method thereof can be applied to the technical field of semiconductors. According to an embodiment, the FDSOI integrated device comprises a plurality of field effect transistors formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprises a buried oxide layer and a SiGe semiconductor layer adjacent to the buried oxide layer on the buried oxide layer, and any field effect transistor comprises the SiGe semiconductor layer serving as a channel part and the SiGe semiconductor layer serving as a channel part; a gate electrode on the channel portion; and a source / drain layer in contact with the channel portion on opposite sides of the gate, in which the SiGe semiconductor layers of the plurality of field effect transistors have different Ge concentrations with respect to each other, so that the plurality of field effect transistors have different threshold voltages with respect to each other.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to an FDSOI integrated device and its manufacturing method. Background Technology

[0002] Fully depleted silicon-on-insulator (FDSOI) devices offer advantages such as low power consumption and low cost. However, as FDSOI devices continue to miniaturize, achieving highly integrated multi-threshold voltage FDSOI devices has become a pressing issue. Summary of the Invention

[0003] In view of the above problems, this disclosure provides an FDSOI integrated device and a method for manufacturing the same.

[0004] According to a first aspect of this disclosure, an FDSOI integrated device is provided, comprising a plurality of field-effect transistors formed on a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a buried oxide layer and a SiGe semiconductor layer on the buried oxide layer adjacent to the buried oxide layer, wherein each field-effect transistor comprises: a SiGe semiconductor layer serving as a channel portion; a gate on the channel portion; and source / drain layers adjoining the channel portion on opposite sides of the gate, wherein the SiGe semiconductor layers of the plurality of field-effect transistors have different Ge concentrations relative to each other, thereby the plurality of field-effect transistors each having different threshold voltages relative to each other.

[0005] According to a second aspect of this disclosure, a method for manufacturing an FDSOI integrated device is provided, the method comprising: forming a plurality of SiGe epitaxial layers with different Ge concentrations on a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate includes a buried oxide layer and a top silicon layer adjacent to the buried oxide layer; performing a thermal oxidation process to drive Ge elements from the plurality of SiGe epitaxial layers into corresponding regions of the top silicon layer in which each of the plurality of SiGe epitaxial layers is located, thereby forming the top silicon layer as a SiGe semiconductor layer with different Ge concentrations in the regions corresponding to the different SiGe epitaxial layers, wherein, after thermal oxidation, the plurality of SiGe epitaxial layers are formed as oxide layers; removing the oxide layers and forming field-effect transistors on different regions of the plurality of SiGe semiconductor layers, each field-effect transistor including a gate on a channel portion and source / drain layers located on opposite sides of the gate portion and connected to the channel portion, the channel portion including the SiGe semiconductor layer.

[0006] According to embodiments of this disclosure, an FDSOI integrated device is provided. In this FDSOI integrated device, the channels of multiple field-effect transistors are formed with different Ge concentrations relative to each other, thus enabling them to have different threshold voltages. In this way, a highly integrated FDSOI device with multiple gate threshold voltages is achieved, and various applications requiring different threshold voltages can be integrated together. Attached Figure Description

[0007] The above-mentioned contents, other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings, which will be described in conjunction with the drawings.

[0008] Figure 1 An FDSOI integrated device according to an embodiment of the present disclosure is illustrated schematically.

[0009] Figure 2 A schematic flowchart illustrating a method for manufacturing an FDSOI integrated device according to an embodiment of the present disclosure is shown.

[0010] Figures 3-13 The illustration schematically depicts some processes for manufacturing FDSOI integrated devices according to embodiments of the present disclosure. Detailed Implementation

[0011] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0012] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0013] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0015] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0016] Figure 1 An FDSOI integrated device according to an embodiment of the present disclosure is illustrated schematically.

[0017] like Figure 1 As shown, the FDSOI integrated device of this embodiment may include a plurality of field-effect transistors formed on a semiconductor-on-insulator (SOI) substrate. For example, the plurality of field-effect transistors may include at least one of p-type field-effect transistors or n-type field-effect transistors, preferably including p-type field-effect transistors. Each field-effect transistor may include a channel, a gate, and a source / drain layer 400.

[0018] In this embodiment, the substrate may be a semiconductor-on-insulator substrate, and the semiconductor device according to this embodiment may be a fully depleted semiconductor-on-insulator (FDSOI) device, specifically a silicon-germanium-on-insulator (SGOI) substrate. The substrate may include a base substrate 100, a buried oxide layer 210, and a semiconductor layer on the buried oxide layer 210, sequentially disposed in a vertical direction. For example, the base substrate 100 may include silicon, the semiconductor layer may include SiGe (silicon-germanium), and the buried oxide layer 210 may include silicon dioxide, etc. The semiconductor layer may be adjacent to the buried oxide layer 210. This semiconductor layer can be used as a channel portion. Furthermore, in the SOI substrate, an active region may be defined by, for example, shallow trench isolation (STI) 220. A semiconductor device such as a field-effect transistor (FET) may be formed on the active region.

[0019] The gate may extend along a first direction (e.g., a direction perpendicular to the plane of the paper), and the gate may include a gate dielectric layer 520 and a gate conductor layer 530 on the gate dielectric layer 520. The gate dielectric layer 520 may include a high-k dielectric such as hafnium oxide. The gate conductor layer 530 may include a work function metal layer such as titanium nitride and a conductive metal such as tungsten. The gate may also include an interface layer. For example, the interface layer may include silicon oxide. The interface layer may be formed on the surface of the channel portion, and the gate dielectric layer 520 may be located between the interface layer and the work function metal layer. It should be noted that the structure of the gate is not limited to the example in the figure, but may include various other configurations. In this example, the gate is formed directly on the semiconductor layer, so that it appears that a planar FET will subsequently be obtained. However, this disclosure is not limited to this. For example, nanosheets or nanowires may also be formed on the substrate, and nanosheet or nanowire FETs may be formed. The concept of embodiments according to this disclosure is still applicable to this. Sidewalls 510 may be formed on the sidewalls of the gate. Sidewalls 510 may include, for example, nitrides. It should be noted that the side wall 510 can be a single layer or multiple layers, and this disclosure does not limit it.

[0020] The source / drain layer 400 may include an epitaxial layer formed on the substrate, which may be located on opposite sides of the gate and connected to the channel portion. In addition, metal silicide 600 may be formed on the source / drain layer 400 and the gate conductor layer 530 to reduce the contact resistance of the source / drain layer 400 and the gate conductor layer 530 and improve device performance.

[0021] In this embodiment, the SiGe in the channels of the plurality of field-effect transistors in the FDSOI integrated device has different Ge (germanium) concentrations relative to each other, thereby each of the plurality of field-effect transistors has a different threshold voltage relative to each other. For example, the Ge concentration of channel 310 may be lower than that of channel 320, and the Ge concentration of channel 320 may be lower than that of channel 330. Accordingly, the threshold voltage of the field-effect transistor based on channel 310 may be higher than that of the field-effect transistor based on channel 320, and the threshold voltage of the field-effect transistor based on channel 320 may be higher than that of the field-effect transistor based on channel 330. However, it should be understood that this disclosure is not limited thereto. In the embodiments of this disclosure, it is sufficient to form the channels of the plurality of field-effect transistors with different Ge concentrations relative to each other. In addition, the FDSOI integrated device may include several groups of field-effect transistors, wherein the field-effect transistors in each group may be based on channels with the same Ge concentration, and the field-effect transistors in different groups may be based on channels with different Ge concentrations.

[0022] In the FDSOI integrated device according to embodiments of the present disclosure, the channels of multiple field-effect transistors are formed with different Ge concentrations relative to each other, thus enabling them to have different threshold voltages. In this way, a highly integrated FDSOI device with multiple gate threshold voltages is achieved, and various applications requiring different threshold voltages can be integrated together.

[0023] According to embodiments of this disclosure, the plurality of field-effect transistors may include at least one of a first field-effect transistor, a second field-effect transistor, or a third field-effect transistor.

[0024] For example, a first field-effect transistor has a first germanium concentration in its channel and a first threshold voltage. A second field-effect transistor has a second germanium concentration in its channel and a second threshold voltage. A third field-effect transistor has a third germanium concentration in its channel and a third threshold voltage. The first germanium concentration is lower than the second germanium concentration, and the second germanium concentration is lower than the third germanium concentration. The first threshold voltage is higher than the second threshold voltage, and the second threshold voltage is higher than the third threshold voltage.

[0025] Specifically, the channel portion of the first field-effect transistor contains 5% to 50% Ge atoms. The channel portion of the second field-effect transistor has a 2% to 20% higher percentage of Ge atoms than the first field-effect transistor, and the channel portion of the third field-effect transistor has a 2% to 20% higher percentage of Ge atoms than the second field-effect transistor.

[0026] Preferably, the channel portion 310 of the first field-effect transistor contains 10% to 25% Ge atomically. The Ge atomic percentage in the channel portion 320 of the second field-effect transistor is 2% to 6% higher than that in the first field-effect transistor. The Ge atomic percentage in the channel portion of the third field-effect transistor 330 is 2% to 6% higher than that in the second field-effect transistor.

[0027] For example, the first field-effect transistor is a conventional threshold voltage (RVT) field-effect transistor, the second field-effect transistor is a low threshold voltage (LVT) field-effect transistor, and the third field-effect transistor is an ultra-low threshold voltage (SLVT) field-effect transistor. It should be noted that in... Figure 1 The layout of the field-effect transistors is only an example. In other embodiments, the field-effect transistors may be arranged in other ways, which will not be described in detail.

[0028] As described below, in the process of manufacturing the FDSOI integrated device of this disclosure, the top silicon layer of the SOI substrate can be processed to form multiple channels as described above based on the same top silicon layer. Thus, the channels of the multiple field-effect transistors can each have substantially equal thickness in the vertical direction. However, this disclosure is not limited to this; the channels of the multiple field-effect transistors can also each have substantially equal height in the vertical direction.

[0029] Furthermore, the gates of the multiple field-effect transistors can each have the same work function. According to embodiments of this disclosure, the threshold voltage is adjusted not by adjusting the work function of the gate, but by adjusting the Ge concentration in the channel. This simplifies the process. For example, the gates of the multiple field-effect transistors can be fabricated together in the same process. For example, the gate dielectric layer 520 and gate conductor layer 530 of the multiple field-effect transistors can be fabricated together. For example, the gate dielectric layer 520 and gate conductor layer 530 of the multiple transistors can be formed simultaneously in a post-gate process. However, this disclosure is not limited to this. The threshold voltage can be adjusted to a greater extent by combining channel Ge concentration adjustment and work function adjustment.

[0030] The method of manufacturing an FDSOI integrated device according to embodiments of the present disclosure will be described in more detail below with reference to examples.

[0031] Figure 2 A schematic flowchart illustrating a method for manufacturing an FDSOI integrated device according to an embodiment of the present disclosure is shown.

[0032] like Figure 2 As shown, the method of this embodiment may include operations S210 to S240.

[0033] In operation S210, multiple SiGe epitaxial layers with different Ge concentrations are formed on a semiconductor-on-insulator substrate.

[0034] In operation S220, a thermal oxidation process is performed to drive Ge elements from multiple SiGe epitaxial layers into the corresponding regions of the top silicon layer where each SiGe epitaxial layer is located, thereby forming a SiGe semiconductor layer in the top silicon layer with different Ge concentrations in the regions corresponding to the different SiGe epitaxial layers. After thermal oxidation, the multiple SiGe epitaxial layers are formed into an oxide layer.

[0035] In operation S230, the oxide layer is removed.

[0036] In operation S240, field-effect transistors are formed on different regions of multiple SiGe semiconductor layers.

[0037] Figures 3-13The illustration schematically depicts some processes for manufacturing FDSOI integrated devices according to embodiments of the present disclosure.

[0038] like Figure 3 As shown, a substrate may be provided. For example, an SOI substrate may be provided, including a base substrate 100, a buried oxide layer 210, and a top silicon layer 340.

[0039] like Figure 4 As shown, a mask layer 900 (e.g., a hard mask formed of a material such as silicon nitride) can be deposited on the top silicon layer 340 to define a region on the top surface of the top silicon layer 340, so as to facilitate the epitaxial growth of a corresponding epitaxial layer in the defined region. For example, in Figure 4 In this process, the mask layer 900 defines a second region on the top surface of the top silicon layer 340. Furthermore, by exposing the second region of the top surface of the top silicon layer 340 using the mask layer 900 while masking other regions, a second SiGe epitaxial layer 352 having a second Ge concentration can be epitaxially grown on the second region. For example, during the epitaxial process, the Ge concentration in the second SiGe epitaxial layer 352 can be increased from 10% to 40%, and the same applies to the other SiGe epitaxial layers described below, which will not be repeated here.

[0040] like Figure 5 As shown, after forming the second SiGe epitaxial layer 352, a mask material can be deposited on the top silicon layer 340, and the mask layer 900 of the third region, which is different from the second region, on the top surface of the top silicon layer 340 can be removed (e.g., by dry etching), so that the mask layer 900 shields other regions except the third region. Then, with the third region on the top surface of the top silicon layer 340 exposed by the mask layer 900 while other regions are shielded, a third SiGe epitaxial layer 353 with a third Ge concentration can be epitaxially grown on the third region.

[0041] like Figure 6As shown, after forming the third SiGe epitaxial layer 353, a mask material can be deposited on the top silicon layer 340, and the mask layer 900 of the first region, which is different from the third and second regions, on the top surface of the top silicon layer 340 can be removed, so that the mask layer 900 shields other regions except the first region. Then, with the first region of the top surface of the top silicon layer 340 exposed by the mask layer 900 while other regions are shielded, a first SiGe epitaxial layer 351 with a first Ge concentration can be epitaxially grown on the first region. Here, the first Ge concentration, the second Ge concentration, and the third Ge concentration are different from each other, and these three can be set according to actual needs. For example, the Ge concentration of each of the multiple SiGe epitaxial layers is determined according to the expected threshold voltage of the field-effect transistor formed on each region. However, it should be understood that this disclosure does not limit the shielding region and the order of epitaxial layer growth. For example, in some embodiments, the first SiGe epitaxial layer, the second SiGe epitaxial layer, and the third SiGe epitaxial layer can be grown sequentially, and this disclosure does not limit this.

[0042] like Figure 7 As shown, after forming the aforementioned epitaxial layers, a thermal oxidation process can be performed to drive the Ge elements from the multiple SiGe epitaxial layers into the corresponding regions of the top silicon layer 340 where each SiGe epitaxial layer is located. Specifically, the Ge elements from the first SiGe epitaxial layer 351 are driven into the first region of the top silicon layer 340, the Ge elements from the second SiGe epitaxial layer 352 are driven into the second region of the top silicon layer 340, and the Ge elements from the third SiGe epitaxial layer 353 are driven into the third region of the top silicon layer 340. In this way, the top silicon layer 340 can be formed as a SiGe layer (i.e., the semiconductor layer described above), and the Ge concentration in the regions corresponding to the different SiGe epitaxial layers is different from each other; that is, the Ge concentration in the first region, the second region, and the third region of the semiconductor layer are different from each other. Furthermore, after thermal oxidation, the multiple SiGe epitaxial layers are formed as oxide layers (e.g., may include silicon dioxide).

[0043] In this regard, such as Figure 8 As shown, the oxide layer can be removed after thermal oxidation (e.g., by dry etching). Thus, the semiconductor-on-insulator substrate previously with a top silicon layer on the buried oxide layer can be transformed into a semiconductor-on-insulator substrate with a SiGe layer on the buried oxide layer, and the SiGe layer on the buried oxide layer has different Ge concentrations in different regions.

[0044] like Figure 9 As shown, in this substrate, active regions can be defined by STI 220. Semiconductor layers can be patterned and defined within the active regions, and then a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor can be formed in each active region, respectively.

[0045] like Figure 10 As shown, a sacrificial gate can be formed in each region. For example, a sacrificial gate 540 extending along a first direction can be formed in each region of the semiconductor layer. For example, the sacrificial gate 540 may include oxide and polysilicon on oxide. Sidewalls 510 can be formed on the sidewalls of the sacrificial gate 540 to define the gate region. On opposite sides of the gate, corresponding epitaxial layers can be epitaxially grown on the semiconductor layer, and in-situ doping, activation, and other processes can be performed on the epitaxial layers to obtain the source / drain layers 400.

[0046] Subsequently, a dielectric material can be deposited on the source / drain layer 400 and planarized. Then, the sacrificial gate 540 can be removed, and a gate stack can be formed in the gate region defined by the sidewalls 510. For example, as... Figure 11 As shown, gate dielectric layers 520 of the same thickness and material can be deposited simultaneously on various regions of the semiconductor layer. Then, as... Figure 12 As shown, a work function metal layer of the same thickness and material can be deposited simultaneously on the gate dielectric layer 520, and the remaining space in the gate region defined by the sidewall 510 can be filled with conductive metal to form the gate conductor layer 530. In this way, a gate with the same work function can be formed.

[0047] After fabricating the gate, as Figure 13 As shown, a metal silicide layer 600 can be formed on the gate conductor layer 530 and the source / drain layer 400 through processes such as thermal annealing. Subsequently, a dielectric material can be deposited on the FDSOI integrated device to form an interlayer dielectric layer 700, and contact plugs 800 on the source / drain layer 400 and the gate conductor layer 530 can be formed within the interlayer dielectric layer.

[0048] Although the above description uses an alternative gate process as an example, this disclosure is not limited thereto. All processes in the art for fabricating field-effect transistors on SOI substrates are applicable here.

[0049] The FDSOI integrated device according to embodiments of this disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such an FDSOI integrated device, and an electronic device can be constructed therefrom. Such an electronic device may also include components such as a display screen that works with the integrated circuit and a wireless transceiver that works with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0050] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0051] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. An FDSOI integrated device, characterized in that, The FDSOI integrated device includes a plurality of field-effect transistors formed on a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate includes a buried oxide layer and a SiGe semiconductor layer adjacent to the buried oxide layer. Among them, any field-effect transistor includes: The SiGe semiconductor layer used as the channel portion; The gate on the channel portion; and The source / drain layers that are connected to the channel portion on opposite sides of the gate. The SiGe semiconductor layers of the plurality of field-effect transistors have different Ge concentrations relative to each other, thereby each of the plurality of field-effect transistors has a different threshold voltage relative to each other.

2. The FDSOI integrated device according to claim 1, characterized in that, The field-effect transistor is a p-type field-effect transistor; The gates of the plurality of field-effect transistors each have the same work function; The channel portions of the plurality of field-effect transistors each have substantially equal thickness in the vertical direction.

3. The FDSOI integrated device according to claim 1 or 2, characterized in that, The plurality of field-effect transistors include: A first field-effect transistor, wherein the channel portion of the first field-effect transistor has a first germanium concentration and a first threshold voltage; The second field-effect transistor has a second germanium concentration in its channel and a second threshold voltage. A third field-effect transistor, wherein the channel portion of the third field-effect transistor has a third germanium concentration and a third threshold voltage, Wherein, the first germanium concentration is lower than the second germanium concentration, and the second germanium concentration is lower than the third germanium concentration; the first threshold voltage is higher than the second threshold voltage, and the second threshold voltage is higher than the third threshold voltage.

4. The FDSOI integrated device according to claim 3, characterized in that, The first field-effect transistor is a conventional threshold voltage RVT field-effect transistor; the second field-effect transistor is a low threshold voltage LVT field-effect transistor; and the third field-effect transistor is an ultra-low threshold voltage SLVT field-effect transistor.

5. The FDSOI integrated device according to claim 4, characterized in that, The channel portion of the first field-effect transistor contains 5% to 50% Ge atomic percentage, the channel portion of the second field-effect transistor has a Ge atomic percentage 2% to 20% higher than that of the first field-effect transistor, and the channel portion of the third field-effect transistor has a Ge atomic percentage 2% to 20% higher than that of the second field-effect transistor.

6. The FDSOI integrated device according to claim 5, characterized in that, The channel portion of the first field-effect transistor contains 10% to 25% Ge atomic percentage, the SiGe channel portion of the second field-effect transistor has a 2% to 6% higher Ge atomic percentage than the first field-effect transistor, and the channel portion of the third field-effect transistor has a 2% to 6% higher Ge atomic percentage than the second field-effect transistor.

7. A method for manufacturing an FDSOI integrated device, characterized in that, The method includes: Multiple SiGe epitaxial layers with different Ge concentrations are formed on a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate includes a buried oxide layer and a top silicon layer adjacent to the buried oxide layer. A thermal oxidation process is performed to drive the Ge element in the plurality of SiGe epitaxial layers into the corresponding region of the top silicon layer in which each of the plurality of SiGe epitaxial layers is located, thereby forming the top silicon layer into a SiGe semiconductor layer with different Ge concentrations in the regions corresponding to the different SiGe epitaxial layers. After the thermal oxidation, the plurality of SiGe epitaxial layers are formed into an oxide layer. The oxide layer is removed, and field-effect transistors are formed on different regions of the plurality of SiGe semiconductor layers. Each field-effect transistor includes a gate on a channel portion and source / drain layers located on opposite sides of the gate portion and connected to the channel portion. The SiGe semiconductor layer serves as the channel portion.

8. The method according to claim 7, characterized in that, Forming the plurality of SiGe epitaxial layers includes: While exposing a first region of the top surface of the top silicon layer using a mask layer and masking other regions, a first SiGe epitaxial layer with a first Ge concentration is epitaxially grown on the first region. While using a second region on the top surface of the top silicon layer to expose other regions on a mask layer, a second SiGe epitaxial layer with a second Ge concentration is epitaxially grown on the second region. While exposing a third region of the top surface of the top silicon layer using a mask layer and masking other regions, a third SiGe epitaxial layer with a third Ge concentration is epitaxially grown on the third region.

9. The method according to claim 7, characterized in that, Forming the gate includes: In each region, a gate with the same work function is formed, the gate comprising a gate dielectric layer of the same material and thickness and a gate conductor layer on the gate dielectric layer.

10. The method according to claim 7, characterized in that, The method further includes: The Ge concentration of each of the plurality of SiGe epitaxial layers is determined based on the expected threshold voltage of the p-type field-effect transistor formed on each of the regions.

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