Image sensor

Abstract

An image sensor includes: a first photodetector (PD) in a substrate, the first PD absorbing visible light; a spacer layer on the substrate; a nano prism on the spacer layer; and a second PD structure on the nano prism, the second PD structure absorbing the infrared light. The nano prism splits incident light into a plurality of light beams by color, and the spacer layer concentrates each of the plurality of light beams into the first PD. The nanoprism includes a first low refractive layer and a first nanopillar pattern extending through the first low refractive layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0131516, filed on September 27, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some example embodiments of this disclosure relate to image sensors. Background Technology

[0004] To improve the sensitivity of image sensors, various methods have been developed that absorb not only visible light but also infrared light, and utilize both visible and infrared light. Summary of the Invention

[0005] Some example embodiments disclosed herein provide an image sensor with improved characteristics.

[0006] Some example embodiments provide an image sensor including: a first photodetector (PD) in a substrate, the first PD absorbing visible light; a spacer layer on the substrate; a nanoprism on the spacer layer; and a second PD structure on the nanoprism, the second PD structure absorbing infrared light. The nanoprism splits the incident light into multiple beams according to color, and the spacer layer focuses each beam of light onto the first PD. The nanoprism includes a first low-refractive-index layer and a first nanopillar pattern extending through the first low-refractive-index layer.

[0007] Some example embodiments also provide an image sensor including: a first photodetector (PD) in a substrate, the first PD absorbing visible light; a second PD structure on the substrate, the second PD structure absorbing infrared light; and a nanoprism on the second PD structure. The nanoprism includes a low-refractive layer and nanopillar patterns in the low-refractive layer, the nanopillar patterns being spaced apart from each other in a horizontal direction, and the diameters of the nanopillar patterns being different from each other.

[0008] Some example embodiments also provide an image sensor including: a first wiring structure and a second wiring structure, below a substrate; a first floating diffuser (FD) region, located at the lower part of the substrate, electrically connected to the first wiring structure; a first photodetector (PD), in the substrate, the first PD absorbing visible light; a second FD region, located at the lower part of the substrate, the second FD region electrically connected to the second wiring structure; a spacer layer, on the substrate; a nanoprism, on the spacer layer; a second PD structure, on the nanoprism, the second PD structure absorbing infrared light; and a via structure extending through the substrate, the spacer layer and the nanoprism, the via structure electrically connected to the second wiring structure and the second PD structure.

[0009] In some exemplary embodiments of the image sensor according to this disclosure, a first photodetector that absorbs visible light and a second photodetector that absorbs infrared light can be arranged in a vertical direction, and thus the image sensor can have enhanced sensitivity. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of an image sensor according to some example embodiments.

[0011] Figure 2 It shows Figure 1 A planar view of the layout of nanopillar patterns included in the nanoprisms of the image sensor.

[0012] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a cross-sectional view illustrating a method for manufacturing an image sensor according to some example embodiments.

[0013] Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a cross-sectional view of an image sensor according to some example embodiments.

[0014] Figure 13 This is a plan view illustrating the layout of nanopillar patterns included in the nanoprism of an image sensor according to some example embodiments. Detailed Implementation

[0015] The following detailed description, taken in conjunction with the accompanying drawings, will provide a clearer understanding of an image sensor and a method for manufacturing the image sensor according to some exemplary embodiments of the invention.

[0016] It will be understood that although the terms “first,” “second,” and / or “third” may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0017] In the following text, two intersecting horizontal directions that are substantially parallel to the upper surfaces of each of the first and second substrates may be referred to as the first direction D1 and the second direction D2, respectively, and a vertical direction that is substantially perpendicular to the upper surfaces of each of the first and second substrates may be referred to as the third direction D3. Each of the first direction D1, the second direction D2, and the third direction D3 may include not only the directions shown in the figures but also the directions opposite to them. In some example embodiments, the first direction D1 and the second direction D2 may be substantially perpendicular to each other.

[0018] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) around the values. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, this is intended not to require precision in the geometry, but rather a tolerance for the shape within the scope of this disclosure. Additionally, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the values ​​or shapes. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0019] Figure 1 This is a cross-sectional view of an image sensor according to some example embodiments. Figure 2 It shows Figure 1 A planar view of the layout of nanopillar patterns included in the nanoprisms of the image sensor. Figure 1 It is along Figure 2 A cross-sectional view taken from line A-A'.

[0020] Reference Figure 1 and Figure 2 The image sensor may include transistors, a fourth wiring structure 352 and a fifth wiring structure 354, a second interlayer insulating layer 360, a first bonding layer 220, a second bonding layer 370, a first wiring structure 202, a second wiring structure 203, a third wiring structure 204, a first interlayer insulating layer 210, a transmission gate (TG) 150, a first substrate 100, a first buffer layer 410, a spacer layer 420, a nanoprism 460, a first electrode layer 510, a second photodetector (PD) 530, a second electrode 550, and a first protective layer 560 on a second substrate 300.

[0021] The image sensor may further include: a first floating diffusion (FD) region 160 and a second floating diffusion (FD) region 165 disposed in the first substrate 100, a first photodetector (PD) 170, a first dividing pattern 130 and a second dividing pattern 140, a fourth insulating pattern 145 and a fifth insulating pattern 147 that may partially extend through the first substrate 100, a first via 135, and a third via 470 that may extend through the first buffer layer 410, the spacer layer 420 and the nanoprism 460.

[0022] In some example embodiments, the image sensor may also include a third substrate on which an image signal processor (ISP) is disposed, the image signal processor including, for example, analog-to-digital converter (ADC) circuitry, the third substrate being bonded to the second substrate 300 below the second substrate 300.

[0023] The second substrate 300 may include a first surface 302 and a second surface 304 that are opposite to each other on a third-direction D3. Figure 1 The diagram shows that the first surface 302 is the lower surface of the second substrate 300, and the second surface 304 is the upper surface of the second substrate 300. The second substrate 300 may include semiconductor materials (e.g., silicon, germanium, silicon-germanium, etc.) or III-V compound materials (e.g., GaP, GaAs, GaSb, etc.).

[0024] Each transistor may include a gate structure on a second surface 304 of the second substrate 300, and a source / drain region at a corresponding upper portion of the second substrate 300 adjacent to the gate structure. In some example embodiments, the transistor may include, for example, a source follower (SF) transistor, a select transistor, and a reset transistor.

[0025] Figure 1 A first transistor and a second transistor are shown as transistors. The first transistor may include a first gate structure 342 on a second substrate 300 and a first impurity region 312 at a corresponding upper portion of the second substrate 300 adjacent to the first gate structure 342, and the second transistor may include a second gate structure 344 on the second substrate 300 and a second impurity region 314 at a corresponding upper portion of the second substrate 300 adjacent to the second gate structure 344. The first gate structure 342 may include a first gate insulating pattern 322 and a first gate electrode 332 stacked on a third-direction D3, and the second gate structure 344 may include a second gate insulating pattern 324 and a second gate electrode 334 stacked on a third-direction D3.

[0026] Each of the first gate insulating pattern 322 and the second gate electrode 324 may include an oxide (e.g., silicon oxide), and each of the first gate electrode 332 and the second gate electrode 334 may include a conductive material (e.g., a metal, a metal nitride, a metal silicide, etc.). Each of the first impurity region 312 and the second impurity region 314 may include, for example, an n-type impurity or a p-type impurity.

[0027] The fourth wiring structure 352 and the fifth wiring structure 354 may be disposed on the second substrate 300 and may be electrically connected to the first transistor and the second transistor, respectively. Each of the fourth wiring structure 352 and the fifth wiring structure 354 may include, for example, a contact plug, wiring, via, etc., and may include a conductive material (e.g., metal, metal nitride, metal silicide, etc.).

[0028] The second interlayer insulating layer 360 can be disposed on the second substrate 300 and can cover the fourth wiring structure 352 and the fifth wiring structure 354. The second interlayer insulating layer 360 may include, for example, silicon oxide, a low-k dielectric material, etc.

[0029] A second bonding layer 370 may be disposed on the second interlayer insulating layer 360 and may include a second bonding pad 380 extending through the second bonding layer 370. A first bonding layer 220 may be disposed on and bonded to the second bonding layer 370 and may include a first bonding pad 230 extending through the first bonding layer 220. The bonded first bonding layer 220 and second bonding layer 370 may together form a bonding layer structure. In some example embodiments, a plurality of first bonding pads 230 may be horizontally spaced apart from each other in the first bonding layer 220, and a plurality of second bonding pads 380 may be horizontally spaced apart from each other in the second bonding layer 370. The first bonding pads 230 and second bonding pads 380 may contact each other and may together form a bonding pad structure.

[0030] Therefore, multiple bonding pad structures can be spaced apart from each other in the horizontal direction in the bonding layer structure, and each bonding pad structure can be electrically connected to the corresponding wiring structure in the fourth wiring structure 352 and the fifth wiring structure 354.

[0031] Each of the first bonding layer 220 and the second bonding layer 370 may include, for example, silicon carbonitride, silicon oxide, etc., and each of the first bonding pad 230 and the second bonding pad 380 may include metal (e.g., copper).

[0032] Each of the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204 can be disposed on the bonding layer structure and can contact a corresponding bonding pad structure in the bonding pad structure for electrical connection thereto.

[0033] Each of the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204 may include, for example, a contact plug, wiring, a via, etc., and may include a conductive material (e.g., a metal, a metal nitride, a metal silicide, etc.). The third wiring structure 204 may also include a second through-hole 207.

[0034] The first interlayer insulating layer 210 can be disposed on the bonding layer structure and can cover the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204. The first interlayer insulating layer 210 may include, for example, silicon oxide, a low-k dielectric material, etc.

[0035] The first substrate 100 may include a first surface 102 and a second surface 104 that are opposite to each other on a third-direction D3. Figure 1 The diagram shows a first substrate 100 with a first surface 102 as its lower surface and a second surface 104 as its upper surface. The first substrate 100 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a III-V compound (e.g., GaP, GaAs, or GaSb). In some example embodiments, a p-type well including a p-type impurity may be formed in a portion or the entirety of the first substrate 100.

[0036] The first dividing pattern 130 may extend through the portion of the first substrate 100 adjacent to the second surface 104 (e.g., extending through the upper portion of the first substrate 100), and the second dividing pattern 140 may extend through the portion of the first substrate 100 adjacent to the first surface 102 (e.g., extending through the lower portion of the first substrate 100) to contact the lower surface of the first dividing pattern 130. Therefore, the second dividing pattern 140 and the first dividing pattern 130 stacked on the third direction D3 may extend through the first substrate 100 and may together form a dividing pattern structure.

[0037] In some example embodiments, the dividing pattern structure in the planar view may have, for example, a lattice shape, and thus the first substrate 100 may be divided into a plurality of unit pixel regions by the dividing pattern structure. However, the unit pixel regions may also be defined in the portions of each of the first buffer layer 410, spacer layer 420, nanoprism 460, first electrode layer 510, second PD 530, second electrode 550, and first protective layer 560 corresponding to the unit pixel regions in the first substrate 100. Furthermore, the unit pixel regions may not only be defined inside the first substrate 100, but may also be defined in the spaces above and below the first substrate 100 on a third-direction D3, and in structures disposed in such spaces.

[0038] In some example embodiments, the width of the first dividing pattern 130 can gradually decrease from its top to its bottom, and the width of the second dividing pattern 140 can gradually increase from its top to its bottom. In some example embodiments, the width of the upper surface of the second dividing pattern 140 can be greater than the width of the lower surface of the first dividing pattern 130. The length of the first dividing pattern 130 in the third direction D3 can be greater than the length of the second dividing pattern 140 in the third direction D3.

[0039] In some example embodiments, the first dividing pattern 130 may include a first conductive pattern 120 and a first insulating pattern 122 covering the sidewalls of the first conductive pattern 120. The first conductive pattern 120 may include a metal (e.g., copper, tungsten, etc.) or doped polycrystalline silicon, and the first insulating pattern 122 may include a metal oxide (e.g., aluminum oxide, tantalum oxide, etc.) or silicon oxide.

[0040] The second dividing pattern 140 may include oxides (e.g., silicon oxide).

[0041] Each of the fourth insulating pattern 145 and the fifth insulating pattern 147 may extend through the portion of the first substrate 100 adjacent to the first surface 102, i.e., the lower portion of the first substrate 100 in each unit pixel region. In some example embodiments, each of the fourth insulating pattern 145 and the fifth insulating pattern 147 may have a width that gradually increases from its top to its bottom. In some example embodiments, the height of the upper surface of each of the fourth insulating pattern 145 and the fifth insulating pattern 147 may be the same as or substantially the same as the height of the upper surface of the second dividing pattern 140.

[0042] Each of the fourth insulating pattern 145 and the fifth insulating pattern 147 may include an oxide (e.g., silicon oxide).

[0043] The first via 135 may extend through a portion of the first substrate 100 adjacent to the second surface 104 (e.g., extending through the upper portion of the first substrate 100 in each unit pixel region) and may contact the upper surface of the fourth insulating pattern 145. In some example embodiments, the width of the first via 135 may gradually decrease from its top to its bottom. In some example embodiments, the width of the lower surface of the first via 135 may be less than the width of the upper surface of the fourth insulating pattern 145. The length of the first via 135 in the third direction D3 may be greater than the length of the fourth insulating pattern 145 in the third direction D3.

[0044] In some example embodiments, the first via 135 may include a second conductive pattern 125 and a second insulating pattern 127 covering the sidewalls of the second conductive pattern 125. The second conductive pattern 125 may include a metal (e.g., copper, tungsten, etc.) or doped polycrystalline silicon, and the second insulating pattern 127 may include a metal oxide (e.g., aluminum oxide, tantalum oxide, etc.) or silicon oxide. In some example embodiments, the second conductive pattern 125 and the second insulating pattern 127 may each include the same or substantially the same material as the first conductive pattern 120 and the first insulating pattern 122.

[0045] The second via 207 may extend through the upper portion of the first interlayer insulating layer 210 in each unit pixel region and may contact the lower surface of the first via 135. The second via 207 may also extend through the fourth insulating pattern 145. In some example embodiments, the width of the second via 207 may gradually increase from its top to its bottom. The second via 207 may comprise a metal (e.g., copper, tungsten, etc.) or doped polysilicon.

[0046] TG 150 may include a buried portion and a protruding portion. The buried portion may extend along a third direction D3 through a portion of the first substrate 100 adjacent to the first surface 102 (e.g., extending through the lower part of the first substrate 100), and the protruding portion may be disposed below the buried portion, having a lower surface below the first surface 102 of the first substrate 100, and contacting the first surface 102 of the first substrate 100 in each unit pixel region. TG 150 may include a metal (e.g., copper, tungsten, etc.) or doped polysilicon.

[0047] The first FD region 160 may be disposed at the lower portion of the first substrate 100 adjacent to TG 150 in each unit pixel region, and the second FD region 165 may be disposed at the lower portion of the first substrate 100 adjacent to the fourth insulating pattern 145. Each of the first FD region 160 and the second FD region 165 may include silicon doped with, for example, n-type impurities.

[0048] The first PD 170 can be disposed inside the first substrate 100 in each unit pixel region and can contact the upper surface of the buried portion of TG 150 or can be configured to be adjacent to the upper surface of the buried portion of TG 150. The first PD 170 can include silicon doped with, for example, n-type impurities, and the first PD 170 and p-type well in the first substrate 100 can jointly form a PN junction diode. Therefore, the first PD 170 can also be referred to as a first photodiode or a silicon photodiode, because the first PD 170 can include doped polycrystalline silicon.

[0049] TG 150, the first PD 170 and the first FD region 160 can together form a transmission transistor.

[0050] The first buffer layer 410 may be disposed on the second surface 104 of the first substrate 100, the upper surface of the first dividing pattern 130, and the upper surface of the first via 135. The first buffer layer 410 may include an oxide (e.g., silicon oxide), and in some example embodiments, the image sensor may not include the first buffer layer 410.

[0051] Spacer layer 420 may be disposed on first buffer layer 410. Spacer layer 420 may include oxide (e.g., silicon oxide), and in some example embodiments, spacer layer 420 may be merged with first buffer layer 410.

[0052] In some example embodiments, the spacer layer 420 may have a sufficiently large thickness on the third-direction D3 such that light passing through the nanoprism 460 can be focused onto the first PD 170. Therefore, the thickness of the spacer layer 420 on the third-direction D3 may have a range that is the same as, substantially the same as, or wider than the wavelength range of visible light. For example, the thickness of the spacer layer 420 on the third-direction D3 may be in the range of about 200 nm to about 1000 nm, preferably in the range of about 400 nm to about 700 nm.

[0053] The nanoprism 460 may be disposed on the spacer layer 420 and may include a first low-refractive-index layer 430 and a high-refractive-index pattern extending through the first low-refractive-index layer 430. The first low-refractive-index layer 430 may include a material with a refractive index equal to or less than about 2 (e.g., silicon oxide). The high-refractive-index pattern may include a material with a refractive index greater than about 2 (e.g., titanium oxide). The high-refractive-index pattern may also be referred to as a nanopillar pattern, and the nanoprism 460 may also be referred to as a superprism.

[0054] In some example embodiments, the nanoprism 460 may include multiple nanopillar patterns with different diameters, which may be spaced apart from each other in various layouts in the horizontal direction.

[0055] Figure 2 A first nanopillar pattern 441, a second nanopillar pattern 442, a third nanopillar pattern 443, and a fourth nanopillar pattern 444 are shown. In some example embodiments, each of the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 may have a pillar shape and may have shapes such as circles, ellipses, polygons, and polygons with rounded corners in a planar view. The first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 may have a first diameter D1, a second diameter D2, a third diameter D3, and a fourth diameter D4, respectively, which may have values ​​decreasing in this order.

[0056] In some example embodiments, in each unit pixel region, some or all of the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 can be spaced apart from each other in the first low-refractive layer 430 in the first direction D1 and the second direction D2, and the incident light can be diffracted according to the arrangement of the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444, and light in a specific wavelength range (e.g., red light R, green light G, and blue light B) can be filtered.

[0057] For example, the first nanopillar pattern 441, the second nanopillar pattern 442, and the fourth nanopillar pattern 444 can be arranged in the first unit pixel region, the second nanopillar pattern 442 and the third nanopillar pattern 443 can be arranged in the second unit pixel region, and the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 can be arranged in the third unit pixel region. The portions of the nanoprism 460 in the first to third unit pixel regions can respectively filter red light (R), green light (G), and blue light (B).

[0058] In some example embodiments, a first nanopillar pattern 441 may be disposed at the center portion of a first unit pixel region, a second nanopillar pattern 442 may be disposed at the edge portions of the first unit pixel region, these edge portions being on opposite sides of the first nanopillar pattern 441 along each of the first direction D1 and the second direction D2, and a fourth nanopillar pattern 444 may be disposed at the four corners of the first unit pixel region.

[0059] The second nanopillar pattern 442 can be disposed at the center portion of the second unit pixel region, and the third nanopillar pattern 443 can be disposed at the edge portion of the second unit pixel region, the edge portions being on opposite sides of the second nanopillar pattern 442 along each of the first direction D1 and the second direction D2.

[0060] Furthermore, the second nanopillar pattern 442 can be disposed at the center of the third unit pixel region, the third nanopillar pattern 443 can be disposed at the edge of the third unit pixel region respectively, these edge portions are on the opposite side of the second nanopillar pattern 442 along each of the first direction D1 and the second direction D2, and the fourth nanopillar pattern 444 can be disposed at the four corners of the third unit pixel region respectively.

[0061] However, the layout of the nanopillar pattern described above is not limiting, and the nanoprism 460 may include nanopillar patterns arranged in other layouts.

[0062] Figure 2 The invention illustrates a group of four unit pixel regions (four Bayer pattern arrays) that are adjacent to each other in the first direction D1 and the second direction D2, which can filter light with the same wavelength range. However, the inventive concept is not limited thereto.

[0063] Combination Figure 13 Reference Figure 1 and Figure 2 For example, the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443 and the fourth nanopillar pattern 444 can be arranged such that light with different wavelength ranges (e.g., red light R, green light G and blue light B) can be filtered by a unit pixel area (Bayer pattern array) respectively.

[0064] In each unit pixel region, the third via 470 can extend through the first buffer layer 410, the spacer layer 420, and the first low-refractive-index layer 430, and can contact the upper surface of the first via 135. The second via 207, the first via 135, and the third via 470, which are sequentially stacked on the third-direction D3, can together form a via structure.

[0065] The first electrode layer 510 can be disposed on the nanoprism 460 and the third via 470, and can include a first electrode 520 therein. The first electrode 520 can be disposed in each unit pixel area and can contact the upper surface of the third via 470.

[0066] The second PD 530 can be disposed on the first electrode layer 510.

[0067] In some example embodiments, the second PD 530 may include an active layer, an electron transport layer (ETL) on the upper surface of the active layer, and a hole transport layer (HTL) on the lower surface of the active layer. In some example embodiments, the active layer may have a bulk heterojunction (BHJ) structure in which the donor and acceptor layers permeate each other. Alternatively, the active layer may have a planar heterojunction (PHJ) structure in which the donor and acceptor layers are stacked in the vertical direction.

[0068] The donor layer may include a thiophene-based polymer (e.g., P3HT (poly(3-hexylthiophene))) and the acceptor layer may include a fullerene-based polymer. Therefore, the second PD 530 may include organic materials and may be referred to as an organic photodetector or an organic photodiode, or a second photodiode.

[0069] Alternatively, the second PD 530 may be a quantum dot photodetector including quantum dots (QDs) of a few nanometers in size. The QD may have a core including, for example, cadmium selenide (CdSe), a shell surrounding the core including, for example, zinc sulfide (ZnS), and a coating covering the shell surface including, for example, trioctylphosphine (TOPO) oxide.

[0070] The second electrode 550 can be disposed on the second PD 530.

[0071] Each of the first electrode 520 and the second electrode 550 may be a transparent electrode, including, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0072] A first protective layer 560 may be disposed on and cover the second electrode 550. The first protective layer 560 may include a metal oxide (e.g., aluminum oxide).

[0073] The first electrode layer 510, the second PD 530, the second electrode 550 and the first protective layer 560 stacked on the third-party D3 can be collectively referred to as a second photodetector structure, an organic photodetector structure, an organic photodiode structure, or a QD photodetector structure, a QD photodiode structure, etc.

[0074] When light is incident on the upper surface of the image sensor (i.e., the second photodetector structure), the near-infrared (NIR) light can be absorbed by the second PD 530, which includes organic materials. For example, the NIR light can be absorbed by the active layer of the second PD 530 to generate excitons, which can be split into holes and electrons to move to the anode and cathode between the first electrode 520 and the second electrode 550 via the HTL and ETL, respectively. Electrons or holes that move to the first electrode 520 can move to the second FD region 165 and be stored through via structures (e.g., through the first via 135, the second via 207, and the third via 470, and a portion of the third wiring structure 204).

[0075] If the second PD 530 is a QD photodetector, then the short-wave infrared (SWIR) light can be absorbed by the second PD 530, and the electrons or holes generated by the SWIR light can move into the second FD region 165 and be stored.

[0076] After the light passes through the second photodetector structure, the portion of the light other than NIR and SWIR rays (e.g., visible light) can be split into red (R), green (G), and blue (B) light as it passes through the nanoprism 460. Each separated beam of light can pass through the spacer layer 420, the first buffer layer 410, and the upper part of the first substrate 100 to converge into the first PD 170, thereby generating electrons and holes. The electrons and holes generated by the first PD 170 can move into the first FD region 160 and be stored.

[0077] Similarly, NIR or SWIR light incident on the image sensor can be absorbed by the second PD 530, while visible light can be absorbed by the first PD 170. Therefore, the sensitivity of this image sensor can be twice that of an image sensor with the same level of first PD 170 and second PD 530 in a unit pixel area. For example, the image sensor can have higher sensitivity even if the unit pixel area has the same area.

[0078] The image sensor may include a nanoprism 460 and a spacer layer 420 between the first PD 170 and the second PD 530, and the incident light may be separated by color, and each separated beam of light may be focused into the first PD 170.

[0079] If, for example, an image sensor includes microlenses and a color filter array, the light incident on the image sensor can be focused by the microlenses, and the focused light can be split into red light (R), green light (G), and blue light (B) by the color filter array. Therefore, only one-third of the total light can be incident on the photodetector in each unit pixel area, potentially resulting in a loss of approximately two-thirds of the light.

[0080] However, in some example embodiments, the image sensor may include a nanoprism 460 and a spacer layer 420 instead of microlenses and a color filter array, and after the light is split into red (R), green (G), and blue (B) light by the nanoprism 460, light of the same color can be partially focused into the first PD 170 not only in the unit pixel region but also in the adjacent unit pixel regions by the spacer layer 420. Accordingly, the image sensor may further have increased sensitivity.

[0081] Image sensors can have enhanced capabilities, for example, in environments where light intensity varies (such as the exit of a dark tunnel or an underground parking lot). This is due to the increased sensitivity of image sensors.

[0082] Figures 3 to 8 This is a cross-sectional view illustrating a method for manufacturing an image sensor according to some example embodiments, which may be along... Figure 2 A cross-sectional view taken from line A-A'.

[0083] Reference Figure 3 A portion of the first substrate 100 can be removed to form a first trench 110 and a second trench 115. The first substrate 100 includes a first surface 102 and a second surface 104 that are opposite to each other in a third direction D3. The portion can be adjacent to the second surface 104. A first insulating layer can be formed on the inner walls of the first trench 110 and the second trench 115 and on the second surface 104 of the first substrate 100. A first conductive layer can be formed on the first insulating layer to fill the first trench 110 and the second trench 115. A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed on the first conductive layer and the first insulating layer until the second surface 104 of the first substrate 100 is exposed.

[0084] As the planarization process is performed, a first dividing pattern 130 can be formed in the first trench 110. The first dividing pattern 130 includes a first conductive pattern 120 and a first insulating pattern 122 covering the sidewalls and lower surface of the first conductive pattern 120. A first through hole 135 can be formed in the second trench 115. The first through hole 135 includes a second conductive pattern 125 and a second insulating pattern 127 covering the sidewalls and lower surface of the second conductive pattern 125.

[0085] In some example embodiments, the first dividing pattern 130 may have a grid shape arranged in a first direction D1 and a second direction D2 in a plan view.

[0086] P-type impurities can be doped into a portion or all of the first substrate 100 to form a p-type well.

[0087] Reference Figure 4 After flipping the first substrate 100, the portion of the first substrate 100 adjacent to the first surface 102 can be removed to form a third trench and a fourth trench. The third trench and the fourth trench expose the upper portions of the first insulating pattern 122 and the second insulating pattern 127, respectively. The exposed upper portions of the first insulating pattern 122 and the third insulating pattern 127 can be removed to enlarge the third trench and the fourth trench, respectively, so that the upper surfaces of the first conductive pattern 120 and the second conductive pattern 125 can be exposed. A third insulating layer can be formed on the first surface 102 of the first substrate 100 and the exposed upper surfaces of the first conductive pattern 120 and the second conductive pattern 125. A planarization process (e.g., CMP process) can be performed on the third insulating layer until the first surface 102 of the first substrate 100 is exposed.

[0088] As the planarization process is performed, a third insulating pattern 140 and a fourth insulating pattern 145 can be formed in the third and fourth trenches, respectively. In some example embodiments, the area of ​​the lower surface of the third insulating pattern 140 and the fourth insulating pattern 145 can be larger than the area of ​​the first dividing pattern 130 and the first through hole 135, respectively, and the third insulating pattern 140 and the fourth insulating pattern 145 can contact the first dividing pattern 130 and the first through hole 135, respectively.

[0089] In some example embodiments, the third insulating pattern 140 may have a grid shape arranged in the first direction D1 and the second direction D2 in a plan view. The third insulating pattern 140 may also be referred to as the second dividing pattern 140, and the first dividing pattern 130 and the second dividing pattern 140 stacked and in contact with each other in the third direction D3 may together form a dividing pattern structure.

[0090] When the third insulating pattern 140 and the fourth insulating pattern 145 are formed, a fifth insulating pattern 147 may also be formed on the portion of the first substrate 100 adjacent to the first surface 102.

[0091] A first photodetector (PD) 170 may be formed in the first substrate 100, a transmission gate (TG) 150 may be formed on the first surface 102 of the first substrate 100, the transmission gate 150 extending through the portion of the first substrate 100 adjacent to the first surface 102, and a first floating diffusion (FD) region 160 and a second floating diffusion (FD) region 165 may be formed at the portion of the first substrate 100 adjacent to the first surface 102.

[0092] In some example embodiments, the first PD 170 can be formed by doping an n-type impurity into the p-type well of the first substrate 100, and the first PD 170 and the p-type well can together form a PN junction diode.

[0093] TG 150 can be formed by forming and filling a fifth trench that extends downward from the first surface 102 of the first substrate 100 along a third direction D3 to expose the upper surface of the first PD 170. In some example embodiments, TG 150 may include a buried portion and a protruding portion, the buried portion filling the fifth trench and contacting the upper surface of the first PD 170, and the protruding portion being disposed on the buried portion, having a height above the upper surface 102 of the first substrate 100 and contacting the first surface 102 of the first substrate 100.

[0094] The first FD region 160 and the second FD region 165 can be formed by doping, for example, an n-type impurity into a portion of the first substrate 100 adjacent to the first surface 102. The first FD region 160 can be formed adjacent to TG 150, and the second FD region 165 can be formed adjacent to the fourth insulating pattern 145.

[0095] Reference Figure 5 The first wiring structure 202, the second wiring structure 203, and the third wiring structure 204 can be formed on the first surface 102 of the first substrate 100 to be electrically connected to the TG 150, the first FD region 160, the second FD region 165, and the first via 135. A first interlayer insulating layer 210 can be formed to cover the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204. A first bonding layer 220 including the first bonding pad 230 can be formed on the first interlayer insulating layer 210.

[0096] In some example embodiments, each of the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204 may include contact plugs, wiring, and vias. For example, the third wiring structure 204 may include a second through-hole 207 that extends through the lower portion of the first interlayer insulating layer 210 and the fourth insulating pattern 145 to contact the upper surface of the first through-hole 135.

[0097] In some example embodiments, the first wiring structure 202 may contact the TG 150 for electrical connection thereto, the second wiring structure 203 may contact the upper surface of the first FD region 160 for electrical connection thereto, and the third wiring structure 204 may contact the upper surface of the first via 135 and the second FD region 165 for electrical connection thereto.

[0098] Each first bonding pad 230 may contact one of the first wiring structure 202, the second wiring structure 203, and the third wiring structure 204 for electrical connection thereto.

[0099] Reference Figure 6 A first transistor and a second transistor may be formed on the second surface 304 of a second substrate 300, which includes a first surface 302 and a second surface 304 that are opposite to each other on a third-direction D3. A fourth wiring structure 352 and a fifth wiring structure 354 may be formed to electrically connect to the first transistor and the second transistor, respectively. A second interlayer insulating layer 360 may be formed on the second surface 304 of the second substrate 300, and a second bonding layer 370 including a second bonding pad 380 may be formed in the second interlayer insulating layer 360.

[0100] The first transistor may include a first gate structure 342 having a first gate electrode 332 and a first gate insulating pattern 322, and a first source / drain region 312 in a portion of the second substrate 300 adjacent to the first gate structure 342. The second transistor may include a second gate structure 344 having a second gate electrode 334 and a second gate insulating pattern 324, and a second source / drain region 314 in a portion of the second substrate 300 adjacent to the second gate structure 344.

[0101] Figure 6 The first transistor and the second transistor are shown; however, the inventive concept is not limited thereto, and additional transistors may be included on the second surface 304.

[0102] In some example embodiments, each of the fourth wiring structure 352 and the fifth wiring structure 354 may include a contact plug, wiring, via, etc.

[0103] In some example embodiments, the fourth wiring structure 352 may be electrically connected to the first transistor, and the fifth wiring structure 354 may be electrically connected to the second transistor.

[0104] Each second bonding pad 380 may contact one of the fourth wiring structure 352 and the fifth wiring structure 354 for electrical connection.

[0105] Reference Figure 7 After the first substrate 100 is flipped, the first bonding layer 220 on the first substrate 100 and the second bonding layer 370 on the second substrate 300 can come into contact with each other, so that the first substrate 100 and the second substrate 300 can be bonded to each other.

[0106] The first bonding pad 230 in the first bonding layer 220 can contact the second bonding pad 380 in the second bonding layer 370.

[0107] A first buffer layer 410 comprising an oxide (e.g., silicon oxide) may be formed on the second surface 104, the first dividing pattern 130, and the first via 135 of the first substrate 100.

[0108] Reference Figure 8 A spacer layer 420 can be formed on the first buffer layer 410, and a nanoprism 460 can be formed on the spacer layer 420.

[0109] Spacer layer 420 may include oxide (e.g., silicon oxide), and in some example embodiments, spacer layer 420 may be incorporated into first buffer layer 410.

[0110] Combination Figure 2 Reference Figure 8The nanoprism 460 can be formed by the following steps: forming a first low-refractive-index layer 430 comprising a low-refractive-index material (e.g., silicon oxide) on a spacer layer 420; partially etching the first low-refractive-index layer 430 to form a first to a fourth hole, each hole exposing the upper surface of the spacer layer 420; forming a high-refractive-index layer comprising a high-refractive-index material (e.g., titanium oxide) on the spacer layer 420 and the first low-refractive-index layer 430 to fill the first to the fourth holes; and performing a planarization process (e.g., CMP process) on the high-refractive-index layer to form a first high-refractive-index pattern 441, a second high-refractive-index pattern 442, a third high-refractive-index pattern 443, and a fourth high-refractive-index pattern 444, respectively, in the first to the fourth holes. The first high-refractive-index pattern 441, the second high-refractive-index pattern 442, the third high-refractive-index pattern 443, and the fourth high-refractive-index pattern 444 can also be referred to as a first nanopillar pattern 441, a second nanopillar pattern 442, a third nanopillar pattern 443, and a fourth nanopillar pattern 444, respectively.

[0111] In some example embodiments, each of the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 may have a pillar shape, and in a planar view may have shapes such as circles, ellipses, polygons, or polygons with rounded corners. The first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 may have a first diameter D1, a second diameter D2, a third diameter D3, and a fourth diameter D4, respectively, in the vertical direction, and these diameters may have values ​​that decrease in this order.

[0112] In some exemplary embodiments, the first nanopillar pattern 441, the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 can have various arrangements in the horizontal direction. For example, the first nanopillar pattern 441, the second nanopillar pattern 442, and the fourth nanopillar pattern 444 can be arranged in a first unit pixel region, the second nanopillar pattern 442 and the third nanopillar pattern 443 can be arranged in a second unit pixel region, and the second nanopillar pattern 442, the third nanopillar pattern 443, and the fourth nanopillar pattern 444 can be arranged in a third unit pixel region. In some exemplary embodiments, the first unit pixel region to the third unit pixel region can be regions that filter red light R, green light G, and blue light B, respectively; however, the inventive concept is not limited thereto.

[0113] A third through-hole 470 can be formed through the first low-refractive layer 430, the spacer layer 420, and the first buffer layer 410 to contact the upper surface of the first through-hole 135. The second through-hole 207, the first through-hole 135, and the third through-hole 470, which are sequentially stacked on the third direction D3, can together form a through-hole structure.

[0114] Refer again Figure 1 and Figure 2 A first electrode layer 510 including a first electrode 520, a second PD 530, a second electrode 550, and a first protective layer 560 can be sequentially stacked on the nanoprism 460 and the third through hole 470.

[0115] In some example embodiments, the first electrode 520 may contact the upper surface of the third through hole 470.

[0116] In some example embodiments, the second PD 530 can be formed by an evaporation process, and thus can form an organic photodetector. Alternatively, the second PD 530 can be formed by a spin-coating process, and thus can form a quantum dot (PD) photodetector.

[0117] The above process can be used to manufacture an image sensor.

[0118] Figures 9 to 12 This illustrates an image sensor (which may correspond to) according to some example embodiments. Figure 1 Cross-sectional view of ).

[0119] Reference Figure 9 The second photodetector structure, including the first electrode layer 510, the second PD 530, the second electrode 550 and the first protective layer 560, the spacer layer 425, and the nanoprism 460 can be sequentially stacked on the spacer layer 420 on the third-direction D3.

[0120] exist Figure 9 In some of the example embodiments shown, the spacer layer 420 may be disposed between the first buffer layer 410 and the second photodetector structure; however, the inventive concept is not limited thereto. In some example embodiments, the spacer layer 420 may not be formed, and the first electrode layer 510 may be disposed directly on the upper surface of the first buffer layer 410.

[0121] Light incident on the upper surface of the image sensor can be split into multiple beams of different colors by the nanoprism 460. Each beam of light can pass through the spacer layer 425, the second photodetector structure, the first buffer layer 410, and the upper part of the first substrate 100 to be focused into the first PD 170.

[0122] Reference Figure 10 Except for excluding the spacer layer 425 on the second photodetector structure, the image sensor can be coupled with... Figure 9 The image sensors are the same or substantially the same or similar.

[0123] Even if the image sensor does not include the spacer layer 425 on the second photodetector structure, the first protective layer 560 of the second photodetector structure can also be used as the spacer layer 420. The first protective layer 560 may include a material with a refractive index less than that of the nanopillar pattern (e.g., aluminum oxide).

[0124] The nanoprism 460 can be disposed on the second photodetector structure, thus having a sufficiently large distance, through which each beam of light in the nanoprism 460 can be focused into the first PD 170 by the second photodetector structure or the spacer layer 420 on the first buffer layer 410.

[0125] Reference Figure 11 The image sensor may also include a color filter array layer between the first buffer layer 410 and the spacer layer 420.

[0126] The color filter array layer may include multiple color filters (e.g., a first color filter, a second color filter, and a third color filter), which are separated from each other by an interference blocking structure 610 on the portion of the first buffer layer 410 that overlaps with the partitioned pattern structure in the first substrate 100 in the third direction D3. Figure 11 It includes a first color filter 632 and a second color filter 634.

[0127] The first color filter 632, the second color filter 634, and the third color filter can be a red color filter, a green color filter, and a blue color filter, respectively; however, the concept of the present invention is not limited thereto.

[0128] The interference blocking structure 610 can be used as a blocker to limit and / or prevent light incident on a unit pixel area from moving to another unit pixel area, thereby blocking interference between adjacent unit pixel areas.

[0129] The interference blocking structure 610 may include a metal nitride (e.g., titanium nitride) or a metal (e.g., tungsten). In some example embodiments, the interference blocking structure 610 may include a first interference blocking pattern and a second interference blocking pattern stacked on a third-direction D3. The first interference blocking pattern may include a metal nitride (e.g., titanium nitride), and the second interference blocking pattern may include a metal (e.g., tungsten).

[0130] The second protective layer 620 may be further disposed on the upper surface of the first buffer layer 410 and on the upper surface and sidewalls of the interference blocking structure 610, and the color filter array layer may be disposed on the second protective layer 620. The second protective layer 620 may include a metal oxide (e.g., aluminum oxide).

[0131] The image sensor may also include a color filter array layer between the first PD 170 and the nanoprism 460, and thus can enhance the color separation capability for visible light and improve crosstalk between adjacent unit pixel areas.

[0132] Reference Figure 12 The nanoprism 460 may include a first low-refractive-index layer 430, a second buffer layer 437, and a second low-refractive-index layer 435 stacked on a third-direction D3.

[0133] In some example embodiments, the second low-refractive-index layer 435 may comprise the same or substantially the same material as the first low-refractive-index layer 430, and may have the same or substantially the same thickness as the first low-refractive-index layer 430 on the third direction D3; however, the inventive concept is not limited thereto.

[0134] The second buffer layer 437 may include oxides (e.g., silicon oxide).

[0135] For example, the fifth to eighth nanopillar patterns can be disposed in the second low-refractive layer 435, and the fifth nanopillar pattern 451 and the sixth nanopillar pattern 453 are as follows: Figure 12 As shown. Figure 12 The fifth nanopillar pattern 451 is shown to have the same or substantially the same diameter as the first nanopillar pattern 441, and the sixth nanopillar pattern 453 has the same or substantially the same diameter as the third nanopillar pattern 443; however, the inventive concept is not limited thereto.

[0136] Since the nanoprism 460 includes nanopillar patterns stacked in the first low-refractive layer 430 and the second low-refractive layer 435 respectively and in the third direction D3, the degree of freedom to design layouts of nanopillar patterns with different diameters can be increased compared to the nanoprism 460 which includes nanopillar patterns in only a single low-refractive layer.

[0137] As described above, although the inventive concept has been described with reference to some exemplary embodiments, those skilled in the art will readily understand that many modifications can be made to these exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. An image sensor, comprising: In the substrate, the first photodetector PD is configured to absorb visible light; A spacer layer on the substrate; Nanoprisms, on the spacer layer; as well as A second PD structure is configured on the nanoprism to absorb infrared light. The nanoprism is configured to split the incident light into multiple beams according to color, and the spacer layer is configured to focus each of the multiple beams onto the first PD. The nanoprism includes: The first low-refractive layer, and The first nanopillar pattern extends through the first low-refractive layer.

2. The image sensor according to claim 1, further comprising: Multiple nanopillar patterns are horizontally spaced apart from each other in the first low-refractive layer, wherein the first nanopillar pattern is one of the multiple nanopillar patterns. The diameters of the nanopillar patterns among the plurality of nanopillar patterns are different from each other.

3. The image sensor according to claim 1, wherein, The first low-refractive layer comprises silicon oxide, and the first nanopillar pattern comprises titanium oxide.

4. The image sensor according to claim 1, wherein, The nanoprism also includes: A second low-refractive layer, on top of the first low-refractive layer; and The second nanopillar pattern is located in the second low-refractive layer.

5. The image sensor according to claim 1, wherein, The spacer layer comprises silicon oxide.

6. The image sensor according to claim 1, wherein, The thickness of the spacer layer is approximately 200 nm to approximately 1000 nm.

7. The image sensor according to claim 1, wherein, The second PD structure includes: First electrode; The second PD is located on the first electrode; and The second electrode is on the second PD.

8. The image sensor according to claim 7, wherein, The second PD includes an organic photodetector, and the organic photodetector is configured to absorb near-infrared (NIR) light.

9. The image sensor according to claim 7, wherein, The second PD includes a quantum dot (QD) photodetector, and the QD photodetector is configured to absorb short-wave infrared (SWIR) light.

10. The image sensor according to claim 7, further comprising: A through-hole structure extends through the substrate, the spacer layer, and the nanoprism, and the through-hole structure contacts the first electrode; Wiring structure, electrically connected to the through-hole structure; as well as A floating diffused FD region is present in the substrate and is electrically connected to the wiring structure.

11. The image sensor according to claim 1, further comprising: A color filter array layer is located between the substrate and the spacer layer.

12. An image sensor, comprising: In the substrate, the first photodetector PD is configured to absorb visible light; A second PD structure is configured on the substrate to absorb infrared light; as well as The nanoprism, on the second PD structure, comprises: Low-refractive layer, and Nanopillar patterns, in the low-refractive layer, are spaced apart from each other in the horizontal direction, and the diameters of the nanopillar patterns are different from each other.

13. The image sensor according to claim 12, wherein, The low-refractive layer comprises silicon oxide, and the nanopillar pattern comprises titanium oxide.

14. The image sensor according to claim 12, further comprising: A spacer layer, located between the second PD structure and the nanoprism, comprises silicon oxide.

15. The image sensor according to claim 12, further comprising: A spacer layer, comprising silicon oxide, is located between the substrate and the second PD structure.

16. The image sensor according to claim 12, wherein, The second PD structure includes: First electrode; The second PD is located on the first electrode; and The second electrode is on the second PD.

17. The image sensor according to claim 16, wherein, The second PD includes a quantum dot (QD) photodetector, and the QD photodetector is configured to absorb short-wave infrared (SWIR) light.

18. An image sensor, comprising: The first wiring structure and the second wiring structure are located below the substrate; A first floating diffusion (FD) region is located at the lower part of the substrate, and the first FD region is electrically connected to the first wiring structure. A first photodetector PD is configured to absorb visible light in the substrate; The second FD region is located at the lower part of the substrate and is electrically connected to the second wiring structure. A spacer layer on the substrate; Nanoprisms, on the spacer layer; A second PD structure is configured on the nanoprism to absorb infrared light; as well as A via structure extends through the substrate, the spacer layer, and the nanoprism, and the via structure is electrically connected to the second wiring structure and the second PD structure.

19. The image sensor according to claim 18, wherein, The nanoprism comprises: Low-refractive layer; and Nanopillar patterns, in the low-refractive layer, are spaced apart from each other in the horizontal direction, and the diameters of the nanopillar patterns are different from each other.

20. The image sensor according to claim 18, wherein, The second PD structure includes: First electrode; The second PD is located on the first electrode; and The second electrode is located on the second PD. The through-hole structure is electrically connected to the first electrode.

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