Preparation method and equipment of BC battery

Abstract

The invention relates to the field of BC batteries, in particular to a preparation method and equipment of a BC battery. The method comprises the following steps: S1, putting a silicon material and an antimony-containing doping source into a single crystal furnace for single crystal growth, and controlling the antimony concentration in a melt to be within a preset concentration in the growth process to obtain an antimony-doped single crystal rod; s2, processing the antimony-doped single crystal rod into a silicon wafer; s3, depositing a composite layer on the back surface of the silicon wafer, wherein the composite layer sequentially comprises a borosilicate glass layer, a phosphorosilicate glass layer and a Sb2O3 layer from the silicon wafer to the outside; s4, selectively irradiating a predetermined region on the back surface of the silicon wafer by adopting laser to enable antimony atoms in the Sb2O3 layer to be activated and diffused downwards to enter the silicon wafer so as to form an n-type heavily doped region; and S5, annealing the silicon wafer and forming a back passivation layer and an electrode. According to the method, the mass production efficiency of the BC battery is improved, the electric leakage rate is reduced, the thermal stability and compatibility of the passivation layer are improved, and the single-tile material and the manufacturing cost are remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of BC batteries, and more specifically, to a method and apparatus for preparing a BC battery. Background Technology

[0002] Traditional BC solar cells use POCl3 (phosphorus oxychloride) doping in the n-region on the back side. During high-temperature diffusion, phosphorus atoms easily penetrate the mask layer and diffuse into the p-region, causing "p-region compensation" and resulting in a net doping concentration decrease of more than 60%. At the same time, the high temperature (950-1000℃) required for phosphorus diffusion has poor thermal matching with the TOPCon passivation layer (tunneling oxide layer + polycrystalline silicon), which easily leads to passivation layer failure and minority carrier lifetime loss. Although antimony doping technology in the semiconductor field involves laser annealing, it relies on "ion implantation + high-temperature co-doping," which is a complex and costly process, making it unsuitable for photovoltaic mass production scenarios.

[0003] Antimony has a segregation coefficient of only 0.023 in silicon, but an evaporation coefficient as high as 7 × 10⁻⁶. -2 In the traditional RCZ (repeated Czochralski) process, the concentration of antimony in the melt is prone to fluctuations due to volatilization and segregation differences, resulting in a resistance difference exceeding 0.2Ω between the beginning and end of the crystal rod. Existing technologies only focus on the structural optimization of the "bell-jar type doping device" to solve the problem of antimony addition efficiency during the crystal pulling stage, but they have not achieved real-time closed-loop control of the antimony concentration in the melt, nor have they linked the antimony-doped single crystal with the subsequent BC battery doping process.

[0004] Existing laser doping equipment (such as Han's Laser LB-7528 series) is only optimized for single-process cell manufacturing (such as selective emitter doping) and is not linked to the single crystal pulling process; the single crystal furnace equipment is only responsible for ingot growth and cannot provide silicon wafers with "precise antimony concentration matching" for subsequent BC cell doping, which means that the advantages of antimony doping in improving the mechanical strength of silicon wafers and reducing stress distortion cannot be realized.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to solve the problems in the prior art, such as the difficulty in accurately controlling the concentration of antimony doping in single crystals, the serious p-region compensation and thermal damage in the traditional phosphorus doping process of BC batteries, and the low efficiency and high cost caused by the separation of front-end and back-end equipment. By providing an integrated device and method that integrates real-time control of antimony doping in single crystal furnaces and the self-masking laser doping process of BC batteries, the invention achieves precise control and seamless connection of the entire process from the preparation of high-quality antimony-doped single crystals to high-efficiency, selective battery doping, thereby improving the photoelectric conversion efficiency, stability and yield of BC batteries, while significantly reducing production costs and process complexity.

[0007] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: One aspect of the present invention relates to a method for preparing a BC battery, comprising the following steps: S1. Silicon material and antimony-containing doping source are put into a single crystal furnace for single crystal growth. During the growth process, the antimony concentration in the melt is controlled within a preset concentration to obtain an antimony-doped single crystal rod. S2. The antimony-doped single crystal rod is processed into a silicon wafer; S3. A composite layer is deposited on the back side of the silicon wafer, the composite layer comprising, from the silicon wafer outwards, a borosilicate glass layer, a phosphosilicate glass layer and an Sb2O3 layer; S4. Selectively irradiate a predetermined area on the back of the silicon wafer with a laser to activate antimony atoms in the Sb2O3 layer and diffuse them downward into the silicon wafer to form an n-type heavily doped region. S5. Anneal the silicon wafer to form a back passivation layer and electrodes.

[0008] The aforementioned preparation method, by combining real-time LIBS concentration monitoring with a self-masked laser doping process, successfully achieved highly uniform growth of antimony-doped single crystals and highly selective, low-temperature doping of the back side of BC solar cells. This method increases the mass production efficiency of BC solar cells to 27.2% and reduces the leakage rate to 0.8%. Furthermore, the use of antimony doping and low-temperature processing significantly improves the thermal stability and compatibility of the passivation layer. Simultaneously, this method reduces the number of steps by 30% by eliminating the external mask and simplifying the process flow, and reduces energy consumption by 20% due to the rapid thermal annealing process, resulting in a significant decrease in material and manufacturing costs per watt.

[0009] Another aspect of the present invention relates to an apparatus for preparing a BC battery, for carrying out the method for preparing the BC battery, comprising: The antimony-doped single crystal furnace control module is used to grow antimony-doped single crystal rods. It includes a raw material feeding unit, a volatilization suppression unit, and a real-time concentration monitoring unit. The BC cell self-mask doping module is used for selective doping of silicon wafers. It includes a chemical vapor deposition unit, a laser activation unit, and a passivation compatibility processing unit. The full-process connection unit is used to transfer silicon wafers between the antimony doping control module of the single crystal furnace and the self-masking doping module of the BC cell.

[0010] The equipment integrates antimony doping control in single-crystal furnaces, self-mask doping, and a complete process connection unit, achieving seamless integration and automated production from single-crystal growth to cell doping. This equipment reduces production line investment costs by 30% and, by minimizing wafer handling and manual intervention, reduces the microcrack rate from 5% to below 0.5%, increasing capacity to 5000 wafers / hour. Its modular design offers strong compatibility, adapting to various silicon wafer and cell technologies, and allows for production line transformation within two weeks, providing a reliable equipment foundation for the large-scale, low-cost mass production of BC cells.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves significant improvements in single-crystal quality by employing an integrated doping device and method: the minority carrier lifetime of antimony-doped silicon wafers reaches 1200 μs (compared to 800 μs for traditional undoped silicon wafers), the head-to-tail resistance difference of the crystal rod is reduced to 0.08 Ω (compared to 0.2 Ω in the traditional process), while the mechanical strength of the silicon wafer is enhanced, with a bending strength of 350 MPa (compared to 280 MPa in the traditional process), and the microcrack rate is reduced from 5% to below 0.5%. The prepared BC cells exhibit excellent performance, with a mass production efficiency of 27.2%, an improvement of 0.7 percentage points compared to the traditional phosphorus doping process (26.5%), a reduction in leakage rate to 0.8% (compared to 2.5% in the traditional process), and a significant improvement in passivation layer stability, with an efficiency decay rate of <2% after 1000 hours of damp heat testing (compared to 3.5% in the traditional process). In terms of cost-effectiveness, the investment for a single integrated production line is 12 million yuan, a 30% reduction compared to the traditional independent equipment solution (17 million yuan). Due to the elimination of the external mask, the material cost per watt is reduced by 0.015 yuan. The rapid thermal annealing time is shortened to 20 seconds (compared to 60 seconds for traditional phosphorus diffusion), reducing energy consumption per watt by 20%, and the manufacturing cost per watt is 0.02 yuan lower than TOPCon technology. Furthermore, this technology is highly compatible, adaptable to P-type / N-type monocrystalline silicon wafers and passivated contact structures such as TOPCon and HJT, requiring no large-scale production line modifications with a modification cycle of ≤2 weeks. The process is simplified, eliminating the external mask step, reducing process steps by 30%, and achieving a production line cycle time of ≤8 seconds per wafer, with a capacity of 5000 wafers per hour, fully meeting the needs of large-scale mass production. Attached Figure Description

[0012] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 An overall framework diagram of the apparatus for preparing BC batteries provided by the present invention; Figure 2 This is a schematic diagram showing the laser activation process before and after the present invention. Figure 3 A cross-sectional comparison of ECV test results before and after laser activation of the antimony-doped layer provided by this invention. Detailed Implementation

[0014] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0015] One aspect of the present invention relates to a method for preparing a BC battery, comprising the following steps: S1. Silicon material and antimony-containing doping source are put into a single crystal furnace for single crystal growth. During the growth process, the antimony concentration in the melt is controlled within a preset concentration to obtain an antimony-doped single crystal rod. S2. The antimony-doped single crystal rod is processed into a silicon wafer; S3. A composite layer is deposited on the back side of the silicon wafer, the composite layer comprising, from the silicon wafer outwards, a borosilicate glass layer, a phosphosilicate glass layer and an Sb2O3 layer; S4. Selectively irradiate a predetermined area on the back side of the silicon wafer with a laser, activating antimony atoms in the Sb₂O₃ layer and causing them to diffuse downwards into the silicon wafer to form an n-type heavily doped region, such as... Figure 2 As shown; S5. Anneal the silicon wafer to form a back passivation layer and electrodes.

[0016] The aforementioned method for fabricating BC cells avoids the p-region compensation problem of traditional phosphorus doping by depositing a composite layer on a silicon wafer and using laser-guided zoning activation, thereby increasing the net doping concentration in the n-region to 1×10⁻⁶. 20 / cm 3 The passivation layer interface state density is reduced by 80%.

[0017] Furthermore, the preset concentration is 1×10⁻⁶. 18 ~5×10 18 / cm 3 , including but not limited to 1×10 18 / cm 3 2×10 18 / cm 3 3×10 18 / cm 3 4×10 18 / cm 3 Or 5×10 18 / cm 3 The point value of any one of them or the range value between any two.

[0018] Further, the annealing treatment temperature is 800~900℃ (e.g., it can be any one of 800℃, 810℃, 820℃, 830℃, 840℃, 850℃, 860℃, 870℃, 880℃, 890℃, or 900℃, or a range between any two), the time is 15~25s (e.g., it can be any one of 15s, 17s, 19s, 21s, 23s, or 25s, or a range between any two), and the heating rate is 95~105℃ / s (e.g., it can be any one of 95℃ / s, 97℃ / s, 99℃ / s, 101℃ / s, 103℃ / s, or 105℃ / s, or a range between any two). The temperature accuracy is controlled within ±2℃, and the time accuracy is controlled within ±1s.

[0019] To match the thermal stress tolerance of the silicon wafer, a thickness of 160~180μm (belonging to the category of thin silicon wafers) is used. If the heating rate exceeds 105℃ / s, a large temperature difference will instantly form between the surface and the interior of the silicon wafer, and the thermal stress will increase sharply. This will directly increase the risk of microcracks and warping of the silicon wafer (in previous production line tests, the microcrack rate rose to more than 2% at a rate of 110℃ / s). If the rate is below 95℃ / s, although the temperature difference is small, the duration of thermal stress will be prolonged, which may also lead to an increase in micro-lattice defects in the silicon wafer and affect the minority carrier lifetime (tests show that the minority carrier lifetime drops below 1000μs at a rate of 80℃ / s).

[0020] The core objective of annealing is to "stabilize the antimony-doped region and create a dense passivation layer." A annealing rate of 95~105℃ / s allows the silicon wafer to rapidly reach the annealing temperature of 800~900℃ in a short time. This avoids premature disordered diffusion of antimony atoms during the heating phase (preventing uneven doping concentration in the n-region) and allows the Al2O3 / SiO2 passivation layer to form and densify rapidly at high temperatures. At this rate, the interface state density of the passivation layer can be stably controlled at ≤1×10⁻⁶. 11 / cm 2 (If the rate deviates, the interface state density will fluctuate to 1.5 × 10⁻⁶) 11 / cm 2 above).

[0021] The production line has a capacity of 5,000 pieces / hour, and the heating rate of 95~105℃ / s is highly matched with the annealing time of 15~25s, which can ensure that the total time for the annealing of a single piece is controlled within a reasonable range (without slowing down the overall process cycle). At the same time, this rate is the stable output range of the existing annealing equipment (Rapid Thermal Annealing (RTA) module), and with the equipment's temperature accuracy of ±2℃ and time accuracy of ±1s, the performance consistency of batch products can be achieved (leakage rate fluctuation within batch ≤0.1%).

[0022] Furthermore, the thickness of the borosilicate glass layer is 30~50nm, including but not limited to a point value of any one of 30nm, 35nm, 40nm, 45nm or 50nm or a range between any two.

[0023] Furthermore, the thickness of the phosphosilicate glass layer is 20~30nm, including but not limited to a point value of any one of 20nm, 23nm, 25nm, 28nm or 30nm or a range between any two.

[0024] Furthermore, the thickness of the Sb2O3 layer is 50~120nm, including but not limited to a point value or a range between any two of 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm or 120nm.

[0025] Furthermore, the thickness of the composite layer is 100~200nm, including but not limited to a point value or a range between any two of 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, or 200nm. The thickness error of the composite layer is controlled within ±5nm.

[0026] Furthermore, the thickness of the silicon wafer is 160~180μm, including but not limited to a point value of any one of 160μm, 165μm, 170μm, 175μm or 180μm or a range between any two.

[0027] Furthermore, the content of Sb2O3 in the composite layer is 5wt%~12wt%, including but not limited to any one of 5wt%, 6wt%, 7wt%, 8wt%, 9wt%, 10wt%, 11wt% or 12wt% or any range between two of them.

[0028] Furthermore, the wavelength of the laser is 530~535nm (for example, it can be a point value or a range between any one of 530nm, 531nm, 532nm, 533nm, 534nm or 535nm, for example, but not limited to), and the energy density is 8-12J / cm². 2 (For example, it can be, but is not limited to, 8J / cm) 2 9J / cm 2 10J / cm 2 11J / cm 2 Or 12J / cm 2The scanning speed is 400~600mm / s (for example, it can be any one of 400mm / s, 430mm / s, 450mm / s, 480mm / s, 500mm / s, 530mm / s, 550mm / s, 580mm / s or 600mm / s or any one of 400mm / s or any one of 6 ... The wavelength of 530~535nm is specifically adapted to the light absorption characteristics of the Sb2O3 layer, ensuring that the laser energy is precisely applied to the Sb2O3 layer and avoiding excessive energy penetration that could damage the silicon wafer. The scanning speed of 400~600mm / s, combined with the production line's capacity cycle design of 5000 wafers / hour, can match the overall production efficiency while ensuring activation effect.

[0029] Furthermore, the interface state density of the back passivation layer is ≤1×10⁻⁶. 11 / cm 2 .

[0030] Furthermore, the back passivation layer comprises, from the silicon wafer outwards, an Al2O3 layer and a SiO2 layer.

[0031] Furthermore, the thickness of the Al2O3 layer is 10~20nm, including but not limited to a point value of any one of 10nm, 12nm, 14nm, 16nm, 18nm or 20nm or a range between any two.

[0032] Furthermore, the thickness of the SiO2 layer is 5~10nm, including but not limited to a point value of any one of 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, or a range between any two. The film thickness error is controlled within ±0.5nm.

[0033] Furthermore, the back passivation layer is subjected to Ar plasma treatment at a power of 300W for 60s to improve the adhesion between the film and the antimony-doped region.

[0034] Furthermore, during the single crystal growth, the pulling speed during the constant diameter growth stage is controlled to be 0.8~1.2 mm / min, including but not limited to any one of 0.8 mm / min, 0.9 mm / min, 1.0 mm / min, 1.1 mm / min, or 1.2 mm / min, or a range between any two. The pulling speed accuracy is controlled to ±0.05 mm / min.

[0035] Furthermore, the junction depth of the n-type heavily doped region is 50~200nm, including but not limited to a point value or a range between any two of 50nm, 80nm, 100nm, 130nm, 150nm, 180nm or 200nm.

[0036] Furthermore, the temperature of the melt is 1410~1420℃, including but not limited to a point value or a range between any two of 1410℃, 1412℃, 1414℃, 1416℃, 1418℃, or 1420℃. The temperature accuracy is controlled to ±1℃.

[0037] Furthermore, within an atmospheric pressure chemical vapor deposition chamber, the composite layer is deposited on the back side of a silicon wafer using SbCl3 (antimony trichloride) and SiH4 (silane) as precursors.

[0038] Furthermore, the flow rate of SbCl3 is 3~7 sccm (for example, it can be a point value or a range between any two of 3 sccm, 4 sccm, 5 sccm, 6 sccm or 7 sccm, for example, it can be a point value or a range between any two of 18 sccm, 19 sccm, 20 sccm, 21 sccm or 22 sccm, for example, it can be a point value or a range between any two of 18 sccm, 19 sccm, 20 sccm, 21 sccm or 22 sccm).

[0039] SbCl3 is the antimony source precursor for the Sb2O3 layer in the composite layer. This flow rate range allows for precise control of the Sb content in the Sb2O3 layer (5wt%~12wt%). When the flow rate is below 3sccm, the Sb source supply is insufficient, resulting in an Sb content in the Sb2O3 layer below 5wt%. Consequently, the diffusion of antimony atoms after laser activation is insufficient, and the concentration of the n-type heavily doped region cannot reach ≥1×10⁻⁶. 20 / cm 3 The requirements are as follows: when the flow rate is higher than 7 sccm, excessive Sb source will cause Sb elements in the Sb2O3 layer to agglomerate, which will increase the defects in the composite layer and also increase the carrier recombination rate on the back of the silicon wafer; the specific point values ​​within the range (such as 3 sccm, 5 sccm) are to adapt to the different thicknesses (50~120nm) of the Sb2O3 layer - thicker layers correspond to slightly higher flow rates, and thinner layers correspond to slightly lower flow rates, to ensure that the Sb content is stable within the target range.

[0040] SiH4 is the silicon source precursor for the borosilicate glass layer and the phosphosilicate glass layer in the composite layer. The flow rate of 18~22 sccm is to ensure the film quality and interlayer bonding of the composite layer: when the flow rate is below 18 sccm, the silicon source supply is insufficient, the film density of the borosilicate / phosphosilicate glass layer is low, and porosity is prone to appear between the layers, increasing the risk of moisture intrusion during subsequent annealing; when the flow rate is above 22 sccm, the excessive silicon source will cause the glass layer to grow too fast, and the layer thickness is likely to exceed the target range of 30~50nm (borosilicate) and 20~30nm (phosphosilicate), while increasing the stress within the layer; the specific point values ​​within the range (such as 18 sccm, 20 sccm) are coordinated with the flow rate of SbCl3 - when the flow rate of SbCl3 is adjusted, the flow rate of SiH4 is finely adjusted simultaneously to ensure that the growth rate of each sublayer of the composite layer is matched and to avoid interface peeling.

[0041] Meanwhile, this flow rate range is compatible with the process window of APCVD equipment, can match a production line cycle of 5000 pieces / hour, and the thickness deviation of the composite layer within a batch can be controlled within ±2nm.

[0042] Furthermore, the method for preparing the BC battery also includes: Step S6: Sintering at a temperature of 840~860℃, including but not limited to any one of 840℃, 845℃, 850℃, 855℃ or 860℃ or any range between two of them.

[0043] This temperature range is the optimal window for forming a stable ohmic contact between the electrode paste (such as silver-based conductive paste) and the heavily n-type doped region on the back of the silicon wafer: temperatures above 840℃ allow the metal particles in the paste to fully melt and diffuse, and the contact resistance can be controlled to ≤2mΩ. cm 2 (The contact resistance will rise to 5mΩ below 840℃) cm 2 (Above); the temperature should not exceed 860℃ to avoid overheating and melting at the electrode edge, while ensuring the adhesion between the electrode and the passivation layer (peel force ≥ 5N, peel force will drop to below 3N when the temperature is above 860℃).

[0044] The Al2O3+SiO2 passivation layer formed by the preceding annealing does not undergo structural degradation at temperatures ranging from 840 to 860°C; within this range, the interface state density of the passivation layer remains ≤1×10⁻⁶. 11 / cm 2 If the temperature is too high (e.g., 870℃), the passivation layer will thermally decompose, leading to an increase in the carrier recombination rate on the back of the silicon wafer; if the temperature is too low, the interfacial bonding between the passivation layer and the electrode cannot be strengthened, and there is a risk of moisture intrusion.

[0045] The sintering time corresponding to this temperature range (10~15s) can match the production line's capacity cycle of 5000 pieces / hour, ensuring smooth transition with the time consumption of previous steps and not affecting the overall process efficiency; specific point values ​​such as 840℃ and 850℃ are adapted to different types of electrode pastes (such as low silver paste and conventional silver paste) - the sintering activity temperature of different pastes varies slightly, and these point values ​​can cover the optimal window of mainstream pastes, ensuring the consistency of electrode performance within batches (leakage rate fluctuation within batches ≤0.1%).

[0046] Another aspect of the invention also relates to an apparatus for manufacturing BC batteries, such as... Figure 1 As shown, the method for preparing the BC battery includes: The antimony-doped single crystal furnace control module is used to grow antimony-doped single crystal rods. It includes a raw material feeding unit, a volatilization suppression unit, and a real-time concentration monitoring unit. The BC cell self-mask doping module is used for selective doping of silicon wafers. It includes a chemical vapor deposition unit, a laser activation unit, and a passivation compatibility processing unit. The full-process connection unit is used to transfer silicon wafers between the antimony doping control module of the single crystal furnace and the self-masking doping module of the BC cell.

[0047] The device combines LIBS online monitoring of monocrystalline silicon pulling with antimony-based doping of BC cells, achieving full-chain control of "melt concentration - silicon wafer doping - cell performance", reducing the resistance difference between the head and tail of the crystal rod to below 0.08Ω, which is 60% better than the traditional process.

[0048] The equipment described above achieves seamless integration of "monocrystalline crystal pulling - BC cell doping", eliminating the intermediate silicon wafer transfer link in the traditional production line, reducing the risk of silicon wafer microcracks, and at the same time, the equipment investment cost is reduced by 30% compared with "independent monocrystalline furnace + independent doping equipment".

[0049] Furthermore, the raw material feeding unit includes a silicon material feeding unit and an antimony source feeding unit.

[0050] The silicon material feeding unit is responsible for feeding silicon material into the single crystal furnace, while the antimony source feeding unit is responsible for feeding antimony source into the single crystal furnace. The separate design of the silicon material feeding unit and the antimony source feeding unit uses a high-precision weighing sensor (accuracy of 0.01g) to control the feeding ratio of the two materials, avoiding contamination caused by the direct addition of antimony powder.

[0051] Furthermore, the volatilization suppression unit can reduce the antimony evaporation rate by about 40%. The volatilization suppression unit has a built-in graphite guide hood coated with SiC (silicon carbide), which, together with dynamic furnace pressure adjustment (5-20 torr) and argon flow gradient control (70-100 slpm), reduces the adhesion loss of antimony vapor on the furnace wall.

[0052] Furthermore, the real-time concentration monitoring unit can be a LIBS online monitoring unit, with a LIBS detection accuracy of ±5×10⁻⁶. 17 / cm 3 The laser energy is 100 mJ, and the detection frequency is 1 time / 5s. The laser-induced breakdown spectroscopy probe is installed above the surface of the melt in the single crystal furnace to collect the characteristic spectrum of antimony (wavelength 259.8 nm) in real time. The data is fed back to the PLC control system to dynamically adjust the amount of antimony alloy preform added.

[0053] Furthermore, the chemical vapor deposition unit includes: an APCVD antimony source pre-deposition component; in the atmospheric pressure chemical vapor deposition unit, using antimony trichloride and silane as precursors, a "Sb2O3-PSG (phosphosilicate glass) / BSG (borosilicate glass)" composite layer is deposited on the back of the silicon wafer at a temperature of 450°C.

[0054] Furthermore, the laser activation unit includes: a laser, which uses a galvanometer scanning system to irradiate only the n-region on the back of the BC battery, activating antimony atoms in Sb2O3 to diffuse to the silicon wafer; the p-region is blocked from antimony diffusion by a BSG layer, eliminating the need for an external mask.

[0055] Furthermore, the passivation-compatible processing unit is used to form the back passivation layer, including: ALD deposition unit and PECVD deposition unit.

[0056] Furthermore, the chemical vapor deposition unit, laser activation unit, ALD deposition unit, and PECVD deposition unit are connected by conveyor belts. The ALD deposition unit is used to deposit an Al2O3 layer, and the PECVD deposition unit is used to deposit a SiO2 layer.

[0057] Furthermore, the entire process integration unit includes a six-axis robotic arm and a silicon wafer stress detection module. The transfer cycle time is ≤8s / wafer, and the stress detection accuracy is ±0.5Mpa.

[0058] The embodiments of the present invention will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0059] Example 1 The apparatus for preparing BC batteries provided in this embodiment includes: The antimony-doped single crystal furnace control module is used to grow antimony-doped single crystal rods. It includes a raw material feeding unit, a volatilization suppression unit, and a real-time concentration monitoring unit. The BC cell self-mask doping module is used for selective doping of silicon wafers. It includes a chemical vapor deposition unit, a laser activation unit, and a passivation compatibility processing unit. The end-to-end connection unit is used to transfer silicon wafers between the antimony doping control module of the single crystal furnace and the self-masking doping module of the BC cell.

[0060] The raw material feeding unit includes a silicon material feeding unit and an antimony source feeding unit.

[0061] The volatilization suppression unit has a built-in graphite guide hood coated with SiC (silicon carbide), which, together with dynamic furnace pressure adjustment and argon flow gradient control, reduces the adhesion loss of antimony vapor on the furnace wall. The real-time concentration monitoring unit can adopt a LIBS online monitoring unit, with a LIBS detection accuracy of ±5×10⁻⁶. 17 / cm 3 The laser energy is 100mJ, and the detection frequency is 1 time / 5s. The laser-induced breakdown spectroscopy probe is installed above the surface of the melt in the single crystal furnace to collect the characteristic spectrum of antimony element (wavelength 259.8nm) in real time. The data is fed back to the PLC control system to dynamically adjust the amount of antimony alloy preform added. The passivation-compatible processing unit is used to form the back passivation layer, including: ALD deposition unit and PECVD deposition unit; The chemical vapor deposition unit, laser activation unit, ALD deposition unit, and PECVD deposition unit are connected by conveyor belts; The entire process connection unit includes: a six-axis robotic arm and a silicon wafer stress detection module; the transfer cycle time is ≤8s / wafer, and the stress detection accuracy is ±0.5Mpa.

[0062] Example 2 The method for preparing the BC battery provided in this embodiment uses the equipment provided in Example 1 and includes the following steps: S1. The silicon material from the silicon material feeding unit and the antimony-doped source from the antimony source feeding unit are fed into the single crystal furnace for single crystal growth. The volatilization suppression unit reduces the loss of antimony vapor. During the growth process, the antimony concentration in the melt is monitored by the concentration real-time monitoring unit and controlled at 1×10⁻⁶. 18 ~5×10 18 / cm 3 Inside, an antimony-doped single crystal rod was obtained; S2. The antimony-doped single crystal rod is processed into a silicon wafer, and the silicon wafer is transferred to the BC cell self-mask doping module through the full-process connection unit. S3. In the chemical vapor deposition unit, a composite layer is deposited on the back side of the silicon wafer. The composite layer, from the silicon wafer outwards, includes: a borosilicate glass layer, a phosphosilicate glass layer, and an Sb₂O₃ layer; the thickness of the borosilicate glass layer is 40 nm; the thickness of the phosphosilicate glass layer is 25 nm; the thickness of the Sb₂O₃ layer is 80 nm; and the content of Sb₂O₃ in the composite layer is 10 wt%. S4. The laser activation unit provides a laser and selectively irradiates a predetermined area on the back of the silicon wafer, activating antimony atoms in the Sb₂O₃ layer and causing them to diffuse downwards into the silicon wafer to form an n-type heavily doped region; the laser wavelength is 532 nm and the energy density is 10 J / cm². 2 The scanning speed is 500 mm / s; S5. Anneal the silicon wafer in the passivation compatibility processing unit to form a back passivation layer and electrodes. The annealing temperature is 850℃ and the time is 20s.

[0063] Example 3 The method for preparing the BC battery provided in this embodiment uses the equipment provided in Example 1 and includes the following steps: S1, Same as Example 2; S2, Same as Example 2; S3. In the chemical vapor deposition unit, a composite layer is deposited on the back side of the silicon wafer. The composite layer, from the silicon wafer outwards, includes: a borosilicate glass layer, a phosphosilicate glass layer, and an Sb₂O₃ layer; the thickness of the borosilicate glass layer is 30 nm; the thickness of the phosphosilicate glass layer is 20 nm; the thickness of the Sb₂O₃ layer is 50 nm; and the content of Sb₂O₃ in the composite layer is 5 wt%. S4. The laser activation unit provides a laser and selectively irradiates a predetermined area on the back of the silicon wafer, activating antimony atoms in the Sb₂O₃ layer and causing them to diffuse downwards into the silicon wafer to form an n-type heavily doped region; the laser wavelength is 530 nm and the energy density is 8 J / cm². 2 The scanning speed is 400 mm / s; S5. Anneal the silicon wafer in the passivation compatibility processing unit to form a back passivation layer and electrodes. The annealing temperature is 800℃ and the time is 15s.

[0064] Example 4 The method for preparing the BC battery provided in this embodiment uses the equipment provided in Example 1 and includes the following steps: S1, Same as Example 2; S2, Same as Example 2; S3. In the chemical vapor deposition unit, a composite layer is deposited on the back side of the silicon wafer. The composite layer, from the silicon wafer outwards, includes: a borosilicate glass layer, a phosphosilicate glass layer, and an Sb₂O₃ layer; the thickness of the borosilicate glass layer is 50 nm; the thickness of the phosphosilicate glass layer is 30 nm; the thickness of the Sb₂O₃ layer is 120 nm; the content of Sb₂O₃ in the composite layer is 12 wt%. S4. The laser activation unit provides a laser and selectively irradiates a predetermined area on the back of the silicon wafer, activating antimony atoms in the Sb₂O₃ layer and causing them to diffuse downwards into the silicon wafer to form an n-type heavily doped region; the laser wavelength is 535 nm and the energy density is 12 J / cm². 2 The scanning speed is 600 mm / s; S5. Anneal the silicon wafer in the passivation compatibility processing unit to form a back passivation layer and electrodes. The annealing temperature is 900℃ and the time is 25s.

[0065] Comparative Example 1 This comparative example uses the traditional RCZ (repeated Czochralski) process to grow antimony-doped single crystals. Silicon and antimony powder are directly mixed and fed into the single crystal furnace without online concentration monitoring, dynamic feeding, or a dedicated volatilization suppression system. The resulting silicon wafer is then subjected to high-temperature (980℃) diffusion of POCl3 in a conventional tube furnace to form an n-type region. A patterned mask using photoresist is used to define the back p / n region, followed by the deposition of a SiNx passivation layer and the fabrication of electrodes.

[0066] Comparative Example 2 This comparative example uses step S1 and the equipment of Example 2 to grow an antimony-doped single crystal rod and cut it into silicon wafers. Subsequent doping does not employ the self-masking process of this invention, but instead uses the traditional POCl3 high-temperature diffusion and external photoresist masking process of Comparative Example 1.

[0067] Comparative Example 3 This comparative example uses commercially available, conventional boron-doped (P-type) or phosphorus-doped (N-type) single-crystal silicon wafers, which are not antimony-doped single crystals grown using the method of this invention. Subsequent steps follow steps S3-S5 of Example 2 and use the corresponding equipment, namely, depositing the same BSG / PSG / Sb2O3 composite layer and performing laser selective activation and low-temperature annealing.

[0068] Comparative Example 4 In this comparative example, steps S1 and S2 are the same as in Example 2. In step S3, only a pure Sb2O3 layer (thickness ~80nm) is deposited on the back side of the silicon wafer, omitting the underlying BSG and PSG layers. Then, the same laser selective irradiation (S4) and annealing (S5) are performed.

[0069] Experimental Example The performance of the antimony-doped single crystal rods and BC batteries prepared in each embodiment and comparative example was tested. The specific testing methods and reference standards for the performance of antimony-doped single crystal rods and BC batteries are described below: I. Performance Testing Methods and Reference Standards for Antimony-Doped Single Crystal Rods Low birth rate lifespan test Test method: Microwave photoconductive decay method (μ-PCD) is used. Non-equilibrium carriers are generated by laser excitation of silicon wafer, and the carrier decay process is detected by microwave to calculate minority carrier lifetime.

[0070] Reference standard: Microwave photoconductivity attenuation method for testing minority carrier lifetime of photovoltaic silicon materials (GB / T35308-2017).

[0071] Crystal rod head-to-tail resistance difference test Test method: The four-probe method is used to take silicon wafer samples from the head, middle and tail of the crystal rod, and test the resistivity of each sample. The resistivity difference between the head and tail is calculated (the resistance difference is converted from the resistivity difference and the silicon wafer size).

[0072] Reference standard: Determination of resistivity of single crystal silicon using the four-probe method (GB / T1551-2022).

[0073] Bending strength test Test method: The three-point bending test method is adopted. The silicon wafer sample is placed on a two-point support platform, and a force is applied through the middle loading head until the sample breaks. The bending strength is then calculated.

[0074] Reference standard: Test method for bending strength of fine ceramics (GB / T6569-2006, applicable to the bending performance test of brittle materials such as silicon wafers).

[0075] II. Performance Testing Methods and Reference Standards for BC Batteries Mass production conversion efficiency test Test method: The solar simulator test method was used to test the IV curve of the battery under standard test conditions (AM1.5G, 1000W / m², 25℃) and calculate the conversion efficiency.

[0076] Reference standard: Photovoltaic devices - Part 1: Measurement of photovoltaic current-voltage characteristics (IEC 60904-1:2021).

[0077] Leakage rate test Test method: The reverse leakage current of the battery is tested under reverse bias (usually -1V) by using the IV curve reverse characteristic test, and the ratio of leakage current to forward operating current (i.e. leakage rate) is calculated.

[0078] Reference standard: Photovoltaic devices - Part 10: Measurement of linearity characteristics (IEC 60904-10:2019).

[0079] 1000h damp heat test attenuation rate test Test method: The accelerated aging test method was adopted. The battery was placed in a humid and hot environment chamber (85℃, 85%RH) for 1000 hours to test the conversion efficiency before and after aging and calculate the degradation rate.

[0080] Reference standard: Ground-mounted crystalline silicon photovoltaic modules - Part 2: Test requirements (IEC 61215-2:2021).

[0081] n-region net doping concentration test Test method: Secondary ion mass spectrometry (SIMS) was used. The surface of the n-region of the battery was bombarded with an ion beam, and the intensity of the antimony ion signal was detected. The doping concentration was then calculated.

[0082] Reference standard: Determination of impurity content in silicon by secondary ion mass spectrometry (GB / T26060-2010).

[0083] The results are shown in Table 1. Table 1

[0084] Figure 3 shows a cross-sectional comparison of ECV test results before and after laser activation of the antimony-doped layer. The difference in the curves reflects the effect of laser activation on increasing the diffusion depth and concentration of Sb atoms.

[0085] This invention achieves higher doping concentration and better uniformity, avoiding p-region compensation. Through "laser-selective activated Sb atom diffusion + real-time closed-loop control of antimony concentration in single-crystal furnace melt," this invention achieves precise enhancement of n-region doping concentration and stable control of diffusion depth; while traditional phosphorus doping is limited by segregation effects and diffusion process uniformity, resulting in weaker concentration and uniformity compared to this invention.

[0086] Although the present invention has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, without departing from the spirit and scope of the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a BC battery, characterized in that, Includes the following steps: S1. Silicon material and antimony-containing doping source are put into a single crystal furnace for single crystal growth. During the growth process, the antimony concentration in the melt is controlled within a preset concentration to obtain an antimony-doped single crystal rod. S2. The antimony-doped single crystal rod is processed into a silicon wafer; S3. A composite layer is deposited on the back side of the silicon wafer, the composite layer comprising, from the silicon wafer outwards, a borosilicate glass layer, a phosphosilicate glass layer and an Sb2O3 layer; S4. Selectively irradiate a predetermined area on the back of the silicon wafer with a laser to activate antimony atoms in the Sb2O3 layer and diffuse them downward into the silicon wafer to form an n-type heavily doped region. S5. Anneal the silicon wafer to form a back passivation layer and electrodes.

2. The method for preparing a BC battery according to claim 1, characterized in that, The laser has a wavelength of 530~535nm and an energy density of 8-12J / cm². 2 The scanning speed is 400~600mm / s.

3. The method for preparing a BC battery according to claim 1, characterized in that, The thickness of the borosilicate glass layer is 30~50nm.

4. The method for preparing a BC battery according to claim 1, characterized in that, The thickness of the phosphosilicate glass layer is 20~30nm.

5. The method for preparing a BC battery according to claim 1, characterized in that, The thickness of the Sb2O3 layer is 50~120nm.

6. The method for preparing a BC battery according to claim 1, characterized in that, The content of Sb2O3 in the composite layer is 5wt%~12wt%.

7. The method for preparing a BC battery according to claim 1, characterized in that, The preset concentration is 1×10 18 ~5×10 18 / cm 3 .

8. The method for preparing a BC battery according to claim 1, characterized in that, The annealing process is performed at a temperature of 800-900℃ for 15-25 seconds.

9. An apparatus for preparing a BC battery, used to implement the method for preparing a BC battery according to any one of claims 1 to 8, characterized in that, include: The antimony-doped single crystal furnace control module is used to grow antimony-doped single crystal rods. It includes a raw material feeding unit, a volatilization suppression unit, and a real-time concentration monitoring unit. The BC cell self-mask doping module is used for selective doping of silicon wafers. It includes a chemical vapor deposition unit, a laser activation unit, and a passivation compatibility processing unit. The full-process connection unit is used to transfer silicon wafers between the antimony doping control module of the single crystal furnace and the self-masking doping module of the BC cell.

10. The apparatus for preparing BC batteries according to claim 9, characterized in that, The raw material feeding unit includes a silicon material feeding unit and an antimony source feeding unit.

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