Technological method for improving uniformity and appearance of LED chip based on ICP multi-section etching
By using a multi-stage etching process and independently controlling the power of the upper and lower electrodes, the problems of etching uniformity and surface defects in the ICP etching process were solved, thereby improving the uniformity and appearance of LED chips and enhancing product quality and consistency.
CN121751831APending Publication Date: 2026-03-27JUCAN PHOTOELECTRIC TECH (SUQIAN) CO LTD
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Patent Information
- Application Number
- CN202511978117.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-03-27
AI Technical Summary
Technical Problem
Existing ICP etching processes in LED chip manufacturing suffer from poor etching uniformity, surface defects (black spots) after etching, and limited process adaptability, which affect chip performance and appearance.
Method used
A multi-stage etching process is adopted, in which the upper electrode power and lower electrode power are independently controlled at different etching stages to optimize etching parameters in stages, thereby improving etching uniformity and surface quality.
Benefits of technology
It significantly improves etching uniformity, eliminates black spots after etching, enhances the consistency and yield of LED chip photoelectric parameters, and improves the flexibility and adaptability of the process.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a technological method for improving uniformity and appearance of an LED chip based on ICP multi-stage etching, which comprises the following steps: placing an LED epitaxial wafer to be etched in an ICP reaction chamber, and introducing etching gas; plasma is started, at least two etching stages are executed in sequence, the set values of the upper electrode power and / or the lower electrode power of the at least two etching stages are different, and all the etching stages are switched according to the preset etching depth or time; and after the etching reaches the target total depth, the process is stopped. And the plasma density and the ion bombardment energy are effectively balanced through the optimized parameters in the second stage, so that the consistency of the etching rates in the wafers and between the wafers is greatly improved. The data of the embodiment shows that the inter-disk uniformity can be optimized to be within 4.80% from 4.50% of a traditional method.
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