Miniature light emitting diode and display panel

Abstract

The invention provides a miniature light-emitting diode chip. The miniature light-emitting diode chip comprises a light-emitting mesa; the passivation layer at least partially covers the side surface of the light-emitting mesa; the top electrode layer is positioned on the passivation layer between the micro light-emitting diodes, and the top electrode layer surrounds the micro light-emitting diodes; the top conducting layer is located on the side face and the top face of the light-emitting mesa and electrically connected with the top electrode layer, and the passivation layer is located between the light-emitting mesa and the top conducting layer. The top electrode layer is arranged between the passivation layer and the top conductive layer, the lower bottom of the top electrode layer sinks, meanwhile, the bottom of the inner wall of the reflection cup moves downwards, and small-angle light is reflected by the inner wall of the top electrode layer to be utilized, so that the light emitting efficiency is improved, upward reflection of the light in the small angle is achieved, and the light emitting efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of light emitting diodes, and more particularly to a micro light emitting diode and a display panel. BACKGROUND

[0002] Micro Light Emitting Diode (Micro LED) technology is a high-pixel-density LED planar display technology that uses micron-scale LEDs as pixel elements and assembles them on a control backplane in micron-scale periods. The core structure of a micro light emitting diode is a PN junction diode, which is composed of a direct bandgap semiconductor material. When the upper and lower electrodes of the micro light emitting diode are applied with a forward bias so that current passes through, electrons and holes recombine in the active region, and single-color light photons are emitted.

[0003] Compared with traditional LEDs, Micro LEDs have better strain relaxation, better light extraction efficiency, uniform current diffusion, and higher output performance. Micro LEDs also have improved thermal effects, faster response speed, a larger operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and higher current density. Micro light emitting diodes are hailed as the next generation of display technology and are gaining increasing attention.

[0004] However, existing micro light emitting diode chips still have many problems, such as low wall-plug efficiency (WPE, also known as electrical-to-optical conversion efficiency), which needs to be further improved. SUMMARY

[0005] To address some or all of the problems in the prior art, the present application provides a micro light emitting diode chip, comprising:

[0006] a light emitting mesa;

[0007] a passivation layer at least partially covering the side surface of the light emitting mesa;

[0008] a top electrode layer located on the passivation layer between the micro light emitting diodes, the top electrode layer surrounding the micro light emitting diodes; and

[0009] a top conductive layer located on the side surface and top surface of the light emitting mesa and electrically connected to the top electrode layer, wherein the passivation layer is located between the light emitting mesa and the top conductive layer.

[0010] By arranging the top electrode layer between the passivation layer and the top conductive layer, the lower bottom of the top electrode layer sinks, and the inner wall bottom of the reflection cup moves down. Light at a small angle is reflected by the inner wall of the top electrode layer and utilized, thereby improving the light extraction efficiency and achieving upward reflection of light at a small angle to improve the light extraction efficiency.

[0011] In one embodiment, the passivation layer has an opening on the top surface of the light emitting mesa, and the top conductive layer is electrically connected to the top of the light emitting mesa through the opening.

[0012] In one embodiment, the adjacent passivation layers are connected, and all the passivation layers are connected as a whole.

[0013] The material of the passivation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0014] In one embodiment, the micro light emitting diode chip further comprises an ohmic contact layer located at the bottom of the light emitting mesa.

[0015] In one embodiment, the top conductive layer covers the top electrode layer, and the bottom of the top electrode layer is in contact with the passivation layer.

[0016] In one embodiment, the bottoms of the adjacent top electrode layers are connected, and all the top electrode layers are connected as a whole.

[0017] In one embodiment, the top electrode layer has a first sidewall facing the light emitting mesa; the first sidewall is in contact with the passivation layer only at the bottom end, and the first sidewall has a first inclined surface.

[0018] In one embodiment, the top electrode layer is in contact with the top conductive layer only at the bottom of the first sidewall.

[0019] Another task of the present application is to provide a micro light emitting diode chip comprising:

[0020] a light emitting mesa;

[0021] a top conductive layer located on the side surface and the top surface of the light emitting mesa; and

[0022] a passivation layer covering the side surface and at least part of the top surface of the light emitting mesa, and the passivation layer is located between the light emitting mesa and the top conductive layer, wherein the passivation layer has an opening on the top surface of the light emitting mesa, at least part of the sidewall of the opening of the passivation layer has an inclined surface, and the thickness of the part of the top conductive layer located on the top surface of the light emitting mesa is greater than the thickness of the part of the top conductive layer located on the side surface of the light emitting mesa. The inclined sidewall of the passivation layer is beneficial to the deposition of the top conductive layer, and improves the coverage and continuity of the top conductive layer.

[0023] In one embodiment, the angle between the inclined surface and the top surface of the light emitting mesa exposed by the opening is greater than 90 degrees.

[0024] In one embodiment, the opening of the passivation layer is located at the central position of the top surface of the light emitting mesa, and the passivation layer covers the edge surface of the top surface of the light emitting mesa.

[0025] In one embodiment, the openings of the passivation layer are located at non-central positions of the top surface of the light emitting mesa, part of the edge surface of the top surface of the light emitting mesa is not covered by the passivation layer, and the sidewall of the opening of the passivation layer on the top surface of the light emitting mesa has an inclined surface.

[0026] In one embodiment, the lateral dimension of the opening of the passivation layer is in the range of 0.3 microns to 1.5 microns.

[0027] In one embodiment, the area of the opening of the passivation layer is smaller than the area of the top surface of the light emitting mesa.

[0028] In one embodiment, the adjacent passivation layers are connected, and all the passivation layers are connected as a whole.

[0029] In one embodiment, the material of the passivation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0030] In one embodiment, the micro light emitting diode chip further comprises:

[0031] an ohmic contact layer located at the bottom of the light emitting mesa; and

[0032] a top electrode layer located between the micro light emitting diodes, the top electrode layer surrounding the micro light emitting diodes, the top electrode layer having a first sidewall facing the light emitting mesa; the first sidewall being in contact with the top conductive layer only at the bottom end, the first sidewall having a first inclined surface.

[0033] The top electrode layer capable of reflecting light is arranged between the micro light emitting diodes, which can avoid light crosstalk between adjacent micro light emitting diodes, in addition, the top electrode layer can reflect the light emitted by the micro light emitting diodes, thereby improving the light emitting brightness of the micro light emitting diode chip, and thus improving the light emitting efficiency of the micro light emitting diode.

[0034] In one embodiment, the bottom end of the first sidewall is closer to the light emitting mesa than the top end.

[0035] In one embodiment, the first inclined surface opens up along the direction of light emission around the light emitting mesa.

[0036] In one embodiment, the top electrode layer comprises a second sidewall, the upper end of the second sidewall being connected to the lower end of the first sidewall and extending downward to the bottom of the top electrode layer; the second sidewall having a second inclined surface.

[0037] In one embodiment, the top of the second sidewall is closer to the light emitting mesa than the bottom of the second sidewall; the second inclined surface opens up along the direction away from the light emission around the light emitting mesa.

[0038] In one embodiment, the intersection of the first sidewall and the second sidewall is lower than the top of the light emitting mesa.

[0039] In one embodiment, the light emitting mesa has a first semiconductor epitaxial layer, a light emitting layer, and a second semiconductor epitaxial layer.

[0040] In one embodiment, the interface is lower than a bottom of the light emitting layer of the light emitting mesa.

[0041] In one embodiment, the light emitting layer comprises a plurality of layers of semiconductor material stacked.

[0042] In one embodiment, a top of the first inclined surface is higher than a top of the light emitting layer.

[0043] In one embodiment, a top of the first inclined surface is higher than a top of the light emitting mesa.

[0044] In one embodiment, a thickness of the top conductive layer at a portion of the top surface of the light emitting mesa is greater than a thickness of the top conductive layer at a portion of the side surface of the light emitting mesa,

[0045] wherein the thickness of the top conductive layer is less than 3000 angstroms and the thickness of the passivation layer is less than 3000 angstroms; and / or the thickness of the top conductive layer is in a range of 500 angstroms to 1500 angstroms; and / or the thickness of the passivation layer is in a range of 500 angstroms to 1500 angstroms.

[0046] In one embodiment, a bottom of the first sidewall is higher than a bottom of the light emitting mesa, and a height difference between the bottom of the first sidewall and the bottom of the light emitting mesa is in a range of 1000 angstroms to 3000 angstroms.

[0047] In one embodiment, an included angle between the first inclined surface and the top of the light emitting mesa is in a range of 95°-130°.

[0048] In one embodiment, an electrode polarity of the ohmic contact layer is opposite to an electrode polarity of the top conductive layer.

[0049] In one embodiment, bottoms of adjacent top electrode layers are connected, and all the top electrode layers are connected as a whole.

[0050] In one embodiment, a longitudinal section of adjacent top electrode layers presents a shape of bifurcated peaks.

[0051] In one embodiment, a longitudinal section of adjacent top electrode layers is symmetrical or asymmetrical.

[0052] In one embodiment, the top electrode layer comprises:

[0053] one or more main metal layers; and

[0054] A mirror layer is coated on the surface of the main metal layer, wherein the material of one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu, and the mirror layer is AL or an AL alloy metal.

[0055] In one embodiment, the bottom of the top electrode layer is lower than the bottom of the light emitting mesa, and the entire surface of the second side wall is in contact with the top conductive layer or the passivation layer.

[0056] In one embodiment, the inclination angle of the second inclined surface relative to the light emitting mesa is different from the inclination angle of the first inclined surface relative to the light emitting mesa.

[0057] In one embodiment, the inclination angle of the second side wall is less than 90°.

[0058] In one embodiment, the top of the top electrode layer is higher than the top of the light emitting mesa; or

[0059] the top of the top electrode layer is flush with the top of the light emitting mesa; or

[0060] the top of the top electrode layer is lower than the top of the light emitting mesa.

[0061] In one embodiment, the top electrode layer is a reflective cup structure, the bottom area of the reflective cup is smaller than the opening area of the reflective cup, and the angle between the inner wall of the reflective cup and the horizontal plane in the direction of the inner side light emitting mesa is in the range of 95°-130°.

[0062] In one embodiment, the adjacent top conductive layers are connected to each other, and all the top conductive layers are connected as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0063] The present application will be further described below with reference to the specific embodiments and the accompanying drawings.

[0064] Figure 1 A top view of a micro light emitting diode chip according to one embodiment of the present application is shown.

[0065] Figure 2 A longitudinal sectional view of a micro light emitting diode chip according to one embodiment of the present application is shown.

[0066] Figure 3 A top view of a top electrode layer of a micro light emitting diode chip according to one embodiment of the present application is shown.

[0067] Figure 4 A longitudinal sectional view of a micro light emitting diode chip according to another embodiment of the present application is shown.

[0068] Figure 5 A longitudinal sectional view of a micro light emitting diode chip according to another embodiment of the present application is shown. Figure 4Top view of the micro LED chip of the embodiment of the present application.

[0069] Figure 6 Longitudinal sectional view of the micro LED chip of the embodiment of the present application.

[0070] Figure 7 Longitudinal sectional view of the micro LED chip of the embodiment of the present application. Figure 6 Top view of the micro LED chip of the embodiment of the present application.

[0071] Figure 8 Longitudinal sectional view of the micro LED chip of the embodiment of the present application.

[0072] Figure 9 Longitudinal sectional view of the micro LED chip of the embodiment of the present application.

[0073] Figure 10A Longitudinal sectional view of the micro LED chip of the embodiment of the present application. Figure 9 Longitudinal sectional view of the micro LED chip of the embodiment of the present application.

[0074] Figure 10B Longitudinal sectional view of the micro LED chip of the embodiment of the present application.

[0075] Figure 11 Longitudinal sectional view of the micro LED chip of the embodiment of the present application. DETAILED DESCRIPTION

[0076] It should be noted that the components in the various figures can be exaggerated for the purpose of illustration and are not necessarily to scale. In the various figures, the same or similar components are denoted by the same reference numerals.

[0077] In the present application, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the presence of an intermediate object between the two. In addition, "arranged on or above" only indicates the relative position relationship between the two components, and in some cases, such as after reversing the product direction, it can also be converted to "arranged below or below", and vice versa.

[0078] In the present application, each embodiment is only intended to illustrate the scheme of the present application and should not be understood as limiting.

[0079] In the present application, unless otherwise specified, the quantifier "one" does not exclude the scenario of multiple elements.

[0080] In the present application, the term "connected" can refer to both direct connection and indirect connection through an intermediate element.

[0081] In the present application, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein the "configuration" includes various alternative technical means to achieve the technical effect, which become apparent under the teaching of the present application.

[0082] It should also be noted that, in the embodiments of the present application, only a part of components or assemblies can be shown for the sake of clarity and simplicity, but those skilled in the art can understand that, under the teaching of the present application, the required components or assemblies can be added according to the specific scene. In addition, the features in different embodiments of the present application can be combined with each other unless otherwise stated. For example, a feature in the second embodiment can replace a corresponding or functionally similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure or recitation range of the present application.

[0083] It should also be noted that, in the scope of the present application, the expressions "same", "equal", "equal to" and the like do not mean that the numerical values of the two are absolutely equal, but allow a certain reasonable error, that is, the expressions also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present application, the terms "perpendicular to", "parallel to" and the like also cover the meanings of "substantially perpendicular to", "substantially parallel to".

[0084] In the present application, the term "bottom of the light-emitting mesa" refers to the side of the light-emitting mesa facing away from the microlens, the term "top of the light-emitting mesa" refers to the side of the light-emitting mesa facing the microlens, and the term "side of the light-emitting mesa" refers to the two sides between the top and the bottom.

[0085] In the present application, the term "profile of the metal layer" refers to the maximum dimension, for example, the length, in the plane (or the plane perpendicular to the thickness) constituted by the length and the width of the metal layer. By analogy, the profile of the bottom of the light-emitting mesa refers to the maximum dimension, for example, the length, of the light-emitting mesa in the bottom plane (i.e., the plane perpendicular to the thickness at the bottom).

[0086] The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application.

[0087] Figure 1 A top view schematic diagram of a micro light-emitting diode chip in an embodiment of the present application is shown. Figure 1 The micro light-emitting diode includes a micro light-emitting diode, a microlens 102 and a top electrode layer 103. Figure 2A longitudinal cross-sectional view of a micro LED chip is shown. As shown, the micro LED chip includes a drive backplane 109, micro LEDs, a top electrode layer 103, and micro lenses 102. The micro LEDs are disposed on an upper surface of the drive backplane 109. The top electrode layer 103 is disposed between the micro LEDs in electrical contact around the micro LEDs. The micro lenses 102 are disposed on an upper surface of the micro LEDs, with adjacent micro lenses 102 spaced apart between the micro LEDs. In some embodiments of the present application, the drive module includes the drive backplane 109.

[0088] The micro LEDs include an ohmic contact layer 106, a light emitting mesa 101, a top conductive layer 104, and a passivation layer 105. The micro LEDs are disposed on an upper surface of the drive backplane 109. The drive backplane 109 is electrically connected to a bonding layer 107, which is electrically connected to the ohmic contact layer 106, which is disposed on a bottom of the light emitting mesa 101.

[0089] The maximum horizontal width of each micro LED chip is no more than 1 centimeter, and preferably no more than 5 millimeters. The micro LEDs are formed in an array in the micro LED chip, with a resolution such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The micro LED structures have a diameter in the micrometer range, such as 50um or less, and in some cases 4um or less. Each micro LED forms at least a portion of a pixel element on the micro LED chip.

[0090] The drive backplane 109 includes:

[0091] For convenience, "upward" is used to mean away from the drive backplane 109, "downward" is used to mean toward the drive backplane 109, and other directional terms such as top, bottom, above, below, directly below, underneath, and the like are interpreted accordingly. In some embodiments of the present application, the drive backplane 109 includes a substrate (not shown), a drive circuit (not shown), and drive electrodes 108.

[0092] In some embodiments of the present application, the substrate is a Si substrate. In other embodiments of the present application, the substrate is a transparent substrate, such as a glass substrate. Other examples of substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 microns thick.

[0093] The driving circuit forms individual pixel drivers to control the operation of each individual micro-LED pixel. The driving circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device, etc.

[0094] Each driving electrode 108 corresponds to one micro-LED, and each driving electrode 108 is electrically connected to the bonding layer 107. In some embodiments of the present application, the material of the driving electrode 108 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0095] In some embodiments of the present application, the light-emitting epitaxial layer structure of the micro-LED is fabricated on the surface of the epitaxial substrate. The micro-LED can be bonded to the surface of the driving backplane 109 through the bonding layer 107, and the bonding of the driving backplane 109 and the micro-LED can be achieved by high-temperature and high-pressure bonding methods such as eutectic bonding, thermal compression bonding, and transient liquid phase (TLP) bonding.

[0096] The bonding layer 107 is introduced as follows:

[0097] In some embodiments of the present application, the bonding layer 107 can be disposed on the driving backplane 109. In other embodiments of the present application, the bonding layer 107 is grown on the driving backplane 109. In some embodiments of the present application, the thickness of the bonding layer 107 is 0.1 to 3 microns. In a preferred embodiment, the thickness of the bonding layer 107 is 0.6 microns. In some embodiments of the present application, the bonding layer 107 comprises a first metal layer (not shown in the figure) and a second metal layer (not shown in the figure). The first metal layer is in direct contact with the ohmic contact layer 106 at the bottom of the light emitting mesa 101, and the second metal layer is at the bottom of the bonding layer 107. In some embodiments of the present application, one or more third metal layers can be disposed between the first metal layer and the second metal layer. By having multiple metal layers in the bonding layer 107, firstly, the total thickness of the bonding layer 107 can be flexibly controlled by depositing multiple metal layers in the manufacturing process; secondly, the material selection of each metal layer is also more flexible, for example, the first metal layer in direct contact with the bottom of the ohmic contact layer 106 can be selected to be a metal material that is not easy to diffuse into the ohmic contact layer 106 or even if it diffuses, it will not cause serious consequences, or a metal material with a small contact resistance with the ohmic contact layer 106, the intermediate layer can be selected to be a metal material with good conductivity, and the second metal layer at the bottom can be selected to be a metal material with good bonding with the driving backplane 109. In some embodiments of the present application, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 107 can also be used as a reflector to reflect the light emitted from the LED structure above.

[0098] In an embodiment of the present application, after the bonding is completed, the epitaxial substrate can be removed by laser stripping. The material of the epitaxial substrate can be sapphire or silicon. The corresponding stripping process can be selected according to the material of the epitaxial substrate. After the epitaxial substrate is removed, the purpose of transferring the epitaxial light emitting structure to the driving backplane 109 is achieved. Removing the epitaxial substrate can further thin the epitaxial buffer layer structure, facilitating subsequent epitaxial structure PN step process.

[0099] In one embodiment of the present invention, after bonding is completed, the light-emitting mesa 101 is etched. By adjusting the photolithographic morphology, ion etching is used to form micro-light-emitting diode pixels with a positive trapezoidal structure. In another embodiment of the present invention, the isolation between the micro-light-emitting diodes requires further deep trench etching, which can be completed by photolithography and IBE inert gas physical etching. For example, the bottom of the isolation trench between the micro-light-emitting diodes is lower than the interface between the bonding layer 107 and the driving backplane 109. That is, at the isolation trench between the micro-light-emitting diodes, the top of the driving backplane 109 is etched to a certain depth to ensure the isolation between the micro-light-emitting diodes.

[0100] like Figure 2 As shown, the driving backplane 109 includes a driving electrode 108, which is electrically connected to the bonding layer 107. In some embodiments, the driving backplane 109 may be an integrated circuit (IC) board. Micro-light-emitting diodes (LEDs) are electrically connected to the driving backplane 109, which controls the lighting and extinguishing of the LEDs. In some embodiments, the IC board may be electrically connected to each LED in the LED array via separate metal interconnects. In some embodiments, each LED may be electrically controlled individually by the IC board. In some embodiments, the IC board may be electrically connected to the driving electrode 108 of the LED chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the LEDs. In some embodiments, the dielectric layer may also be formed in the gaps between interconnects.

[0101] In some embodiments, the micro LED chip includes multiple micro LED arrays, each array comprising multiple micro LEDs. The micro LEDs are driven, for example, in a passive matrix (PM) drive, where the cathodes of all micro LEDs in each array are connected to a common cathode line NL, while micro LEDs with the same number in each array are connected to their respective anode lines PL. Thus, the on / off state and brightness of each micro LED can be individually controlled by controlling the signals on the corresponding cathode and anode lines.

[0102] In some embodiments, the micro-light-emitting diodes (LEDs) can be arranged in a regular or irregular manner on the upper surface of the driving module, serving as pixels of the micro-LED chip. The micro-LED includes: an ohmic contact layer 106 located at the bottom of the light-emitting mesa 101, and the ohmic contact layer 106 being electrically connected to the bonding layer 107; and a top conductive layer 104 located on the side and top surfaces of the light-emitting mesa 101, and the top conductive layer 104 being electrically connected to the top electrode layer 103.

[0103] In some embodiments, the thickness of the portion of the top conductive layer 104 located on the top surface of the light emitting mesa can be greater than the thickness of the portion of the top conductive layer 104 located on the side surface of the light emitting mesa. In other embodiments, the thickness of the portion of the top conductive layer 104 located on the top surface of the light emitting mesa is substantially the same as the thickness of the portion of the top conductive layer 104 located on the side surface of the light emitting mesa.

[0104] In order to improve the conductivity efficiency of the top conductive layer 104, the inventors of the present application increased the thickness of the top conductive layer 104 in the design. However, the top conductive layer located on the side surface of the light emitting mesa occupies a certain lateral space of the micro light emitting diode, which leads to a decrease in the lateral size of the light emitting mesa in the micro light emitting diode under the premise of a certain lateral size of the micro light emitting diode, thereby affecting the light emitting efficiency of the light emitting mesa. Therefore, in order to ensure the conductivity efficiency of the top conductive layer 104 and not affect the light emitting efficiency of the light emitting mesa, the thickness of the portion of the top conductive layer 104 located on the top surface of the light emitting mesa is greater than the thickness of the portion of the top conductive layer 104 located on the side surface of the light emitting mesa.

[0105] In the process of preparing the top conductive layer by the plating process, the wafer is placed on the hemispherical plating pot, the plating pot is placed above the source, and the planar evaporation is from beginning to end, while the plating film on the side wall has angle selectivity, thereby forming the characteristics of the thin side wall and the thick top of the top conductive layer 104, i.e., the thickness of the portion of the top conductive layer 104 located on the top surface of the light emitting mesa can be greater than the thickness of the portion of the top conductive layer 104 located on the side surface of the light emitting mesa.

[0106] In some embodiments, the passivation layer 105 at least partially covers the side surface of the light-emitting mesa 101, the bottom surface and the side surface of the isolation trench, and the passivation layer 105 is located between the light-emitting mesa 101 and the top conductive layer 104. In some embodiments, the passivation layer 105 may cover a portion of the top surface of the light-emitting mesa 101. In some embodiments, materials such as silicon dioxide, silicon nitride, silicon oxide, and silicon oxynitride are deposited using plasma chemical vapor deposition equipment to form the passivation layer. However, due to the limited passivation effect of the film, including density and breakdown resistance, the film thickness is greater than 4000 angstroms. In some embodiments of the present invention, the passivation layer 105 can be formed using atomic layer deposition (ALD). The passivation layer 105 formed using ALD has advantages such as uniform film formation, dense and pore-free structure, and step coverage. The thickness of the passivation layer 105 formed thereby can be reduced to less than 3000 angstroms. In one embodiment of the present invention, the thickness of the passivation layer 105 is in the range of 500 angstroms to 1500 Å, while effectively reducing chip leakage current and meeting chip requirements. Thinning the passivation layer 105 allows for the recessed placement of the annular reflective electrode, improving luminous efficiency. A photolithography process is used to create apertures in the passivation layer 105 on the top surface of the light-emitting mesa 101, exposing at least a portion of the top surface of the light-emitting mesa 101. These apertures in the passivation layer enable electrical contact between the light-emitting mesa 101 and the top conductive layer 104. In some embodiments of the invention, adjacent passivation layers are connected, forming a single unit. In some embodiments of the invention, the passivation layer is made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0107] In some embodiments, the electrode polarity of the ohmic contact layer 106 is opposite to that of the top conductive layer 104. The ohmic contact layer 106 can be, for example, a P-electrode or an anode electrode, while the top conductive layer 104 is an electrode with the opposite polarity to that of the ohmic contact layer 106, such as an N-electrode or a cathode electrode. In some embodiments of the present invention, the ohmic contact layer 106, the top conductive layer 104, and their connecting components can be one or more combinations of graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0108] In some embodiments of the present invention, a top conductive layer 104 can be formed on the top surface of the light-emitting platform 101 and the top surface of the passivation layer 105 using a sputtering process.

[0109] In some embodiments of the present application, the adjacent top conductive layers 104 are connected, and all the top conductive layers 104 are connected as a whole. In some embodiments of the present application, the top conductive layer 104 is a full-area transparent electrode for the display area, which is usually made of conductive material indium tin oxide. The indium tin oxide is generally made by electron beam evaporation. Due to poor step coverage and continuity, the film thickness is generally greater than 3000 angstroms. In some embodiments of the present application, the top conductive layer 104 can be formed by sputtering process. Since the coverage and continuity of the top conductive layer 104 formed by sputtering process are better than evaporation, the thickness of the top conductive layer 104 formed thereby can be reduced to less than 3000 angstroms. In an embodiment of the present application, the thickness of the top conductive layer 104 is in the range of 500 angstroms to 1500 angstroms, while ensuring that the coverage and continuity meet the requirements of the chip. Reducing the thickness of the top conductive layer 104 not only reduces the light absorption effect of the top conductive layer 104, but also sinks the annular reflective electrode, thereby improving the light efficiency.

[0110] In some embodiments, the top conductive layer 104 can be shared by all the micro light emitting diodes in the micro light emitting diode array.

[0111] In some embodiments of the present application, the light emitting mesa 101 can be a trapezoidal platform, and the lateral dimension of the bottom of the light emitting mesa 101 is greater than the lateral dimension of the top. In some embodiments of the present application, the inclination angle of the sidewall of the light emitting mesa 101 is in the range of 60° to 85°. In some embodiments of the present application, the lateral dimension of the bottom of the light emitting mesa 101 is not more than 3 microns. In some embodiments of the present application, the lateral dimension of the top of the light emitting mesa 101 is not more than 1.5 microns. In some embodiments of the present application, the lateral dimension of the ohmic contact layer 106 and the bonding layer 107 is greater than the lateral dimension of the bottom of the light emitting mesa 101.

[0112] As Figure 2As shown, the light emitting mesa 101 includes a first type epitaxial layer 1011, a second type epitaxial layer 1013, and a light emitting layer 1012 therebetween. The first type epitaxial layer 1011 is electrically connected with the ohmic contact layer 106. The second type epitaxial layer 1013 is electrically connected with the top conductive layer 104. In some embodiments, the light emitting mesa 101 of each micro light emitting diode in the micro light emitting diode array can be a micron-level light emitting mesa 101. In some embodiments, the micron-level light emitting mesa 101 can include, from bottom to top, the first type epitaxial layer 1011, the light emitting layer 1012, and the second type epitaxial layer 1013. That is, in a three-layer structure, the first type epitaxial layer 1011 is closest to the driving backplate 109; the light emitting layer 1012 is above the first type epitaxial layer 1011 and further away from the driving backplate 109; and the second type epitaxial layer 1013 is above the light emitting layer 1012 and farthest away from the driving backplate 109. In some embodiments, the light emitting layer 1012 is formed by a plurality of stacked quantum well layers, in particular, superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include a plurality of pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer 1011 is a semiconductor material with a first conductivity type and includes a plurality of semiconductor layers. The main base material of the first type epitaxial layer 1011 can be, but is not limited to, composed of Ga, N, As, P, In, or Al, etc. In addition, the first type epitaxial layer 1011 can include, from top to bottom, but not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, the ohmic contact layer 106 can be formed below the window layer. In some embodiments, the second type epitaxial layer 1013 is a semiconductor material with a second conductivity type and includes a plurality of semiconductor layers. The main base material of the second type epitaxial layer 1013 can be, but is not limited to, composed of Ga, N, As, P, In, or Al, etc. In addition, the second type epitaxial layer 1013 can include, from top to bottom, but not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, the ohmic contact layer 106 can be formed on the confinement layer. In some embodiments of the present application, the first conductivity type is different from the second conductivity type.

[0113] In some embodiments, the first type epitaxial layer 1011 is an N-type GaN layer or an N-type AlGaN layer, and the second type epitaxial layer 1013 is a P-type GaN layer or a P-type AlGaN layer, i.e., the material of the second type epitaxial layer 1013 can be a material layer containing Ga, N, As, Al, In, P, and at least one or more other elements, and the first type epitaxial layer 1011 can be a material layer containing Ga, N, As, Al, In, P, and at least one or more other elements. In some embodiments, the light emitting layer 1012 includes a plurality of quantum well layers and an electron blocking layer, and the plurality of quantum well layers are InGaN / GaN quantum well layers, InGaN / AlGaN quantum well layers, or InGaAs / AlGaAs quantum well layers. In some embodiments, the light emitting layer 1012 further includes an electron blocking layer disposed on a first side of the light emitting layer 1012, the first side referring to a side from which electrons migrate out of the light emitting layer 1012. In other embodiments of the present application, the first type epitaxial layer 1011 can also be a P-type GaN layer or a P-type AlGaN layer, and the second type epitaxial layer 1013 is an N-type GaN layer or an N-type AlGaN layer.

[0114] In some embodiments, the light emitting layer 1012 includes at least one quantum well layer (not shown in the figure). The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9, and y ranges from 0.3 to 0.5. For example, x is 0.8, and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0115] In some embodiments, one of the first type epitaxial layer 1011 and the second type epitaxial layer 1013 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3The material of the doped N-type contact layer is GaAs. In some embodiments, the doped N-type contact layer has a thickness of 10 nm to 30 nm. In some embodiments, the doped N-type contact layer has a doping concentration of 2e 18 cm -3 to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The N-type spacer layer has a thickness of 50 nm to 75 nm, for example, 65 nm.

[0116] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light emitting layer 1012 and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such embodiments, the P-type cladding layer has a thickness of no more than 380 nm, for example, the P-type cladding layer has a thickness of 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The doped P-type contact layer has a thickness of 10 nm to 30 nm, for example, 20 nm.

[0117] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the P-type spacer layer has a thickness of 50 nm to 70 nm, for example, 65 nm.

[0118] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the first doped P-type transition layer has a thickness of 20 nm to 40 nm, for example 30 nm.

[0119] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where x ranges from 0.5 to 0.9, for example x is 0.6. In some embodiments, the second doped P-type transition layer has a thickness of 10 nm to 30 nm, for example 20 nm.

[0120] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times the doping concentration of the second doped P-type transition layer.

[0121] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times the doping concentration of the first doped P-type transition layer.

[0122] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 The doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 The doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0123] The top electrode layer can reflect light emitted by the micro light emitting diode, thereby significantly increasing the total light emission. At the same time, the top electrode layer can also isolate light to prevent light crosstalk between adjacent micro light emitting diodes. By arranging the top electrode layer to surround the micro light emitting diode in an electrical contact manner and electrically connecting with the top conductive layer, the electrical contact area of the top electrode layer and the micro light emitting diode can be significantly increased, so that the active layer (light emitting layer) of the micro light emitting diode can emit light more uniformly, effectively avoiding the situation that only the electrical contact part or its vicinity emits light or the situation that the light emitting brightness of the electrical contact part or its vicinity is high.

[0124] Figure 3 A top view schematic diagram of the top electrode layer of a micro light emitting diode chip of an embodiment of the present application is shown. As Figure 3As shown, the bottoms of adjacent top electrode layers 103 are connected, and all the top electrode layers are connected as a whole. Figure 3 In some embodiments of the present application, the top view shape (i.e. cross-sectional shape) of the micro light emitting diode is circular, and the top view shape of the whole top electrode layer is a grid shape left after the circular shape is removed. In some embodiments of the present application, the top view shape of the micro light emitting diode can also be other suitable shapes, such as rectangular, square or regular polygon, etc., and the top view shape of the whole top electrode layer is a shape left after the other suitable shape is removed, such as a grid shape left after the rectangular, square or polygon is removed. As shown in FIG. 1, the top view shape of the micro light emitting diode is circular, and the top view shape of the whole top electrode layer is a grid shape left after the circular shape is removed. Figure 2 As shown, the longitudinal section of adjacent top electrode layers presents a shape of bifurcated peaks. In some embodiments of the present application, the longitudinal section shape of adjacent top electrode layers can be symmetrical or asymmetrical, and the height can be the same or different, which is not limited herein.

[0125] The top electrode layer includes a first sidewall facing the light emitting mesa, and the first sidewall is in contact with the top conductive layer only at the bottom end. The first sidewall is an inclined sidewall having a first inclined surface. The first inclined surface opens around the light emitting mesa in a direction toward light emission. The bottom end of the first sidewall is closer to the center of the light emitting mesa than the top end. The inclination angle b of the first sidewall is in the range of 95°-130°. The top electrode layer further includes a second sidewall, the upper end of the second sidewall is connected to the lower end of the first sidewall, and the second sidewall extends downward to the bottom of the top electrode layer, and the entire surface of the second sidewall is in contact with the top conductive layer.

[0126] In some embodiments, the second sidewall has a second inclined surface, and the inclination angle of the second inclined surface relative to the light emitting mesa is different from the inclination angle of the first inclined surface relative to the light emitting mesa. The inclination angle of the second sidewall is less than 90°. In some embodiments, the top of the second sidewall is closer to the light emitting mesa than the bottom of the second sidewall; the second inclined surface opens around the light emitting mesa in a direction away from light emission. The intersection of the first sidewall and the second sidewall is lower than the top of the light emitting mesa. In one embodiment, the intersection is lower than the bottom of the light emitting layer of the light emitting mesa. The top of the first inclined surface is higher than the top of the light emitting layer. The top of the first inclined surface is higher than the top of the light emitting mesa.

[0127] In embodiments of the present application, the top electrode layer is formed at the isolation trench between the micro light emitting diodes. The bottom of the top electrode layer is in contact with the top conductive layer formed in the isolation trench and protrudes upward, and the bottom sidewall (second sidewall) of the top electrode layer is in contact with the top conductive layer covering the sidewall of the ohmic contact layer and the bonding layer, thus most of the bottom surface is below the bottom surface of the light emitting mesa. The upper sidewall (first sidewall) of the top electrode layer is higher than the bottom surface of the light emitting mesa. The height difference between the bottom of the first sidewall and the bottom of the light emitting mesa is the sum of the thicknesses of the passivation layer and the top conductive layer.

[0128] In embodiments of the present application, the bottom of the top electrode layer 103 is lower than the bottom of the light emitting mesa 101.

[0129] In embodiments of the present application, the top of the top electrode layer 103 can be higher than the top of the light emitting mesa 101; the top of the top electrode layer 103 can also be flush with the top of the light emitting mesa 101; the top of the top electrode layer 103 can also be lower than the top of the light emitting mesa 101 (e.g. 0-1 microns lower than the top of the light emitting mesa 101). One, two or all of the above-mentioned situations can exist in one chip.

[0130] Preferably, the top of the top electrode layer 103 is higher than the top of the light emitting mesa 101. By making the height of the top of the top electrode layer 103 greater than the height of the top plane of the light emitting mesa 101, a higher top electrode layer 103 can be obtained, further improving the chance of light reflection and increasing the light extraction efficiency.

[0131] In some embodiments of the present application, the top electrode layer 103 is in a ring cup shape, thus forming a reflecting cup effect, with the light emitting mesa 101 at the bottom of the reflecting cup and the bottom area of the reflecting cup smaller than the cup opening area. The angle b between the inner wall of the reflecting cup and the horizontal plane in the direction of the inner side of the light emitting mesa is in the range of 95°-130°. When the micro light emitting diode light is irradiated to the cup-shaped metal inner wall, the light path reflection improves the light extraction efficiency at a small angle. The cup-shaped structure can achieve better light focusing effect.

[0132] In other embodiments, the number of top electrode layers 103 can also be 1 / 4 or 1 / 9 of the number of micro light emitting diodes, with each top electrode layer 103 surrounding 4 micro light emitting diodes or 9 micro light emitting diodes, without limitation.

[0133] The top electrode layer can increase the current spreading between adjacent micro light emitting diodes, reduce the resistance between adjacent micro light emitting diodes, and reduce the loss. The top electrode layer can make the current spread quickly and uniformly to all micro light emitting diodes.

[0134] In embodiments of the present application, the top electrode layer 103 can be a multi-layer structure, and the top electrode layer 103 includes one or more main metal layers. In some embodiments of the present application, the top electrode layer 103 includes a mirror surface layer covering the surface of the main metal layer. The material of the one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr and Cu. The mirror surface layer can be made of AL or AL alloy metal. The top electrode layer 103 can be formed by magnetron sputtering or evaporation, etc.

[0135] In some embodiments, the top electrode layer 103 can further include: an isolation layer corresponding to each layer of the main metal layer; wherein the isolation layer and the main metal layer are staggered, and each layer of the main metal layer is located on the corresponding isolation layer.

[0136] By adopting the isolation layer corresponding to each layer of the main metal layer, and the isolation layer and the main metal layer are staggered, and each layer of the main metal layer is located on the corresponding isolation layer, the influence of electromigration in the top electrode layer 103 can be effectively suppressed by setting the isolation layer. Especially in the case of high density of micro light emitting diodes in the micro light emitting diode chip, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the isolation layer, and the light extraction efficiency is further improved by the higher top electrode layer 103.

[0137] Further, the isolation layer can include: a titanium (Ti) metal layer. It should be pointed out that the material of the isolation layer can also include other appropriate materials, such as titanium nitride (TiN).

[0138] In some embodiments, the top electrode layer 103 can further include: an adhesion layer located at the bottom layer of the top electrode layer 103, and the isolation layer and the main metal layer are located on the adhesion layer. The adhesion effect of the adhesion layer can effectively improve the stability of the bottom of the top electrode layer 103. Especially in the case of high density of micro light emitting diodes, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the adhesion layer, and the light extraction efficiency is further improved by the higher top electrode layer 103.

[0139] Further, the adhesion layer can include: a chromium (Cr) metal layer. It should be pointed out that the material of the adhesion layer can also include other appropriate materials, such as one or more of the following: titanium (Ti), titanium nitride (TiN), tungsten (W).

[0140] In the embodiments of the present application, the top electrode layer 103 can further include: an anti-diffusion layer corresponding to the isolation layer, and each layer of the isolation layer is located on the corresponding anti-diffusion layer.

[0141] By forming the anti-diffusion layer corresponding to the isolation layer, and each layer of the isolation layer is located on the corresponding anti-diffusion layer, the stability of the top electrode layer 103 can be improved by the characteristics of high hardness and good corrosion resistance of the anti-diffusion layer. Especially in the case of high density of micro light emitting diodes in the micro light emitting diode chip, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the anti-diffusion layer, and the light extraction efficiency is further improved by the higher top electrode layer 103.

[0142] The anti-diffusion layer can include a platinum (Pt) metal layer, a nickel (Ni) metal layer. It is to be noted that the anti-diffusion layer can be a single platinum metal layer, a single nickel metal layer, or a stack of a single platinum metal layer and a single nickel metal layer.

[0143] Figure 2 In some embodiments, the lateral dimension of the bottom of the microlens 102 is greater than the lateral dimension of the micro light emitting diode light emitting region. In some embodiments, the lateral dimension of the bottom of the microlens 102 can be equal to the lateral dimension of the micro light emitting diode light emitting region.

[0144] In some embodiments, one microlens 102 can cover multiple lensless micro light emitting diodes. A plurality of microlenses form a microlens array. The microlens array is disposed above the micro light emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light emitting diode. The microlens is mainly used to converge and / or collimate light rays, for example, by adjusting the thickness, curvature, etc. of the microlens, the focal point of the microlens can be located in the light emitting mesa 101 of the micro light emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. As shown in FIG. 1, in some embodiments of the present application, the microlens 102 includes an upper curvature portion and a lower spacing portion. In some embodiments of the present application, the typical shape of the lower spacing portion of each microlens 102 includes a circle, a square, a rectangle, and a hexagon. The individual microlenses in the microlens array of the display panel can be the same or different in shape, curvature, optical power, size, base, spacing, etc. Figure 2

[0145] In some embodiments of the present application, the curvature centers of each position of the sidewall of the lower spacing portion do not coincide with the curvature centers of each position of the upper curvature portion. The thickness of the lower spacing portion is set such that the focal point of the microlens is located in the light emitting mesa 101 of the micro light emitting diode. In some embodiments of the present application, the lower spacing portion of the microlens has a height of 0.5 to 3 microns, and / or the upper curvature portion of the microlens has a height of 0.5 to 2 microns, and / or the spherical width of the microlens is 3 to 4 microns. In yet another embodiment, the microlens can be, for example, a positive half-spherical shape.

[0146] ​In some embodiments, the shape of the microlens 102 can be a curved hemispherical shape. In some embodiments, the height of the microlens 102 is no greater than 2 microns. In some embodiments, the height of the microlens 102 is no greater than 1 micron. In some embodiments, the height of the microlens 102 is no greater than 0.5 microns. In some embodiments, the width of the microlens 102 is no greater than 4 microns. In some embodiments, the width of the microlens 102 is no greater than 3 microns. In some embodiments, the width of the microlens 102 is no greater than 2 microns. In some embodiments, the width of the microlens 102 is no greater than 1 micron. In some embodiments, the width to height ratio of the microlens 102 is greater than 1.5.

[0147] In some embodiments, the microlens 102 can be made of various materials that are transparent to the wavelengths of light emitted by the micro light emitting diodes. Exemplary transparent materials for the microlens 102 include polymers, dielectric materials. In some embodiments, the dielectric materials include one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 102 is made of photoresist.

[0148] In some embodiments, the manufacturing process of the microlens 102 is mainly based on CVD deposition of SiO2 film layer, and the actual deposition film thickness is between 2.5 and 4 um. The deposition procedure generally uses a high deposition rate film forming method, so that deposition defects and micro cracks may occur in the deep trench area. After deposition is completed, a photoresist with appropriate viscosity, such as positive photoresist, is selected to perform wafer surface coating. Then, the light shielding area of the exposure mask plate is arranged in coincidence with the pixel point position, and then exposed to form a microlens 102 photoetching pattern. The photoresist topography is subjected to secondary full exposure and hard film baking to improve the shrinkage of the photoresist due to the photosensitive properties and thermal temperature properties, and the cross section forms a hemispherical topography. At this time, the photoetching process is completed, and subsequent ICP dry etching is performed to etch the ion etching dominated by chemical etching. Then, based on the hemispherical topography of the photoetching, according to the actual deposition thickness of SiO2, a certain SiO2 etching time is set to obtain the remaining etching allowance, at which time the microlens 102 appearance similar to that shown in the figure is formed. Since the SiO2 etching rate is relatively stable and controllable, the etching time is set to achieve the desired etching depth. The position of the microlens 102 is photoetched to form a hemispherical SiO2 topography. The ball height here refers to the height of the hemispherical SiO2, which is generally between 1.5 and 1.8 um. Similarly, the ball width is the diameter width of the arc-shaped hemispherical shape. The height below the ball to the bottom of the pixel point is the spacer height. The curvature radius can be considered as the bending degree of the hemispherical curve of SiO2. The greater the curvature radius, the larger the circle it represents, and the flatter the curve. The smaller the curvature radius, the smaller the circle it represents, and the more curved the curve, and the greater the curvature. Figure 1

[0149] ​However, through data simulation and multiple experimental verifications, the inventors find that the smaller the radius of curvature, that is, the larger the ball width of the microlens 102, is conducive to light emission. Correspondingly, changing the ball height of the originally hemispherical microlens 102 also allows the escaped light to be emitted from the microlens 102, increases the full emission angle of the microlens 102 by changing the curvature, and makes it difficult to form totally reflected light, which is conducive to the light emission effect. In addition, in order to achieve a uniform photoetching pattern, the photoresist generally cannot be too thick, because the photoresist is also consumed as a mask layer in the etching process, and too much or too little etching cannot obtain a relatively ideal ball height of the microlens 102. When the ball width and the ball height can form a semicircular shape, that is, twice the ball height is equal to the ball width, the effect is best.

[0150] The inventors further find that the remaining amount of the lower spacing part also affects the light emission effect. With the same ball height and ball width, the lower spacing part generally does not exceed the ball height. Under the current process, micro gap defects exist on both sides of the SiO2 of the lower spacing part, and the light source is prone to diffuse reflection at this position. If the photoetching size of the microlens 102 is adjusted, the defects can be eliminated or reduced in the previous microlens 102 etching, and the effect of defect repair can be achieved through subsequent secondary SiO2 deposition.

[0151] In the existing process procedure, the ball width and the ball height of the microlens 102 after etching are not the best conditions. For example, the SiO2 film layer of the microlens 102 is deposited for the first time through PECVD, about 2.5-3.5 microns. Subsequently, the photoetching topography of the microlens 102 is adjusted, such as the thickness of the photoresist, the exposure energy, and the hardening temperature, to complete the photoetching array topography of the corresponding pixel point position. The ion etching microlens 102 passivation protection layer SIO2 material forms a semispherical SIO2 microlens 102 with a lens-like topography. After the SIO2 etching of the microlens 102 is completed, due to the photoetching size and ion etching of the microlens 102, the radius of curvature, the lower spacing part height, the ball height, and the lens ball width of the microlens 102 are all small. Therefore, secondary SiO2 deposition is performed on the microlens 102 to increase the radius of curvature, the lower spacing part height, the ball height, and the lens ball width of the microlens 102. The film thickness of the secondary SiO2 deposition needs to be determined according to the film thickness of the previously deposited SiO2 of the microlens 102 and the etching topography of the microlens 102. The secondary deposition is generally 0.2-1 microns, which can be single or multiple deposition operations. The inventors find that the secondary deposition can obtain a more optimal brightness improvement effect.

[0152] Based on this, the present application provides a microminiature light-emitting diode chip and a manufacturing method thereof. The microlens 102 is formed by multiple deposition to change the lower spacing part height, the radius of curvature, and the lens ball height of the microlens 102, improve the lens micro-defects, and effectively improve the light efficiency of the microminiature light-emitting diode chip.

[0153] Figure 4A longitudinal sectional view of a micro LED chip is shown. Figure 4 The micro LED chip shown in Figure 2 The micro LED chip shown in Figure 4 The sidewall of the opening of the passivation layer 105 in Figure 2 The sidewall of the opening of the passivation layer 105 in Figure 2 The vertical sidewall in

[0154] As shown in Figure 4 The passivation layer 105 covers the side surface and at least part of the top surface of the light emitting mesa 101. At the top of the light emitting mesa 101, the passivation layer 105 has an opening 1051, the passivation layer 105 at the edge of the opening 1051 has a sidewall 1052, the sidewall 1052 has an inclined surface, which is beneficial for the deposition of the top conductive layer 104 and improves the coverage and continuity of the top conductive layer 104.

[0155] In some embodiments, the inclined surface of the sidewall 1052 has an angle c with the top surface of the light emitting mesa 101 exposed by the opening 1051, which is greater than 90 degrees, for example, greater than 90 degrees and less than 180 degrees.

[0156] In some embodiments, the opening 1051 is formed by etching the passivation layer 105 on the top surface of the light emitting mesa 101, and at least part of the surface of the top surface of the light emitting mesa 101 is exposed by etching. By adjusting the etching process parameters, a predetermined inclined angle is formed on the sidewall of the opening of the passivation layer.

[0157] Figure 5 A top view of the opening of the passivation layer of the micro LED chip shown in Figure 4 As shown in Figure 5 The opening 1051 of the passivation layer is located at the central position of the top of the light emitting mesa 101. The top surface of the light emitting mesa 101 has a circular shape in the top view (i.e. cross-sectional shape), the opening 1051 of the passivation layer has a circular shape in the top view (i.e. cross-sectional shape), and the passivation layer 105 has a grid shape in the top view after removing the opening 1051 of the passivation layer. In some embodiments of the present application, the top surface of the light emitting mesa 101 and the opening 1051 of the passivation layer can also have other appropriate shapes, such as rectangular, square or regular polygon, etc., and the passivation layer 105 has a shape corresponding to the shape after removing the opening 1051 of the passivation layer, such as a grid shape after removing the rectangle, square or polygon. The area of the opening 1051 of the passivation layer is smaller than the area of the top surface of the light emitting mesa 101, so the passivation layer 105 covers the edge surface of the top surface of the light emitting mesa 101, such as Figure 5The overlap of the passivation layer 105 and the light emitting mesa 101 is the portion of the light emitting mesa 101 covered by the passivation layer 105.

[0158] In some embodiments, the lateral dimension (i.e. the maximum dimension in the horizontal direction) of the passivation layer opening 1051 is in the range of 0.3 to 1.5 microns.

[0159] Figure 6 A longitudinal cross-sectional view of a micro light emitting diode chip is shown. Figure 7 A top view of a micro light emitting diode chip is shown. Figure 6 A top view of a micro light emitting diode chip is shown. In some embodiments, as shown in Figure 6 and Figure 7 As shown, the passivation layer opening 1051 is off-center on the top of the light emitting mesa 101. In some embodiments, as shown in Figure 6 In the cross-sectional view, the passivation layer opening 1051 is asymmetric with respect to the center of the light emitting mesa 101.

[0160] Figure 8 A longitudinal cross-sectional view of a micro light emitting diode chip is shown. In some embodiments, as shown in Figure 8 As shown, only part of the passivation layer opening 1051 has a sloped side, while the rest of the passivation layer opening 1051 can have a vertical sidewall. Alternatively, part of the passivation layer opening 1051 is on the top of the light emitting mesa and has a sloped sidewall, while another part of the passivation layer opening 1051 reaches or exceeds the top edge of the light emitting mesa, such that the top edge of this part of the light emitting mesa is not covered by the passivation layer.

[0161] In the above embodiments, the passivation layer covers the side and at least part of the top of the light emitting mesa, and the passivation layer on the top of the light emitting mesa has an opening, and the passivation layer at the edge of the opening has a sloped sidewall, which is beneficial for the deposition of the top conductive layer and improves the coverage and continuity of the top conductive layer.

[0162] Figure 9 A top view of a micro light emitting diode chip is shown. Figure 9 The micro light emitting diode, the microlens 102 and the top electrode layer 103 are included. Figure 10A A longitudinal cross-sectional view of a micro light emitting diode chip is shown. As shown in Figure 10AAs shown, the micro light emitting diode chip includes a driving backplate 109, micro light emitting diodes, a top electrode layer 103, and micro lenses 102. The micro light emitting diodes are arranged on the upper surface of the driving backplate 109. The top electrode layer 103 is arranged to electrically contact the micro light emitting diodes. The micro lenses 102 are arranged on the upper surface of the micro light emitting diodes, and adjacent micro lenses 102 are spaced apart from each other. In some embodiments of the present application, the driving module includes the driving backplate 109.

[0163] The micro light emitting diode includes an ohmic contact layer 106, a light emitting mesa 101, a top conductive layer 104, and a passivation layer 105. The micro light emitting diode is arranged on the upper surface of the driving backplate 109. The driving backplate 109 is electrically connected to the bonding layer 107, which is electrically connected to the ohmic contact layer 106 arranged at the bottom of the light emitting mesa 101.

[0164] In some embodiments, the passivation layer 105 at least partially covers the side surface of the light emitting mesa 101, the bottom surface and the side surface of the isolation trench. In some embodiments, the passivation layer 105 can cover part of the top surface of the light emitting mesa 101. In other embodiments, the passivation layer 105 does not cover the top surface of the light emitting mesa 101. In some embodiments, a material such as silicon dioxide, silicon nitride, silicon oxide, silicon oxynitride, etc. is used to form the passivation layer 105 by plasma chemical vapor deposition equipment, and the film thickness can be greater than 4000 angstroms. In some embodiments, the passivation layer 105 can be formed by atomic layer deposition process. The passivation layer 105 formed by atomic layer deposition process has the advantages of uniform film formation, density without pores, and step coverage. The thickness of the passivation layer 105 formed in this way can be thinned to less than 3000 angstroms. In one embodiment of the present application, the thickness of the passivation layer 105 is in the range of 500 angstroms to 1500 angstroms, which can effectively reduce the chip leakage rate and meet the chip requirements. Thinning the thickness of the passivation layer 105 can sink the annular reflective electrode (top electrode layer) and improve the light efficiency. Then, the passivation layer 105 is etched by lithography process on the top surface of the light emitting mesa 101 to expose at least part of the top surface of the light emitting mesa 101, and the electrical contact between the light emitting mesa 101 and the top conductive layer 104 is realized through the passivation layer opening. In some embodiments of the present application, adjacent passivation layers are connected, and all passivation layers are connected as a whole. In some embodiments of the present application, the material of the passivation layer is one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0165] In some embodiments, the top electrode layer 103 can reflect light emitted by the micro light emitting diodes, thereby significantly increasing the total light emission. Meanwhile, the top electrode layer 103 can also isolate light, preventing light crosstalk between adjacent micro light emitting diodes. By arranging the top electrode layer 103 to surround the micro light emitting diodes in an electrical contact manner and electrically connecting with the top conductive layer 104, the electrical contact area of the top electrode layer 103 with the micro light emitting diodes can be significantly increased, thereby enabling the active layer (light emitting layer) of the micro light emitting diodes to emit light more uniformly, effectively avoiding light emission only at the electrical contact position or near the electrical contact position or light emission with high brightness only at the electrical contact position or near the electrical contact position.

[0166] The bottoms of adjacent top electrode layers 103 are connected, and all the top electrode layers are connected as a whole. The top view shape (i.e. cross-sectional shape) of the micro light emitting diodes is circular, and the top view shape of the whole top electrode layer is a grid shape remaining after the circular shape is removed. In some embodiments of the present application, the top view shape of the micro light emitting diodes can also be other appropriate shapes, such as rectangular, square or regular polygon, and the top view shape of the whole top electrode layer is a grid shape remaining after the other appropriate shape is removed, such as a grid shape remaining after a rectangular, square or polygon is removed. As shown in FIG. 1, the longitudinal cross-sectional shape of adjacent top electrode layers presents a bifurcated peak shape. In some embodiments of the present application, the longitudinal cross-sectional shape of adjacent top electrode layers can be symmetrical or asymmetrical, and the height can be the same or different, which is not limited herein. Figure 10A

[0167] In embodiments of the present application, the top electrode layer 103 is formed at the isolation trenches between the micro light emitting diodes. The top electrode layer 103 can be formed on the passivation layer 105. The bottom of the top electrode layer 103 is in contact with the passivation layer formed in the isolation trenches and protrudes upward.

[0168] In embodiments of the present application, as shown in FIG. 2, the top electrode layer 103 includes a first side wall facing the light emitting platform, and the bottom end of the first side wall is in contact with the passivation layer 105. The first side wall is an inclined side wall having a first inclined surface. The first inclined surface is open along the direction of light emission around the light emitting platform. The bottom end of the first side wall is closer to the center of the light emitting platform than the top end. The inclination angle b of the first side wall is in the range of 95°-130°. The top electrode layer 103 also includes a second side wall, the upper end of the second side wall is connected with the lower end of the first side wall, and the second side wall extends downward to the bottom of the top electrode layer, and the entire surface of the second side wall is in contact with the passivation layer 105. Figure 10A

[0169] ​​In some embodiments, the second side wall has a second inclined surface with an inclined angle relative to the light emitting mesa different from the inclined angle of the first inclined surface relative to the light emitting mesa. The inclined angle c of the second side wall is less than 90°. In some embodiments, the top of the second side wall is closer to the light emitting mesa than the bottom of the second side wall; the second inclined surface is open in a direction away from the light emitting mesa. The intersection of the first side wall and the second side wall is lower than the top of the light emitting mesa. In one embodiment, the intersection is lower than the bottom of the light emitting layer of the light emitting mesa. In one embodiment, the top of the first inclined surface is higher than the top of the light emitting layer. In one embodiment, the top of the first inclined surface is higher than the top of the light emitting mesa.

[0170] In one embodiment, the bottom of the first side wall of the top electrode layer 103 is higher than the bottom surface of the light emitting mesa. The height difference between the bottom of the first side wall and the bottom of the light emitting mesa is the thickness of the passivation layer.

[0171] In embodiments of the present application, the bottom of the top electrode layer 103 is lower than the bottom of the light emitting mesa 101.

[0172] In embodiments of the present application, the top of the top electrode layer 103 can be higher than the top of the light emitting mesa 101; the top of the top electrode layer 103 can also be flush with the top of the light emitting mesa 101; the top of the top electrode layer 103 can also be lower than the top of the light emitting mesa 101 (e.g. 0-1 microns lower than the top of the light emitting mesa 101). In one chip, one, two or three of the above situations can exist at the same time.

[0173] Preferably, the top of the top electrode layer 103 is higher than the top of the light emitting mesa 101. By making the height of the top of the top electrode layer 103 greater than the height of the top plane of the light emitting mesa 101, a higher top electrode layer 103 can be obtained, further improving the chance of light reflection and increasing the light extraction efficiency.

[0174] In some embodiments of the present application, the top electrode layer 103 has a ring-shaped cup structure, thereby forming a reflective cup effect. The light emitting mesa 101 is at the bottom of the reflective cup, and the bottom area of the reflective cup is smaller than the cup opening area of the reflective cup. The angle b between the inner wall of the reflective cup and the horizontal plane in the direction of the inner side light emitting mesa is in the range of 95°-130°. When the micro light emitting diode light irradiates the cup-shaped metal inner wall, the light path reflection improves the small angle light extraction efficiency. The cup structure can achieve better light collection effect.

[0175] In other embodiments, the number of top electrode layers 103 can also be 1 / 4 or 1 / 9 of the number of micro light emitting diodes. Each top electrode layer 103 surrounds 4 micro light emitting diodes or 9 micro light emitting diodes, without limitation.

[0176] The top electrode layer 103 can increase current spreading between adjacent micro light emitting diodes, reduce resistance between adjacent micro light emitting diodes, and reduce loss. The top electrode layer 103 can quickly and uniformly spread current to all micro light emitting diodes.

[0177] In embodiments of the present application, the top electrode layer 103 can be a multi-layer structure, and the top electrode layer 103 includes one or more main metal layers. In some embodiments of the present application, the top electrode layer 103 includes a mirror layer covering the surface of the main metal layer. The material of the one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu. The mirror layer can be made of AL or an AL alloy metal. The top electrode layer 103 can be formed by magnetron sputtering or evaporation.

[0178] In some embodiments, the top electrode layer 103 can further include an isolation layer corresponding to each main metal layer; wherein the isolation layer and the main metal layer are arranged alternately, and each main metal layer is located on the corresponding isolation layer.

[0179] By using an isolation layer corresponding to each main metal layer, and arranging the isolation layer and the main metal layer alternately, and locating each main metal layer on the corresponding isolation layer, the influence of electromigration in the top electrode layer 103 can be effectively suppressed by setting the isolation layer. Especially in the case of a high density of micro light emitting diodes in the micro light emitting diode chip, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the isolation layer, and the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0180] Further, the isolation layer can include a titanium (Ti) metal layer. It should be noted that the material of the isolation layer can also include other appropriate materials, such as titanium nitride (TiN).

[0181] In some embodiments, the top electrode layer 103 can further include an adhesion layer located at the bottom layer of the top electrode layer 103, and the isolation layer and the main metal layer are located above the adhesion layer. The adhesion effect of the adhesion layer can effectively improve the stability of the bottom of the top electrode layer 103. Especially in the case of a high density of micro light emitting diodes, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the adhesion layer, and the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0182] Further, the adhesion layer can include a chromium (Cr) metal layer. It should be noted that the material of the adhesion layer can also include other appropriate materials, such as one or more of the following: titanium (Ti), titanium nitride (TiN), tungsten (W).

[0183] In the embodiments of the present application, the top electrode layer 103 can further comprise: an anti-diffusion layer corresponding to each of the isolation layers, and each of the isolation layers is located on the corresponding anti-diffusion layer.

[0184] By forming the anti-diffusion layer corresponding to each of the isolation layers, and each of the isolation layers is located on the corresponding anti-diffusion layer, the stability of the top electrode layer 103 can be improved by the characteristics of the anti-diffusion layer having high hardness and good corrosion resistance. Especially in the case of a micro light emitting diode chip with a large density of micro light emitting diodes, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the anti-diffusion layer, and the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0185] The anti-diffusion layer can comprise: a platinum (Pt) metal layer, a nickel (Ni) metal layer. It should be pointed out that the anti-diffusion layer can be a single platinum metal layer, also can be a single nickel metal layer, also can be a single platinum metal layer and a single nickel metal layer.

[0186] In some embodiments, the electrode polarity of the ohmic contact layer 106 is opposite to that of the top conductive layer 104. For example, the ohmic contact layer 106 can be a P electrode or an anode electrode, and the top conductive layer 104 is an electrode opposite to the polarity of the ohmic contact layer 106, for example, an N electrode or a cathode electrode. In some embodiments of the present application, the ohmic contact layer 106, the top conductive layer 104 and the connecting components thereof can be one or more combinations of, such as graphene or indium tin oxide (ITO) or antimony doped zinc oxide (AZO) or fluorine doped tin oxide (FTO) or other transparent conductive oxides (TCO).

[0187] In some embodiments of the present application, the top conductive layer 104 is formed on the top surface of the light emitting mesa, the surface of the passivation layer 105, and the surface of the top electrode layer 103. The adjacent top conductive layers 104 are connected, and all the top conductive layers 104 are connected as a whole. In some embodiments of the present application, the top conductive layer 104 is a full-area transparent electrode of the display area. The top conductive layer 104 covers the light emitting mesa, the passivation layer 105, and the top electrode layer 103, and contacts and forms an electrical connection with the light emitting mesa at the position of the opening of the passivation layer. The top electrode layer 103 is between the top conductive layer 104 and the passivation layer. Generally, the top conductive layer 104 is made of conductive material indium tin oxide, and the indium tin oxide is made by evaporating film layer material by electron beam evaporation, and the film thickness is generally greater than 3000 angstroms. In some embodiments of the present application, the top conductive layer 104 can be formed by a sputtering process. Since the coverage and continuity of the top conductive layer 104 formed by the sputtering process are better than evaporation. The thickness of the top conductive layer 104 formed thereby can be thinned to less than 3000 angstroms. In an embodiment of the present application, the thickness of the top conductive layer 104 is in the range of 500 angstroms to 1500 angstroms, while ensuring that the coverage and continuity meet the requirements of the chip. Thinning the thickness of the top conductive layer 104 can reduce the light absorption effect of the top conductive layer 104, thereby improving the light efficiency.

[0188] In some embodiments, the top conductive layer 104 can be shared by all the micro light emitting diodes in the micro light emitting diode array.

[0189] Figure 10A In some embodiments, the lateral dimension of the bottom of the microlens 102 is greater than the lateral dimension of the light emitting area of the micro light emitting diode. In some embodiments, the lateral dimension of the bottom of the microlens 102 can be equal to the lateral dimension of the light emitting area of the micro light emitting diode.

[0190] Figure 10B A longitudinal sectional view of a micro light emitting diode chip of another embodiment of the present application is shown. Figure 10B The micro light emitting diode chip shown is different from Figure 10A The micro light emitting diode chip shown is different from

[0191] In some embodiments, the angle c between the inclined surface of the sidewall 1052 and the top of the light emitting mesa exposed by the aperture is greater than 90 degrees, for example, greater than 90 degrees and less than 180 degrees. In some embodiments, the aperture is formed by etching the passivation layer 105 on the top surface of the light emitting mesa 101 to expose at least a portion of the top surface of the light emitting mesa 101. By adjusting the etching process parameters, a predetermined inclined angle is formed on the sidewall of the aperture in the passivation layer.

[0192] Figure 11 A longitudinal cross-sectional view of a micro light emitting diode chip is shown. Figure 11 The micro light emitting diode chip shown is similar to Figure 10A The micro light emitting diode chip shown differs from Figure 11 The top conductive layer 104 does not cover the surface of the top electrode layer 103. The top conductive layer 104 only forms an electrical connection with the top electrode layer 103 at the lower region of the first sidewall of the top electrode layer 103.

[0193] In some embodiments, the micro light emitting diode chip can include red, blue, and / or green micro light emitting diodes. In some embodiments, the pitch of the micro light emitting diode array, i.e., the minimum center-to-center distance between the micro light emitting diodes, can be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro light emitting diode chip can be between thousands and millions.

[0194] While the foregoing describes various embodiments of the present application, it is to be understood that they are presented by way of example only, and not as a limitation. It will be apparent to persons skilled in the relevant art that various changes, modifications and alterations can be made to the embodiments described without departing from the spirit and scope of the present application. Thus, the breadth and scope of the present application should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A miniature light-emitting diode chip, comprising: Illuminated tabletop; A passivation layer, wherein the passivation layer at least partially covers the side surface of the light-emitting platform; A top electrode layer is located above the passivation layer between the micro LEDs, and the top electrode layer surrounds the micro LEDs; as well as A top conductive layer is located on the side and top surfaces of the light-emitting platform and is electrically connected to the top electrode layer, wherein the passivation layer is located between the light-emitting platform and the top conductive layer.

2. The micro light-emitting diode chip according to claim 1, characterized in that, On the top surface of the light-emitting platform, the passivation layer has an opening, and the top conductive layer is electrically connected to the top of the light-emitting platform through the opening.

3. The micro light-emitting diode chip according to claim 1, characterized in that, The adjacent passivation layers are connected, and all the passivation layers are connected into a whole. The passivation layer is made of one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

4. The miniature light-emitting diode chip according to claim 1, characterized in that, The top conductive layer covers the top electrode layer, and the bottom of the top electrode layer is in contact with the passivation layer.

5. The micro light-emitting diode chip according to claim 1, characterized in that, The bottoms of adjacent top electrode layers are connected, and all the top electrode layers are connected as a whole.

6. The miniature light-emitting diode chip according to claim 1, characterized in that, The top electrode layer has a first sidewall facing the light-emitting platform; the first sidewall contacts the passivation layer only at its bottom end, and the first sidewall has a first inclined surface.

7. The miniature light-emitting diode chip according to claim 6, characterized in that, The top electrode layer only contacts the top conductive layer at the bottom of the first sidewall.

8. A miniature light-emitting diode chip, comprising: Illuminated tabletop; A top conductive layer is located on the side and top surfaces of the light-emitting platform; as well as A passivation layer covers the side surface and at least a portion of the top surface of the light-emitting platform, and the passivation layer is located between the light-emitting platform and the top conductive layer. On the top surface of the light-emitting platform, the passivation layer has an opening, and at least a portion of the sidewall of the opening has an inclined surface. The thickness of the top conductive layer located on the top surface of the light-emitting platform is greater than the thickness of the portion located on the side surface of the light-emitting platform.

9. The micro light-emitting diode chip according to claim 8, characterized in that, The angle between the inclined surface and the exposed top surface of the light-emitting platform is greater than 90 degrees.

10. The micro light-emitting diode chip according to claim 8, characterized in that, The passivation layer has an opening located in the center of the top surface of the light-emitting platform, and the passivation layer covers the edge surface of the top surface of the light-emitting platform.

11. The micro light-emitting diode chip according to claim 8, characterized in that, The opening in the passivation layer is located in a non-centered position on the top surface of the light-emitting platform. Part of the edge surface of the top surface of the light-emitting platform is not covered by the passivation layer, and the sidewall of the passivation layer opening on the top surface of the light-emitting platform has an inclined surface.

12. The micro light-emitting diode chip according to claim 8, characterized in that, The lateral dimensions of the openings in the passivation layer are in the range of 0.3 micrometers to 1.5 micrometers.

13. The micro light-emitting diode chip according to claim 8, characterized in that, Also includes: An ohmic contact layer is located at the bottom of the light-emitting platform; as well as A top electrode layer is located between the micro light-emitting diodes, the top electrode layer surrounds the micro light-emitting diodes, and the top electrode layer has a first sidewall facing the light-emitting platform; The first sidewall contacts the top conductive layer only at its bottom end, and the first sidewall has a first inclined surface.

14. The micro light-emitting diode chip according to claim 13 or 6, characterized in that, The bottom of the first sidewall is closer to the light-emitting platform than the top.

15. The micro light-emitting diode chip according to claim 13 or 6, characterized in that, The first inclined surface opens around the light-emitting platform along the direction of light emission.

16. The micro light-emitting diode chip according to claim 1 or 13, characterized in that, The bottoms of adjacent top electrode layers are connected, and all the top electrode layers are connected as a whole.

17. The micro light-emitting diode chip according to claim 1 or 13, characterized in that, The top electrode layer includes: One or more main metal layers; and A reflective mirror layer covering the surface of the main metal layer, wherein the material of one or more main metal layers is one or more alloys of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr and Cu, and the reflective mirror layer is Al or an Al alloy metal.

18. The micro light-emitting diode chip according to claim 1 or 13, characterized in that, The top electrode layer is a reflective cup-shaped structure. The bottom area of ​​the reflective cup is smaller than the opening area of ​​the reflective cup. The angle between the inner wall of the reflective cup and the horizontal plane of the inner light-emitting platform is in the range of 95°-130°.

19. The micro light-emitting diode chip according to claim 1 or 13, characterized in that, The adjacent top conductive layers are connected to each other, and all the top conductive layers are connected as a whole.

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