Display device

Abstract

A display device according to one embodiment includes: a substrate including a display area including a plurality of pixels, each pixel including a plurality of sub-pixels, and a non-display area surrounding the display area; a first electrode disposed in each of the plurality of sub-pixels on the substrate; a first bank disposed on the first electrode, at a boundary between adjacent sub-pixels, and including an upper surface and a side surface; and a second bank disposed on a side surface of the first bank and exposing at least a portion of an upper surface of the first bank.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0131831, filed on September 27, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This manual relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices are being utilized, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices.

[0005] Display devices include multiple pixels and multiple switching elements for driving and controlling the pixels. Summary of the Invention

[0006] Embodiments of this specification relate to providing a display device in which at least a portion of the upper surface of a black embankment is exposed to improve the reflection of external light.

[0007] Embodiments of this specification also relate to providing a display device in which a transparent dam is provided on the side surface of a black dam to form an additional light extraction area surrounding the light-emitting area.

[0008] Embodiments of this specification also relate to providing a display device in which light extraction can be improved and low power consumption can be achieved because the second dike covers some or all of the side surface of the first dike.

[0009] The purpose of this specification is not limited to the above-described purposes, and other technical purposes can be deduced from the following embodiments.

[0010] According to one embodiment, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of pixels; a first electrode disposed in each sub-pixel on the substrate; a dam disposed on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface; and a second dam disposed on the side surface of the first dam and exposing at least a portion of the upper surface of the first dam.

[0011] According to another embodiment, a display apparatus is provided, the display apparatus including: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of pixels; a first electrode disposed in each sub-pixel on the substrate; a bank disposed on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface; and a second bank disposed on the side surface of the first bank and exposing at least a portion of the upper surface of the first bank, wherein each sub-pixel includes a non-light emitting area corresponding to the first bank and a light emitting area exposed by the first bank, and the non-light emitting area includes an additional light extraction area corresponding to the second bank.

[0012] Details of other embodiments are included in the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a plan view of a display apparatus according to an embodiment.

[0014] Figure 2 is a cross-sectional view showing a bending state of a display panel according to Figure 1 .

[0015] Figure 3 is a cross-sectional view along line A-A' in Figure 1 .

[0016] Figure 4 is a detailed cross-sectional view of a light emitting part of Figure 3 .

[0017] Figure 5 is a detailed cross-sectional view of a light emitting part according to a modified example.

[0018] Figure 6 is a cross-sectional view of a touch part according to Figure 3 .

[0019] Figure 7 is a cross-sectional view along line B-B' in Figure 1 .

[0020] Figure 8 is a cross-sectional view along line C-C' in Figure 1 .

[0021] Figure 9 is an enlarged cross-sectional view of a region Q1 in Figure 3 .

[0022] Figure 10 is a plan view of a pixel according to an embodiment.

[0023] Figure 11 is a cross-sectional view of a display apparatus according to another embodiment.

[0024] Figure 12 is a cross-sectional view of a display apparatus according to still another embodiment.

[0025] Figure 13 is a cross-sectional view of a display apparatus according to still another embodiment.

[0026] Figure 14 is a cross-sectional view of a display apparatus according to still another embodiment.

[0027] Figure 15 is a cross-sectional view of a display apparatus according to still another embodiment.

[0028] Figure 16 is a cross-sectional view of a display apparatus according to still another embodiment.

[0029] Figure 17 is a cross-sectional view of a display apparatus according to still another embodiment.

[0030] Figure 18 is a perspective view of a display apparatus according to still another embodiment.

[0031] Figure 19 is a cross-sectional view along line D-D' in Figure 18 DETAILED DESCRIPTION

[0032] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0033] The same reference denotations are used throughout the drawings and the same elements are denoted by the same reference denotations. Further, in the drawings, the thickness, the proportion, and the size of components can be exaggerated for effective description of the technical content. The proportions of components shown in the drawings are different from actual proportions, and thus are not limited to the proportions shown in the drawings.

[0034] In the specification, when a first component (or a region, a layer, a part, etc.) is described as being "on", "connected to", or "coupled to" a second component, it can be directly connected / coupled to the second component, or a third component can be disposed therebetween.

[0035] The term "and / or" includes all of the possible combinations of the associated items.

[0036] Terms such as first and second can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component without departing from the scope of the embodiments. Singular includes plural unless context clearly indicates otherwise. ​

[0037] Terms such as "below," "beneath," "above," and "on top," are used to describe relationships of components shown in the drawings. These terms are relative concepts and are described with respect to the orientation marked in the drawings. For example, one or more other portions can be positioned between two portions as long as "immediately" or "directly" is not used. The spatially relative terms "under", "below", "lower", "above", "upper", and the like can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. For example, in the case where an element is turned over in the figure, the element described as being "below" or "beneath" another element can be oriented "above" the other element. Thus, the exemplary term "below" can encompass both a direction which is downward as well as a direction which is upward.

[0038] It is to be understood that the terms such as "include" or "have" are intended to indicate the existence of described features, numbers, steps, operations, components, parts, or combinations thereof, and are not precluded to the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0039] Features of various embodiments of the present disclosure can be partially or wholly coupled or combined, various technologies are interconnected and driven, and embodiments can be implemented independently of each other or together in an associated relationship.

[0040] Hereinafter, a display apparatus of the present specification will be described with reference to the following drawings and embodiments.

[0041] Figure 1 is a plan view of a display apparatus according to one embodiment.

[0042] Referring to Figure 1 The display apparatus 1 according to one embodiment can include a display panel 100. The display panel 100 can include a display area DA including a plurality of pixels PX and a non-display area NDA surrounding the display area DA. A flat surface shape of the display area DA can have a rectangular shape. However, embodiments of the present specification are not limited thereto, and the flat surface shape of the display area DA can be a square shape, a circular shape, an elliptical shape, or other polygonal shapes. For example, the display area DA can have a rectangular shape with rounded corners, but is not limited thereto, and can also have a rectangular shape with angled corners.

[0043] In an embodiment, the first direction DR1 and the second direction DR2 are different directions and intersect each other, for example, directions that perpendicularly intersect in a plan view. In Figure 1 In an embodiment, the first direction DR1 can be substantially the same as an extension direction of a short side of the display panel 100, and the second direction DR2 can be the same as an extension direction of a long side of the display panel 100. However, the directions described in the embodiments should be understood to indicate relative directions, and the embodiments are not limited to the described directions.

[0044] The display area DA can include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA can surround the display area DA. The non-display area NDA can be provided on one side and the other side in the first direction DR1 of the display area DA, and on one side and the other side in the second direction DR2 of the display area DA.

[0045] The display panel 100 can further include a sensor non-display area NDA_S and sensor holes SH surrounded by the sensor non-display area NDA_S. In a plan view, the sensor holes SH1 and SH2 can be surrounded by the display area DA. The sensor holes SH1 and SH2 can be, for example, Figure 1 two sensor holes in the embodiment of the present specification, but the embodiments of the present specification are not limited thereto. For example, the sensor holes can be provided as one sensor hole. The two sensor holes SH1 and SH2 can each include a sensor hole in which an infrared sensor is provided and a sensor hole in which a camera sensor is provided, but the embodiments of the present specification are not limited thereto. The sensor non-display area NDA_S can be provided between the sensor holes SH1 and SH2 and the display area DA. The sensor non-display area NDA_S can completely surround the sensor holes SH1 and SH2. The pixels PX can not be provided in the sensor non-display area NDA_S.

[0046] The gate driving unit GIP can be provided in the non-display area NDA at one side and the other side in the first direction DR1 of the display area DA. The low potential voltage line VSSL can be provided outside the gate driving unit GIP on the non-display area NDA. For example, as Figure 1 indicated in FIG. 1B, the low potential voltage line VSSL can extend from the printed circuit board FPCB, pass through the sub area SR and the bending area BR, can be located outside the gate driving unit GIP on the non-display area NDA, and be provided to surround the display area DA.

[0047] The non-display area NDA located on the other side of the second direction DR2 of the display area DA can extend further from the center portion of the other side of the second direction DR2 of the display area DA toward the other side of the second direction DR2. The width of the non-display area NDA extending further from the center portion of the other side of the second direction DR2 of the display area DA toward the other side of the second direction DR2 in the first direction DR1 can be smaller than the width of the non-display area NDA adjacent to the other side of the second direction DR2 of the display area DA in the first direction DR1.

[0048] Display device 1 may include a main region MR, a sub-region SR, and a curved region BR between the main region MR and the sub-region SR. A display region DA and a non-display region NDA surrounding the four surfaces of the display region DA may form the main region MR, and a portion extending from the center of the other side of the display region DA in a second direction DR2 towards that other side may form the curved region BR and the sub-region SR. The curved region BR may be disposed between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 located at the end of the sub-region SR in the second direction DR2. Display device 1 may also include a data driver unit DIC and a printed circuit board FPCB. The data driver unit DIC may be disposed in the first pad region PA1, and the printed circuit board FPCB may be attached to the second pad region PA2. A plurality of pads connected to the data driver unit DIC and the printed circuit board FPCB may be disposed in each of the first pad region PA1 and the second pad region PA2. The data driver unit (DIC) can be configured, for example, in the form of a driver chip (IC), but is not limited thereto. In one embodiment, a method for setting the data driver unit (DIC) by directly mounting it on a chip-on-plastic substrate on the display panel 100 is described, but the embodiments described herein are not limited thereto, and the data driver unit (DIC) can be set using a chip-on-glass or chip-on-film method.

[0049] According to one embodiment, the display panel 100 may further include a crack sensing pattern CSP surrounding a low-potential voltage line VSSL. For example... Figure 1 As shown, the crack sensing pattern CSP can be configured to completely surround the display area DA. For example, the crack sensing pattern CSP can be disposed outside the low-potential voltage line VSSL. However, the embodiments described in this specification are not limited to this, and a portion of the crack sensing pattern CSP may not be disposed in the non-display area NDA on the other side of the second direction DR2 of the display area DA.

[0050] Figure 2 is a cross-sectional view illustrating a bending state of a display panel according to an embodiment of the disclosure. Figure 1

[0051] Referring to Figure 2 , a bending area BR of a display panel 100 of a display apparatus 1 according to an embodiment can be bent in a thickness direction (or a third direction DR3). Accordingly, a main area MR and a sub area SR can overlap each other in the thickness direction. The display panel 100 can be bent in a manner that a lower surface of the main area MR faces an upper surface of the sub area SR. A printed circuit board FPCB can be attached to an end portion of the sub area SR.

[0052] Figure 3 is a cross-sectional view along line A-A' in Figure 1

[0053] Referring to Figure 3 , a pixel PX (see Figure 1 ) of the display panel 100 can include a plurality of sub-pixels PX1, PX2, and PX3. The first sub-pixel PX1 can be a red sub-pixel, the second sub-pixel PX2 can be a green sub-pixel, and the third sub-pixel PX3 can be a blue sub-pixel, but embodiments of the disclosure are not limited thereto. In some embodiments, the pixel PX further includes a fourth sub-pixel, and the fourth sub-pixel can be a white sub-pixel, but embodiments of the disclosure are not limited thereto. In some embodiments, the pixel can include one red sub-pixel, two green sub-pixels, and one blue sub-pixel, but embodiments of the disclosure are not limited thereto. For example, the plurality of sub-pixels PX1, PX2, and PX3 can be arranged in a stripe manner in the first direction DR1, but are not limited thereto, and can be arranged in a pentile manner.

[0054] The display panel 100 can include a substrate 101, a first thin film transistor 120, a second thin film transistor 130, a light emitting part 150, an encapsulating part 170, a touch part 180, a color filter insulating layer 114, a black matrix BM, color filters 191, 192, and 193, and a planarization layer OC. The display panel 100 can include at least one panel insulating layer between the substrate 101 and the light emitting part 150 and at least one touch insulating layer. The at least one panel insulating layer can include at least one of a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a 3-1 insulating layer 105-1, a 3-2 insulating layer 105-2, a fourth insulating layer 106, a fifth insulating layer 108, a sixth insulating layer 109, a first protection layer 111, and a second protection layer 112, and the at least one touch insulating layer can include at least one of a touch buffer layer 181, a first touch insulating layer 183, and a second touch insulating layer 184.

[0055] ​​The substrate 101 can include one or more plastic materials. For example, the substrate 101 can be a multi-substrate including a plurality of plastic materials such as polyimide or the like. For example, the substrate 101 can include a first substrate portion 101a and a second substrate portion 101b each including a plastic material, and a third substrate portion 101c including an inorganic insulating material between the first substrate portion 101a and the second substrate portion 101b, but embodiments of the present specification are not limited thereto.

[0056] A buffer layer 102 can be provided on the substrate 101. The buffer layer 102 can minimize or delay diffusion of moisture or oxygen permeating the substrate 101. The buffer layer 102 can be formed by alternately stacking silicon nitride (SiN x ) and silicon oxide (SiO x ) at least once, but embodiments of the present specification are not limited thereto.

[0057] A first light shielding layer 126 can be provided on the buffer layer 102. The first light shielding layer 126 can prevent light from being transmitted through the first semiconductor layer 123 of the first thin film transistor 120. For example, the first semiconductor layer 123 can be disposed to overlap the first light shielding layer 126. The first light shielding layer 126 can be formed of a single layer or a plurality of layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but embodiments of the present specification are not limited thereto.

[0058] A first insulating layer 103 can be provided on the buffer layer 102 and the first light shielding layer 126. The first insulating layer 103 can prevent a short circuit between components of the first thin film transistor 120 and the first light shielding layer 126. The first insulating layer 103 can be formed of the same material as the buffer layer 102, but embodiments of the present specification are not limited thereto. For example, the first insulating layer 103 can be formed of an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ), but embodiments of the present specification are not limited thereto.

[0059] The first thin film transistor 120 can be provided on the first insulating layer 103. The first thin film transistor 120 can include a first source electrode 121, a first gate electrode 122, a first semiconductor layer 123, and a first drain electrode 124.

[0060] The first semiconductor layer 123 can be provided on the first insulating layer 103. The first semiconductor layer 123 can include a metal oxide semiconductor such as indium gallium zinc oxide (IGZO) and a silicon-based semiconductor material such as amorphous silicon, polysilicon, or the like, but embodiments of the present specification are not limited thereto. The first semiconductor layer 123 can include a channel region, a source region, and a drain region.

[0061] Since the polycrystalline semiconductor layer has higher mobility than the amorphous semiconductor layer and the oxide semiconductor layer, power consumption can be lower and reliability can be excellent. Thus, the driver transistor can be formed of the polycrystalline semiconductor layer.

[0062] The second insulating layer 104 can be provided over the first semiconductor layer 123. The second insulating layer 104 can be formed of the same material as the first insulating layer 103, and can prevent short-circuiting between the first semiconductor layer 123 and another component of the first thin film transistor 120.

[0063] The first gate electrode 122 can be provided over the second insulating layer 104. The first gate electrode 122 can be provided over the second insulating layer 104 so as to overlap with the channel region of the first semiconductor layer 123. The first gate electrode 122 can be formed of a single layer or a plurality of layers formed of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof, but embodiments of the present specification are not limited thereto. The first gate electrode 122 can be provided together with a gate line.

[0064] The third insulating layers 105-1 and 105-2 can be provided over the first gate electrode 122. The third insulating layers 105-1 and 105-2 can be formed by alternately stacking silicon nitride (SiN x ) and silicon oxide (SiO x ) at least once, but embodiments of the present specification are not limited thereto. For example, the 3-1 insulating layer 105-1 can include silicon oxide (SiO x ), and the 3-2 insulating layer 105-2 can include silicon nitride (SiN x ), but embodiments of the present specification are not limited thereto.

[0065] The first source electrode 121 and the first drain electrode 124 can be provided over the third insulating layers 105-1 and 105-2.

[0066] The first source electrode 121 and the first drain electrode 124 can be electrically connected to the first semiconductor layer 123 through a contact hole. The first source electrode 121 and the first drain electrode 124 can be formed of a metal material. For example, the first source electrode 121 and the first drain electrode 124 can be formed of a single layer or a plurality of layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but embodiments of the present specification are not limited thereto.

[0067] The first source electrode 121 and the first drain electrode 124 can be provided together with a data line. For example, the data line can be formed of the same material as the first source electrode 121 and the first drain electrode 124, and formed on the same layer as the first source electrode 121 and the first drain electrode 124, but embodiments of the present specification are not limited thereto.

[0068] The storage electrode 140 can be provided to be spaced apart from the first thin film transistor 120. The storage electrode 140 can include a first storage electrode 141 and a second storage electrode 142.

[0069] The first storage electrode 141 can be formed of the same material as the first gate electrode 122, and provided on the same layer as the first gate electrode 122, but embodiments of the present specification are not limited thereto.

[0070] The second storage electrode 142 can be provided on the first storage electrode 141. The second storage electrode 142 can be provided on the third insulating layers 105-1 and 105-2, and the third insulating layers 105-1 and 105-2 between the first storage electrode 141 and the second storage electrode 142 can serve as a dielectric to generate a capacitance. The second storage electrode 142 can be formed of the same material as the first storage electrode 141, but embodiments of the present specification are not limited thereto.

[0071] The second thin film transistor 130 can be provided to be spaced apart from the first thin film transistor 120 and the storage electrode 140. The second thin film transistor 130 can include a second source electrode 131, a second gate electrode 132, a second semiconductor layer 133, and a second drain electrode 134.

[0072] The second light shielding layer 136 can be provided on the same layer as the second storage electrode 142.

[0073] Similar to the first light shielding layer 126, the second light shielding layer 136 can prevent light from traveling to the second semiconductor layer 133, thereby extending the lifespan of the second thin film transistor 130. For example, the second semiconductor layer 133 can be provided to overlap the second light shielding layer 136.

[0074] The fourth insulating layer 106 can be provided on the second light shielding layer 136. The fourth insulating layer 106 can be formed of the same material as the first insulating layer 103, the second insulating layer 104, or the third insulating layers 105-1 and 105-2, but embodiments of the present specification are not limited thereto.

[0075] The second semiconductor layer 133 can be provided on the fourth insulating layer 106. The second semiconductor layer 133 can include a source region, a drain region, and a channel region between the source region and the drain region.

[0076] The second semiconductor layer 133 can include a metal oxide semiconductor such as indium gallium zinc oxide (IGZO) and a silicon-based semiconductor material such as amorphous silicon, polysilicon, or the like, but embodiments of the present specification are not limited thereto.

[0077] The fifth insulating layer 108 can be provided on the second semiconductor layer 133. The fifth insulating layer 108 can be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2, or the fourth insulating layer 106, but embodiments of the present specification are not limited thereto.

[0078] The second gate electrode 132 can be provided on the fifth insulating layer 108.

[0079] The second gate electrode 132 can be formed of the same material as the first gate electrode 122. For example, the second gate electrode 132 can be formed of a single layer or a plurality of layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof, but embodiments of the present specification are not limited thereto.

[0080] The sixth insulating layer 109 can be provided on the second gate electrode 132. The sixth insulating layer 109 can be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2, the fourth insulating layer 106, or the fifth insulating layer 108, but embodiments of the present specification are not limited thereto.

[0081] The first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134 can be provided on the sixth insulating layer 109.

[0082] The second source electrode 131 and the second drain electrode 134 can be formed of the same material as the first source electrode 121 and the first drain electrode 124, and provided on the same layer as the first source electrode 121 and the first drain electrode 124, but embodiments of the present specification are not limited thereto. For example, the second source electrode 131 and the second drain electrode 134 can be formed of a single layer or a plurality of layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but embodiments of the present specification are not limited thereto. For example, the second source electrode 131 can be electrically connected to the second storage electrode 142. The second source electrode 131 can pass through the sixth insulating layer 109, the fifth insulating layer 108, and the fourth insulating layer 106, and can be electrically connected to the second storage electrode 142.

[0083] The first thin film transistor 120 can be a driving transistor, and the second thin film transistor 130 can be a switching transistor, but embodiments of the present specification are not limited thereto.

[0084] A first protective layer 111 can be provided on the first source electrode 121 and the first drain electrode 124.

[0085] The first protective layer 111 can planarize an upper portion of the first thin film transistor 120 and protect the first thin film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin, but embodiments of the present specification are not limited thereto.

[0086] A second protective layer 112 can be provided on the first protective layer 111. The second protective layer 112 can be formed of the same material as the first protective layer 111, but embodiments of the present specification are not limited thereto.

[0087] In some embodiments, a third protective layer can also be provided on an upper surface of the second protective layer 113, but embodiments of the present specification are not limited thereto.

[0088] A connection electrode 145 can be provided between the first protective layer 111 and the second protective layer 112.

[0089] The connection electrode 145 can electrically connect the first thin film transistor 120 to the light emitting portion 150. The connection electrode 145 can be formed of the same material as the first source electrode 121 and the first drain electrode 124, but embodiments of the present specification are not limited thereto.

[0090] The connection electrode 145 can be formed of a single layer or a plurality of layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but embodiments of the present specification are not limited thereto.

[0091] The light emitting portion 150 can be provided on the second protective layer 112. The light emitting portion 150 can include a first electrode 151, an organic layer 152, and a second electrode 153. The first electrode 151 can function as an anode, and the second electrode 153 can function as a cathode.

[0092] A first electrode 151 can be provided on the second protective layer 112. The first electrode 151 can be electrically connected to the first thin film transistor 120 through a contact hole formed in the second protective layer 112. The first electrode 151 can be a reflective electrode that reflects light, but embodiments of the present specification are not limited thereto. The first electrode 151 can include a metal material having high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and can be formed of a single layer or a plurality of layers, but embodiments of the present specification are not limited thereto.

[0093] An organic layer 152 can be provided on the first electrode 151. The organic layer 152 can include one or more light emitting structures (or one or more light emitting elements) stacked on the first electrode 151 in the order of a hole transfer layer and an electron transfer layer or in the reverse order. For example, the hole transfer layer can include a hole transport layer, a hole injection layer, an electron blocking layer, a p-type charge generation layer, or the like, but embodiments of the present specification are not limited thereto. For example, the electron transfer layer can include an electron transport layer, an electron injection layer, a hole blocking layer, an n-type charge generation layer, or the like, but embodiments of the present specification are not limited thereto. The organic layer 152 can be an organic light emitting layer, an inorganic light emitting layer, a quantum dot light emitting layer, a micro light emitting diode, or a micro mini light emitting diode, or the like, but embodiments of the present specification are not limited thereto. For example, the organic layer 152 of the display panel 100 according to an embodiment of the present specification can include an organic light emitting layer. The organic layer 152 can include a red light emitting layer, a green light emitting layer, and a blue light emitting layer. The organic layer 152 can be a white light emitting layer, but embodiments of the present specification are not limited thereto. Hereinafter, a specific structure of the organic layer 152 according to an embodiment will be described.

[0094] Figure 4 is Figure 3 a specific cross-sectional view of the light emitting part.

[0095] Referring to Figure 4 , the light emitting part 150 can include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3.

[0096] The thickness of the light emitting part 150 in each of the sub-pixels PX1, PX2, or PX3 can be different, but embodiments of the present specification are not limited thereto, and the thickness of the light emitting part 150 in each of the sub-pixels PX1, PX2, or PX3 can be the same.

[0097] The organic layer 152 can include a first organic layer 152a disposed in the first sub-pixel PX1, a second organic layer 152b disposed in the second sub-pixel PX2, and a third organic layer 152c disposed in the third sub-pixel PX3. The emission layers EML1, EML2, and EML3 in the organic layers 152a, 152b, and 152c can be physically separated, but lower and upper layers of the emission layers EML1, EML2, and EML3 can be integrally formed across the sub-pixels PX1, PX2, and PX3. The thickness of each of the emission layers EML1, EML2, or EML3 can be different. For example, the thickness of the first emission layer EML1 can be the greatest, the thickness of the second emission layer EML2 can be the second greatest, and the thickness of the third emission layer EML3 can be the least, but embodiments of the present specification are not limited thereto.

[0098] A hole injection layer HIL can be disposed on the first electrode 151. The hole injection layer HIL can be located between the first electrode 151 and the emission layers EML1, EML2, and EML3. The hole injection layer HIL can be integrally formed across the sub-pixels PX1, PX2, and PX3. For example, the hole injection layer HIL can be formed of a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(biphenyl-4-yl)-9,9-dimethyl-N-(4-(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine, and the like, but embodiments of the present specification are not limited thereto.

[0099] A hole transport layer HTL can be disposed on the hole injection layer HIL. The hole transport layer HTL can be located between the hole injection layer HIL and the emission layers EML1, EML2, and EML3. The hole transport layer HTL can be integrally formed across the sub-pixels PX1, PX2, and PX3. The hole transport layer HTL can be formed of one or more materials selected from the group including arylamine-based materials, such as NPB (N,N-naphthyl-N,N'-phenylphenylamine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-phenylamine), PPD, TTBND, FFD, p-dmDPS, and TAPC; starburst arylamine-based materials, such as TCTA, PTDATA, TDAPB, TDBA, 4-a, and TCTA; spiro and ladder materials, such as spiro-TPD, spiro-mTTB, and spiro-2, and NPD (N,N-dinaphthyl-N,N'-diphenylphenylamine), s-TAD, and MTDATA (4,4',4"-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine), but embodiments of the present specification are not limited thereto.

[0100] The light emitting layers EML1, EML2, and EML3 can be provided on the hole transport layer HTL. The first light emitting layer EML1 can be provided in the first sub-pixel PX1, the second light emitting layer EML2 can be provided in the second sub-pixel PX2, and the third light emitting layer EML3 can be provided in the third sub-pixel PX3.

[0101] The thickness of each light emitting layer EML1, EML2, or EML3 can be different. For example, the first light emitting layer EML1 can be formed with a thickness of to , the second light emitting layer EML2 can be formed with a thickness of to , and the third light emitting layer EML3 can be formed with a thickness of to , but embodiments of the present specification are not limited thereto.

[0102] Each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 can include a material that can emit light in the visible light range by receiving and combining holes and electrons.

[0103] An electron blocking layer EBL can be provided on each light emitting layer EML1, EML2, or EML3. The electron blocking layer EBL can be integrally provided across the sub-pixels PX1, PX2, and PX3.

[0104] An electron transport layer ETL can be provided on the electron blocking layer EBL. The electron transport layer ETL can be integrally provided across the sub-pixels PX1, PX2, and PX3. The electron transport layer ETL can be formed of an anthracene derivative and lithium quinolate (Liq), or formed of one or more selected from oxadiazole, triazole, phenanthroline, benzoxazole, benzothiazole, or benzimidazole (for example, 2-[4-(9,10-di-2-naphthyl-2-anthryl)phenyl]-1-phenyl-1H-benzimidazole), but embodiments of the present specification are not limited thereto.

[0105] A second electrode 153 can be provided on the electron transport layer ETL.

[0106] Figure 5 is a detailed cross-sectional view of a light emitting portion according to a modification example.

[0107] Referring to Figure 4 and Figure 5 , the organic layer 152_1 can include a first organic layer 152a_1 provided in the first sub-pixel PX1, a second organic layer 152b_1 provided in the second sub-pixel PX2, and a third organic layer 152c_1 provided in the third sub-pixel PX3.

[0108] The light emitting layer of each organic layer 152a_1, 152b_1, or 152c_1 can be physically separated, but the lower and upper layers of the light emitting layer can be integrally formed across the sub-pixels PX1, PX2, and PX3. The thickness of each light emitting layer can be different. For example, the thickness of the first light emitting layer of the first sub-pixel can be the greatest, the thickness of the second light emitting layer of the second sub-pixel can be the second greatest, and the thickness of the third light emitting layer of the third sub-pixel can be the least, but embodiments of the present specification are not limited thereto. In addition, the light emitting layer of each organic layer 152a_1, 152b_1, or 152c_1 can be provided as two or more light emitting layers.

[0109] A hole injection layer HIL can be provided on the first electrode 151. The hole injection layer HIL can be located between the first electrode 151 and the light emitting layers EML1a, EML2a, and EML3a. The hole injection layer HIL can be integrally formed across the sub-pixels PX1, PX2, and PX3. For example, the hole injection layer HIL can be formed of a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(biphenyl-4-yl)-9,9-dimethyl-N-(4-(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine, and the like, but embodiments of the present specification are not limited thereto.

[0110] A first hole transport layer HTL1 can be provided on the hole injection layer HIL. The first hole transport layer HTL1 can be located between the hole injection layer HIL and the light emitting layers EML1a, EML2a, and EML3a. The first hole transport layer HTL1 can be integrally formed across the sub-pixels PX1, PX2, and PX3. The first hole transport layer HTL1 can be formed of one or more materials selected from the group including arylamine-based materials, such as NPB (N,N-naphthyl-N,N'-phenylphenylamine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-phenylamine), PPD, TTBND, FFD, p-dmDPS, and TAPC; starburst arylamine-based materials, such as TCTA, PTDATA, TDAPB, TDBA, 4-a, and TCTA; spiro and ladder materials, such as spiro-TPD, spiro-mTTB, and spiro-2, and NPD (N,N-dinaphthyl-N,N'-diphenylphenylamine), s-TAD, and MTDATA (4,4',4"-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine), but embodiments of the present specification are not limited thereto.

[0111] The light-emitting layers EML1a, EML2a, and EML3a can be disposed on the first hole transport layer HTL1. The 1-1 light-emitting layer EML1a can be disposed in the first sub-pixel PX1, the 2-1 light-emitting layer EML2a can be disposed in the second sub-pixel PX2, and the 3-1 light-emitting layer EML3a can be disposed in the third sub-pixel PX3. Each of the light-emitting layers EML1a, EML2a, and EML3a can be the same as each of the light-emitting layers EML1, EML2, and EML3 of the light-emitting device 1000. Figure 4

[0112] The thickness of each of the light-emitting layers EML1a, EML2a, or EML3a can be different. For example, the 1-1 light-emitting layer EML1a can be formed with a thickness of to , the 2-1 light-emitting layer EML2a can be formed with a thickness of to , and the 3-1 light-emitting layer EML3a can be formed with a thickness of to , but embodiments of the present specification are not limited thereto.

[0113] The hole blocking layer HBL can be disposed on each of the light-emitting layers EML1a, EML2a, or EML3a. The hole blocking layer HBL can be integrally disposed across the sub-pixels PX1, PX2, and PX3.

[0114] The first electron transport layer ETL1 can be disposed on the hole blocking layer HBL. The first electron transport layer ETL1 can be integrally formed across the sub-pixels PX1, PX2, and PX3. The first electron transport layer ETL1 can be formed of an anthracene derivative and lithium quinolate (Liq), or one or more selected from an oxadiazole, a triazole, a phenanthroline, a benzoxazole, a benzothiazole, or a benzimidazole (for example, 2-[4-(9,10-di-2-naphthyl-2-anthryl)phenyl]-1-phenyl-1H-benzimidazole), but embodiments of the present specification are not limited thereto.

[0115] The common charge layer CGL can be disposed on the first electron transport layer ETL1. The common charge layer CGL can be disposed between the first electron transport layer ETL1 and the second hole transport layer HTL2. The common charge layer CGL can include a conductive material, but embodiments of the present disclosure are not limited thereto.

[0116] ​A second hole transport layer HTL2 can be disposed on the common charge generation layer CGL. The second hole transport layer HTL2 can be disposed between the hole blocking layer HBL and the light emitting layers EML1b, EML2b, and EML3b. The second hole transport layer HTL2 can be integrally formed across the sub-pixels PX1, PX2, and PX3. The material of the second hole transport layer HTL2 can be the same as that of the first hole transport layer HTL1, but embodiments of the present specification are not limited thereto.

[0117] The light emitting layers EML1b, EML2b, and EML3b can be disposed on the second hole transport layer HTL2. The 1-2 light emitting layer EML1b can be disposed in the first sub-pixel PX1, the 2-2 light emitting layer EML2b can be disposed in the second sub-pixel PX2, and the 3-2 light emitting layer EML3b can be disposed in the third sub-pixel PX3. Each of the light emitting layers EML1b, EML2b, and EML3b can be the same as each of the light emitting layers EML1a, EML2a, and EML3a.

[0118] The thickness of each of the light emitting layers EML1b, EML2b, or EML3b can be different. For example, the 1-2 light emitting layer EML1b can be formed with a thickness of to , the 2-2 light emitting layer EML2b can be formed with a thickness of to , and the 3-2 light emitting layer EML3b can be formed with a thickness of to , but embodiments of the present specification are not limited thereto.

[0119] An electron blocking layer EBL can be disposed on each of the light emitting layers EML1b, EML2b, or EML3b. The electron blocking layer EBL can be integrally disposed across the sub-pixels PX1, PX2, and PX3.

[0120] A second electron transport layer ETL2 can be disposed on the electron blocking layer EBL. The second electron transport layer ETL2 can be integrally formed across the sub-pixels PX1, PX2, and PX3. The second electron transport layer ETL2 can be formed of an anthracene derivative and lithium quinolate (Liq), or one or more selected from an oxadiazole, a triazole, a phenanthroline, a benzoxazole, a benzothiazole, or a benzimidazole (for example, 2-[4-(9,10-di-2-naphthyl-2-anthryl)phenyl]-1-phenyl-1H-benzimidazole), but embodiments of the present specification are not limited thereto.

[0121] A second electrode 153 can be disposed on the second electron transport layer ETL2.

[0122] Referring back to Figure 3The second electrode 153 can be provided on the organic layer 152. The second electrode 153 can be a transparent electrode that transmits light, but embodiments of the present specification are not limited thereto. For example, the second electrode 153 can include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal that transmits visible light, but embodiments of the present specification are not limited thereto.

[0123] The bank 154 can be provided to expose the first electrode 151. The bank 154 can define openings (or light emitting areas EA1, EA2, and EA3) of the subpixels PX1, PX2, and PX3, and can be provided to cover an edge portion (or a periphery) of the first electrode 151. That is, the first subpixel PX1 can include the first light emitting area EA1 and a first non-light emitting area NEA1 surrounding the first light emitting area EA1, the second subpixel PX2 can include the second light emitting area EA2 and a second non-light emitting area NEA2 surrounding the second light emitting area EA2, and the third subpixel PX3 can include the third light emitting area EA3 and a third non-light emitting area NEA3 surrounding the third light emitting area EA3. That is, each of the non-light emitting areas NEA1, NEA2, or NEA3 can correspond to a boundary between adjacent subpixels PX1, PX2, and PX3.

[0124] The bank 154 can include a first bank 154a and a second bank 154b. In the present specification, the second bank 154b can also be referred to as a bank pattern, but embodiments of the present specification are not limited thereto.

[0125] The first bank 154a can include a black-based material. For example, the first bank 154a can be formed of a material containing a black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, or the like, but embodiments of the present specification are not limited thereto. In the case where the first bank 154a is formed of a material containing a black pigment or a black dye, the first bank 154a can be a black bank. In the case where the first bank 154a is formed of a material containing a black pigment or a black dye, external light or light reflected from the outside can be shielded, thereby further increasing the brightness of the display apparatus.

[0126] The first bank 154a can include an upper surface and a side surface. The upper surface of the first bank 154a can be flat in a horizontal direction, and the side surface of the first bank 154a can be tapered in a thickness direction.

[0127] The second bank 154b can be provided on the side surface of the first bank 154a. The second bank 154b can expose a portion of the upper surface of the first bank 154a. The second bank 154b can expose the entire upper surface of the first bank 154a, but embodiments of the present specification are not limited thereto. The second bank 154b can not include a black-based material.

[0128] For example, as described above, the first bank 154a can suppress surface reflection of external light. For example, the first bank 154a can absorb external light by including a black-based material. That is, the first bank 154a can include a resin, a black-based material in the resin, an additive for dispersing the black-based material in the resin, or the like. For example, the resin can include an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, or the like, and the additive can be, for example, a dispersant, but embodiments of the present specification are not limited thereto.

[0129] The second bank 154b can include a material having a lower content of a black-based material than the material included in the first bank 154a, or can not include a black-based material at all. For example, the second bank 154b can be a transparent bank, but embodiments of the present specification are not limited thereto.

[0130] Hereinafter, optical density is introduced to distinguish the materials of the first bank 154a and the second bank 154b.

[0131] The concept that the bank 154 absorbs external light is related to optical density. The higher the optical density (hereinafter referred to as "OD") as an index of a specific material that absorbs light, the higher the light absorption rate. That is, the lower the OD, the higher the light transmittance. For example, OD can be calculated using 1 µm as a reference thickness and in proportion to the thickness. Hereinafter, OD calculated using 1 µm as a reference thickness is referred to as "reference OD".

[0132] Since the second bank 154b includes less or no black-based material compared to the first bank 154a, the reference OD of the first bank 154a can be higher than that of the second bank 154b.

[0133] A barrier RAS can also be provided on the first bank 154a. As shown in Figure 3 The barrier RAS can be provided at all boundaries NEA1, NEA2, and NEA3 between the sub-pixels PX1, PX2, and PX3, but embodiments of the present specification are not limited thereto. The barrier RAS can be directly provided on the upper surface of the first bank 154a, but embodiments of the present specification are not limited thereto. The barrier RAS can serve to separate the organic layer 152 from the boundaries of the adjacent sub-pixels PX1, PX2, and PX3. In some embodiments, the barrier layer RAS is not provided, and a trench can be formed on the first bank 154a. The first bank 154a can be recessed in the thickness direction by the trench.

[0134] A spacer 155 can be further provided on the first bank 154a. The spacer 155 can be formed of the same material as the second bank 154b, but embodiments of the present specification are not limited thereto. For example, the spacer 155 can be a transparent bank, but is not limited thereto, and can be formed of the same material as the first bank 154a. For example, the spacer 155 can be provided on at least one of the boundaries of the first to third sub-pixels PX1, PX2, and PX3, but embodiments of the present specification are not limited thereto. The second bank 154b and the spacer 155 can be formed of the same material and formed at the same time through a half-tone mask or a slit, but embodiments of the present specification are not limited thereto.

[0135] The organic layer 152 can be provided on the first electrode 151, the bank 154, and the spacer 155. The second electrode 153 can be provided on the organic layer 152.

[0136] The encapsulation part 170 can be provided on the second electrode 153. The encapsulation part 170 can include one or more insulating layers. For example, the encapsulation part 170 can include a first encapsulation layer 171, a second encapsulation layer 172 provided on the first encapsulation layer 172, and a third encapsulation layer 173 provided on the second encapsulation layer 172. The encapsulation part 170 can include one or more inorganic insulating material layers and one or more organic material layers. For example, the first encapsulation layer 171 and the third encapsulation layer 173 can include an inorganic insulating material, and the second encapsulation layer 172 can include an organic material, but embodiments of the present specification are not limited thereto.

[0137] The touch part 180 can be provided on the encapsulation part 170. The touch part 180 can include a touch buffer layer 181, a first touch conductive layer, a first touch insulating layer 183, a second touch insulating layer 184, and a second touch conductive layer. In some embodiments, one or more touch organic layers can be further provided on the second touch conductive layer, but embodiments of the present specification are not limited thereto.

[0138] Figure 6 is a cross-sectional view of a touch part according to Figure 3

[0139] Referring to Figure 3 and Figure 6 The touch buffer layer 181 can be provided on the encapsulation part 170. For example, the touch buffer layer 181 can be provided on the third encapsulation layer 173. The touch buffer layer 181 can be formed of the same material as the buffer layer 102, but embodiments of the present specification are not limited thereto.

[0140] ​The first touch conductive layer can be disposed on the touch buffer layer 181. The first touch conductive layer can include a bridge electrode 182. The bridge electrode 182 and the sensor electrode 185 to be described below can be disposed at each of the boundaries between the adjacent sub-pixels PX1, PX2, and PX3. For example, the bridge electrode 182 and the sensor electrode 185 can be disposed in the non-emitting areas NEA1, NEA2, and NEA3. The bridge electrode 182 and the sensor electrode 185 can overlap the black matrix BM to be described below in a thickness direction. The black matrix BM can cover the bridge electrode 182 and the sensor electrode 185. Accordingly, the bridge electrode 182 and the sensor electrode 185 can be prevented from being visible from the outside.

[0141] The first touch insulating layer 183 and the second touch insulating layer 184 disposed on the first touch insulating layer 183 can be disposed on the first touch conductive layer. The first touch insulating layer 183 and the second touch insulating layer 184 disposed thereon can prevent short circuiting between the first touch conductive layer and the second touch conductive layer. The first touch insulating layer 183 can be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), or a plurality of layers thereof, but embodiments of the present specification are not limited thereto. The second touch insulating layer 184 can include an organic insulating material, but embodiments of the present specification are not limited thereto, and the second touch insulating layer 184 can include the same material as the first touch insulating layer 183.

[0142] The second touch conductive layer can be disposed on the second touch insulating layer 184. The second touch conductive layer can include a first sensor electrode 185a and a second sensor electrode 185b. The sensor electrode 185 can include the first sensor electrode 185a extending in a first direction DR1 (see Figure 1 ) and the second sensor electrode 185b extending in a second direction DR2 (see Figure 1 ) different from the first direction DR1.

[0143] The bridge electrode 182 can be electrically connected to the first sensor electrode 185a through a contact hole formed in the first touch insulating layer 183 and the second touch insulating layer 184. For example, the first sensor electrode 185a and the bridge electrode 182 can extend in the first direction DR1 (see Figure 1 ).

[0144] The sensor electrode 185 and the bridge electrode 182 can include a metal material. For example, the sensor electrode 185 and the bridge electrode 182 can be formed of titanium (Ti), nickel (Ni), aluminum (Al), or an alloy thereof, and formed of three layers such as titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of the present specification are not limited thereto.

[0145] Referring back toFigure 3 A filter insulating layer 114 can be disposed on the second touch conductive layer. The filter insulating layer 114 can be formed of an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO x ), but embodiments of the present specification are not limited thereto.

[0146] A black matrix BM can be disposed on the filter insulating layer 114. The black matrix BM can include a black-based material. For example, the black matrix BM can include a light-blocking material or a light-absorbing material. For example, the black matrix BM can be formed of a material including a black pigment, a black dye, or the like. The black matrix BM can cover the bridge electrode 182 and the sensor electrode 185. Accordingly, it is possible to prevent the bridge electrode 182 and the sensor electrode 185 from being visible from the outside. For example, a width of the black matrix BM can be less than a width of the bank 154.

[0147] For example, the interval distance between the end portion of the black matrix BM and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3 can be greater than the interval distance between the end portion of the bank 154 and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3. The end portion of the bank 154 can be aligned with the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3, but embodiments of the present specification are not limited thereto. In the case of the display panel 100 according to one embodiment, since the bank 154 can include a black-based material and the interval distance between the end portion of the black matrix BM and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3 can be greater than the interval distance between the end portion of the bank 154 and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3, light emitted from the light emitting areas EA1, EA2, and EA3 can be emitted upward with the same angle of view as the interval space between the end portion of the black matrix BM and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3. Thus, a decrease in luminance can be minimized according to the angle of view. However, in the case where the interval distance between the end portion of the black matrix BM and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3 can be greater than the interval distance between the end portion of the bank 154 and the boundary between the light emitting areas EA1, EA2, and EA3 and the non-light emitting areas NEA1, NEA2, and NEA3, and the bank 154 is formed of only a transparent material, light incident from the outside can be reflected by the bank 154, thereby generating a visible ring-shaped spot. However, in the case of the display panel 100 according to one embodiment, light incident from the outside can be absorbed or blocked by the bank 154 including a black-based material, thereby preventing the occurrence of a ring-shaped spot.

[0148] The color filters 191, 192, and 193 can be disposed on the black matrix BM. The color filters 191, 192, and 193 can be disposed on the first to third sub-pixels PX1, PX2, and PX3, respectively, and can block specific colors in light emitted from the light emitting areas EA1, EA2, and EA3 of the sub-pixels PX1, PX2, and PX3. The first color filter 191 can be provided to block light of other colors except for red (R) light. In this case, the first color filter 191 can be disposed as a red color filter. The second color filter 192 can be provided to block light of other colors except for green (G) light. In this case, the second color filter 192 can be disposed as a green color filter. The third color filter 193 disposed in the third sub-pixel PX3 can be provided to block light of other colors except for blue (B) light. In this case, the third color filter 193 can be disposed as a blue color filter. However, embodiments of the present specification are not limited thereto.

[0149] For example, each of the color filters 191, 192, or 193 can be in direct contact with the side surface and the upper surface of the black matrix BM. For example, each of the color filters 191, 192, or 193 can be spaced apart from the boundary of the adjacent sub-pixels PX1, PX2, and PX3, but embodiments of the present specification are not limited thereto, and the color filters 191, 192, and 193 can overlap each other in the thickness direction.

[0150] The planarization layer OC can be disposed on the color filters 191, 192, and 193. The planarization layer OC can be used to planarize a step formed by the color filters 191, 192, and 193. For example, the planarization layer OC can include an organic insulating material.

[0151] Figure 7 is a cross-sectional view taken along line B-B' of Figure 1

[0152] Referring to Figure 7 At least one of the panel inorganic layers 102, 103, 104, 105-1, 105-2, 106, 108, and 109 can not extend to the end portion of the substrate 101. That is, at least one of the panel inorganic layers 102, 103, 104, 105-1, 105-2, 106, 108, and 109 can expose the end portion of the substrate 101, but embodiments of the present specification are not limited thereto.

[0153] The display panel 100 according to one embodiment can further include a crack sensing pattern CSP, a low potential voltage line VSSL, and a gate driving unit GIP. As described above Figure 1 ​As described in the foregoing embodiments, the low-potential voltage line VSSL can be positioned between the crack sensing pattern CSP and the display region DA, and the gate driving unit GIP can be positioned between the low-potential voltage line VSSL and the display region DA.

[0154] For example, as Figure 7 illustrated in the foregoing embodiments, the gate driving unit GIP can be formed of a conductive layer positioned on the same layer as the first gate electrode 122 (see Figure 3 ), a conductive layer positioned on the same layer as the second light shielding layer 136 (see Figure 3 ), or a conductive layer positioned on the same layer as the first source electrode 121, but embodiments of the present specification are not limited thereto.

[0155] For example, the crack sensing pattern CSP can be provided between the first dam D1 and the second dam D2. The crack sensing pattern CSP can be formed of a conductive layer positioned on the same layer as the first gate electrode 122 (see Figure 3 ) or a conductive layer positioned on the same layer as the second light shielding layer 136 (see Figure 3 ). For example, the crack sensing pattern CSP can include a conductive layer positioned on the same layer as the first source electrode 121, but embodiments of the present specification are not limited thereto.

[0156] The low-potential voltage line VSSL can be provided between the crack sensing pattern CSP and the gate driving unit GIP. The low-potential voltage line VSSL can be formed of a conductive layer positioned on the same layer as the first source electrode 121, but embodiments of the present specification are not limited thereto.

[0157] The first protective layer 111 can cover the gate driving unit GIP, partially cover one end portion of the low-potential voltage line VSSL, and expose the other end portion of the low-potential voltage line VSSL. In the present specification, one end portion can refer to a region of a certain component positioned in a direction from the non-display region NDA toward the display region DA, and the other end portion can refer to a region of a certain component positioned in a direction from the display region DA toward the non-display region NDA.

[0158] The first connection electrode CNE1 positioned on the same layer as the connection electrode 145 can be provided on the first protective layer 111. The first connection electrode CNE1 can be directly connected to the region of the low-potential voltage line VSSL exposed by the first protective layer 111. The first connection electrode CNE1 can cover the other end portion of the low-potential voltage line VSSL, but embodiments of the present specification are not limited thereto.

[0159] The second protective layer 112 can be provided on the first connection electrode CNE1. The second protective layer 112 can be in direct contact with and cover one end portion of the first connection electrode CNE1, and expose the other end portion of the first connection electrode CNE1. The second protective layer 112 can form the first layer of the first dam D1 and the first layer of the second dam D2. The first dam D1 can overlap, for example, the low-potential voltage line VSSL, and cover the other end portion of the low-potential voltage line VSSL. The first dam D1 can be in direct contact with the first connection electrode CNE1, and cover the other end portion of the first connection electrode CNE1. The second protective layer 112 forming the first layer of the second dam D2 can be in direct contact with the exposed side surface of at least one of the panel inorganic layers 102, 103, 104, 105, 106, 107, and 109, and can be in direct contact with the upper surface of the substrate 101, but embodiments of the present specification are not limited thereto. The second protective layer 112 can overlap the gate drive unit GIP. In the present specification, for example, the dam is provided as two dams, but the dam can also be provided as three or more dams or one dam.

[0160] The low-potential connection electrode 151' located on the same layer as the first electrode 151 (see Figure 3 ) can be provided on the second protective layer 112 and the first connection electrode CNE1 exposed by the second protective layer 112. The low-potential connection electrode 151' can be electrically connected to the first connection electrode CNE1 exposed by the second protective layer 112. The low-potential connection electrode 151' can be electrically connected to the second electrode 153 (see Figure 3 ) described above in Figure 3 ).

[0161] The first dam 154a can be provided on the low-potential connection electrode 151' and the second protective layer 112. The first dam 154a can overlap the gate drive unit GIP, overlap the low-potential connection electrode 151', and cover the other end portion of the low-potential connection electrode 151'. The first dam 154a can completely cover the low-potential connection electrode 151', but embodiments of the present specification are not limited thereto. The first dam 154a can expose the central portion and the other end portion of the first connection electrode CNE1, but embodiments of the present specification are not limited thereto. The first dam 154a can form the second layer of the first dam D1 and the second layer of the second dam D2. In each dam D1 or D2, the first dam 154a can overlap and completely cover the second protective layer 112 forming the first layer, but embodiments of the present specification are not limited thereto. In the second dam D2, the first dam 154a can be in contact with the side surface of the second protective layer 112 and the upper surface of the substrate 101, but embodiments of the present specification are not limited thereto.

[0162] The spacer 155 can be disposed on the first bank 154a. The spacer 155 can overlap the gate driving unit GIP. The spacer 155 can form a third layer of the dam D1 and the dam D2. The spacer 155 forming the third layer of each of the dam D1 or the dam D2 can overlap and completely cover the first bank 154a forming the second layer, but embodiments of the present specification are not limited thereto. In the second dam D2, the spacer 155 can be in contact with the side surface of the first bank 154a and the upper surface of the substrate 101, but embodiments of the present specification are not limited thereto.

[0163] The encapsulation part 170 can be disposed on the spacer 155. The first encapsulation layer 171 can extend to the gate driving unit GIP, the low-potential voltage line VSSL, the first dam D1, and the second dam D2, and cover the outer surface of the second dam D2. The second encapsulation layer 172 can end at the first dam D1. The second encapsulation layer 172 can overlap the gate driving unit GIP and the low-potential voltage line VSSL. The third encapsulation layer 173 can extend to the gate driving unit GIP, the low-potential voltage line VSSL, the first dam D1, and the second dam D2, and be in direct contact with the first encapsulation layer 171 on the first dam D1, the crack sensing pattern CSP, and the second dam D2.

[0164] The touch buffer layer 181 and the first touch insulating layer 183 can extend to the gate driving unit GIP, the low-potential voltage line VSSL, the first dam D1, and the second dam D2, and cover the outer surface of the second dam D2. The second touch insulating layer 184 can extend to the gate driving unit GIP, the low-potential voltage line VSSL, the first dam D1, and the crack sensing pattern CSP, and end on the second dam D2, but embodiments of the present specification are not limited thereto.

[0165] The filter insulating layer 114 can extend to the gate driving unit GIP, the low-potential voltage line VSSL, the first dam D1, and the second dam D2, and be in direct contact with the outer surface of the second touch insulating layer 184, but embodiments of the present specification are not limited thereto.

[0166] Figure 8 is a cross-sectional view along a line C-C' in Figure 1 .

[0167] Referring to Figure 3 , Figure 7 and Figure 8 , a bending area BR can be disposed between the sub-area SR and the crack sensing pattern CSP. In the bending area BR, the panel inorganic layers 102, 103, 104, 105, 106, 107, and 109 can be removed to expose the upper surface of the substrate 101.

[0168] In the first pad area PA1, a first source electrode 121 (see FIG. 1) can be disposed to be in contact with the first gate electrode 122 (see FIG. 1). The first source electrode 121 can be disposed to be in contact with the first gate electrode 122 and the first drain electrode 123 (see FIG. 1).Figure 3 ) the same layer as the first source electrode 121 (see Figure 3 ) the third connection electrode CNE3 provided on the same layer as the first source electrode 121 (see

[0169] The first protective layer 111 can be provided on the pad electrode PAD and the third connection electrode CNE3. The first protective layer 111 can be provided in the bending region BR, and the first protective layer 111 can be in direct contact with the upper surface of the substrate 101 and in the bending region BR, the first protective layer 111 can be in direct contact with the side surfaces of the panel inorganic layers 102, 103, 104, 105, 106, 107, and 109.

[0170] The second connection electrode CNE2 can be provided on the first protective layer 111, and the second connection electrode CNE2 can be provided on the same layer as the connection electrode 145 (see Figure 3 ) the third connection electrode CNE3. The second connection electrode CNE2 can be provided on the bending region BR, and also on the first pad region PA1 and the crack sensing pattern CSP.

[0171] The data driving unit DIC can be provided on the pad electrode PAD. The data driving unit DIC can include the bump BUMP, the anisotropic conductive film ACF can be provided between the pad electrode PAD and the bump BUMP, and the anisotropic conductive film ACF can electrically connect the pad electrode PAD to the bump BUMP. The anisotropic conductive film ACF can include the resin RS and a plurality of conductive balls CB dispersed in the resin RS. The pad electrode PAD and the bump BUMP can be electrically connected by the conductive balls CB.

[0172] The second protective layer 112 can be provided on the second connection electrode CNE2. The second protective layer 112 can expose the pad electrode PAD.

[0173] The first encapsulation layer 171 and the third encapsulation layer 173 of the encapsulation portion 170 can extend up to before the bending region BR. For example, the first encapsulation layer 171 and the third encapsulation layer 173 can extend up to before the crack sensing pattern CSP, but embodiments of the present specification are not limited thereto, and the first encapsulation layer 171 and the third encapsulation layer 173 can also overlap the crack sensing pattern CSP. The first encapsulation layer 171 and the third encapsulation layer 173 can not be provided in the bending region BR.

[0174] The touch buffer layer 181 and the first touch insulating layer 183 can extend up to before the bending area BR. For example, the touch buffer layer 181 and the first touch insulating layer 183 can extend up to before the crack sensing pattern CSP, but embodiments of the present specification are not limited thereto, and the touch buffer layer 181 and the first touch insulating layer 183 can also overlap the crack sensing pattern CSP. The touch buffer layer 181 and the first touch insulating layer 183 can not be disposed in the bending area BR.

[0175] The second touch insulating layer 184 can overlap the first dam D1 and the second dam D2. The second touch insulating layer 184 can not be disposed outside the second dam D2, but embodiments of the present specification are not limited thereto.

[0176] The touch connection line 185' can be electrically connected to the second connection electrode CNE2. The touch connection line 185' can be used to provide a signal applied from the pad electrode PAD and the second connection electrode CNE2 to the first sensor electrode 185a or the second sensor electrode 185b described above in the first sensor electrode 185a or the second sensor electrode 185b. The touch connection line 185' can be located on the same layer as the first sensor electrode 185a of the second touch conductive layer (182), but embodiments of the present specification are not limited thereto, the touch connection line 185' can be located on the same layer as the bridge electrode 182 of the first touch conductive layer (181), or be formed of two first touch conductive layers and second touch conductive layers, but embodiments of the present specification are not limited thereto. Figure 3 Figure 6 Figure 3

[0177] The filter insulating layer 114 can be disposed on the touch connection line 185', and the filter insulating layer 114 can not be disposed in the bending area BR.

[0178] Figure 9 is Figure 3 an enlarged sectional view of the area Q1 in

[0179] In Figure 9 , only the first sub-pixel PX1 is illustrated. Referring to Figure 3 and Figure 9 , the first bank 154a can include an upper surface 154S1 and a side surface 154S2. The second bank 154b can completely cover the side surface 154S2 of the first bank 154a and expose the upper surface 154S1. The second bank 154b can expose the upper surface 154S1 of the first bank 154a such that external light is absorbed by the first bank 154a, thereby improving surface reflection or external light reflection.

[0180] ​​​The first bank 154a can have a first thickness t1, and the second bank 154b can have a second thickness t2. In this specification, the thicknesses t1 and t2 can refer to the maximum thickness of each bank 154a or 154b. For example, the first thickness t1 refers to the maximum thickness of the first bank 154a in the upward direction, and the second thickness t2 refers to the maximum thickness of the second bank 154b in the lateral direction. The second bank 154b can extend, for example, from one end (an end in contact with the first electrode 151) of the side surface 154S2 of the first bank 154a to the other end (an end in contact with the side surface 154S2 and the upper surface 154S1). The second bank 154b can cover the lower end and the upper end of the side surface 154S2 of the first bank 154a. The second bank 154b can be in direct contact with the side surface of the first bank 154a.

[0181] Since the second bank 154b exposes the upper surface of the first bank 154a, external light L2 can be absorbed by the first bank 154a. Thus, external light reflection (or surface reflection) of the display apparatus can be improved.

[0182] In addition, the second bank 154b of the display panel 100 according to one embodiment can be used to extract some light emitted upward from the first light emitting area EA1.

[0183] For example, the organic layer 152 can emit light. For example, the organic layer 152 can emit light in the first light emitting area EA1. Some light L1a of the light emitted from the organic layer 152 can travel upward. In the case where the second bank 154b is not provided, other light of the light emitted from the organic layer 152 that travels toward the first bank 154a can be absorbed by the first bank 154a.

[0184] However, in the case of the display panel 100 according to one embodiment, the other light emitted toward the first bank 154a can be emitted upward, thereby improving the light extraction effect of the display panel 100. Figure 9 L1b and L1c in FIG. 1A indicate light emitted to the organic layer 152 of the first light emitting area EA1 but traveling toward the first bank 154a.

[0185] For example, some light L1b emitted from the first light emitting area EA1 can be reflected from the surfaces of the organic layer 152 and the second bank 154b and extracted upward.

[0186] In addition, light incident on the second bank 154b from the organic layer 152 can travel in the second bank 154b and then can be incident on the first bank 154a and absorbed by the first bank 154a (see L1d in FIG. 1A), but also can be reflected from the surfaces of the second bank 154b and the first bank 154a and extracted upward (see L1c in FIG. 1A). Figure 9 Figure 9 ​​

[0187] As in L1b and L1c of Figure 9 , light can be extracted from the first non-light emitting area NEA1 instead of the first light emitting area EA1. That is, the first non-light emitting area NEA1 can include an extra light extraction area EXP. The extra light extraction area EXP can be an area in contact with the first light emitting area EA1. In a case where the extra light extraction area EXP is spaced apart from the first light emitting area EA1, light identified by the extra light extraction area EXP can be identified as a ring-shaped spot spaced apart from and surrounding the first light emitting area EA1. Accordingly, the extra light extraction area EXP is preferably in contact with the first light emitting area EA1, for which the second bank 154b forming the extra light extraction area EXP preferably covers the lower end portion of the side surface 154S2 of the first bank 154a. The extra light extraction area EXP can not overlap the black matrix BM, but can partially overlap the black matrix MM.

[0188] Further, the second thickness t2 of the second bank 154b is preferably in the range of about 1 / 6 to about 2 / 3 of the first thickness t1. For example, in a case where the second thickness t2 is less than about 1 / 6 of the first thickness t1, the second thickness t2 of the second bank 154b can be too small so that light traveling toward the first bank 154a can not be reflected from the surface of the second bank 154b and the organic layer 152 (L1b does not occur), and it can be difficult to form a small second thickness t2 in terms of process. Figure 10

[0189] Figure 9 is a plan view of a pixel according to one embodiment.

[0190] Referring to Figure 10 and Figure 10 As described above, each non-light emitting area NEA1, NEA2, or NEA3 can further include an extra light extraction area EXP formed by the second bank 154b. Since the second bank 154b extends from the lower end portion of the first bank 154a, the extra light extraction area EXP can be formed to be in contact with each light emitting area EA1, EA2, or EA3, as shown in Figure 1 to Figure 10 .

[0191] Hereinafter, display apparatuses according to other embodiments will be described. In the following embodiments, detailed descriptions of the reference numerals or components described in Figure 11 will be omitted, or repetitive descriptions thereof will be omitted.

[0192] Figure 11 is a cross-sectional view of a display apparatus according to another embodiment.

[0193] Referring to Figure 9 , the display panel 100_1 of the display apparatus according to the present embodiment is similar to the display panel 100 of the display apparatus according to​Figure 3 The display panel 100 according to the present embodiment differs from the display panel 100 according to the

[0194] More specifically, the second bank 154b_1 can cover some of the upper surface 154S1 of the first bank 154a and expose other portions of the upper surface 154S1.

[0195] Even in the present embodiment, since the second bank 154b_1 covers some of the upper surface 154S1 of the first bank 154a and exposes other portions of the upper surface 154S1, external light can be absorbed by the first bank 154a, thereby improving surface reflection or external light reflection.

[0196] In addition, since the second bank 154b_1 covers the side surface 154S2 of the first bank 154a, some light emitted from the light emitting regions EA1, EA2, and EA3 (see Figure 9 ) and advancing to the first bank 154a can be extracted upward, thereby improving light extraction efficiency.

[0197] Since the remaining portions have been described above in Figure 12 , detailed descriptions thereof will be omitted.

[0198] Figure 12 is a cross-sectional view of a display apparatus according to still another embodiment.

[0199] Referring to Figure 9 , the display panel 100_2 of the display apparatus according to the present embodiment differs from the display panel 100 according to Figure 3 in that a second bank 154b_2 of the bank 154_2 can cover a lower end portion of the first bank 154a and expose an upper end portion of the first bank 154a.

[0200] More specifically, the second bank 154b_2 can completely expose the upper surface 154S1 of the first bank 154a and cover a lower end portion of the side surface 154S2.

[0201] Even in the present embodiment, the second bank 154b_2 can expose the upper surface 154S1 of the first bank 154a such that external light is absorbed by the first bank 154a, thereby improving surface reflection or external light reflection.

[0202] In addition, since the second bank 154b_2 covers the lower end portion of the side surface 154S2 of the first bank 154a, some light emitted from the light emitting regions EA1, EA2, and EA3 (see Figure 9) Some light emitted from the organic layer 152 of the first light-emitting region EA1 and traveling toward the first bank 154a can be extracted upward, thereby improving the light extraction efficiency. In addition, the second bank 154b_2 can cover the lower end portion of the side surface 154S2 of the first bank 154a and expose the upper end portion thereof. As described above in Figure 9 , some light (see L1d in Figure 9 ) emitted from the organic layer 152 of the first light-emitting region EA1 but traveling toward the first bank 154a and incident on the second bank 154b can be absorbed by the first bank 154a, reflected at the boundary between the first bank 154a and the second bank 154b, and extracted upward (see L1c in Figure 3 ). However, some light can travel in the direction in which the second bank 154b extends inside the second bank 154b. The light traveling in the direction in which the second bank 154b extends can be emitted from the non-light-emitting region, rather than the extra light extraction region EXP, and in this case, the light can be absorbed by the black matrix BM of Figure 9 .

[0203] However, it is advantageous that the second bank 154b_2 according to the present embodiment can cover the lower end portion of the side surface 154S2 of the first bank 154a and expose the upper end portion thereof, thereby improving the light extraction efficiency in the extra light extraction region EXP.

[0204] For example, the second bank 154b_2 can be provided in a region of the side surface 154S2 of the first bank 154a corresponding to about 1 / 2 of the length from one end portion (the end portion in contact with the first electrode 151).

[0205] Since the remaining portions have been described above in Figure 13 , a detailed description thereof will be omitted.

[0206] Figure 13 is a cross-sectional view of a display device according to still another embodiment.

[0207] Referring to Figure 12 , the display panel 100_3 of the display device according to the present embodiment is different from the display panel 100_2 according to Figure 9 in that the second bank 154b_3 of the bank 154_3 can cover the lower end portion of the first bank 154a and can be provided in a region corresponding to about 1 / 4 of the length from one end portion (the end portion in contact with the first electrode 151).

[0208] Since the remaining portions have been described above in Figure 14 , a detailed description thereof will be omitted.

[0209] Figure 15 is a cross-sectional view of a display device according to still another embodiment. Figure 16is a cross-sectional view of a display apparatus according to still another embodiment. Figure 14 to Figure 16 is a cross-sectional view of a display apparatus according to still another embodiment.

[0210] Referring to Figure 3 , a display panel 100_4 of a display apparatus according to the present embodiment differs from the display panel 100 according to Figure 7 , Figure 8 and Figure 15 in that the display panel 100_4 can further include a third protection layer 113 on the second protection layer 112.

[0211] More specifically, the display panel 100_4 according to the present embodiment can further include a third protection layer 113 between the second protection layer 112 and the first electrode 151. The material of the third protection layer 113 can include at least one of the materials exemplified as the material of the second protection layer 112, but embodiments of the present specification are not limited thereto.

[0212] As illustrated in Figure 16 and Figure 3 , each of the first dam D1_1 and the second dam D2_1 can include the third protection layer 113 as a first layer, and can not include the second protection layer 112, but embodiments of the present specification are not limited thereto.

[0213] Since the remaining portions have been described above in Figure 7 , Figure 8 and Figure 17 , detailed descriptions thereof will be omitted below.

[0214] Figure 17 is a cross-sectional view of a display apparatus according to still another embodiment.

[0215] Referring to Figure 3 , color filters 191_1, 192_1 and 193_1 of a display panel 100_5 of a display apparatus according to the present embodiment differ from the display panel 100 according to Figure 17 in that the color filters 191_1, 192_1 and 193_1 can overlap each other in non-emitting areas NEA1, NEA2 and NEA3.

[0216] Figure 3 It is illustrated that, in each of the non-emitting areas NEA1, NEA2 or NEA3, the second color filter 192_1 is located at the top, the first color filter 191_1 is located below the second color filter 192_1, and finally, the third color filter 193_1 is located at the bottom, but the stacking order of the color filters 191_1, 192_1 and 193_1 in the non-emitting areas NEA1, NEA2 and NEA3 can vary according to the process order.

[0217] Since the remaining portions have been described above in Figure 18 detail, a detailed description thereof will be omitted.

[0218] Figure 19 is a perspective view of a display device according to still another embodiment. Figure 18 is a cross-sectional view along line D-D' in Figure 18 .

[0219] Referring to Figure 19 and Figure 1 , the display device 2 according to the present embodiment is different from the display device 1 according to ​ in that the display device 2 is a foldable display device.

[0220] In the present specification, a folding axis A1 along which the display device 2 is folded can be the same as the second direction DR2.

[0221] A top frame TF is disposed at a top of the display device 2. The top frame TF includes a first top frame TF1 disposed at one side and a second top frame TF2 disposed at the other side with respect to the folding axis A1. The top frame TF can be disposed to cover edges of the display panel 100_6. The top frame TF can protect the display panel 100_6 from an external impact. The top frame TF can form a bezel of the display device 2.

[0222] A cover layer CG can be disposed below the top frame TF. The cover layer CG can be disposed above the display panel 100_6.

[0223] The cover layer CG can be disposed above the display panel 100_6 to protect members disposed below the cover layer CG from the outside.

[0224] A panel assembly is disposed below the cover layer CG. The panel assembly includes the display panel 100_6 and a plate PLT. The display panel 100_6 can be substantially the same as one of the display panels 100, 100_1, 100_2, 100_3, 100_4, and 100_5.

[0225] The plate PLT can be disposed below the display panel 100_6 and can include various plates for supporting the display panel 100_6. For example, one or more plates can include a back plate for supporting the display panel 100_6, a top plate disposed below the back plate and formed of a stainless steel (SUS) material, a bottom plate disposed below the top plate with a pattern formed on a folding portion and formed of a SUS material, a heat sink performing a heat dissipation function, an intermediate plate for covering a non-planarized flat surface caused by various components of the hinge assembly, etc.

[0226] A slit pattern PTN can be formed in the plate PLT. The slit pattern PTN can be formed at a position corresponding to the folding area FA of the display panel 100_6. The slit pattern PTN can be a slit-shaped etching portion formed in the plate PLT. For example, the plate PLT can be formed of a metal such as a SUS material, but the strong properties of the metal can cause a problem when folding or unfolding the plate PLT. The slit pattern PTN can complement the flexibility of the plate PLT.

[0227] The middle plate MST is disposed below the panel assembly. The middle plate MST supports components disposed upward. Also, the hinge assembly 200 and the cover frame CF are disposed downward from the middle plate MST, and their upper surfaces can not be flat. The middle plate MST can flatten the non-flattened lower surface. The middle plate MST can be formed of a material such as plastic, polyimide, or metal to increase the rigidity of the display device 2. For example, the middle plate MST can include aluminum or SUS, but is not limited thereto.

[0228] The middle plate MST can include a first middle plate portion MSTH1 disposed in the first unfolding area NFA1 and a second middle plate portion MSTH2 disposed in the second unfolding area NFA2.

[0229] The hinge assembly 200 is disposed below the panel assembly. The hinge assembly 200 is disposed below the folding area FA. The hinge assembly 200 can have a shape extending along the folding axis A1. The hinge assembly 200 can perform a folding motion in which one side and the other side rotate about the folding axis A1.

[0230] The cover frame CF is disposed below the hinge assembly 200. An upper surface of the cover frame CF can form a receiving groove in which a portion of the hinge assembly 200 can be seated. With respect to the folding axis A1, the cover frame CF includes a first cover frame CF1 disposed at one side and a second cover frame CF2 disposed at the other side. The cover frame CF can be a housing for defining side surfaces and a rear surface of the display device 2. The cover frame CF can protect the display device 2 from external impact. The cover frame CF can be coupled to the hinge assembly 200. The folding and unfolding of the display device 2 can be achieved according to the rotation of the cover frames CF1 and CF2.

[0231] Coupling members BM1, BM2, and BM3 for coupling adjacent members MST, PLT, PTN, and CG can also be provided between the adjacent members. In each of the unfolded areas NFA1 and NFA2, the first coupling member BM1 can couple the middle plate portions MSTH1 and MSTH2 to the plate PLT provided above the middle plate portions MSTH1 and MSTH2, the second coupling member BM2 can couple the plates PLT and PTN to the display panel 100_6 provided above the plates PLT and PTN, and the third coupling member BM3 can couple the display panel 100_6 to the cover layer CG.

[0232] The coupled plate PLT and middle plate MST can be seated on the cover frames CF1 and CF2. The display device 2 can perform a folding and unfolding operation through the hinge assembly 200 provided on the cover frames CF1 and CF2.

[0233] Since the display panel 100_6 has been described above, a detailed description thereof will be omitted below.

[0234] The display device according to various embodiments of the present specification can be described as follows.

[0235] According to an embodiment of the disclosure, a display device is provided, including: a substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area; a first electrode provided in each of the sub-pixels on the substrate; a first bank provided on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface; and a second bank provided on the side surface of the first bank and exposing at least a portion of the upper surface of the first bank, wherein the first bank includes a black-based material.

[0236] In the display device according to various embodiments of the present specification, the light density of the first bank can be greater than the light density of the second bank.

[0237] In the display device according to various embodiments of the present specification, the first bank can be a black bank, and the second bank can be a transparent bank.

[0238] In the display device according to various embodiments of the present specification, the second bank can be in contact with the first bank.

[0239] In the display device according to various embodiments of the present specification, the second bank can completely cover the side surface of the first bank.

[0240] In the display device according to various embodiments of the present specification, the second bank can partially cover the upper surface of the first bank.

[0241] In the display device according to various embodiments of the present disclosure, the second bank can cover a lower end portion of the side surface of the first bank, and expose an upper end portion of the side surface of the first bank.

[0242] In the display device according to various embodiments of the present disclosure, a thickness of the second bank can range from 1 / 6 times to 2 / 3 times a thickness of the first bank.

[0243] The display device according to various embodiments of the present disclosure can further include a first transistor between the substrate and the first electrode, and a second transistor between the first transistor and the first electrode.

[0244] In the display device according to various embodiments of the present disclosure, the semiconductor layer of the first transistor can include polysilicon, and the semiconductor layer of the second transistor can include an oxide.

[0245] The display device according to various embodiments of the present disclosure can further include a first protection layer between the second transistor and the first electrode, a connection electrode between the first protection layer and the first electrode, and a second protection layer between the connection electrode and the first electrode.

[0246] In the display device according to various embodiments of the present disclosure, the plurality of sub-pixels can include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the organic layer on the first electrode can be disposed across the first sub-pixel to the third sub-pixel, and the organic layer can include a first light emitting layer on the first sub-pixel, a second light emitting layer on the second sub-pixel, and a third light emitting layer on the third sub-pixel.

[0247] In the display device according to various embodiments of the present disclosure, in each of the sub-pixels, each of the first light emitting layer, the second light emitting layer, and the third light emitting layer can be stacked in two or more layers.

[0248] The display device according to various embodiments of the present disclosure can further include an organic layer on the first electrode, a second electrode on the organic layer, and a black matrix at a boundary between adjacent sub-pixels on the second electrode, wherein a width of the black matrix can be less than a width of the first bank, and an end portion of the black matrix can be closer to the boundary between the adjacent sub-pixels than an end portion of the bank.

[0249] According to various embodiments of the present specification, a display apparatus is provided, including a substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area, a first electrode disposed in each of the sub-pixels on the substrate, a first bank disposed on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface, and a second bank disposed on the side surface of the first bank and exposing at least a portion of the upper surface of the first bank, wherein the sub-pixel includes a non-light emitting area corresponding to the first bank and a light emitting area exposed by the first bank, and the non-light emitting area includes an additional light extraction area corresponding to the second bank.

[0250] In the display apparatus according to various embodiments of the present specification, the light density of the first bank can be greater than the light density of the second bank.

[0251] In the display apparatus according to various embodiments of the present specification, the first bank can be a black bank, and the second bank can be a transparent bank.

[0252] In the display apparatus according to various embodiments of the present specification, the second bank can completely cover the side surface of the first bank.

[0253] In the display apparatus according to various embodiments of the present specification, the second bank can partially cover the upper surface of the first bank.

[0254] In the display apparatus according to various embodiments of the present specification, the second bank can cover a lower end portion of the side surface of the first bank and expose an upper end portion of the side surface of the first bank.

[0255] According to embodiments of the present specification, by omitting the polarization unit, the display apparatus can have improved flexibility and can be applied to a foldable product in which the display area is folded.

[0256] According to embodiments of the present specification, external light reflection can be improved by arranging the color filter and the first bank including a black-based material.

[0257] According to embodiments of the present specification, since the second bank exposes a portion of the upper surface of the first bank, external light reflection can be improved.

[0258] According to embodiments of the present specification, since the second bank covers a portion of the side surface of the first bank, light extraction can be improved.

[0259] According to embodiments of the present specification, since the second bank covers some or all of the side surface of the first bank, light extraction can be improved and low power can be achieved.

[0260] However, the effects obtainable from the present specification are not limited to those described above, and it will be apparent to those skilled in the art that other effects not mentioned above will be clearly understood based on the following description.

[0261] Although the various embodiments of the present disclosure have been described above with reference to the accompanying drawings, it will be understood by those skilled in the art that the above-described technical configurations of the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and are not restrictive. In addition, the scope of the present disclosure is described by the claims described below rather than the detailed description. In addition, the meaning and scope of the claims and all modifications or variations derived from equivalent concepts should be interpreted as being included in the scope of the present disclosure.

[0262] Description of reference numerals

[0263] 1, 2: display device 100, 100_1, 100_2, 100_3, 100_4, 100_5, 100_6: display panel D1, D2: dam.

Claims

1. A display device, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of pixels each including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels on the substrate; a first bank disposed on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface; and a second bank disposed on the side surface of the first bank and exposing at least a portion of the upper surface of the first bank, wherein the first bank includes a black-based material.

2. The display device of claim 1, wherein, An optical density of the first bank is greater than an optical density of the second bank.

3. The display device of claim 2, wherein, The first bank is a black bank and the second bank is a transparent bank.

4. The display device of claim 1, wherein, The second bank is in direct contact with the first bank.

5. The display device of claim 1, wherein, The second bank completely covers the side surface of the first bank.

6. The display device of claim 5, wherein, The second bank partially covers the upper surface of the first bank.

7. The display device of claim 1, wherein, The second bank covers a lower end portion of the side surface of the first bank and exposes an upper end portion of the side surface of the first bank.

8. The display device of claim 1, wherein, A thickness of the second bank is in a range of 1 / 6 to 2 / 3 of a thickness of the first bank.

9. The display device of claim 1, further comprising: a first transistor between the substrate and the first electrode; and a second transistor between the first transistor and the first electrode.

10. The display device of claim 9, wherein, A semiconductor layer of the first transistor includes polysilicon and a semiconductor layer of the second transistor includes an oxide.

11. The display device of claim 9, further comprising: a first protective layer between the second transistor and the first electrode; a connection electrode between the first protective layer and the first electrode; and a second protective layer between the connection electrode and the first electrode.

12. The display device of claim 1, wherein, The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, an organic layer on the first electrode is disposed across the first sub-pixel to the third sub-pixel, and the organic layer includes a first light-emitting layer on the first sub-pixel, a second light-emitting layer on the second sub-pixel, and a third light-emitting layer on the third sub-pixel.

13. The display device of claim 12, wherein, In each sub-pixel, each of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer is stacked into two or more layers.

14. The display device of claim 1, further comprising: an organic layer on the first electrode; a second electrode on the organic layer; and a black matrix at a boundary between adjacent sub-pixels on the second electrode, wherein a width of the black matrix is less than a width of the first bank, and an end portion of the black matrix is closer to the boundary between the adjacent sub-pixels than an end portion of the first bank.

15. The display device of claim 14, wherein, Each of the plurality of sub-pixels includes a non-light-emitting area and a light-emitting area, and wherein a separation distance between an end portion of the black matrix and a boundary between the light-emitting area and the non-light-emitting area is greater than a separation distance between an end portion of each of the first bank and the second bank and the boundary between the light-emitting area and the non-light-emitting area. 16.A display device, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of pixels each including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels on the substrate; a first bank disposed on the first electrode at a boundary between adjacent sub-pixels and including an upper surface and a side surface; and a second bank disposed on the side surface of the first bank and exposing at least a portion of the upper surface of the first bank, wherein each of the plurality of sub-pixels includes a non-light emitting area corresponding to the first bank and a light emitting area exposed by the first bank, and wherein the non-light emitting area includes an additional light extraction area corresponding to the second bank.

17. The display device of claim 16, wherein, An optical density of the first bank is greater than an optical density of the second bank.

18. The display device of claim 17, wherein, The first bank is a black bank and the second bank is a transparent bank.

19. The display device of claim 16, wherein, The second bank completely covers the side surface of the first bank.

20. The display device of claim 19, wherein, The second bank partially covers the upper surface of the first bank.

21. The display device of claim 16, wherein, The second bank covers a lower end portion of the side surface of the first bank and exposes an upper end portion of the side surface of the first bank.

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