Display device

Abstract

The invention provides a display device. According to an embodiment, a display device includes: a display area including a plurality of sub-pixels; a partition wall surrounding each of the plurality of sub-pixels, the partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; a plurality of display elements that are respectively disposed in the plurality of sub-pixels and that include an organic layer that emits light in response to the application of a voltage; and a plurality of sealing layers formed of an inorganic insulating material and covering the plurality of display elements, respectively. The partition wall includes: a first section and a second section arranged in a second direction intersecting the first direction, the first section and the second section being partitioned by a slit extending in the first direction; and a first connection part that traverses the slit and connects the first section and the second section. In addition, in a plan view, two adjacent sealing layers among the plurality of sealing layers are respectively overlapped with at least a part of the first connecting part.

Description

[0001] Cross-referencing of related applications This application claims priority based on Japanese Patent Application No. 2024-168284, filed on September 27, 2024, and incorporates all the contents of that Japanese Patent Application. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, technologies to improve yield are needed. Summary of the Invention

[0004] Generally, according to an embodiment, the display device includes: a display area comprising a plurality of sub-pixels; a partition surrounding each of the plurality of sub-pixels, comprising a conductive lower portion and an upper portion having an end portion projecting from the side of the lower portion; a plurality of display elements respectively disposed on the plurality of sub-pixels, comprising an organic layer that emits light upon application of voltage; and a plurality of sealing layers formed of an inorganic insulating material, respectively covering the plurality of display elements. The partition includes: a first segment and a second segment arranged in a second direction intersecting the first direction, separated by a slit extending in the first direction; and a first connecting portion traversing the slit and connecting the first segment and the second segment. Furthermore, when viewed from above, at least a portion of two adjacent sealing layers of the plurality of sealing layers overlaps with the first connecting portion.

[0005] This configuration can improve the yield rate of display devices. Attached Figure Description

[0006] Figure 1 This is a diagram showing an example of the configuration of the display device according to the first embodiment.

[0007] Figure 2 This is a schematic top view showing an example of the layout of subpixels.

[0008] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device along line III-III.

[0009] Figure 4 This is a schematic top view showing some elements of the display device according to the first embodiment.

[0010] Figure 5 This is a schematic top view showing an example of the configuration of the partition and sealing layer that can be applied to the first embodiment.

[0011] Figure 6A It is along Figure 5 A schematic cross-sectional view of the AA line display device.

[0012] Figure 6B It is along Figure 5 A schematic cross-sectional view of the BB line display device.

[0013] Figure 6C It is along Figure 5 A schematic cross-sectional view of the display device with the CC line in the image.

[0014] Figure 7A This is a schematic cross-sectional view showing a variation of the first embodiment.

[0015] Figure 7B This is another schematic cross-sectional view showing a variation of the first embodiment.

[0016] Figure 7C This is another schematic cross-sectional view showing a variation of the first embodiment.

[0017] Figure 8 This is a flowchart illustrating an example of a method for manufacturing a display device according to the first embodiment.

[0018] Figure 9A This is a schematic cross-sectional view showing the manufacturing process of the display device.

[0019] Figure 9B It shows the next step. Figure 9A A rough cross-sectional view of the process.

[0020] Figure 9C It shows the next step. Figure 9B A rough cross-sectional view of the process.

[0021] Figure 9D It shows the next step. Figure 9C A rough cross-sectional view of the process.

[0022] Figure 9E It shows the next step. Figure 9D A rough cross-sectional view of the process.

[0023] Figure 9F It shows the next step. Figure 9E A rough cross-sectional view of the process.

[0024] Figure 9G It shows the next step. Figure 9F A rough cross-sectional view of the process.

[0025] Figure 10 This is a schematic top view of the partition and sealing layer of the second embodiment.

[0026] Figure 11A It is along Figure 10 A schematic cross-sectional view of the AA line display device.

[0027] Figure 11B It is along Figure 10 A schematic cross-sectional view of the BB line display device.

[0028] Figure 11C It is along Figure 10 A schematic cross-sectional view of the display device with the CC line in the image.

[0029] Figure 12A This is a schematic cross-sectional view showing a first variation of the second embodiment.

[0030] Figure 12B This is another schematic cross-sectional view showing the first variant example.

[0031] Figure 13A This is a schematic cross-sectional view showing a second variation of the second embodiment.

[0032] Figure 13B This is another schematic cross-sectional view showing the second variation.

[0033] Figure 13C This is another schematic cross-sectional view showing the second variation.

[0034] Figure 14 This is a schematic top view of the display device according to the third embodiment.

[0035] Figure 15 This is a schematic top view showing an example of a structure that can be applied to a dummy pixel area.

[0036] Figure 16A It is along Figure 15 A schematic cross-sectional view of the AA line display device.

[0037] Figure 16B It is along Figure 15 A schematic cross-sectional view of the BB line display device.

[0038] Figure 16C It is along Figure 15 A schematic cross-sectional view of the display device with the CC line in the image. Detailed Implementation

[0039] Several implementation methods are described with reference to the accompanying drawings.

[0040] The disclosure is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the width, thickness, shape, etc., of various parts of the drawings are sometimes shown schematically compared to the actual form, but this is merely an example and not a limitation on the interpretation of the invention. Additionally, in this specification and the figures, the same reference numerals are used to denote elements that perform the same or similar functions as those described in the preceding figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0041] It should be noted that, for ease of understanding, the X, Y, and Z axes are shown as mutually orthogonal axes in the accompanying drawings. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane that includes the X and Y directions. Furthermore, viewing various elements parallel to the Z-direction is called a top-down view.

[0042] The display device in each embodiment is an organic electroluminescent display device that uses organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet computers, smartphones, mobile phone terminals, and wearable terminals.

[0043] [First Implementation]

[0044] Figure 1 This is a diagram illustrating a configuration example of the display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0045] In this embodiment, the substrate 10 and the display area DA are circular when viewed from above. However, the shape of the substrate 10 and the display area DA when viewed from above is not limited to a circle, and may also be other shapes such as rectangle, square or ellipse.

[0046] The display area DA has multiple pixels PX arranged in a matrix in the X and Y directions. Each pixel PX contains multiple sub-pixels SP that display different colors. In this embodiment, it is envisioned that pixel PX contains a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Pixel PX may also contain sub-pixels SP of other colors, such as white, along with or replacing one of the sub-pixels SP1, SP2, and SP3.

[0047] The display device DSP also includes a terminal section T disposed in the peripheral area SA. The terminal section T is connected to a flexible circuit board that supplies, for example, voltage or signals for driving the display device DSP.

[0048] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements, for example, made of thin-film transistors.

[0049] The display area DA is equipped with multiple scan lines G that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines S that supply image signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. Figure 1 In this example, the scan line G and the power line PL extend in the X direction, and the signal line S extends in the Y direction, but this is not limited to this example.

[0050] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0051] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0052] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute a pixel PX. Figure 2 In the example, subpixels SP1 and SP3 are arranged in the Y direction. Additionally, subpixels SP1 and SP3 are arranged in the X direction along with subpixel SP2.

[0053] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP1 and SP3 arranged alternately in the Y direction, and multiple columns of sub-pixels SP2 arranged repeatedly in the Y direction. These columns are arranged alternately in the X direction. It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to this. Figure 2 Examples.

[0054] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 2In this example, pixel openings AP1, AP2, and AP3 are all rectangular. The areas of pixel openings AP1 and AP2 are larger than the area of ​​pixel opening AP3. Pixel opening AP2 extends longer along the Y direction than each of pixel openings AP1 and AP3. However, the shapes of pixel openings AP1, AP2, and AP3 are not limited to this example.

[0055] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0056] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element DE1 of sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element DE2 of sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0057] A conductive partition 6 is disposed above the rib layer 5. The partition 6 separates the display elements DE1, DE2, and DE3 and serves as wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3. The partition 6 overlaps with the rib layer 5 as a whole and has the same planar shape as the rib layer 5. The partition 6 surrounds the sub-pixels SP1, SP2, and SP3.

[0058] The partition 6 has multiple slits SL extending in the Y direction (first direction). The slits SL do not overlap with the lower electrodes LE1, LE2, and LE3. Figure 2 In the example, the sub-pixels SP1, SP2, and SP3 constituting a pixel PX are arranged between two slits SL in the X direction (the second direction). Furthermore, the partition 6 has a connecting portion CT that connects the portions (segments described later) separated by the slits SL. It should be noted that the arrangement of the slits SL and the connecting portion CT is not limited to... Figure 2 Examples.

[0059] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III. A circuit layer 11 is disposed on the substrate 10 described above. The circuit layer 11 includes... Figure 1The diagram shows various circuits and wiring, including pixel circuit 1, scan line G, signal line S, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by circuit layer 11.

[0060] The lower electrodes LE1, LE2, and LE3 are respectively disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are all covered by the rib layer 5.

[0061] The partition 6 includes a lower portion 61 disposed on the rib layer 5 and having electrical conductivity, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. That is, the partition 6 is a suspended structure in which both ends of the upper portion 62 protrude beyond the sides of the lower portion 61.

[0062] exist Figure 3 In this example, the lower part 61 has a bottom layer 63 and a axial layer 64. The bottom layer 63 is thinner than the axial layer 64 and is located between the axial layer 64 and the rib layer 5. The two ends of the bottom layer 63 protrude from the two sides of the axial layer 64, respectively.

[0063] Organic layer OR1 passes through pixel opening AP1 and covers lower electrode LE1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 passes through pixel opening AP2 and covers lower electrode LE2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 passes through pixel opening AP3 and covers lower electrode LE3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of partition 6.

[0064] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. Capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3.

[0065] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0066] Subpixels SP1, SP2, and SP3 are respectively provided with sealing layers SE11, SE12, and SE13 covering the laminated films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the capping layer CP1 and the partition wall 6 surrounding subpixel SP1. Sealing layer SE12 continuously covers the capping layer CP2 and the partition wall 6 surrounding subpixel SP2. Sealing layer SE13 continuously covers the capping layer CP3 and the partition wall 6 surrounding subpixel SP3.

[0067] exist Figure 3 In this example, the sealing layers SE11 and SE12 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP2. Additionally, the sealing layers SE11 and SE13 overlap in the Z direction above the partition 6 between sub-pixels SP1 and SP3. However, not limited to this example, the sealing layers SE11, SE12, and SE13 may also be separated above the partition 6.

[0068] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated films FL1, FL2, FL3 may also be disposed in at least a portion of these gaps.

[0069] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the surrounding area SA.

[0070] exist Figure 3 In the example, the touch panel electrode TP, used to detect the user's touch operation, is disposed on the sealing layer SE2. The touch panel electrode TP is formed of, for example, a metallic material and has the same shape as the partition 6 when viewed from above.

[0071] Alternatively, a polarizer, protective film, or cover glass can be further disposed above the resin layer RS2. Such a cover component can also be bonded to the resin layer RS2 using an adhesive layer such as OCA (Optical Clear Adhesive).

[0072] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0073] The lower electrodes LE1, LE2, and LE3 have, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0074] The upper electrodes UE1, UE2, and UE3 are formed, for example, of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0075] Organic layers OR1, OR2, and OR3 are composed of multiple thin films including light-emitting layers. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure containing multiple light-emitting layers.

[0076] The capping layers CP1, CP2, and CP3, for example, have a stacked structure composed of multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0077] The bottom layer 63 and the axial layer 64 of the partition 6 are formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that the axial layer 64 can also be formed of an insulating material.

[0078] The upper portion 62 of partition 6 may comprise, for example, a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. In this case, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used as the metallic material for the lower layer. Additionally, ITO or IZO can be used as the conductive oxide for the upper layer. It should be noted that the upper portion 62 may have three or more layers, or it may be formed from a single layer. Furthermore, the upper portion 62 may also include a layer formed of an insulating material.

[0079] A common voltage is supplied to the adjacent 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively supply the pixel voltages corresponding to the image signals of the signal line S to the lower electrodes LE1, LE2, and LE3.

[0080] Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emitting layer of organic layer OR1 emits light in the blue wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the emitting layer of organic layer OR2 emits light in the green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the emitting layer of organic layer OR3 emits light in the red wavelength range.

[0081] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can also include a color filter that converts the light emitted by the light-emitting layers into light of the colors corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can also include a layer containing quantum dots, which are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0082] Figure 4 This is a schematic top view showing some elements of the display device DSP. (Block 6 is...) Figure 2 The multiple slits SL partitions shown are divided into multiple sections SG. It should be noted that... Figure 4 The diagram schematically illustrates the slit SL and the segment SG. For example, as shown... Figure 2 As shown, when the slits SL are located on both sides of the pixel PX in the X direction, more slits SL are formed in the display area DA.

[0083] like Figure 2 As shown, at least a portion of the multiple segments SG are connected by a connecting portion CT that crosses the slit SL. On the other hand, there may also be a configuration in which multiple slits SL are not equipped with connecting portions CT.

[0084] Each segment SG has a first end Ea and a second end Eb in the extension direction of the slit SL (Y direction in this embodiment). The first end Ea is connected to a power supply line PW disposed in the peripheral area SA. The power supply line PW is connected to a terminal section T. A common voltage is applied to each segment SG from the terminal section T via the power supply line PW. Figure 4 In the example, the second end Eb of each segment SG is separated by a slit SL and is not connected together by a conductive component such as the power supply line PW.

[0085] Figure 5 This is a schematic top view showing an example of the configuration in which the partition wall 6 and sealing layers SE11, SE12, and SE13 can be applied according to this embodiment. In this figure, a portion of the two sections SG1 and SG2 (section 1 and section 2) separated by the slit SL is shown. The sealing layer SE11 is marked with a diagonal line. In the following description, the portion of section SG1 extending in the Y direction adjacent to the slit SL is referred to as partition wall 6A, and the portion of section SG2 extending in the Y direction adjacent to the slit SL is referred to as partition wall 6B.

[0086] Sections SG1 and SG2 are connected by multiple connecting parts (CTs). Figure 5 In the example, connecting portions CT are provided at positions between sub-pixels SP1 and SP3 and adjacent pixels 6 in the X direction. However, the positions of the connecting portions CT are not limited to this example.

[0087] Encapsulating layer SE11 overlaps with a sub-pixel SP1 (display element DE1). Encapsulating layer SE13 overlaps with a sub-pixel SP3 (display element DE3). Encapsulating layer SE12 is formed, for example, continuously over the area of ​​a plurality of sub-pixels SP2 (display elements DE2) arranged in the Y direction.

[0088] Sealing layers SE11 and SE12 are arranged in the X direction with slits SL between them. Sealing layers SE12 and SE13 are arranged in the X direction with slits SL between them. Sealing layers SE11 and SE13 are arranged in the Y direction without slits SL between them.

[0089] Sealing layer SE11 has ends E1a and E1b in the X direction and ends E1c and E1d in the Y direction. Sealing layer SE12 has ends E2a and E2b in the X direction. Sealing layer SE13 has ends E3a and E3b in the X direction and ends E3c and E3d in the Y direction. For example, ends E1a, E1b, E2a, E2b, E3a, and E3b are straight lines parallel to the Y direction. Additionally, ends E1c, E1d, E3c, and E3d are straight lines parallel to the X direction.

[0090] exist Figure 5In the example, ends E1c and E3d overlap. Alternatively, ends E1d and E3c overlap. However, not limited to this example, ends E1c and E3d can also be separated. Similarly, ends E1d and E3c can also be separated.

[0091] The sealing layer SE11 has two protrusions PT1 that protrude from end E1a in a direction parallel to the X direction (towards the sealing layer SE12). These protrusions PT1 are located at the corner formed by ends E1a and E1c and the corner formed by ends E1a and E1d, respectively.

[0092] In addition, the sealing layer SE13 has two protrusions PT3 protruding from the end E3a in a direction parallel to the X direction (towards the sealing layer SE12). These protrusions PT3 are located at the corner formed by the ends E3a and E3c and the corner formed by the ends E3a and E3d, respectively.

[0093] In this embodiment, adjacent sealing layers SE11 and SE13 each overlap with at least a portion of a connecting portion CT. Specifically, the protrusion PT1 of sealing layer SE11 overlaps with a portion of the connecting portion CT, and the protrusion PT3 of sealing layer SE13 adjacent to sealing layer SE11 overlaps with a portion of the connecting portion CT. Figure 5 In the example, the protrusions PT1 and PT3 also overlap with a portion of the slit SL.

[0094] Figure 6A It is along Figure 5 A schematic cross-sectional view of the DSP display device with AA line in the image. The partitions 6A and 6B are separated by the slit SL. Figure 3 The partition 6 shown is also suspended. The rib layer 5 has no opening in the slit SL. That is, the slit SL overlaps entirely with the rib layer 5.

[0095] exist Figure 6A In the cross-section, sealing layer SE11 covers partition wall 6A. End E1a of sealing layer SE11 is located in slit SL. Sealing layer SE12 covers partition wall 6B. End E2b of sealing layer SE12 is located, for example, in slit SL, spaced apart from end E1a. Alternatively, end E1a may be located above partition wall 6A, and end E2b may be located above partition wall 6B.

[0096] Figure 6B It is along Figure 5 A schematic cross-sectional view of the display device DSP with BB line in the diagram. Sealing layer SE13 covers partition 6A. End E3a of sealing layer SE13 is located in slit SL, spaced apart from end E2b of sealing layer SE12. Alternatively, end E3a may be located above partition 6A.

[0097] Figure 6C It is along Figure 5 A schematic cross-sectional view of the display device DSP with CC line in the middle. The connecting part CT, like the partitions 6A and 6B, includes a lower part 61 (bottom layer 63 and axial layer 64) and an upper part 62. The cross-sectional shape of the connecting part CT along the Y direction is the same as that of the partitions 6A and 6B, which is suspended.

[0098] Convex portion PT1 covers one side of the connecting portion CT in the Y direction. Convex portion PT3 covers the other side of the connecting portion CT in the Y direction. Figure 6C In the example, one end of the protrusion PT1 is located above the slit SL, and the other end is located above the connector CT. Similarly, one end of the protrusion PT3 is located above the slit SL, and the other end is located above the connector CT.

[0099] like Figure 6C As shown, the protrusions PT1 and PT3 may also overlap above the connecting portion CT. Alternatively, the protrusions PT1 and PT3 may separate in the Y direction above the connecting portion CT.

[0100] exist Figures 6A to 6C In the example, apart from the portions overlapping with display elements DE1, DE2, and DE3, a gap GP1 is formed below the sealing layer SE11, a gap GP2 is formed below the sealing layer SE12, and a gap GP3 is formed below the sealing layer SE13. Specifically, gap GP1 is formed between the upper part 62 of partition 6A and the sealing layer SE11, between the rib layer 5 in the slit SL and the sealing layer SE11, between the upper part 62 of the connecting part CT and the protrusion PT1, and between the rib layer 5 in the slit SL and the protrusion PT1. Furthermore, gap GP2 is formed between the upper part 62 of partition 6B and the sealing layer SE12, and between the rib layer 5 in the slit SL and the sealing layer SE12. Additionally, gap GP3 is formed between the upper part 62 of partition 6A and the sealing layer SE13, and between the upper part 62 of the connecting part CT and the protrusion PT3.

[0101] The gaps GP1, GP2, and GP3 correspond to the spaces created by the temporary formation of the laminated films FL1, FL2, and FL3 during the manufacturing process of the display device's DSP, which disappear due to various etching processes. These gaps GP1, GP2, and GP3 can be voids or at least partially formed by the resin layer RS1 (see [link to documentation]). Figure 3 Fill it.

[0102] Figures 7A to 7C This is a schematic cross-sectional view showing a variation of this embodiment. Figure 7A Along Figure 5 The cross-section of line AA in the middle is quite similar. Figure 7B Along Figure 5The cross-section of the BB line in the middle is quite similar. Figure 7C Along Figure 5 The cross-section of the CC line in the middle is quite similar.

[0103] exist Figures 7A to 7C In the middle, in with Figures 6A to 6C The portions corresponding to the gaps GP1, GP2, and GP3 are respectively equipped with laminated films FL1, FL2, and FL3. It should be noted that the laminated films FL1, FL2, and FL3 can also be configured to... Figures 6A to 6C The gaps between GP1, GP2, and GP3 are partially filled.

[0104] Next, an example of a manufacturing method for a display device DSP will be described.

[0105] Figure 8 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figures 9A to 9G This is a schematic cross-sectional view showing the manufacturing process of the display device DSP. Figures 9A to 9G In this paper, the main focus is on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0106] In manufacturing the display device DSP, a circuit layer 11 is first formed on top of the substrate 10. Figure 8 The process PR1). This then forms the organic insulating layer 12 covering the circuit layer 11. Figure 8 Process PR2).

[0107] After process PR2, such as Figure 9A As shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 8 Process PR3). In addition, a rib layer 5 is formed covering the lower electrodes LE1, LE2, and LE3. Figure 8 (Process PR4). At this point in time, pixel openings AP1, AP2, and AP3 are not set in rib layer 5. Rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0108] After the formation of rib layer 5, as Figure 9B As shown, a partition wall 6 is formed above the rib layer 5. Figure 8 (Process PR5). For example, when forming the partition 6, material layers of bottom layer 63, axial layer 64, and top layer 62 are formed on the entire mother substrate MB. In addition, a photoresist in the shape of the partition 6 is disposed on these layers. By etching each layer with the photoresist as a mask, openings can be made in each sub-pixel SP1, SP2, SP3, and a partition 6 comprising multiple segments SG separated by slits SL is formed.

[0109] Next, as Figure 9C As shown, pixel openings AP1, AP2, and AP3 are formed in rib layer 5. Figure 8 (Process PR6). It should be noted that pixel openings AP1, AP2, and AP3 can also be formed before the adjacent 6.

[0110] The process for forming the display element DE1 is performed after process PR6. Figure 8 Process PR7). When forming the display element DE1, firstly as follows... Figure 9D As shown, a laminated film FL1 and a sealing layer SE11 are formed on the entire substrate. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that is in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1.

[0111] The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE11 can be formed, for example, by CVD. The laminated film FL1 is separated by suspended partitions 6. The sealing layer SE11 continuously covers the separated portions of the laminated film FL1 and the partitions 6.

[0112] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 9D As shown, resist RT1 is disposed on top of the sealing layer SE11. Resist RT1 covers a portion of the sub-pixel SP1 and its surrounding partition 6.

[0113] Then, an etching process is performed using resist RT1 as a mask. Thus, as... Figure 9E As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist RT1 are removed. Thus, the display element DE1 is formed in the sub-pixel SP1.

[0114] This etching process can include wet or dry etching of the sealing layer SE11, capping layer CP1, upper electrode UE1, and organic layer OR1 in sequence. After these etchings, the resist RT1 is removed (stripped off).

[0115] In this etching process, the laminated film FL1 near the end of the sealing layer SE11 can also be removed to form the aforementioned gap GP1. It should be noted that the gap GP1 can also be formed by performing various etching processes after this etching process. Alternatively, the laminated film FL1 may remain in at least a portion of the gap GP1.

[0116] The process for forming the display element DE2 is performed after process PR7. Figure 8The process PR8). Display element DE2 can be formed using the same steps as display element DE1. That is, when forming display element DE2, a laminated film FL2 and a sealing layer SE12 are formed on the entire substrate. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that is in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2.

[0117] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE12 can be formed, for example, by CVD. By patterning such a laminated film FL2 and the sealing layer SE2, as... Figure 9F As shown, display element DE2 is formed in sub-pixel SP2.

[0118] exist Figure 9F In the example, the laminated film FL2 near the end of the sealing layer SE12 is removed to form the aforementioned gap GP2. The gap GP2 can also be formed by various etching processes performed after this etching step. Alternatively, the laminated film FL2 may remain in at least a portion of the gap GP2.

[0119] The process for forming the display element DE3 is performed after process PR8. Figure 8 The process PR9). Display element DE3 can be formed using the same steps as display elements DE1 and DE2. That is, when forming display element DE3, a laminated film FL3 and a sealing layer SE13 are formed on the entire substrate. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 that is in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0120] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE13 can be formed, for example, by CVD. By patterning such a laminated film FL3 and the sealing layer SE13, as... Figure 9G As shown, a display element DE3 is formed in sub-pixel SP3.

[0121] exist Figure 9G In the example, the laminated film FL3 near the end of the sealing layer SE13 is removed, forming the aforementioned gap GP3. Alternatively, the laminated film FL3 may remain in at least a portion of the gap GP3.

[0122] It should be noted that this scenario assumes that display elements DE1, DE2, and DE3 are formed in sequence, but they can also be formed in other orders.

[0123] After process PR9, for example, resin layer RS1 is formed by inkjet printing. Figure 8 Process PR10). Furthermore, for example, a sealing layer SE2 is formed via CVD (…). Figure 8 Process PR11).

[0124] After process PR11, the aforementioned touch panel electrode TP is formed on the sealing layer SE2. Figure 8 The process PR12). Then, the resin layer RS2 covering the touch panel electrodes TP and the sealing layer SE2 is formed, for example, by inkjet printing. Figure 8 (Process PR13). The display device DSP is completed by a manufacturing method that includes at least the above processes.

[0125] Here, several effects of the display device DSP in this embodiment will be explained.

[0126] Electronic devices equipped with a display DSP sometimes include optical sensors such as illuminance sensors to detect external light. When such optical sensors are located on the back side of the display DSP, the display DSP needs to be transparent.

[0127] However, the lower electrodes LE1, LE2, and LE3 all contain the aforementioned reflective layer. Furthermore, at least a portion of the partition 6, formed of a metallic material, has light-shielding properties. Therefore, when the lower electrodes LE1, LE2, LE3, and partition 6 are arranged without gaps in the display area DA, most of the light incident on the display surface of the display device DSP will not be transmitted to the back side and will be reflected or blocked.

[0128] Conversely, in the case where a slit SL is provided in the partition 6, as in this embodiment, a portion of the light incident on the display surface is transmitted through the slit SL to the back side of the display device DSP. This improves the light transmittance of the display device DSP. In this embodiment, as... Figure 6A and Figure 6B As shown, a region is formed at the slit SL that does not overlap with the sealing layers SE11, SE12, and SE13. Further increases in transmittance can be expected in such a region.

[0129] Furthermore, electronic devices equipped with a display device DSP sometimes have an antenna for near-field communication (NFC). This antenna is, for example, configured opposite to the back of the display device DSP, enabling wireless communication between the display device DSP and other electronic devices. During wireless communication, eddy currents are generated in the partition 6 due to the magnetic field formed by the antenna. Because these eddy currents form a magnetic field in a direction that cancels out the aforementioned magnetic field, the signal strength of the wireless communication is attenuated. Therefore, in the case of wireless communication via the display device DSP, the communication sensitivity may be reduced.

[0130] The aforementioned eddy currents can be reduced by using the partition wall 6. That is, as in Figure 4 As described in the description, by setting a slit SL without a connecting part CT, it is not easy to generate large eddy currents in the partition 6, thus suppressing the reduction in communication sensitivity.

[0131] Thus, according to this embodiment, a display device DSP with good compatibility with optical sensors and antennas for wireless communication can be provided. Furthermore, as will be explained below, the yield rate of the display device DSP can be improved according to this embodiment.

[0132] like Figure 7C As shown, the two sides of the connector CT are suspended. During the manufacturing of the display device DSP, if this type of connector CT is covered with various photoresists, air bubbles may become trapped in the photoresist. In this case, these air bubbles will burst during the depressurized drying of the photoresist, potentially exposing areas that should have been covered by the photoresist. In contrast, in this embodiment, the two sides of the connector CT are covered by protrusions PT1 and PT3, respectively. Therefore, it is possible to suppress the inclusion of air bubbles in the photoresist formed after the protrusions PT1 and PT3.

[0133] The sealing layer SE11, formed from inorganic insulating material, is particularly prone to cracking at its corners. If the base shape at the corner of the sealing layer SE11 is unstable, the formation of these cracks can become significant. Such cracks can also be one of the reasons why air bubbles can mix into the resist disposed on the sealing layer SE11. In this embodiment, a protrusion PT1 is formed at the corner of the sealing layer SE11 on the slit SL side. Furthermore, the protrusion PT1 overlaps with the connecting portion CT. Therefore, the base shape at the corner of the sealing layer SE11 is stable, suppressing crack formation. The same effect is achieved in the sealing layer SE13, which has a protrusion PT3.

[0134] When the resin layer RS1 is formed using the inkjet method described above, droplets of uncured resin ejected from the nozzle adhere to the ribs 5 in the sealing layers SE11, SE12, SE13, and slit SL, wetting and spreading over the area where the resin layer RS1 is to be formed. If the connecting portion CT is not covered by the protrusions PT1 and PT3, the suspended sides of the connecting portion CT may obstruct droplet diffusion. In contrast, if, as in this embodiment, the sides of the connecting portion CT are covered by the protrusions PT1 and PT3, the droplets diffuse well, thus suppressing shape defects in the resin layer RS1.

[0135] In addition to the above, various preferred effects can be obtained from this embodiment.

[0136] [Second Implementation]

[0137] The second embodiment will be described. For configurations not specifically mentioned, the same configuration as in the first embodiment can be applied.

[0138] Figure 10 This is a schematic top view of the partition 6 and sealing layers SE11, SE12, and SE13 in this embodiment. The shapes of the sealing layers SE11, SE12, and SE13 in this embodiment differ from those in the first embodiment.

[0139] That is, in Figure 10 In the example, the sealing layer SE11 does not have Figure 5 The protrusion PT1 is shown. Additionally, the sealing layer SE13 does not have... Figure 5 The convex portion PT3 is shown. On the other hand, the sealing layer SE12 has a plurality of convex portions PT2 protruding from the end E2b in a direction parallel to the X direction.

[0140] exist Figure 10 In the example, the end E1a of the sealing layer SE11 and the end E3a of the sealing layer SE13 are offset in the X direction. Specifically, end E1a is located near partition 6B, and end E3a is located near partition 6A. As a result, most of the slit SL between sub-pixels SP1 and SP2 overlaps with the sealing layer SE11. On the other hand, the sealing layer SE13 hardly overlaps with the slit SL.

[0141] Each protrusion PT2 is positioned parallel to the sealing layer SE13 in the X direction. As a result, most of the slit SL between sub-pixels SP2 and SP3 overlaps with the protrusion PT2.

[0142] In this embodiment, the sealing layers SE11 and SE12 overlap with the connecting portion CT. Specifically, the ends E1a, E1c, and E1d of the sealing layer SE11 overlap with the connecting portion CT. In addition, the two ends of the protrusion PT2 in the Y direction overlap with the connecting portion CT.

[0143] Figure 11A It is along Figure 10 A schematic cross-sectional view of the display device DSP with AA line in the diagram. Sealing layer SE11 covers partition 6A. End E1a of sealing layer SE11 is located in slit SL. Sealing layer SE12 covers partition 6B. End E2b of sealing layer SE12 is located, for example, in slit SL, spaced apart from end E1a. Alternatively, end E2b may be located above partition 6B.

[0144] Figure 11B It is along Figure 10A schematic cross-sectional view of the display device DSP with BB line in the middle. Sealing layer SE13 covers partition 6A. The end E3a of sealing layer SE13 is located in slit SL. Alternatively, end E3a may be located above partition 6A. The protrusion PT2 of sealing layer SE12 is located above rib layer 5 in slit SL, spaced apart from end E3a.

[0145] Figure 11C It is along Figure 10 A schematic cross-sectional view of the display device DSP with CC line in the image. The sealing layer SE11 covers one side of the connector CT in the Y direction. The protrusion PT2 covers the other side of the connector CT in the Y direction. Figure 11C In the example, the end E1c of the sealing layer SE11 is located above the slit SL. Additionally, the end of the protrusion PT2 is located above the slit SL. For example... Figure 11C As shown, the end portion E1c and the protrusion PT2 may also overlap above the connecting portion CT. Alternatively, the end portion E1c and the protrusion PT2 may separate in the Y direction above the connecting portion CT.

[0146] exist Figures 11A to 11C In the example, apart from the portions overlapping with display elements DE1, DE2, and DE3, a gap GP1 is formed below the sealing layer SE11, a gap GP2 is formed below the sealing layer SE12, and a gap GP3 is formed below the sealing layer SE13. Specifically, gap GP1 is formed between the upper part 62 of partition 6A and the sealing layer SE11, and between the rib layer 5 at the slit SL and the sealing layer SE11, respectively. Furthermore, gap GP2 is formed between the upper part 62 of partition 6B and the sealing layer SE12, and between the rib layer 5 at the slit SL and the protrusion PT2, respectively. Additionally, gap GP3 is formed between the upper part 62 of partition 6A and the sealing layer SE13, and between the rib layer 5 at the slit SL and the sealing layer SE13, respectively.

[0147] Figure 12A and Figure 12B This is a schematic cross-sectional view showing the first modified example of this embodiment. Figure 12A Along Figure 10 The cross-section of line AA in the middle is quite similar. Figure 12B Along Figure 10 The cross-section of the BB line in the middle is quite similar.

[0148] At once Figure 12A In terms of configuration, the end E2b of the sealing layer SE12 overlaps with the end E1a of the sealing layer SE11. Figure 11A The structures are different. End E2b is located above end E1a in the Z direction.

[0149] In addition, Figure 12BIn terms of structure, the end E3a of the sealing layer SE13 overlaps with the protrusion PT2 of the sealing layer SE12. Figure 11B The structures are different. End E3a is located above the protrusion PT2 in the Z direction.

[0150] Figures 13A to 13C This is a schematic cross-sectional view showing the second variation of this embodiment. Figure 13A Along Figure 10 The cross-section of line AA in the middle is quite similar. Figure 13B Along Figure 10 The cross-section of the BB line in the middle is quite similar. Figure 13C Along Figure 10 The cross-section of the CC line in the middle is quite similar.

[0151] exist Figures 13A to 13C In the middle, in with Figures 11A to 11C The portions corresponding to the gaps GP1, GP2, and GP3 are respectively equipped with laminated membranes FL1, FL2, and FL3. It should be noted that the laminated membranes FL1, FL2, and FL3 can also be configured to fill the gaps corresponding to the gaps GP1, GP2, and GP3. Figures 11A to 11C It is part of the corresponding area of ​​the gaps GP1, GP2, and GP3. Additionally, in Figure 12A and Figure 12B In the configuration of the first modified example shown, laminated films FL1, FL2, and FL3 may also be disposed at positions corresponding to gaps GP1, GP2, and GP3, respectively.

[0152] This embodiment also achieves the same effects as the first embodiment. However, when forming narrow protrusions PT1 and PT3 as in the first embodiment, the machining accuracy is limited depending on the dimensions of the sealing layers SE11, SE12, and SE13. In contrast, in this embodiment, the connecting portion CT is covered by a rectangular sealing layer SE11 and protrusions PT2 with widths equal to the spacing between the connecting portions CT. With this configuration, the impact on machining accuracy is reduced, and sealing layers SE11, SE12, and SE13 with stable shapes can be formed.

[0153] [Third Implementation]

[0154] The third embodiment will be described. For configurations not specifically mentioned, the same configurations as those in the above embodiments can be applied.

[0155] Figure 14 This is a schematic top view of the display device DSP according to this embodiment. Figure 1 Similarly, the display device DSP shown has an insulating substrate 10, a display area DA for displaying an image, and a peripheral area SA surrounding the display area DA. Furthermore, the peripheral area SA has a dummy pixel area DMY surrounding the display area DA.

[0156] exist Figure 14 The image shows a portion of the dummy pixel region DMY enlarged. Multiple dummy pixels DPX are configured within the dummy pixel region DMY. For example, each dummy pixel DPX includes dummy subpixels DP1, DP2, and DP3. The dummy subpixels DP1, DP2, and DP3 have a similar structure to the subpixels SP1, SP2, and SP3 configured in the display region DA.

[0157] That is, the dummy sub-pixel DP1 has a lower electrode LE1, an organic layer OR1, and a upper electrode UE1. Additionally, the dummy sub-pixel DP2 has a lower electrode LE2, an organic layer OR2, and a upper electrode UE2. Furthermore, the dummy sub-pixel DP3 has a lower electrode LE3, an organic layer OR3, and a upper electrode UE3.

[0158] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. This configuration can be achieved, for example, by disconnecting a portion of the pixel circuit 1 of each of the dummy sub-pixels DP1, DP2, and DP3. Furthermore, pixel openings AP1, AP2, and AP3 can be omitted from the dummy sub-pixels DP1, DP2, and DP3, respectively. Thus, with the rib layer 5 sandwiched between the organic layers OR1, OR2, and OR3 and the lower electrodes LE1, LE2, and LE3, no current for emitting light flows into the organic layers OR1, OR2, and OR3.

[0159] Part of the partition 6 is located in the dummy pixel region DMY, and surrounds multiple dummy pixels DPX. More specifically, the partition 6 surrounds dummy sub-pixels DP1, DP2, and DP3 respectively. The shape and layout of the opening of the partition 6 for each of the dummy sub-pixels DP1, DP2, and DP3 are the same as the shape and layout of the opening of the partition 6 for each of the sub-pixels SP1, SP2, and SP3.

[0160] In the above embodiments, a portion of the slit SL is located in the dummy pixel region DMY. Additionally, a connecting portion CT (second connecting portion) is also provided in the dummy pixel region DMY.

[0161] Figure 15 This is a schematic top view showing a specific example of the configuration that can be applied to a dummy pixel region DMY. Within the dummy pixel region DMY, there are dummy sealing layers DSE1 overlapping with dummy sub-pixel DP1, DSE2 overlapping with dummy sub-pixel DP2, and DSE3 overlapping with dummy sub-pixel DP3. Figure 15 In the diagram, the dummy sealing layers DSE1 and DSE3 are marked with diagonal lines. The dummy sealing layers DSE1, DSE2, and DSE3 are formed from the same inorganic insulating material as the sealing layers SE11, SE12, and SE13.

[0162] The partition 6 in the dummy pixel region DMY and the dummy sealing layers DSE1, DSE2, and DSE3 can be applied to... Figure 5 and Figure 10 The partition wall 6 and sealing layers SE11, SE12, and SE13 shown have the same configuration. As an example, in... Figure 15 The diagram shows that partition 6 and the dummy sealing layers DSE1, DSE2, and DSE3 have the same... Figure 5 The partition 6 and sealing layers SE11, SE12, and SE13 shown are identical in configuration.

[0163] That is, such as Figure 15 As shown, a portion of segments SG1 and SG2, separated by slits SL, is located within a dummy pixel region DMY. Within the dummy pixel region DMY, segments SG1 and SG2 are connected by multiple connecting portions CT. The dummy sealing layer DSE1 has ends E1a and E1b in the X direction and ends E1c and E1d in the Y direction. The dummy sealing layer DSE2 has ends E2a and E2b in the X direction. The dummy sealing layer DSE3 has ends E3a and E3b in the X direction and ends E3c and E3d in the Y direction. Additionally, the dummy sealing layer DSE1 has two protrusions PT1. The dummy sealing layer DSE3 has two protrusions PT3. The dummy sealing layer DSE2 is continuously formed within, for example, the area of ​​multiple dummy sub-pixels DP2 arranged in the Y direction.

[0164] exist Figure 15 In the example, adjacent dummy sealing layers DSE1 and DSE3 each overlap with at least a portion of a connecting portion CT. Specifically, the protrusion PT1 of dummy sealing layer DSE1 overlaps with a portion of the connecting portion CT, and the protrusion PT3 of dummy sealing layer DSE3 adjacent to dummy sealing layer DSE1 overlaps with a portion of the connecting portion CT. Protrusions PT1 and PT3 also overlap with portions of the slit SL.

[0165] Figure 16A It is along Figure 15 A schematic cross-sectional view of the DSP display device with AA lines. Figure 16A In the cross-section, a dummy sealing layer DSE1 covers partition wall 6A. End E1a of the dummy sealing layer DSE1 is located in the slit SL. A dummy sealing layer DSE2 covers partition wall 6B. End E2b of the dummy sealing layer DSE2 is located, for example, in the slit SL, spaced apart from end E1a. Alternatively, end E1a may be located above partition wall 6A. Furthermore, end E2b may also be located above partition wall 6B.

[0166] Figure 16B It is along Figure 15A schematic cross-sectional view of the display device DSP with BB line in the diagram. The end E3a of the dummy sealing layer DSE3 is located in the slit SL, and is positioned opposite the end E2b of the dummy sealing layer DSE2 at a distance. As another example, the end E3a may also be located above the partition 6A.

[0167] Figure 16C It is along Figure 15 A schematic cross-sectional view of the display device DSP with CC line in the image. Protrusion PT1 covers one side of the connecting portion CT in the Y direction. Protrusion PT3 covers the other side of the connecting portion CT in the Y direction. Figure 16C In the example, one end of the protrusion PT1 is located above the slit SL, and the other end is located above the connector CT. Similarly, one end of the protrusion PT3 is located above the slit SL, and the other end is located above the connector CT.

[0168] like Figure 16C As shown, the protrusions PT1 and PT3 may also overlap above the connecting portion CT. Alternatively, the protrusions PT1 and PT3 may separate in the Y direction above the connecting portion CT.

[0169] exist Figures 16A to 16C In the example, gaps GP1 are formed between the upper part 62 of partition 6A and the dummy sealing layer DSE1, between the rib layer 5 at the slit SL and the dummy sealing layer DSE1, between the upper part 62 of the connecting part CT and the protrusion PT1, and between the rib layer 5 at the slit SL and the protrusion PT1, respectively. Additionally, gaps GP2 are formed between the upper part 62 of partition 6B and the dummy sealing layer DSE2, and between the rib layer 5 at the slit SL and the dummy sealing layer DSE2, respectively. Furthermore, gaps GP3 are formed between the upper part 62 of partition 6A and the dummy sealing layer DSE3, between the rib layer 5 in the slit SL and the dummy sealing layer DSE3, and between the upper part 62 of the connecting part CT and the protrusion PT3, respectively. As another example, a laminated film FL1 may be disposed in at least a portion of gap GP1, a laminated film FL2 may be disposed in at least a portion of gap GP2, and a laminated film FL3 may be disposed in at least a portion of gap GP3.

[0170] exist Figure 16A and Figure 16B In this embodiment, dummy sub-pixels DP1, DP2, and DP3 do not have pixel openings AP1, AP2, and AP3. Therefore, rib layers 5 are provided between the lower electrode LE1 and the laminated film FL1, between the lower electrode LE2 and the laminated film FL2, and between the lower electrode LE3 and the laminated film FL3. Alternatively, the dummy sub-pixels DP1, DP2, and DP3 may also have pixel openings AP1, AP2, and AP3.

[0171] When the dummy pixel region DMY has the above-described configuration, the dummy pixel region DMY can also achieve the same effect as in the first embodiment. It should be noted that when the same configuration as the partition 6 and sealing layers SE11, SE12, SE13 disclosed in the second embodiment is applied to the partition 6 and dummy sealing layers DSE1, DSE2, DSE3 of the dummy pixel region DMY, the dummy pixel region DMY can also achieve the same effect as in the second embodiment.

[0172] In the above embodiments, the term "partition" encompasses a variety of suspended structures. Even for suspended structures whose shape differs from the partitions disclosed in the embodiments, the portion extending to the side is equivalent to the "upper part," and the portion receding below that portion is equivalent to the "lower part."

[0173] Any display device that can be appropriately designed and implemented by those skilled in the art based on the display device disclosed in each embodiment, as long as it contains the spirit of the present invention, is also within the scope of the present invention.

[0174] Within the scope of this invention, various modifications will be conceived by those skilled in the art, and these modifications should also be considered within the scope of this invention. For example, any method obtained by adding, deleting, or designing constituent elements appropriately based on the above-described embodiments, or by adding, omitting, or changing processes or conditions, as long as it captures the essence of this invention, is also included within the scope of this invention.

[0175] Furthermore, any other effects resulting from the methods described in the above embodiments, as known from the description in this specification or that can be reasonably conceived by those skilled in the art, should naturally be considered as effects brought about by the present invention.

Claims

1. A display device, characterized in that, include: The display area contains multiple sub-pixels; A partition, which surrounds each of the plurality of sub-pixels, includes a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion; Multiple display elements, each disposed on the multiple sub-pixels, include an organic layer that emits light according to the application of voltage; as well as Multiple sealing layers, formed of inorganic insulating material, respectively cover the multiple display elements. The partition wall comprises: The first and second segments, arranged in a second direction intersecting the first direction, are separated by slits extending in the first direction; and A first connecting portion, which traverses the slit and connects the first segment to the second segment, When viewed from above, two adjacent sealing layers of the plurality of sealing layers overlap with at least a portion of the first connection portion.

2. The display device according to claim 1, characterized in that, When viewed from above, the two sealing layers overlap with at least a portion of the slit.

3. The display device according to claim 1, characterized in that, A gap is formed beneath each of the two sealing layers in the slit.

4. The display device according to claim 1, characterized in that, The two sealing layers overlap above the first connection.

5. The display device according to claim 1, characterized in that, The plurality of sealing layers includes a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer and the second sealing layer are arranged in the second direction through the slit. The first sealing layer and the third sealing layer are arranged in the first direction. When viewed from above, the first sealing layer and the third sealing layer overlap with at least a portion of the first connecting portion.

6. The display device according to claim 5, characterized in that, The first sealing layer has a first protrusion that protrudes in a direction parallel to the second direction. The third sealing layer has a second protrusion that protrudes in a direction parallel to the second direction. When viewed from above, the first protrusion and the second protrusion overlap with at least a portion of the first connecting portion.

7. The display device according to claim 6, characterized in that, A gap is formed between the first connecting portion and the first protrusion located above the first connecting portion.

8. The display device according to claim 7, characterized in that, A gap is formed between the first connecting portion and the second protrusion located above the first connecting portion.

9. The display device according to claim 6, characterized in that, When viewed from above, the first protrusion overlaps with a portion of the slit.

10. The display device according to claim 9, characterized in that, When viewed from above, the second protrusion overlaps with a portion of the slit.

11. The display device according to claim 6, characterized in that, The first protrusion and the second protrusion overlap above the first connecting portion.

12. The display device according to claim 1, characterized in that, The plurality of sealing layers includes a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer and the second sealing layer are arranged in the second direction through the slit. The first sealing layer and the third sealing layer are arranged in the first direction. When viewed from above, the first sealing layer and the second sealing layer overlap with at least a portion of the first connecting portion.

13. The display device according to claim 12, characterized in that, When viewed from above, the end of the first sealing layer in the first direction overlaps with at least a portion of the first connecting portion.

14. The display device according to claim 13, characterized in that, A gap is formed between the first connecting portion and the end of the first sealing layer located above the first connecting portion.

15. The display device according to claim 13, characterized in that, The second sealing layer has a protrusion that protrudes in a direction parallel to the second direction. When viewed from above, the convex portion overlaps with at least a portion of the first connecting portion.

16. The display device according to claim 15, characterized in that, A gap is formed between the first connecting portion and the protrusion located above the first connecting portion.

17. The display device according to claim 1, characterized in that, It also includes a dummy pixel region located outside the display area, the dummy pixel region comprising multiple dummy sub-pixels. A portion of the partition is located within the dummy pixel region and surrounds each of the plurality of dummy sub-pixels.

18. The display device according to claim 17, characterized in that, A portion of the slit is located within the dummy pixel region. The partition also includes a second connecting portion in the dummy pixel region that connects the first segment and the second segment.

19. The display device according to claim 18, characterized in that, The plurality of sealing layers also include a dummy sealing layer that overlaps with at least one of the plurality of dummy sub-pixels and at least a portion of the second connection when viewed from above.

20. The display device according to any one of claims 1 to 19, characterized in that, It also has a resin layer covering the multiple sealing layers.

Images