Display device and electronic device

Abstract

A display device and an electronic device are provided. A display device according to an embodiment includes: a substrate; a semiconductor layer disposed on the substrate; a first insulating layer, a first organic layer, a second insulating layer, and a second organic layer sequentially disposed on the semiconductor layer; a first electrode disposed on the second organic layer; a partition wall disposed on the first electrode and including a pixel opening; and a light emitting layer disposed in the pixel openings, in which the second insulating layer includes a plurality of first openings filled with a second organic layer, and a thickness of the first organic layer and the second organic layer is about 1.5 [mu] m to about 3 [mu] m.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device and an electronic device. BACKGROUND

[0002] A display device is a device for visually displaying an image. The display device can be used as a display of a small product such as a mobile phone or can be used as a display of a large product such as a television.

[0003] The display device includes a plurality of sub-pixels that receive an electrical signal and emit light to display an image to the outside. Each sub-pixel can include a light emitting device. For example, an emissive display device includes a light emitting diode (LED) as a light emitting device. Generally, the emissive display device includes a thin film transistor and an LED on a substrate, and the LED itself emits light.

[0004] Recently, as the use of display devices has diversified, various designs have been attempted to improve the quality of the display device. SUMMARY

[0005] Embodiments attempt to provide a display device capable of preventing pixel contraction caused by gas by patterning an insulating layer that protects an additional wiring layer for implementing high resolution and by controlling the thickness of an organic layer for planarization to discharge gas that can be generated by the organic layer.

[0006] A display device according to an embodiment includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer, a first organic layer, a second insulating layer, and a second organic layer sequentially disposed on the semiconductor layer, a first electrode disposed on the second organic layer, a partition wall disposed on the first electrode and including a pixel opening, and a light emitting layer disposed in the pixel opening, wherein the second insulating layer includes a plurality of first openings, the plurality of first openings are filled with the second organic layer, and a thickness of the first organic layer and a thickness of the second organic layer are about 1.5 µm to about 3 µm.

[0007] The semiconductor layer can include a channel region, a first region disposed on one side of the channel region, and a second region disposed on the other side of the channel region.

[0008] The display device can further include a first wiring layer disposed under the first organic layer and connected to the first region, and a second wiring layer disposed on the first organic layer and connected to the first wiring layer.

[0009] At least some of the plurality of first openings can overlap the first region or the second region.

[0010] At least two of the plurality of first openings can overlap the channel region.

[0011] In the cross-sectional view, a width of one of the plurality of first openings can be greater than the length of the first region and the length of the second region.

[0012] In the cross-sectional view, a width of one of the plurality of first openings can have a size of about 20% to about 23% of a width of the pixel opening.

[0013] The first insulating layer and the second insulating layer can include silicon nitride.

[0014] The display device can further include a gate insulating film disposed on the channel region, an oxygen supply layer disposed on the gate insulating film, and a gate electrode disposed on the oxygen supply layer.

[0015] The first wiring layer and the second wiring layer can include at least one of Cu, Ti, Al, Pt, Ag, Mg, Ni, and W.

[0016] The semiconductor layer can include an oxide semiconductor.

[0017] The semiconductor layer can include at least one of an In-Zn oxide, an In-Ga oxide, a Sn-Zn oxide, an In-Sn-Zn oxide, an In-Ga-Zn oxide, a Sn-Ga-Zn oxide, and an In-Sn-Ga-Zn oxide.

[0018] A display device according to an embodiment includes a substrate, a semiconductor layer disposed on the substrate, a first wiring layer, a second wiring layer, a first organic layer, a second organic layer, and an insulating layer disposed on the semiconductor layer, a first electrode disposed on the first organic layer, a partition wall disposed on the first electrode and including a pixel opening, and an emission layer disposed in the pixel opening, wherein the semiconductor layer includes a channel region, and a first region disposed on one side of the channel region and a second region disposed on the other side of the channel region, the first wiring layer is connected to the first region under the first organic layer, the second wiring layer is connected to the first wiring layer, and a thickness of the first organic layer and a thickness of the second organic layer are about 1.5 µm to about 3 µm.

[0019] The insulating layer can include a first insulating layer and a second insulating layer, the second insulating layer can include a plurality of first openings, and the plurality of first openings can be filled with a second organic layer.

[0020] The first insulating layer can be disposed between the semiconductor layer and the first organic layer, and the second insulating layer can be disposed between the first organic layer and the second organic layer.

[0021] At least some of the plurality of first openings can overlap the first region or the second region.

[0022] At least two of the plurality of first openings can overlap the channel region.

[0023] In a sectional view, the width of one of the multiple first openings can be greater than the length of the first zone and the length of the second zone.

[0024] In the cross-sectional view, the width of one of the plurality of first openings may be approximately 20% to approximately 23% of the width of the pixel opening.

[0025] An electronic device according to an embodiment includes: a memory; a processor for executing an application stored in the memory; and a display device including a display module that outputs video information provided by the application, wherein the display device includes: a substrate; a semiconductor layer disposed on the substrate; a first insulating layer, a first organic layer, a second insulating layer, and a second organic layer sequentially disposed on the semiconductor layer; a first electrode disposed on the second organic layer; a partition wall disposed on the first electrode and including a pixel opening; and a light-emitting layer disposed in the pixel opening, wherein the second insulating layer includes a plurality of first openings filled with the second organic layer, and the thickness of the first organic layer and the thickness of the second organic layer are about 1.5 μm to about 3 μm.

[0026] According to an embodiment, by patterning the insulating layer used to protect the wiring layer to form openings, gases generated in the organic layer can be effectively discharged to the outside, and the amount of gas generated can be reduced by controlling the thickness of the organic layer. This structure can provide a display device that reduces pixel shrinkage caused by gas by preventing gas from moving to the electrode layer. Attached Figure Description

[0027] Figure 1 This is a schematic cross-sectional view of a display device according to an embodiment.

[0028] Figure 2 This is a cross-sectional view showing the gas exhaust structure of the display device according to an embodiment.

[0029] Figure 3 This is a graph illustrating the performance of the semiconductor layer of the display device according to an embodiment.

[0030] Figure 4 This is a table showing the design values ​​of the pixel aperture area of ​​the display device according to an embodiment.

[0031] Figure 5 Image (A) is an image showing the design values ​​of the pixel aperture area of ​​the display device according to an embodiment.

[0032] Figure 5 (B) is an image showing a display device according to an embodiment when the pixels are turned on.

[0033] Figure 6It is a graph showing the brightness reduction rate of the red pixels of the display device according to the example and comparative examples.

[0034] Figure 7 This is a table illustrating the improvement in pixel shrinkage of the display device according to an embodiment.

[0035] Figure 8 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0036] Figure 9 A block diagram of an electronic device according to an embodiment is shown.

[0037] Figure 10 Schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0038] This disclosure will be described in detail below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure.

[0039] The accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature, and the same reference numerals denote the same elements throughout the specification.

[0040] Furthermore, since the dimensions and thicknesses of the components shown in the accompanying drawings can be arbitrarily given for ease of understanding and description, the disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for ease of understanding and description.

[0041] It should be understood that when a layer, film, region, substrate, or element is referred to as being "on" another element, the layer, film, region, substrate, or element may be directly on the other element, or an intermediary element may be present. Conversely, when an element is referred to as being "directly on" another element, no intermediary element is present. Furthermore, when an element is referred to as being "on" or "above" a reference element, the element may be disposed above or below the reference element, and the element need not necessarily be referred to as being disposed "on" or "above" the reference element in a direction opposite to gravity.

[0042] Furthermore, unless explicitly stated to the contrary, the words “including” and variations such as “comprising” should be understood as implying the inclusion of the stated element but excluding any other element.

[0043] Additionally, the phrase "in a plan view" refers to a view taken from above the object (e.g., from the top), while the phrase "in a sectional view" refers to a view of a section of the object cut vertically from the side.

[0044] First, the following will refer to Figure 1 A display device according to an embodiment is described. Figure 1 A display device according to an embodiment is shown.

[0045] like Figure 1 As shown, the display device according to an embodiment may include a substrate SUB, a lower metal layer BML disposed on the substrate SUB, a buffer layer BF disposed on the lower metal layer BML, a semiconductor layer ACT disposed on the buffer layer BF, a gate electrode GAT superimposed on the semiconductor layer ACT, and a first wiring layer SD1 connected to the semiconductor layer ACT. The first wiring layer SD1 may include a source electrode S and a drain electrode D.

[0046] The substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0047] The substrate SUB can be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The substrate SUB can be single-layered or multi-layered. In the substrate SUB, at least one matrix layer comprising a polymer resin and at least one inorganic layer can be stacked alternately.

[0048] The lower metal layer BML can be stacked on top of the semiconductor layer ACT and can have a width wider than the semiconductor layer ACT. The lower metal layer BML can be connected to a source electrode S, which is an electrode connected to the first region A1 of the semiconductor layer ACT. The lower metal layer BML can be connected to the first wiring layer SD1. The lower metal layer BML can be disposed below the channel region CH of the semiconductor layer ACT and can block light incident on the semiconductor layer ACT to stabilize the operating characteristics of the semiconductor layer ACT.

[0049] A buffer layer (BF) can be disposed between the substrate (SUB) and the semiconductor layer (ACT), and can prevent impurities from the substrate (SUB) from flowing into the semiconductor layer (ACT), thereby improving the characteristics of the semiconductor layer (ACT). In addition, the buffer layer (BF) can planarize the substrate (SUB) and reduce the stress on the semiconductor layer (ACT) formed on the buffer layer (BF). The buffer layer (BF) can have a single-layer structure or a multi-layer structure. The buffer layer (BF) can include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y Inorganic insulating materials.

[0050] The semiconductor layer ACT may include a first region A1, a channel region CH, and a second region A2. The first region A1 and the second region A2 may be respectively disposed on opposite sides of the channel region CH of the semiconductor layer ACT. The semiconductor layer ACT may be formed of an oxide semiconductor. The oxide semiconductor may include at least one of the following: a single-component metal oxide, such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn); a two-component metal oxide, such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, or In-Ga oxide; a three-component metal oxide, such as In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, or In-Ce-Zn oxide. In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides; and four-component metal oxides, such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. For example, the semiconductor layer ACT may include indium gallium zinc oxide (IGZO) among In-Ga-Zn oxides.

[0051] The gate insulating film GI can be disposed on the semiconductor layer ACT. The gate insulating film GI can have a single-layer structure or a multi-layer structure. The gate insulating film GI can include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y The gate insulating film GI is an inorganic insulating material. It can be stacked with the channel region CH of the semiconductor layer ACT. The gate insulating film GI may not be stacked with the first region A1 or the second region A2 of the semiconductor layer ACT. However, it is not limited to this, and the gate insulating film GI can be formed entirely on the substrate SUB.

[0052] An oxygen supply layer (OS) can be disposed on the gate insulating film (GI). The OS can also be disposed between the gate insulating film (GI) and the gate electrode (GAT). The OS can control the electrical properties of the oxide semiconductor and improve its stability. Oxygen defects can be prevented in the oxide semiconductor by supplying it with the necessary oxygen. The electrical characteristics of the oxide semiconductor can be optimized by preventing oxygen defects.

[0053] The oxygen supply layer OS may include silicon dioxide (SiO2), titanium dioxide (TiO2), aluminum oxide (Al2O3), or cerium dioxide (CeO2).

[0054] The gate electrode (GAT) can be disposed on the oxygen supply layer (OS). The gate electrode (GAT) can be stacked with the channel region (CH) of the semiconductor layer (ACT). The gate electrode (GAT) can comprise metallic materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti). After forming the gate electrode (GAT), a doping process or plasma treatment can be performed. The portion of the semiconductor layer (ACT) covered by the gate electrode (GAT) is undoped or untreated by plasma, while the portion of the semiconductor layer (ACT) not covered by the gate electrode (GAT) is doped or treated by plasma to have the same properties as a conductor.

[0055] The interlayer insulating film (ILD) can be disposed on the gate electrode (GAT). The ILD can be entirely formed on the substrate (SUB). The ILD can have a single-layer or multi-layer structure. The ILD can comprise inorganic or organic insulating materials.

[0056] A first wiring layer SD1 can be disposed on an interlayer insulating film (ILD). The first wiring layer SD1 may include a source electrode S and a drain electrode D. Wiring connecting the first region A1 of the semiconductor layer ACT and the source electrode S can be disposed in an opening penetrating the interlayer insulating film (ILD). The source electrode S can be connected to the first region A1 of the semiconductor layer ACT. Wiring connecting the second region A2 of the semiconductor layer ACT and the drain electrode D can be disposed in an opening penetrating the interlayer insulating film (ILD). The drain electrode D can be connected to the second region A2 of the semiconductor layer ACT. The first wiring layer SD1 is disposed below a first insulating layer PVX1 and can be connected to both the first region A1 and the second region A2.

[0057] The source electrode S and drain electrode D may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu).

[0058] A transistor can be formed by a source electrode S, a drain electrode D, a semiconductor layer ACT, and a gate electrode GAT.

[0059] A first insulating layer PVX1 may be disposed on the first wiring layer SD1. The first insulating layer PVX1 is a passivation layer formed of inorganic insulating material and may cover the first wiring layer SD1. The first insulating layer PVX1 may cover the source electrode S and the drain electrode D.

[0060] A first organic layer VIA1 may be disposed on a first insulating layer PVX1. The first organic layer VIA1 is intended to provide a flat upper surface. After the formation of the first organic layer VIA1, a chemical mechanical polishing process may be performed on the upper surface of the first organic layer VIA1. The first organic layer VIA1 may include polycarbonate, benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), general polymers such as polymethyl methacrylate (PMMA) or polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers (such as photosensitive polyimide or polyimide), aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers. Figure 1 In the diagram, the first organic layer VIA1 is shown as a single layer, but the first organic layer VIA1 can be multiple layers.

[0061] A second wiring layer SD2 can be disposed on the first organic layer VIA1. The second wiring layer SD2 can be used to implement a display device with a higher resolution. Since there is a pixel integration problem when achieving high resolution using only the first wiring layer SD1, a second wiring layer SD2 can be introduced. The second wiring layer SD2 can comprise the same material as the first wiring layer SD1, for example, a metal such as Cu or Ti. The second wiring layer SD2 is disposed on top of the first organic layer VIA1 and can be electrically connected to the first wiring layer SD1 and the first electrode E1.

[0062] The first electrode E1 of the light-emitting diode ED can be disposed on the second wiring layer SD2. The first electrode E1 can be connected to the source electrode S through the second wiring layer SD2.

[0063] The first electrode E1 can be formed from a single layer comprising a metallic material or a transparent conductive oxide, or from a multilayer comprising a metallic material and a transparent conductive oxide. The first electrode E1 can include metals such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), or gold (Au), and can also include transparent conductive oxides (TCOs) such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the first electrode E1 can have a three-layer film structure of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0064] A separator wall (PDL) may be disposed on the first electrode E1. The separator wall (PDL) may comprise an organic insulating material such as a general-purpose polymer (such as polymethyl methacrylate (PMMA) or polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer (such as polyimide), and a siloxane polymer. A pixel opening (OP) is formed through the separator wall (PDL), and the pixel opening (OP) may be disposed in the region corresponding to the first electrode E1.

[0065] The emissive layer EML can be disposed within the pixel opening OP of the partition wall PDL. The emissive layer EML may include material layers that uniquely emit primary colors of light, such as red, green, and blue. The emissive layer EML may have a structure in which multiple layers of material emitting different colors of light are stacked. The emissive layer EML is shown only disposed within the pixel opening OP, but is not limited thereto. The emissive layer EML can be disposed not only within the pixel opening OP, but also on the partition wall PDL. That is, the emissive layer EML can be disposed entirely on the substrate SUB.

[0066] The second electrode E2 can be disposed on the light-emitting layer EML and the separator wall PDL. The second electrode E2 may include a reflective metal or a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO). The reflective metal includes calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or lithium (Li).

[0067] The first electrode E1, the light-emitting layer EML, and the second electrode E2 form a light-emitting diode ED. Here, the first electrode E1 can be the anode, serving as a hole injection electrode, and the second electrode E2 can be the cathode, serving as an electron injection electrode. However, the embodiment is not limited to this, and according to the driving method of the organic light-emitting display device, the first electrode E1 can be the cathode, and the second electrode E2 can be the anode.

[0068] Holes and electrons are injected into the light-emitting layer EML from the first electrode E1 and the second electrode E2, respectively, and light is emitted when the excitons formed by recombination of the injected holes and electrons descend from the excited state to the ground state.

[0069] Although not shown in the accompanying drawings, an encapsulation layer comprising inorganic and organic insulating materials may be disposed on the second electrode E2, and a filler layer comprising filler may be disposed on the encapsulation layer. A capping layer comprising insulating materials, a color conversion layer, a transmissive layer, etc., may be disposed on the filler layer. The color conversion layer may be disposed on some pixels, while the transmissive layer may be disposed on other pixels. The color conversion layer may comprise semiconductor nanocrystals, and the semiconductor nanocrystals may comprise at least one of phosphors and quantum dot materials that convert incident light into different colors. Quantum dots can control the color of emitted light according to particle size, thus quantum dots can emit light of various colors such as blue, red, and green. The transmissive layer can transmit incident light and may comprise polymer materials.

[0070] The display device according to an embodiment may have a second insulating layer PVX2 disposed on a second wiring layer SD2. The second insulating layer PVX2 may completely surround the second wiring layer SD2. At least a portion of the second insulating layer PVX2 may be disposed on a first organic layer VIA1. The second insulating layer PVX2 may protect the second wiring layer SD2 and may comprise a moisture-resistant material. Silicon nitride (SiN) x This material can be used to form the second insulating layer PVX2. When forming the second insulating layer PVX2, the hydrogen content in the display device may increase. When the hydrogen content in the display device increases, the first region A1 and the second region A2 of the semiconductor layer ACT may expand, making it difficult to ensure device characteristics.

[0071] The second organic layer VIA2 can be formed on the second insulating layer PVX2 to planarize the upper surfaces of the second wiring layer SD2 and the second insulating layer PVX2. The second organic layer VIA2 can be directly disposed on the second insulating layer PVX2. Like the first organic layer VIA1, the second organic layer VIA2 can be formed from an imide polymer (such as photosensitive polyimide or polyimide).

[0072] The first organic layer VIA1 and the second organic layer VIA2 may comprise polymers, and due to the properties of polymers, gases containing at least one of carbon (C) and hydrogen (H), such as hydrocarbon gases, oxygen-containing hydrocarbon gases, etc., may remain within the polymer after coating. Additionally, when heat is applied to the first organic layer VIA1 and the second organic layer VIA2 during subsequent processes, gases generated in the first organic layer VIA1 and the second organic layer VIA2 may be released. When the display panel is driven, these gases may flow through the electrodes into the display area and cause defects in the display device.

[0073] If gas flows into the display area, pixel shrinkage may occur. Pixel shrinkage refers to the phenomenon where the actual pixel aperture area becomes smaller than the designed pixel aperture area due to gas flowing into the display area when the pixel is on. To ensure that the actual pixel aperture area equals the designed pixel aperture area when the pixel is on, the second insulating layer PVX2 may include multiple first openings MP for gas venting. Additionally, the thicknesses of the first organic layer VIA1 and the second organic layer VIA2 can be adjusted to facilitate gas venting.

[0074] The second insulating layer PVX2 may include a plurality of first openings MP. The plurality of first openings MP may be pores formed by removing the second insulating layer PVX2. Gases such as hydrogen can be discharged through the plurality of first openings MP. The plurality of first openings MP may be filled with a second organic layer VIA2.

[0075] In a cross-sectional view, the width W of one of the plurality of first openings MP can be 20% to 23% of the width WW of the pixel opening OP. In the cross-sectional view, the width W of one of the plurality of first openings MP can be greater than the length I1 of the first region A1 and the length I2 of the second region A2. At least some of the plurality of first openings MP can be configured to overlap with the first region A1 or the second region A2. At least two of the plurality of first openings MP can be configured to overlap with the channel region CH. The plurality of first openings MP can be formed across the entire panel area.

[0076] The thickness of each of the first organic layer VIA1 and the second organic layer VIA2 can be from about 1.5 μm to about 3 μm. If the thickness of the first organic layer VIA1 and the second organic layer VIA2 exceeds 3 μm, gas venting may be difficult even if the organic layers are fully cured. Therefore, the thickness of the organic layers can be set to be relatively thin to facilitate gas venting.

[0077] Figure 2 This is a cross-sectional view showing the gas exhaust structure of the display device according to an embodiment.

[0078] Even after the first organic layer VIA1 has been cured, the gas BU remaining in the first organic layer VIA1 can be discharged to the outside of the display device through multiple first openings MP. Therefore, the movement of residual hydrogen and gas BU from the lower organic layer to the electrodes (e.g., the second wiring layer SD2) can be suppressed. Thus, the second wiring layer SD2 can be protected from the effects of residual hydrogen and gas BU. The hydrogen content in the display device is also reduced, thereby preventing degradation of the display device's characteristics.

[0079] The width of the multiple first openings MP in the cross-sectional view can be adjusted to prevent hydrogen and gas BU from flowing in from the outside. Even with multiple first openings MP, the second wiring layer SD2 can be completely surrounded by the second insulating layer PVX2 to prevent moisture from penetrating into the second wiring layer SD2.

[0080] Figure 3 This is a graph illustrating the performance of the semiconductor layer of the display device according to an embodiment. Now refer to... Figure 1 and Figure 3 This will explain how the performance of the oxide semiconductor device in the display device is ensured by including a plurality of first openings MP in the second insulating layer PVX2.

[0081] Reference Figure 1 The first insulating layer PVX1 and the second insulating layer PVX2, which contain silicon nitride, can have a high hydrogen content. Hydrogen in the first insulating layer PVX1 and the second insulating layer PVX2 can diffuse along the first wiring layer SD1 and the second wiring layer SD2 into the semiconductor layer ACT. If a large amount of hydrogen flows into the semiconductor layer ACT, the first region A1, which serves as the source region of the oxide semiconductor device, and the second region A2, which serves as the drain region of the oxide semiconductor device, will expand due to the high hydrogen content, and it may be difficult to ensure the characteristics of the oxide semiconductor device. Furthermore, the device characteristics of the oxide semiconductor device may deteriorate due to the hydrogen remaining in the first organic layer VIA1 and the second organic layer VIA2.

[0082] The display device according to the embodiment can protect the wiring by forming a plurality of first openings MP in the second insulating layer PVX2 to suppress the movement of residual hydrogen and gas in the first organic layer VIA1 and the second organic layer VIA2 to the upper electrode layer, thereby ensuring quality by blocking external moisture penetration. Furthermore, by including a plurality of first openings MP, the hydrogen content of the second insulating layer PVX2 itself is reduced, thereby ensuring the device characteristics of the oxide semiconductor device. Additionally, by providing pathways for releasing hydrogen and gas remaining in the first organic layer VIA1 and the second organic layer VIA2, the hydrogen content can be reduced, thereby preventing the semiconductor layer ACT from becoming conductive.

[0083] Figure 3 This is a graph showing the performance of an oxide semiconductor device when the second insulating layer PVX2 includes multiple first openings MP. According to... Figure 3 It can be seen that when the second insulating layer PVX2 includes multiple first openings MP, the transistors, including oxide semiconductors, operate normally. The X-axis represents the gate-source voltage, determined by V... GS Indicates. V GS It can have a range of values ​​between -10V and 20V. The Y-axis represents the drain-source current, determined by I... DS Indicates. I DSIt can have 1E -14 A and 1E -2 The graph shows the range of values ​​between A and V. GS More than V th Time I DS It increases rapidly. This indicates the point at which the transistor begins to conduct. Within the range of -10V to 0V, I... DS With 1E -14 A and 1E -12 A value between A and V indicates that the transistor is off. GS Above 0V, I DS Rapidly increased to nearly 1E -4 The value of A indicates that the transistor is turned on. The voltage at which the transistor begins to conduct is called the threshold voltage V. th According to an embodiment, the semiconductor layer ACT of the display device has a threshold voltage V of approximately 0.48V. th Threshold voltage V th It can have an error range of ±0.06V. Figure 3 The graph shows that the transistor operates normally when the second insulating layer PVX2 includes multiple first openings MP.

[0084] Below, refer to Figure 4 and Figure 5 This will describe the pixel aperture area of ​​the display device and the image when the actual pixels are turned on. Figure 4 This is a table showing the design values ​​of the pixel aperture area of ​​the display device according to an embodiment.

[0085] Reference Figure 4 The pixel aperture area of ​​the red pixel R is 982.46μm. 2 The pixel aperture area of ​​the green pixel G is 801.575μm. 2 The pixel aperture area of ​​blue pixel B is 1178.76μm. 2 .

[0086] Figure 5 Image (A) is an image showing the pixel aperture area of ​​a display device according to an embodiment. Figure 5 (B) is an image of the display device when the pixel is on according to an embodiment.

[0087] It can be seen that when the second insulating layer PVX2 includes multiple first openings MP and the first organic layer VIA1 and the second organic layer VIA2 have a thickness of 1.5 μm, the light-emitting area can be maintained as designed. It can also be seen that the second insulating layer PVX2 includes multiple first openings MP, and the thickness of the first organic layer VIA1 and the second organic layer VIA2 is adjusted to 1.5 μm to prevent pixel shrinkage.

[0088] According to the stacked structure such as a first insulating layer PVX1, a first organic layer VIA1 disposed on the first insulating layer PVX1, and a second organic layer VIA2 disposed on the first organic layer VIA1, the gas remaining in the first organic layer VIA1 and the second organic layer VIA2 may not be able to be fully discharged, causing the gas to diffuse into the display area and causing pixel shrinkage.

[0089] The display device according to the embodiment can protect the wiring by introducing a second insulating layer PVX2 to prevent residual hydrogen in the organic layers VIA1 and VIA2 from moving to the upper electrode layer, and prevent pixel shrinkage by including a plurality of first openings MP to provide a path for gas to escape from the organic layers VIA1 and VIA2, thereby ensuring the quality of the display device.

[0090] Additionally, the gas content present in the first organic layer VIA1 and the second organic layer VIA2 can be reduced by decreasing the thickness of the latter. As the thickness of organic layers VIA1 and VIA2 decreases, the residual gas decreases, allowing moisture or gas remaining in the layers to be easily expelled when the organic layers VIA1 and VIA2 cure.

[0091] under, Figure 6 and Figure 7 Comparison examples and references are shown. Figure 1 The example shows the effect of pixel shrinkage.

[0092] Figure 6 This is a graph showing the brightness reduction rate of the red pixel R in the display device according to the example and comparative examples.

[0093] Reference Figure 6 and Figure 1 The graph in Example 1 shows the rate of brightness reduction of the red pixel R when the thickness of the first organic layer VIA1 is 1.5 μm. Example 1 shows that the brightness reduction level of the red pixel R remains at 0% not only after 24 hours but also after 504 hours. This is because the thickness of the first organic layer VIA1 in Example 1 is thinner than that in Comparative Example 1, so the amount of residual hydrogen and gas is smaller, and the gas can be fully released when the first organic layer VIA1 cures.

[0094] Reference Figure 6 and Figure 1The graph in Comparative Example 1 shows the rate of brightness reduction of the red pixel R when the thickness of the first organic layer VIA1 is 3.0 μm. Other conditions are the same as in Example 1. In Comparative Example 1, the brightness reduction of the red pixel R is 0% until 24 hours have elapsed, as in Example 1. However, it can be seen that over time, hydrogen and gases released from the first organic layer VIA1 diffuse into the display area, causing a decrease in the brightness of the red pixel R. Specifically, the brightness of the red pixel R decreases by approximately 20% after 48 hours, approximately 45% after 72 hours, and approximately 100% after 144 hours.

[0095] Figure 7 This is a table illustrating the improvement in pixel shrinkage of the display device according to an embodiment. Figure 7 In this context, pixel shrinkage is represented by PS.

[0096] according to Figure 7 Comparative Example 2 shows a case where the thicknesses of the first organic layer VIA1 and the second organic layer VIA2 are set to 1.6 μm and no second insulating layer PVX2 is applied. Although the thicknesses of the first organic layer VIA1 and the second organic layer VIA2 are reduced, because there is no second insulating layer PVX2 to inhibit the movement of residual hydrogen and gas within the organic layers VIA1 and VIA2 towards the electrode layer, hydrogen and gas diffuse into the display area, causing pixel shrinkage (PS).

[0097] Comparative Example 3 shows a case where the thicknesses of the first organic layer VIA1 and the second organic layer VIA2 are set to 1.5 μm and the second insulating layer PVX2 is not applied. As in Comparative Example 2, the thicknesses of the first organic layer VIA1 and the second organic layer VIA2 are reduced, but because the second insulating layer PVX2, which is used to suppress the movement of residual hydrogen and gas within the organic layers VIA1 and VIA2 to the electrode layer, is absent, hydrogen and gas diffuse into the display area and cause pixel shrinkage PS.

[0098] Comparative Example 4 introduces a second insulating layer PVX2 to suppress the migration of residual hydrogen and gas within the organic layers VIA1 and VIA2 to the electrode layer, and the second insulating layer PVX2 includes multiple first openings MP for releasing hydrogen and gas; however, only the thickness of the second organic layer VIA2 is reduced to 1.5 μm. The thickness of the first organic layer VIA1 is not reduced. In this case, the first organic layer VIA1 is thick, resulting in a high content of residual hydrogen and gas, and even when the first organic layer VIA1 is cured, the hydrogen and gas are not sufficiently expelled, leading to pixel shrinkage PS.

[0099] Example 1 includes a second insulating layer PVX2 comprising multiple first openings MP, wherein both the first organic layer VIA1 and the second organic layer VIA2 have a thickness of 1.5 μm. In the cross-sectional view, the width of the multiple first openings MP is approximately 21.7% of the pixel opening OP. In this case, the thickness of the first organic layer VIA1 and the second organic layer VIA2 is thin enough that the content of residual hydrogen and gas is small, and a large amount of hydrogen and gas can be discharged even when the organic layers VIA1 and VIA2 are cured after coating. Hydrogen and gas that are not discharged during curing can be discharged to the outside of the display device through the multiple first openings MP included in the second insulating layer PVX2. Furthermore, the presence of the second insulating layer PVX2 prevents hydrogen and gas from moving to the electrode layer. In the case of Example 1, it can be seen that no pixel shrinkage PS occurs, the wiring is protected, and the quality of the display device is ensured.

[0100] Figure 8 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment. (Refer to...) Figure 1 describe Figure 8 .

[0101] Reference Figure 1 and Figure 8 The lower metal layer BML is patterned using the first mask (S1).

[0102] Then, the semiconductor layer ACT is patterned using a second mask (S2).

[0103] Then, the gate electrode GAT is patterned using a third mask (S3). In this step, the gate electrode GAT, the oxygen supply layer OS, and the gate insulating film GI can be patterned simultaneously. According to an embodiment, the gate electrode GAT and the oxygen supply layer OS can be formed by wet etching, and then the gate insulating film GI can be dry etched to pattern it.

[0104] Then, a contact hole (S4) is formed using a fourth mask. A contact hole for connecting the lower metal layer BML and the source electrode S can be formed in the interlayer insulating film ILD and the buffer layer BF, and a contact hole for connecting the first region A1 and the source electrode S and a contact hole for connecting the second region A2 and the drain electrode D can be formed in the interlayer insulating film ILD.

[0105] Then, the first wiring layer SD1 is patterned using a fifth mask (S5). In this step, the first wiring layer SD1 may include a source electrode S and a drain electrode D.

[0106] After patterning the first wiring layer SD1, a first insulating layer PVX1 and a first organic layer VIA1 are formed on the patterned first wiring layer SD1.

[0107] Then, the first organic layer VIA1 and the first insulating layer PVX1 are patterned using a sixth mask (S6). In this step, the first insulating layer PVX1 is dry-etched to form contact holes, which are spaces for connecting the second wiring layer SD2 and the first wiring layer SD1.

[0108] Then, the second wiring layer SD2, which is an additional wiring layer, is patterned using the seventh mask (S7).

[0109] After forming the second wiring layer SD2, an eighth mask is used to pattern the second insulating layer PVX2 to protect the second wiring layer SD2 (S8). The second insulating layer PVX2 is patterned to have a plurality of first openings MP.

[0110] After forming the second insulating layer PVX2, the second organic layer VIA2 is patterned using a ninth mask (S9). The second organic layer VIA2 may have a substantially flat upper surface.

[0111] Then, the first electrode E1 connected to the second wiring layer SD2 is patterned using the tenth mask (S10).

[0112] Then, the partition wall PDL is patterned using the eleventh mask (S11). Pixel openings (OPs) can be formed by patterning the partition wall PDL.

[0113] By introducing a second wiring layer SD2 as additional wiring, a total of 11 masks can be used to pattern components included in the display device according to the embodiment. The display device including the second wiring layer SD2 can be formed using 11 masks, enabling high resolution. Furthermore, when forming the second insulating layer PVX2 to protect the second wiring layer SD2, a plurality of first openings MP can be included to prevent pixel shrinkage, thereby maintaining high resolution.

[0114] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device, and may also include modules or devices with additional functions in addition to the display device. Figure 9 This is a block diagram of an electronic device according to an embodiment. (Refer to...) Figure 9The electronic device 10 according to the embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14. The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The memory 13 may store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, video data signals and / or input control signals are transmitted to the display module 11, and the display module 11 may process the received signals to output video information through a display screen. The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10. At least one of the components of the electronic device 10 may be included within the display device according to the above embodiments. Furthermore, some of the various modules functionally included within the electronic device 10 may be incorporated into the display device, while other modules may be disposed separately from the display device. For example, the display device may include a display module 11, while the processor 12, memory 13 and power module 14 may be disposed within the electronic device 10 as other devices that are not part of the display device.

[0115] Figure 10 Schematic diagrams of electronic devices according to various embodiments are shown. (Refer to...) Figure 10 Various electronic devices having a display device according to the embodiments may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices with display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices with display modules 10_3 (such as car dashboards, central instrument panels, CID (central information displays), interior mirror displays, etc.).

[0116] While the inventive concept has been described in conjunction with exemplary embodiments which are now considered practical, it will be understood that the inventive concept is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0117] While this disclosure has been described in conjunction with embodiments that are now considered practical, it should be understood that the disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, the display device comprising: Base; A semiconductor layer is disposed on the substrate; A first insulating layer, a first organic layer, a second insulating layer, and a second organic layer are sequentially disposed on the semiconductor layer; The first electrode is disposed on the second organic layer; A partition wall, disposed on the first electrode and including a pixel opening; and A light-emitting layer is disposed in the pixel opening. The second insulating layer includes a plurality of first openings. The plurality of first openings are filled with the second organic layer, and The thickness of the first organic layer and the thickness of the second organic layer are 1.5 μm to 3 μm.

2. The display device as claimed in claim 1, wherein, The semiconductor layer includes a channel region, a first region disposed on one side of the channel region, and a second region disposed on the other side of the channel region.

3. The display device as claimed in claim 2, further comprising: A first wiring layer is disposed below the first organic layer and connected to the first region; as well as A second wiring layer is disposed on the first organic layer and connected to the first wiring layer.

4. The display device as claimed in claim 3, wherein, At least some of the plurality of first openings overlap with the first region or the second region.

5. The display device as claimed in claim 3, wherein, At least two of the plurality of first openings overlap with the channel region.

6. The display device as claimed in claim 3, wherein, In the cross-sectional view, the width of one of the plurality of first openings is greater than the length of the first region and the length of the second region.

7. The display device as claimed in claim 3, wherein, In the cross-sectional view, the width of one of the plurality of first openings has a dimension of 20% to 23% of the width of the pixel opening.

8. The display device as claimed in claim 3, wherein, The first insulating layer and the second insulating layer comprise silicon nitride.

9. The display device as claimed in claim 3, wherein, The display device further includes: A gate insulating film is disposed on the channel region; An oxygen supply layer is disposed on the gate insulating film; and A gate electrode is disposed on the oxygen supply layer.

10. The display device as claimed in claim 3, wherein, The first wiring layer and the second wiring layer include at least one of Cu, Ti, Al, Pt, Ag, Mg, Ni and W.

11. The display device as claimed in claim 3, wherein, The semiconductor layer includes an oxide semiconductor.

12. The display device as claimed in claim 11, wherein, The semiconductor layer includes at least one of In-Zn oxide, In-Ga oxide, Sn-Zn oxide, In-Sn-Zn oxide, In-Ga-Zn oxide, Sn-Ga-Zn oxide, and In-Sn-Ga-Zn oxide.

13. A display device, the display device comprising: Base; A semiconductor layer is disposed on the substrate; A first wiring layer, a second wiring layer, a first organic layer, a second organic layer, and an insulating layer are disposed on the semiconductor layer; The first electrode is disposed on the first organic layer; A partition wall is disposed on the first electrode and includes a pixel opening; as well as A light-emitting layer is disposed in the pixel opening. The semiconductor layer includes: a channel region; and a first region and a second region, wherein the first region is disposed on one side of the channel region, and the second region is disposed on the other side of the channel region. The first wiring layer is connected to the first region beneath the first organic layer. Wherein, the second wiring layer is connected to the first wiring layer, and The thickness of the first organic layer and the thickness of the second organic layer are 1.5 μm to 3 μm.

14. The display device as claimed in claim 13, wherein, The insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer including a plurality of first openings, and the plurality of first openings being filled with the second organic layer.

15. The display device as claimed in claim 14, wherein, The first insulating layer is disposed between the semiconductor layer and the first organic layer, and the second insulating layer is disposed between the first organic layer and the second organic layer.

16. The display device as claimed in claim 14, wherein, At least some of the plurality of first openings overlap with the first region or the second region.

17. The display device as claimed in claim 14, wherein, At least two of the plurality of first openings overlap with the channel region.

18. The display device as claimed in claim 14, wherein, In the cross-sectional view, the width of one of the plurality of first openings is greater than the length of the first region and the length of the second region.

19. The display device as claimed in claim 14, wherein, In the cross-sectional view, the width of one of the plurality of first openings has a dimension of 20% to 23% of the width of the pixel opening.

20. An electronic device, the electronic device comprising: Memory; The processor executes the applications stored in the memory; as well as A display device, including a display module, wherein the display module outputs video information provided by the application. The display device includes: Base; A semiconductor layer is disposed on the substrate; A first insulating layer, a first organic layer, a second insulating layer, and a second organic layer are sequentially disposed on the semiconductor layer; The first electrode is disposed on the second organic layer; A partition wall, disposed on the first electrode and including a pixel opening; and A light-emitting layer is disposed in the pixel opening. The second insulating layer includes a plurality of first openings, the plurality of first openings being filled with the second organic layer, and the thickness of the first organic layer and the thickness of the second organic layer being 1.5 μm to 3 μm.

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