Display device

Abstract

The embodiment of the invention relates to a display device. Specifically, the display device may simplify a structure of the sub-pixel circuit portion and reduce a size of the sub-pixel circuit portion by forming an overlapping structure of an opening of the protective layer and an opening of the gate insulating film.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0130893, filed on September 26, 2024, in the Republic of Korea, the contents of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] The embodiments disclosed herein relate to display devices. Background Technology

[0004] A display device may include at least driving transistors and storage capacitors for each sub-pixel. The display device may have sub-pixels with different aperture ratios depending on the structure of the different sub-pixels, and the image quality or resolution of the display panel may vary depending on the aperture ratio of the sub-pixels. As the resolution of the display device increases, increasing the aperture ratio of each sub-pixel becomes useful.

[0005] However, due to the limitations on the number or type of components (e.g., transistors, storage capacitors, light-emitting devices) included in each sub-pixel, it is difficult to optimize the sub-pixel structure to increase the aperture ratio of the sub-pixels. Summary of the Invention

[0006] The embodiments disclosed herein can provide a display device that can reduce the size of the sub-pixel circuit portions disposed in each sub-pixel through structural optimization.

[0007] Such an implementation can also provide a display device that can reduce the size of the sub-pixel circuit through structural optimization, thereby increasing the size of the aperture in each sub-pixel, improving light extraction efficiency, and reducing power consumption.

[0008] Furthermore, embodiments of this disclosure can provide a display device that simplifies the structure of the sub-pixel circuit and reduces its size by applying an overlapping structure of openings in the protective layer and openings in the gate insulating film to the sub-pixel circuit.

[0009] Such an implementation can also provide a display device that simplifies the structure of the sub-pixel circuit and reduces its size by applying an opening to the protective layer and a non-overlapping structure to the storage capacitor.

[0010] Another implementation can provide a display device in which the pixel electrode is electrically connected to the active layer with the electrode of the driving transistor inserted between the pixel electrode and the active layer, so as to form a current path in the sub-pixel circuit, thereby reducing the contact resistance compared to a direct connection structure between the pixel electrode and the active layer.

[0011] Furthermore, embodiments of this disclosure can provide a display device comprising: a substrate; an active layer disposed on the substrate, wherein the active layer includes a channel region, a first region located on one side of the channel region, and a second region located on the other side of the channel region. A gate insulating film may be disposed on the active layer and have a first opening. A first electrode may be electrically connected to at least a portion of the first region in the first opening. A second electrode may be disposed on the gate insulating film and overlap with the channel region. A protective layer may be disposed on the first electrode and the second electrode, overlapping at least a portion of the first electrode, and having a second opening overlapping at least a portion of the first opening. Further, a pixel electrode may be disposed on the protective layer and electrically connected to the first electrode in the second opening.

[0012] Further embodiments of this disclosure may provide a display device having a substrate and a driving transistor disposed on the substrate, wherein the driving transistor includes an active layer, a first electrode, a second electrode, and a third electrode. The light-emitting device may include a pixel electrode electrically connected to the first electrode, a common electrode facing the pixel electrode, and a storage capacitor disposed on the driving transistor and overlapping a channel region of the active layer of the driving transistor.

[0013] As described herein, a display device can be provided that can reduce the size of the sub-pixel circuitry portion disposed in each sub-pixel through structural optimization.

[0014] It is also possible to provide a display device that can reduce the size of the sub-pixel circuit through structural optimization, thereby increasing the size of the aperture in each sub-pixel, improving light extraction efficiency, and reducing power consumption.

[0015] It is further possible to provide a display device that simplifies the structure of the sub-pixel circuit and reduces its size by applying an overlapping structure of openings in the protective layer and openings in the gate insulating film to the sub-pixel circuit.

[0016] Therefore, a display device can be provided that simplifies the structure of the sub-pixel circuit and reduces its size by applying openings in the protective layer to the sub-pixel circuit and a non-overlapping structure of the storage capacitor.

[0017] A display device can also be provided in which the pixel electrode is electrically connected to the active layer when the electrode of the driving transistor is inserted between the pixel electrode and the active layer, so as to form a current path in the sub-pixel circuit, thereby reducing the contact resistance compared to the direct connection structure between the pixel electrode and the active layer. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0019] Figure 1 A diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 and Figure 3 An example of a sub-pixel disposed in a display device according to an embodiment of the present disclosure is shown;

[0021] Figure 4 Another example of a sub-pixel of a display device according to an embodiment of the present disclosure is shown;

[0022] Figure 5 and Figure 6 An implementation example of a subpixel according to an embodiment of the present disclosure is shown;

[0023] Figure 7 and Figure 8 Another implementation example of a subpixel according to an embodiment of this disclosure is shown; and

[0024] Figure 9 and Figure 10 Another implementation example of a subpixel according to the embodiments of this disclosure is shown. Detailed Implementation

[0025] In the following disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and the same reference numerals and symbols in the drawings may be used to indicate the same or similar components, even when these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of the various related / comparative functions and components incorporated herein may render the subject matter of some embodiments of this disclosure rather unclear.

[0026] Terms such as “comprising,” “having,” “including,” “constituting,” “composed of,” and “formed by” as used herein are generally intended to allow for the addition of additional components unless said terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0027] Furthermore, the features of the various embodiments of this disclosure can be interconnected or combined in whole or in part, and can be interlocked and operated in a wide variety of technical ways, and the embodiments can be performed independently or in relation to each other. In addition, the term "can" as used herein includes all the meanings and definitions of the term "may".

[0028] Furthermore, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0029] When referring to a first element as "connected to," "attached to," "in contact with," or "overlapping" with a second element, it should be interpreted as meaning that the first element can not only be "directly connected to" or "attached to" the second element or "directly in contact with" or "overlapping" with the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected to," "attached to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can include at least one of two or more elements that are "connected," "attached," "in contact," or "overlapping" with each other.

[0030] When time-related terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0031] Additionally, when referring to any size, relative dimensions, etc., it should be considered that, even without a specific description, the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) include tolerances or error ranges that may be caused by a variety of factors (e.g., process factors, internal or external influences, noise, etc.). Furthermore, the term "may" fully encompasses all the meanings of the term "able to".

[0032] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0033] In particular, Figure 1 A diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0034] Reference Figure 1 The display device 100 may include a display panel 110 and a driving circuit for driving the display panel 110.

[0035] As shown, the driving circuit may include a data driving circuit 120, a gate driving circuit 130, and a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.

[0036] In addition, the display panel 110 may include a substrate SUB and a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate SUB. The display panel 110 may also include a plurality of sub-pixels SP connected to the data lines DL and the gate lines GL.

[0037] The display panel 110 may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed. In the display area DA of the display panel 110, sub-pixels SP for displaying images are provided. In the non-display area NDA, a data driving circuit 120, a gate driving circuit 130, and a controller 140 may be electrically connected, or one or more of the data driving circuit 120, the gate driving circuit 130, and the controller 140 may be installed, and pads for connecting integrated circuits or printed circuits may be provided.

[0038] Furthermore, the data driving circuit 120 is used to drive the data line DL and can supply data signals to the data line DL. The gate driving circuit 130 can be a circuit for driving the gate line GL and can supply gate signals to the gate line GL. The controller 140 can supply data control signals DCS to the data driving circuit 120 to control the operating timing of the data driving circuit 120, can supply image data DATA to the data driving circuit 120, and can supply gate control signals GCS to the gate driving circuit 130 to control the operating timing of the gate driving circuit 130.

[0039] In addition, the controller 140 can receive input image data from an external source (e.g., host system 150), scan the received input image data according to the timing implemented in each frame of the received input image data, convert the input image data received from the external source into a data signal format used by the data drive circuit 120, supply image data DATA to the data drive circuit 120, and control the data drive at appropriate times according to the scanning of the received input image data.

[0040] In addition, the controller 140 can output a variety of gate control signals GCS, including gate start pulse (GSP), gate shift clock (GSC) and gate output enable signal (GOE), to control the gate drive circuit 130.

[0041] In addition, the controller 140 can output a variety of data control signals DCS, including source start pulse (SSP), source sampling clock (SSC), and source output enable signal (SOE), to control the data drive circuit 120.

[0042] The controller 140 can be implemented as a component independent of the data drive circuit 120, or it can be implemented as an integrated circuit by integrating it with the data drive circuit 120.

[0043] Furthermore, the data driving circuit 120 can receive image data DATA from the controller 140 and supply data voltage to a plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 can also be referred to as a source driving circuit.

[0044] In addition, the data driving circuit 120 may include at least one source driver integrated circuit (SDIC). For example, each source driver integrated circuit (SDIC) may be connected to the display panel 110 via tape-automated-bonding (TAB), connected to the bonding pads of the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP), or implemented and connected to the display panel 110 via chip-on-film (COF).

[0045] Furthermore, the gate drive circuit 130 can output a gate signal at the on-state voltage level or a gate signal at the off-state voltage level according to the control of the controller 140. The gate drive circuit 130 can also sequentially drive a plurality of gate lines GL by sequentially supplying gate signals at the on-state voltage level to a plurality of gate lines GL.

[0046] The gate driving circuit 130 can be connected to the display panel 110 via tape auto-bonding (TAB), to the bonding pads of the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP), or to the display panel 110 via chip-on-film (COF). Alternatively, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110 as a gate-in-panel (GIP) type. Furthermore, the gate driving circuit 130 can be disposed on or connected to the substrate SUB. If the gate driving circuit 130 is a GIP type device, it can be disposed in the non-display area NDA of the substrate SUB. If the gate driving circuit 130 is a chip-on-glass (COG) or chip-on-film (COF) type, it can also be connected to the substrate SUB.

[0047] Furthermore, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be configured not to overlap with the sub-pixel SP, or may be configured to partially or completely overlap with the sub-pixel SP.

[0048] Next, for each specific gate line driven by the gate driving circuit 130, the data driving circuit 120 can convert the image data DATA received from the controller 140 into analog data voltages and supply the converted image data to a plurality of data lines DL to activate individual sub-pixels SP with specific colors and intensities. The data driving circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method and panel design method, the data driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 110.

[0049] Furthermore, the gate driving circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the gate driving method and panel design method, the gate driving circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 110.

[0050] Next, the display controller 140 can be a timing controller used in related / comparative examples of display technology, a control device including a timing controller capable of performing other control functions, a control device other than a timing controller, or circuitry within a control device. The controller 140 can be implemented using a wide variety of circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0051] Furthermore, the controller 140 can be mounted on a printed circuit board, flexible printed circuit, or the like. The controller 140 can also be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via a printed circuit board, flexible printed circuit, or the like.

[0052] Furthermore, the display device 100 can be a display including a backlight unit, such as a liquid crystal display (LCD), or a self-emissive display, such as an organic light-emitting display (OLED), a quantum dot display, or a micro-light-emitting diode (LED) display. If the display device 100 is an organic light-emitting display, each sub-pixel SP can include a self-emissive organic light-emitting diode (OLED) as a light-emitting device. If the display device 100 is a quantum dot display, each sub-pixel SP can include a light-emitting device made of quantum dots, where quantum dots are self-emissive semiconductor crystals. If the display device 100 is a micro-LED display, each sub-pixel SP can include a self-emissive micro-LED made of inorganic materials as a light-emitting device.

[0053] The display panel 110 may have a top-emitting structure or a bottom-emitting structure, and in some cases may have a dual-sided emitting structure.

[0054] Then, Figure 2 and Figure 3 An example of a subpixel SP disposed in a display device 100 is shown. Specifically, Figure 2 An example of the equivalent circuit of a sub-pixel SP according to an embodiment of the present disclosure is shown, and Figure 3 For further explanation Figure 2 The diagram shows the equivalent circuit of the sub-pixel SP.

[0055] Reference Figure 2 Each sub-pixel SP may include a light-emitting device ED and a sub-pixel circuit SPC configured to drive the light-emitting device ED.

[0056] For example Figure 2 As shown, the sub-pixel circuit SPC may include a driving transistor DT for driving the light-emitting device ED, a scanning transistor SCT for transmitting the data voltage VDATA to the first node N1 of the driving transistor DT, and a storage capacitor Cst between the first node N1 and the second node N2 for maintaining a constant voltage within a frame.

[0057] The light-emitting device ED may include a pixel electrode PE and a common electrode CE, as well as a light-emitting layer EL positioned between the pixel electrode PE and the common electrode CE.

[0058] Furthermore, the pixel electrode PE of the light-emitting device ED can be an electrode arranged for each sub-pixel SP, and the common electrode CE can be an electrode arranged for all sub-pixels SP. Here, the pixel electrode PE can be the anode, and the common electrode CE can be the cathode. Alternatively, the pixel electrode PE can be the cathode, and the common electrode CE can be the anode.

[0059] In addition, the common electrode CE of the light-emitting device ED can be connected to the low-potential voltage line VSSL that applies the low-potential voltage EVSS.

[0060] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting device.

[0061] In addition, the driving transistor DT is used to drive the light-emitting device ED, and may include a first node N1, a second node N2, a third node N3, etc.

[0062] The first node N1 of the driving transistor DT can be the source node or the drain node of the driving transistor DT, and can be electrically connected to the pixel electrode PE of the light-emitting device ED.

[0063] The second node N2 of the driving transistor DT can be the gate node of the driving transistor DT, and can be electrically connected to the source node or drain node of the scanning transistor SCT.

[0064] The third node N3 of the driving transistor DT can be either the drain node or the source node of the driving transistor DT, and can be electrically connected to the high-potential voltage line VDDL that supplies the high-potential power supply voltage EVDD.

[0065] Furthermore, the driving transistor DT can have unique characteristics such as threshold voltage and mobility. If the unique characteristics of the driving transistor DT are changed, the current driving capability (e.g., current supply performance) of the driving transistor DT will change, and the light emission characteristics of the corresponding sub-pixel SP can also be changed.

[0066] The device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor DT can change over time. Furthermore, if light shines on the driving transistor DT, especially if the light shines on the channel region of the driving transistor DT, the device characteristics (e.g., threshold voltage, mobility, etc.) of the driving transistor DT can also change.

[0067] Therefore, as Figure 2 As shown, a shielding pattern LS can be formed near the driving transistor DT to reduce variations in the device characteristics of the driving transistor DT (e.g., threshold voltage variation, mobility variation, etc.). For example, the shielding pattern LS can be formed below the active layer of the driving transistor DT.

[0068] In addition to its light-blocking effect, the shading pattern LS can be formed below the channel region of the driving transistor DT, and can also be used as a functional part of the driving transistor DT.

[0069] Therefore, the blocking pattern LS can block light for the driving transistor DT. For example, when the display panel 110 is a bottom-emitting structure, it reduces the reflection of external light. When the blocking pattern LS is electrically connected to the first node N1 of the driving transistor DT, it will also affect the electric field of the channel region of the driving transistor DT.

[0070] Furthermore, the scanning transistor SCT can be controlled by the scanning gate signal SCAN (which is a type of gate signal) and can be connected between the second node N2 of the driving transistor DT and the data line DL.

[0071] Therefore, the scan transistor SCT can be turned on or off according to the scan gate signal SCAN supplied through the scan gate line SCL (which is a type of gate line GL) to control the connection between the data line DL and the second node N2 of the drive transistor DT.

[0072] Furthermore, the scan transistor SCT can be turned on by the scan gate signal SCAN with a turn-on level voltage, and the data voltage VDATA supplied from the data line DL can be transmitted to the second node N2 of the drive transistor DT.

[0073] Here, if the scanning transistor SCT is an n-type transistor, the on-state voltage of the scanning gate signal SCAN can be a high-level voltage. If the scanning transistor SCT is a p-type transistor, the on-state voltage of the scanning gate signal SCAN can be a low-level voltage.

[0074] Furthermore, the storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can be charged with an amount of charge corresponding to the voltage difference between the two terminals, and can maintain the voltage difference between the two terminals for a set frame time. Therefore, the corresponding sub-pixel SP can emit light during a given frame time.

[0075] Reference Figure 2 and Figure 3 The sub-pixel SP may include a light-emitting region EA (i.e., an opening) in which a light-emitting device ED is disposed, and a sub-pixel circuit SPC in which a driving transistor DT and a scanning transistor SCT are disposed. Here, the sub-pixel circuit SPC may include a scanning transistor region SCTA in which the scanning transistor SCT is disposed, and a driving transistor region DTA in which the driving transistor DT is disposed.

[0076] As shown, the first electrode E1, the second electrode E2, and the third electrode E3 of the driving transistor DT can be set in the driving transistor region DTA.

[0077] For example, the first electrode E1 can be the source electrode or drain electrode of the driving transistor DT, the second electrode E2 can be the gate electrode of the driving transistor DT, and the third electrode E3 can be the drain electrode or source electrode of the driving transistor DT.

[0078] Reference Figure 3 The third electrode E3, which is located in the driving transistor region DTA, can overlap with the high-potential voltage line VDDL, and the third electrode E3 can be electrically connected to the high-potential voltage line VDDL at the position where it overlaps with the high-potential voltage line VDDL.

[0079] Accordingly, the third electrode E3 can be disposed on the high-potential voltage line VDDL and can be electrically connected to the high-potential voltage line VDDL.

[0080] Reference Figure 2 and Figure 3 The light-emitting device ED disposed in the light-emitting region EA may include a pixel electrode PE, a light-emitting layer EL, and a common electrode CE. Here, the pixel electrode PE can extend from the light-emitting region EA in the direction of the driving transistor region DTA and overlap with the first electrode E1 and the second electrode E2 of the driving transistor DT.

[0081] Furthermore, the driving transistor region (DTA) can be formed with an overlapping structure in which the openings of the protective layer and the gate insulating film overlap, thereby simplifying the structure of the sub-pixel circuit SPC and reducing the size of the sub-pixel circuit SPC.

[0082] Please refer to later Figures 5 to 10 The specific description applies to the aperture overlap structure of the sub-pixel circuit SPC.

[0083] For reference only. Figure 5 and Figure 6 An implementation example of subpixel SP is shown. Figure 7 and Figure 8 Another implementation example of subpixel SP is shown, and Figure 9 and Figure 10 Another implementation example of the subpixel SP is shown. However, the embodiments disclosed herein are not limited to this, and the following references may also be applied. Figures 5 to 10 The described configuration is a single implementation instance of the subpixel SP.

[0084] Then, Figure 4 Another example of a subpixel SP of a display device 100 is shown.

[0085] Specifically, Figure 4 Another example of the equivalent circuit of a sub-pixel SP according to an embodiment of the present disclosure is shown. For example... Figure 4As shown, each of the plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 may further include a sensing transistor SENT.

[0086] Furthermore, the sensing transistor SENT can be controlled by the sensing gate signal SENSE (which is a type of gate signal) and can be connected between the first node N1 of the driving transistor DT and the reference voltage line RVL. In other words, the sensing transistor SENT can be turned on or off according to the sensing gate signal SENSE supplied from the sensing gate line SENL (which is another type of gate line GL) to control the connection between the reference voltage line RVL and the first node N1 of the driving transistor DT.

[0087] Furthermore, the sensing transistor SENT can be turned on by the sensing gate signal SENSE with a turn-on level voltage, and the reference voltage Vref supplied from the reference voltage line RVL can be transmitted to the first node N1 of the driving transistor DT.

[0088] Furthermore, the sensing transistor SENT can be turned on by the sensing gate signal SENSE with a turn-on level voltage, and the voltage of the first node N1 of the driving transistor DT can be transmitted to the reference voltage line RVL.

[0089] Here, if the sensing transistor SENT is an n-type transistor, the on-state voltage of the sensing gate signal SENSE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-state voltage of the sensing gate signal SENSE can be a low-level voltage.

[0090] The function of the sensing transistor SENT in transmitting the voltage of the first node N1 of the driving transistor DT to the reference voltage line RVL can be used when driving to sense the feature value of the sub-pixel SP. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage used to calculate the feature value of the sub-pixel SP or a voltage reflecting the feature value of the sub-pixel SP.

[0091] Furthermore, the driving transistor DT, the scanning transistor SCT, and the sensing transistor SENT can each be an n-type transistor or a p-type transistor. In the embodiments of this disclosure, for ease of illustration, the driving transistor DT, the scanning transistor SCT, and the sensing transistor SENT in the current example are n-type.

[0092] Furthermore, the storage capacitor Cst can be an external capacitor intentionally designed to be outside the driving transistor DT, rather than a parasitic capacitor, such as the internal capacitor (Cgs) existing between the gate node and the source node of the driving transistor DT and the internal capacitor (Cgd) existing between the gate node and the drain node of the driving transistor DT.

[0093] Furthermore, the scan gate line SCL and the sensing gate line SENL can be different gate lines GL. In this case, the scan gate signal SCAN and the sensing gate signal SENSE can be separate gate signals, and the on / off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be independent. The on / off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be the same or different.

[0094] Alternatively, the scan gate line SCL and the sensing gate line SENL can be the same gate line GL, and the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in a sub-pixel SP can be connected to a single gate line GL. In this case, the scan gate signal SCAN and the sensing gate signal SENSE can be the same gate signal, and the on / off timing of the scan transistor SCT in a sub-pixel SP and the on / off timing of the sensing transistor SENT in a sub-pixel SP can be the same.

[0095] Figure 2 and Figure 4 The structure of the sub-pixel SP shown is merely an example and can be modified in various ways to include one or more transistors or one or more capacitors.

[0096] Then, Figure 5 and Figure 6 A diagram illustrating another implementation example of the subpixel SP.

[0097] Specifically, Figure 5 A plan view of an implementation example of the driving transistor region DTA set in the sub-pixel SP is shown, and Figure 6 The driving transistor region DTA along is shown. Figure 5 The plan view shows the cross-sectional view of line A-A'.

[0098] Reference Figure 5 and Figure 6 An example subpixel SP may include a substrate 610, an occlusion pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the occlusion pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0099] The sub-pixel SP may also include a gate insulating film 640 disposed on the active layer ACT, a first electrode E1 and a second electrode E2 disposed to overlap at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1 and the second electrode E2, and a pixel electrode PE disposed on the protective layer 630 for the light-emitting device ED.

[0100] In addition, the sub-pixel SP may also include an outer coating 650 disposed on the protective layer 630.

[0101] The active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH.

[0102] The active layer ACT can be implemented as a single-film structure, and in this case, the active layer ACT can contain at least one material selected from indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO), but the embodiments disclosed herein are not limited thereto.

[0103] In addition, the sub-pixel SP may also include an auxiliary electrode disposed between the active layer ACT and the first electrode E1, and the auxiliary electrode may contain a transparent conductive oxide.

[0104] For example, transparent conductive oxides may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxide (FTO).

[0105] As another example, if an auxiliary electrode is disposed between the active layer ACT and the first electrode E1, one of the active layer ACT and the auxiliary electrode may contain indium gallium zinc oxide (IGZO) material, and the other may contain indium zinc oxide (IZO) material. However, embodiments of this disclosure are not limited thereto.

[0106] If no auxiliary electrode is provided, the active layer ACT can be an active layer in which at least a portion of the active layer ACT is conductive. For example, the active layer ACT can be conductive in at least a portion of the remaining region other than the region overlapping with the channel region CH, but embodiments of this disclosure are not limited thereto.

[0107] Furthermore, the gate insulating film 640 may include a first opening H1, and the first electrode E1 may be electrically connected in the first opening H1 to at least a portion of the first region CT1 of the active layer ACT.

[0108] Accordingly, the first opening H1 of the gate insulating film 640 may include a second connection portion CA2, in which the first electrode E1 is electrically connected to the first region CT1 of the active layer ACT.

[0109] Furthermore, the first electrode E1 can be electrically connected to the first region CT1 and can overlap with a portion of the gate insulating film 640. For example, the first electrode E1 can be the source electrode or drain electrode of the driving transistor DT. The second electrode E2 can be disposed on the gate insulating film 640 and can overlap with the channel region CH. Therefore, the second electrode E2 can be the gate electrode of the driving transistor DT.

[0110] The protective layer 630 may include a second opening H2, which overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0111] In addition, the pixel electrode PE can be electrically connected to the first electrode E1 at the second opening H2, and can also be electrically connected to the occlusion pattern LS at the second opening H2.

[0112] Accordingly, the second opening H2 may include a first connecting portion CA1 and a third connecting portion CA3. The pixel electrode PE is electrically connected to the first electrode E1 through the first connecting portion CA1, and the pixel electrode PE is electrically connected to the occlusion pattern LS through the third connecting portion CA3.

[0113] Furthermore, in a single opening of the protective layer 630 (e.g., in the second opening H2), the pixel electrode PE can be electrically connected to both the first electrode E1 and the masking pattern LS simultaneously.

[0114] Since at least a portion of the first opening H1 overlaps with at least a portion of the second opening H2, at least a portion of the first connecting portion CA1 and at least a portion of the second connecting portion CA2 can also overlap with each other.

[0115] Through the first connection portion CA1, the second connection portion CA2 and the third connection portion CA3, the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT and the occlusion pattern LS can be electrically connected to each other to form a node, namely the first node N1.

[0116] For example, the node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the occlusion pattern LS can be the source node of the driving transistor DT, but the embodiments of this disclosure are not limited thereto.

[0117] The second opening H2 may not overlap with the storage capacitor Cst disposed in each of the plurality of sub-pixels SP, and the node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT and the occlusion pattern LS may not overlap with the storage capacitor Cst.

[0118] Reference Figure 5 and Figure 6The storage capacitor Cst may overlap with the channel region CH, which may include the gate node of the driving transistor DT (i.e., the second node N2).

[0119] The second electrode E2 can be any of the capacitor electrodes constituting the storage capacitor Cst, and the pixel electrode PE can be the other capacitor electrode constituting the storage capacitor Cst.

[0120] Specifically, the storage capacitor Cst may include a second electrode E2 serving as a first capacitor electrode, and a pixel electrode PE adjacent to the second electrode E2 serving as a second capacitor electrode. Furthermore, a protective layer 630 disposed between the first capacitor electrode and the second capacitor electrode may be included as an insulator for the storage capacitor Cst.

[0121] Reference Figure 5 and Figure 6 The active layer ACT may include an outer peripheral region of a first connection portion CA1 disposed in the second opening H2 and a second connection portion CA2 disposed in the first opening H1. Furthermore, a current path C / P in the active layer ACT may be formed in the outer peripheral region.

[0122] Accordingly, the vertically overlapping pixel electrodes PE and active layer ACT can be connected to each other through the first electrode E1 instead of directly. This forms a current path (C / P) for the active layer ACT around the first opening H1 and the second opening H2. Therefore, the size of the sub-pixel circuit SPC can be reduced and drive failures caused by high contact resistance when the pixel electrodes PE and active layer ACT are directly connected can be prevented.

[0123] Reference Figure 5 The second electrode E2, which overlaps with the channel region CH of the active layer ACT, can extend to a region that does not overlap with the active layer ACT, and can be electrically connected to the source electrode or drain electrode ACT_SC of the scan transistor SCT. For ease of illustration, the reference numeral "ACT_SC" can be used to describe the source electrode of the scan transistor SCT.

[0124] Figure 5 The sub-pixel SP may also include a third electrode E3, which extends into the region where the active layer ACT is formed and the high-potential voltage line VDDL is formed, and overlaps with the high-potential voltage line VDDL and the second region CT2.

[0125] The third electrode E3 can be electrically connected to at least a portion of the high-potential voltage line VDDL and at least a portion of the second region CT2 of the active layer ACT on the high-potential voltage line VDDL. Therefore, a high-potential power supply voltage EVDD can be applied to the second region CT2 through the high-potential voltage line VDDL. The third electrode E3 can be the drain or source electrode of a driving transistor. If an auxiliary electrode is provided between the active layer ACT and the first electrode E1, an auxiliary electrode can also be provided between the active layer ACT and the third electrode E3.

[0126] according to Figure 5 For example, the high-potential voltage line VDDL and the data line DL can be formed from the same material as the shielding pattern LS.

[0127] Furthermore, the scan gate line and the first electrode E1, second electrode E2, and third electrode (E3) of the driving transistor DT can be formed of the same material. Even further, the active layer ACT of the driving transistor DT and the source electrode ACT_SC of the scan transistor SCT can be formed of the same material.

[0128] Then, Figure 7 and Figure 8 A diagram illustrating another implementation example of subpixel SP.

[0129] Specifically, Figure 7 A plan view of another embodiment of the driving transistor region DTA set in the sub-pixel SP, and showing the relationship with... Figure 5 Compared to the magnified view of the first electrode E1 and the second electrode E2 of the driving transistor DT, and Figure 8 The driving transistor region DTA along is shown. Figure 7 The plan view shows the cross-sectional view of line B-B'.

[0130] like Figure 7 and Figure 8 As shown, the example sub-pixel SP may include a substrate 610, a masking pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the masking pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0131] The sub-pixel SP may include a gate insulating film 640 disposed on the active layer ACT and having a first opening H1, a first electrode E1 disposed to overlap at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1, and a pixel electrode PE of the light-emitting device ED disposed on the protective layer 630.

[0132] Furthermore, the sub-pixel SP may also include an outer coating 650 disposed on the protective layer 630. The sub-pixel SP may also include an auxiliary electrode 800 disposed between the active layer ACT and the first electrode E1, and the auxiliary electrode 800 may comprise a transparent conductive oxide.

[0133] For example, the transparent conductive oxide may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxide (FTO). Furthermore, one of the active layer ACT and the auxiliary electrode may comprise indium gallium zinc oxide (IGZO) material, and the other may comprise indium zinc oxide (IZO) material, but embodiments of this disclosure are not limited thereto.

[0134] Furthermore, the active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH. The first electrode E1 may be electrically connected to at least a portion of the first region CT1 of the active layer ACT in the first opening H1.

[0135] In other words, the first electrode E1 can be electrically connected to the auxiliary electrode 800 and the active layer ACT in the first opening H1. Accordingly, the first opening H1 of the gate insulating film 640 may include a second connection portion CA2, through which the first electrode E1 is electrically connected to the first region CT1 of the active layer ACT.

[0136] Next, the first electrode E1 can be the source electrode or drain electrode of the driving transistor DT.

[0137] The protective layer 630 is disposed on the first electrode E1 and may have a second opening H2, which overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0138] The pixel electrode PE can be electrically connected to the first electrode E1 at the second opening H2, and can also be electrically connected to the occlusion pattern LS at the second opening H2.

[0139] The second opening H2 may include a first connecting portion CA1 and a third connecting portion CA3. In the first connecting portion CA1, the pixel electrode PE is electrically connected to the first electrode E1, and in the third connecting portion CA3, the pixel electrode PE is electrically connected to the occlusion pattern LS.

[0140] Accordingly, the pixel electrode PE can be electrically connected to the first electrode E1 and the masking pattern LS simultaneously in a single opening of the protective layer 630, i.e., at the second opening H2.

[0141] Through the first connection portion CA1, the second connection portion CA2 and the third connection portion CA3, the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT and the occlusion pattern LS can be electrically connected to each other to form a node, namely the first node N1.

[0142] For example, the node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the occlusion pattern LS can be the source node of the driving transistor DT, but the embodiments of this disclosure are not limited thereto.

[0143] The node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the masking pattern LS can be free from overlapping with the storage capacitor Cst disposed in each of the plurality of sub-pixels SP formed on the substrate.

[0144] As Figure 6 A variation of the apparatus shown may omit the first electrode E1 to allow the pixel electrode PE to directly contact the first region CT1 of the active layer ACT. The first electrode E1 may also be omitted in the following embodiments. In a variety of other embodiments, the layer used to generate the pixel electrode PE may be patterned to also provide an electrode that directly contacts the third region CT3 of the active layer ACT.

[0145] Reference Figure 7 The storage capacitor Cst may overlap with the channel region CH, which in this case includes a second node N2 that serves as the gate node of the driving transistor DT.

[0146] Reference Figure 7 and Figure 8 A current path C / P of the active layer ACT can be formed in the region of the second connection portion CA2, which passes through the first region CT1 where the first electrode E1 and the active layer ACT are electrically connected.

[0147] In other words, the embodiments of this disclosure can form the current path C / P of the active layer ACT in the lower region of the first electrode E1 by connecting the pixel electrodes PE, which are perpendicularly overlapping each other, to the active layer ACT via the first electrode E1 and the auxiliary electrode 800, instead of directly connecting the pixel electrodes PE to the active layer ACT. This reduces the size of the sub-pixel circuit SPC and prevents drive failures caused by the high contact resistance that would result when the pixel electrodes PE are directly connected to the active layer ACT.

[0148] Furthermore, portions of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may not overlap with the masking pattern LS, and each of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may have steps in the regions that do not overlap with the masking pattern LS.

[0149] In other words, the subpixel SP can be implemented as a structure without PAD, wherein the occlusion pattern LS is not set below at least some areas of the second connecting portion CA2.

[0150] Then, Figure 9 and Figure 10 A diagram illustrating another implementation example of the subpixel SP.

[0151] Specifically, Figure 9 This is a plan view of another embodiment of the driving transistor region DTA set in the sub-pixel SP, and for... Figure 7 Compared to a horizontally flipped image, the plan view, and Figure 10 To drive the transistor region DTA along Figure 9 The plan view shows the cross-sectional view of line C-C'.

[0152] Reference Figure 9 and Figure 10 According to the embodiments of the present disclosure, the sub-pixel SP may include a substrate 610, a masking pattern LS disposed on the substrate 610, a buffer layer 620 disposed on the substrate 610 and the masking pattern LS, and an active layer ACT disposed on the buffer layer 620.

[0153] In addition, the sub-pixel SP may include a gate insulating film 640 disposed on the active layer ACT, a first electrode E1 and a second electrode E2 disposed to overlap at least a portion of the gate insulating film 640, a protective layer 630 disposed on the first electrode E1 and the second electrode E2, and a pixel electrode PE disposed on the protective layer 630 for the light-emitting device ED.

[0154] In addition, the sub-pixel SP may also include an outer coating 650 disposed on the protective layer 630.

[0155] The sub-pixel SP may also include an auxiliary electrode 800 disposed between the active layer ACT and the first electrode E1, and the auxiliary electrode 800 may contain a transparent conductive oxide.

[0156] For example, transparent conductive oxides may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxide (FTO).

[0157] In addition, the auxiliary electrode may contain indium gallium zinc oxide (IGZO) material, and another may contain indium zinc oxide (IZO) material, but the embodiments disclosed herein are not limited thereto.

[0158] In addition, the active layer ACT may include a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH.

[0159] The gate insulating film 640 may include a first opening H1, and the first electrode E1 may be electrically connected to the first region CT1 and the shielding pattern LS in the first opening H1.

[0160] In other words, the first opening H1 of the gate insulating film 640 may include a second connection portion CA2 and a fourth connection portion CA4, in which the first electrode E1 is electrically connected to the first region CT1 of the active layer ACT, and in the fourth connection portion CA4, the first electrode E1 is electrically connected to the shielding pattern LS.

[0161] The first electrode E1 can be configured to be electrically connected to the first region CT1, and can be configured to overlap with a portion of the gate insulating film 640. For example, the first electrode E1 can be the source electrode or drain electrode of the driving transistor DT.

[0162] Reference Figure 9 and Figure 10 The second electrode E2 can be configured to overlap with the channel region CH on the gate insulating film 640, and the second electrode E2 can extend to a region that does not overlap with the active layer ACT.

[0163] For example, the second electrode E2 can be the gate electrode of the driving transistor DT.

[0164] The protective layer 630 may include a second opening H2, which overlaps with at least a portion of the first electrode E1 and at least a portion of the first opening H1.

[0165] The pixel electrode PE can be electrically connected to the first electrode E1 in the second opening H2. In addition, the second opening H2 may include a first connection portion CA1 in which the pixel electrode PE is electrically connected to the first electrode E1, and the second opening H2 may also include a second connection portion CA2 and a fourth connection portion CA4.

[0166] Accordingly, in a single opening (i.e., the second opening H2) of the protective layer 630, the pixel electrode PE can be electrically connected simultaneously to the first electrode E1, the first region CT1 of the active layer ACT, and the occlusion pattern LS.

[0167] At least a portion of the first opening H1 and at least a portion of the second opening H2 may overlap each other. At least a portion of the first connecting portion CA1 and at least a portion of the second connecting portion CA2 may overlap each other. At least a portion of the first connecting portion CA1 and at least a portion of the fourth connecting portion CA4 may overlap each other.

[0168] Through the first connection portion CA1, the second connection portion CA2 and the fourth connection portion CA4, the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT and the occlusion pattern LS can be electrically connected to each other to form a node, namely the first node N1.

[0169] For example, the node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the occlusion pattern LS can be the source node of the driving transistor DT, but the embodiments of this disclosure are not limited thereto. The node formed by the pixel electrode PE, the first electrode E1, the first region CT1 of the active layer ACT, and the occlusion pattern LS may not overlap with the storage capacitor Cst disposed in each of the plurality of sub-pixels SP.

[0170] Furthermore, the storage capacitor Cst can overlap with the channel region CH. In other words, the storage capacitor Cst disposed in the sub-pixel SP can overlap with the gate node (i.e., the second node N2) of the driving transistor DT.

[0171] The second electrode E2 can be one of the capacitor electrodes constituting the storage capacitor Cst, and the pixel electrode PE can be the other capacitor electrode constituting the storage capacitor Cst.

[0172] For example, the storage capacitor Cst may include a second electrode E2 as a first capacitor electrode, a pixel electrode PE adjacent to the second electrode E2 as a second capacitor electrode, and may include at least a portion of a protective layer 630 disposed between the first capacitor electrode and the second capacitor electrode, including an insulator as the storage capacitor Cst.

[0173] Reference Figure 9 and Figure 10 A current path C / P of the active layer ACT can be formed in the region of the second connection portion CA2, which passes through the first region CT1 where the first electrode E1 and the active layer ACT are electrically connected.

[0174] Accordingly, the current path (C / P) of the active layer ACT can be formed in the lower region of the first electrode E1 by connecting the pixel electrodes PE, which are perpendicularly overlapping each other, to the active layer ACT via the first electrode E1 and the auxiliary electrode 800. This reduces the size of the sub-pixel circuit SPC and prevents drive failures caused by the high contact resistance generated when the pixel electrodes PE are directly connected to the active layer ACT.

[0175] Some regions of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may not overlap with the masking pattern LS, and each of the buffer layer 620, protective layer 630, gate insulating film 640, first electrode E1, and active layer ACT may have steps in the regions that do not overlap with the masking pattern LS.

[0176] Accordingly, the subpixel SP can be implemented as a structure without PAD, wherein at least some areas of the second connecting portion CA2 are not provided with an occlusion pattern LS below it.

[0177] The embodiments of the present disclosure described above are briefly described below. A display device according to an embodiment of the present disclosure may include: a substrate; an active layer disposed on the substrate and including a channel region, a first region located on one side of the channel region, and a second region located on the other side of the channel region; a gate insulating film disposed on the active layer and having a first opening; a first electrode electrically connected to at least a portion of the first region in the first opening; a second electrode disposed on the gate insulating film and overlapping the channel region; a protective layer disposed on the first electrode and the second electrode, overlapping at least a portion of the first electrode, and having a second opening overlapping at least a portion of the first opening; and a pixel electrode disposed on the protective layer and electrically connected to the first electrode in the second opening. The display device may further include a masking pattern disposed on the substrate and a buffer layer disposed on the substrate and the masking pattern. The masking pattern may be electrically connected to the pixel electrode at the second opening. The pixel electrode, the first electrode, the active layer, and the masking pattern may be electrically connected to each other. The display device may further include a storage capacitor disposed on the substrate and including a plurality of capacitor electrodes. The storage capacitor may not overlap with the second opening. One of the capacitor electrodes may be a second electrode, and the other of the capacitor electrodes may be a pixel electrode. The second electrode may extend to a region that does not overlap with the channel region.

[0178] The active layer may include an outer peripheral region, which includes a first connection portion in which a pixel electrode is electrically connected to a first electrode and a second connection portion in which the first electrode is electrically connected to a first region. Current paths in the active layer may be formed in the outer peripheral region. The display device may also include an auxiliary electrode disposed between the active layer and the first electrode. The auxiliary electrode may comprise a transparent conductive oxide.

[0179] A current path in the active layer can be formed in the region through which the first electrode is electrically connected to the first region. The first electrode can be electrically connected to the shielding pattern at the second opening. At least a portion of the second connection portion in which the first electrode is electrically connected to the first region may not overlap with the shielding pattern.

[0180] The display device according to embodiments of this disclosure may further include a light-emitting device and a driving transistor for driving the light-emitting device. The first electrode may be the source electrode or drain electrode of the driving transistor, and the second electrode may be the gate electrode of the driving transistor. The first electrode and the second electrode may be formed of the same material. The display device may further include a high-potential voltage line to which a high-potential voltage is applied; and a third electrode electrically connected between the second region and the high-potential voltage line. The first electrode, the second electrode, and the third electrode may contain the same material.

[0181] A display device according to an embodiment of the present disclosure may include: a substrate; a driving transistor disposed on the substrate and including an active layer, a first electrode, a second electrode, and a third electrode. The display device may further include a light-emitting device including a pixel electrode electrically connected to the first electrode and a common electrode facing the pixel electrode; and a storage capacitor disposed on the driving transistor. The storage capacitor may overlap with the channel region of the active layer of the driving transistor.

[0182] The display device according to an embodiment of the present disclosure may further include: a gate insulating film disposed on an active layer and having a first opening; and a protective layer disposed on a first electrode and a second electrode, wherein the protective layer overlaps with at least a portion of the first electrode and has a second opening overlapping with at least a portion of the first opening. The display device may further include a pixel electrode disposed on the protective layer and connected to the first electrode in the second opening, the first electrode being electrically connected to at least a portion of the active layer through the first opening.

[0183] The foregoing description has been presented to enable any person skilled in the art to access and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and alternatives to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The foregoing description and figures are provided for illustrative purposes only as examples of the technical concepts of this disclosure.

Claims

1. A display device, comprising: substrate; A transistor on the substrate, the transistor including an active layer, wherein the active layer includes a channel region, a first region located on one side of the channel region and a second region located on the other side of the channel region; A gate insulating film, wherein the gate insulating film is disposed on the active layer and has a first opening; A first electrode, wherein the first electrode is electrically connected in the first opening to at least a portion of the first region of the active layer; The second electrode is disposed on the gate insulating film and overlaps with the channel region; A protective layer is disposed on the first electrode and the second electrode, the protective layer overlapping at least a portion of the first electrode and having a second opening overlapping at least a portion of the first opening; as well as A pixel electrode is disposed on the protective layer and electrically connected to the first electrode in the second opening.

2. The display device according to claim 1, further comprising: A shielding pattern is provided on the substrate; as well as A buffer layer is disposed on the substrate and the shielding pattern.

3. The display device according to claim 2, wherein the occlusion pattern is electrically connected to the pixel electrode at the second opening.

4. The display device according to claim 2, wherein the pixel electrode, the first electrode, the active layer and the occlusion pattern are electrically connected to each other.

5. The display device according to claim 1 further includes a storage capacitor disposed on the substrate and comprising a plurality of capacitor electrodes. The storage capacitor therein does not overlap with the second opening.

6. The display device according to claim 5, wherein one of the plurality of capacitor electrodes is the second electrode.

7. The display device according to claim 5, wherein another of the plurality of capacitor electrodes is the pixel electrode.

8. The display device of claim 5, wherein the second electrode extends into a region that does not overlap with the channel region.

9. The display device of claim 1, wherein the active layer includes an outer peripheral region, the outer peripheral region including a first connection portion wherein the pixel electrode is electrically connected to the first electrode, and a second connection portion wherein the first electrode is electrically connected to the first region, and The current path in the active layer is formed in the outer peripheral region.

10. The display device according to claim 1, further comprising an auxiliary electrode disposed between the active layer and the first electrode. The auxiliary electrode comprises a transparent conductive oxide.

11. The display device of claim 10, wherein a current path in the active layer is formed in a region through a second connection portion wherein the first electrode is electrically connected to the first region.

12. The display device of claim 2, wherein the first electrode is electrically connected to the occlusion pattern at the second opening.

13. The display device of claim 2, wherein the first electrode and the first region are electrically connected at the second connection portion, and in, At least a portion of the second connection portion in which the first electrode is electrically connected to the first region does not overlap with the occlusion pattern.

14. The display device according to claim 1, The transistor mentioned is a driving transistor used to drive the light-emitting device. The first electrode is the source or drain electrode of the driving transistor, and the second electrode is the gate electrode of the driving transistor. The first electrode and the second electrode are formed of the same material.

15. The display device according to claim 1, further comprising: A high-potential voltage line to which a high-potential voltage is applied; and A third electrode is electrically connected between the second region and the high-potential voltage line.

16. The display device of claim 15, wherein the first electrode, the second electrode, and the third electrode comprise the same material.

17. A display device, comprising: substrate; A driving transistor is disposed on the substrate and includes an active layer, a first electrode, a second electrode, and a third electrode; A light-emitting device, the light-emitting device comprising a pixel electrode electrically connected to the first electrode and a common electrode facing the pixel electrode; as well as A storage capacitor is disposed on the driving transistor and overlaps with the channel region of the active layer of the driving transistor.

18. The display device according to claim 17, further comprising: A gate insulating film disposed on the active layer and having a first opening; A protective layer disposed on the first electrode and the second electrode, overlapping at least a portion of the first electrode, the protective layer having a second opening overlapping at least a portion of the first opening; as well as A pixel electrode is disposed on the protective layer and connected to the first electrode in the second opening, wherein the first electrode is electrically connected to at least a portion of the active layer through the first opening.

19. A display device, comprising: substrate; A light-shielding portion disposed on the substrate; A transistor disposed on the light-shielding portion and overlapping the light-shielding portion in a plan view, the transistor includes an active layer, the active layer including a channel region overlapping the light-shielding portion, a first region located on one side of the channel region, and a second region located on the other side of the channel region; A first electrode electrically connected to the first region, a second electrode overlapping the channel region, and a third electrode electrically connected to the second region; as well as The light-emitting device includes a common electrode connected to a first power supply voltage line to which a first power supply voltage is applied, a pixel electrode, and a light-emitting element disposed between the common electrode and the pixel electrode. The pixel electrode includes an integrally formed portion that overlaps with the second electrode to form a storage capacitor. The pixel electrode directly contacts the first electrode and overlaps with the common electrode and the light-emitting element in a plan view.

20. The display device according to claim 19, further comprising: An insulating film between the light-shielding portion and the channel region; A gate insulating film including a first hole between the second electrode and the active layer; as well as An insulating layer between the pixel electrode and the second electrode includes a second hole that overlaps with the first hole in the plan view. The first hole and the second hole overlap at a position directly above the light-shielding part.

Images