Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel comprises a display area and first frame areas, the first frame areas are arranged on the two opposite sides of the display area, the display panel comprises a back plate, and the back plate is provided with first signal lines in the first frame areas; the first metal layer is arranged on one side of the back plate, the first metal layer extends from the display area to the first frame area, and the first metal layer is electrically connected with the first signal line in the first frame area; in the display area, the first metal layer comprises a plurality of metal patterns, pixel openings are formed between adjacent metal patterns, pixel units are arranged in the pixel openings, and cathode patterns of the pixel units are electrically connected with the metal patterns.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular, to a display panel and a display device. BACKGROUND

[0002] With the pursuit of high-quality display and the progress of technology, the resolution of color display is constantly improved, and the application of active matrix organic light-emitting diode or active matrix organic light-emitting diode display panel (AMOLED for short) as the next generation display technology is also becoming more and more important.

[0003] However, since the resistance of the cathode metal layer in the existing AMOLED display panel is high, when directly lapping with the VSS signal line, due to the high resistance of the cathode material, when the current passes through the cathode metal layer, it will cause the VSS signal line to generate a high voltage drop IR Drop, thereby causing adverse effects on the display performance of the display panel. Therefore, how to reduce the voltage drop of the VSS signal line in the display panel and improve the display performance has become a problem to be solved in the current field. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, aiming to solve the problem of how to reduce the voltage drop of the VSS signal line in the display panel and improve the display performance.

[0005] The first aspect of the embodiments of the present application provides a display panel, the display panel comprising a display area and a first frame area, the first frame area being arranged on opposite sides of the display area, and the display panel comprising:

[0006] a back plate, the back plate being provided with a first signal line in the first frame area;

[0007] a first metal layer, the first metal layer being arranged on one side of the back plate, the first metal layer extending from the display area to the first frame area and forming an electrical connection with the first signal line in the first frame area;

[0008] In the display area, the first metal layer comprises a plurality of metal patterns, a pixel opening is formed between adjacent metal patterns, a pixel unit is arranged in the pixel opening, and a cathode pattern of the pixel unit forms an electrical connection with the metal pattern.

[0009] In an optional implementation, the pixel unit comprises a first pixel unit, a second pixel unit and a third pixel unit, and the display panel further comprises:

[0010] A first encapsulation layer, within the display area, is configured to at least cover one surface of the cathode pattern of the first pixel unit facing away from the backplate.

[0011] A second encapsulation layer, within the display area, is configured to at least cover the side surface of the cathode pattern of the second pixel unit facing away from the backplate.

[0012] A third encapsulation layer, within the display area, is configured to at least cover the side surface of the cathode pattern of the third pixel unit facing away from the backplate.

[0013] In one alternative embodiment, within the first frame area, the first encapsulation layer and the second encapsulation layer are sequentially stacked on the side of the first metal layer facing away from the back plate, with the first encapsulation layer disposed close to the first metal layer.

[0014] Within the first border area, the boundaries of the first encapsulation layer and the second encapsulation layer are staggered.

[0015] In one alternative embodiment, within the first bezel area, the back panel is further provided with a gate driving circuit, which is disposed on the side of the first signal line near the display area.

[0016] The boundaries of the first encapsulation layer and the second encapsulation layer are located on the side of the gate driving circuit near the display area.

[0017] In one alternative implementation, within the first border area, the distance between the boundary of the first encapsulation layer and the boundary of the second encapsulation layer along a first direction is greater than or equal to a first distance threshold, the first distance threshold being greater than or equal to 40 micrometers and less than or equal to 60 micrometers, and the first direction being the direction from the display area to the first border area.

[0018] In one optional embodiment, within the first border area, the distance between the boundary of the first encapsulation layer and the boundary of the second encapsulation layer and the display area along the first direction is greater than or equal to 100 micrometers and less than or equal to 200 micrometers, respectively. The first direction is the direction from the display area to the first border area.

[0019] In one alternative embodiment, within the first border area, the third encapsulation layer is disposed on the side of the second encapsulation layer opposite to the backplate;

[0020] The display panel also includes a barrier dam, which is disposed on the side of the first metal layer away from the display area, and the boundary of the third encapsulation layer is disposed on the side of the barrier dam away from the display area.

[0021] In one alternative embodiment, the display panel further includes a planarization layer disposed on the side of the back panel near the first metal layer;

[0022] Within the first frame area, the first metal layer includes a first part and a second part that are connected to each other, wherein the first part is disposed on the side of the flat layer opposite to the back plate.

[0023] The second part is disposed away from the display area relative to the first part, and the second part is disposed on the side of the flat layer away from the display area.

[0024] In one alternative embodiment, the display panel further includes a barrier dam disposed on the side of the second part away from the display area and disposed on the same layer as the planarization layer;

[0025] The second part's orthographic projection on the back plate covers the first signal line, and the orthographic projection of the blocking dam on the back plate does not overlap with the first signal line.

[0026] In one alternative embodiment, the display panel further includes a barrier dam disposed on the side of the second portion away from the display area and disposed on the same layer as the planarization layer;

[0027] The orthographic projection of the second part on the back plate partially overlaps with the first signal line, and the orthographic projection of the blocking dam on the back plate at least partially overlaps with the first signal line.

[0028] In one alternative embodiment, the display panel further includes a pixel defining layer disposed between the planarization layer and the first metal layer;

[0029] Within the first border area, the display panel includes an opening area, in which a plurality of through holes are provided, the plurality of through holes being configured to penetrate the pixel defining layer and the first metal layer.

[0030] In an optional embodiment, the back panel is further provided with a gate driving circuit in the first frame area, and the gate driving circuit is disposed on the side of the first signal line near the display area.

[0031] The orthographic projection of the plurality of vias on the backplate is located inside the region where the gate drive circuit is located.

[0032] In one alternative embodiment, the metal pattern is an undercut structure, the undercut structure including a groove, the groove forming an opening on the side opposite to the back plate, and in a second direction, the size of the groove opening is smaller than the size of the groove interior, the second direction being the arrangement direction of the back plate and the first metal layer.

[0033] In one alternative embodiment, the cathode pattern extends from the pixel opening into the recess of the undercut structure and forms an electrical connection with the sidewall of the metal pattern inside the recess.

[0034] In one optional embodiment, the display panel further includes a second border area disposed on one side of the display area, with the first border area disposed opposite to both sides of the second border area;

[0035] Within the second frame area, the back panel is provided with a second signal line, and the boundary of the first metal layer is located on the side of the second signal line near the display area.

[0036] In one alternative embodiment, the boundary of the first metal layer is located on the side of the boundary of the first encapsulation layer away from the display area.

[0037] A second aspect of this application provides a display panel, the display panel including a display area and a first border area, the first border area being disposed on opposite sides of the display area, the display panel including:

[0038] A backplate, wherein a first signal line is provided within the first frame area;

[0039] A first metal layer is disposed on one side of the back panel, and the first metal layer extends from the display area to the first bezel area;

[0040] Within the display area, the first metal layer includes multiple metal patterns, with pixel openings formed between adjacent metal patterns. Pixel units are disposed within the pixel openings, and the cathode pattern of the pixel unit is electrically connected to the metal patterns.

[0041] An anode layer is disposed between the first metal layer and the back plate. Within the first frame area, the first metal layer is electrically connected to the first signal line through the anode layer.

[0042] In one alternative embodiment, the display panel further includes a planarization layer disposed between the back panel and the first metal layer;

[0043] Within the first frame area, the anode layer includes a third part and a fourth part that are interconnected, the third part being disposed on the side of the flat layer opposite to the back plate;

[0044] The fourth part is disposed away from the display area relative to the third part, and the fourth part is disposed on the side of the flat layer away from the display area. The orthographic projection of the fourth part on the back plate at least partially overlaps with the first signal line.

[0045] In one alternative embodiment, the thickness of the anode layer along the second direction is less than the thickness of the first metal layer along the second direction, where the second direction is the arrangement direction of the backplate and the first metal layer.

[0046] A third aspect of this application provides a display device, the display device comprising a display panel as described in any one of the first aspects of this application, or the display device comprising a display panel as described in any one of the second aspects of this application.

[0047] Beneficial effects:

[0048] This application provides a display panel and a display device. The display panel includes a display area and a first bezel area, with the first bezel area disposed on opposite sides of the display area. The display panel includes: a back plate, with a first signal line disposed within the first bezel area; and a first metal layer disposed on one side of the back plate, extending from the display area to the first bezel area and electrically connected to the first signal line within the first bezel area. Within the display area, the first metal layer includes multiple metal patterns, with pixel openings formed between adjacent metal patterns. Pixel units are disposed within the pixel openings, and the cathode patterns of the pixel units are electrically connected to the metal patterns. By providing a first metal layer that extends from the display area to the first bezel area and directly connects to the cathode patterns in the pixel units within the display area, while simultaneously directly connecting to the first signal line within the first bezel area, this application achieves the connection between the cathode and the first signal line through a first metal layer with lower resistance, effectively reducing the voltage drop of the first signal line and improving the display performance of the display panel.

[0049] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a top view schematic diagram of a display panel according to an embodiment of this application;

[0052] Figure 2 This is a schematic diagram of the structure of multiple pixel units in the display area of ​​a display panel according to an embodiment of this application;

[0053] Figure 3 This is a schematic diagram of a display panel structure in which the first metal layer and the first signal line are completely overlapped in the first frame area, according to an embodiment of this application.

[0054] Figure 4 This is a partially enlarged schematic diagram of a display panel in an embodiment of this application, showing the portion of the display panel away from the display area when the first metal layer and the first signal line are fully overlapped in the first frame area;

[0055] Figure 5 This is a partially enlarged schematic diagram of the portion of a display panel near the display area when the first metal layer and the first signal line are fully overlapped in the first frame area, according to an embodiment of this application.

[0056] Figure 6 This is a partially enlarged schematic diagram of a display panel in an embodiment of this application, showing the portion of the display panel away from the display area when the first metal layer and the first signal line portion overlap in the first frame area;

[0057] Figure 7 This is a partially enlarged schematic diagram of a display panel in an embodiment of this application, showing the portion of the display panel away from the display area when the anode layer overlaps with the first signal line in the first frame area;

[0058] Figure 8 This is a schematic diagram of the structure of a display panel within the second border area according to an embodiment of this application;

[0059] Figure 9 This is a schematic diagram of the structure for forming the first metal layer in a display panel fabrication method according to an embodiment of this application;

[0060] Figure 10 This is a schematic diagram of the structure for forming a first pixel unit in a display panel manufacturing method according to an embodiment of this application;

[0061] Figure 11This is a schematic diagram of the structure for forming a second pixel unit in a display panel manufacturing method according to an embodiment of this application;

[0062] Figure 12 This is a schematic diagram of the structure for forming a third pixel unit in a display panel manufacturing method according to an embodiment of this application.

[0063] Explanation of reference numerals in the attached drawings: 11, Backplate; 111, First signal line; 112, Second signal line; 113, Gate driving circuit; 114, Virtual pixel unit; 21, First metal layer; 211, First part; 212, Second part; 213, Metal pattern; 311, First pixel unit; 3111, First light-emitting layer; 312, Second pixel unit; 3121, Second light-emitting layer; 313, Third pixel unit; 3131, Third light-emitting layer; 32, Cathode layer; 321, Cathode pattern; 33, Anode layer; 331, Third part; 332, Fourth part; 41, First encapsulation layer; 42, Second encapsulation layer; 43, Third encapsulation layer; 44, Fourth encapsulation layer; 45, Organic encapsulation layer; 51, Barrier dam; 52, Planarization layer; 53, Pixel boundary layer; 61, Through-hole; AA, Display area; B1, First border area; B2, Second border area; F1, First direction; F2, Second direction. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas may sometimes be exaggerated for clarity. Therefore, any implementation of this application is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and any implementation of this application is not limited to the shapes or values ​​shown in the drawings.

[0066] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0067] With the pursuit of high-quality displays and technological advancements, the resolution of color displays continues to improve, and the application of Active Matrix Organic Light-Emitting Diode (AMOLED) display panels, known as the next generation of display technology, is becoming increasingly important.

[0068] In related technologies, the VSS signal line serves as the cathode voltage (or ground voltage) of the display panel. When current flows through the cathode metal layer, a certain voltage drop, known as IR Drop, occurs. Because the cathode metal layer in existing AMOLED display panels has high resistance, when directly connected to the VSS signal line, the high resistance of the cathode material causes a significant IR Drop when current flows through the cathode metal layer, thus adversely affecting the display performance of the panel.

[0069] In view of this, embodiments of this application propose a display panel, Figure 1 This illustration shows a top view of a display panel according to an embodiment of this application, as shown below. Figure 1 As shown, the display panel includes a display area AA and a non-display area. The non-display area includes a first border area B1, which is disposed on opposite sides of the display area AA. The display area AA refers to the area in the display panel used for displaying images and information. The non-display area refers to the part of the display panel other than the display area AA. The non-display area is disposed around the display area AA. The non-display area does not directly participate in the display of images and is usually used to provide space for the display panel, including driving circuits, signal lines, borders, and functional devices (such as front-facing cameras, sensors, etc.) that may be arranged at the edge of the screen.

[0070] In this embodiment of the application, the display panel may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc., and this embodiment of the application does not make specific limitations.

[0071] In the embodiments of this application, Figure 2 This illustration shows a schematic diagram of the structure of multiple pixel units in the display area of ​​a display panel according to an embodiment of this application. Figure 3 This illustration shows a schematic diagram of a display panel according to an embodiment of the present application, in which the first metal layer and the first signal line are completely overlapped in the first bezel area. Figure 2 and Figure 3As shown, the display panel includes a backplate 11. The backplate 11 has a first signal line 111 disposed within the first frame area B1. The first signal line 111 is configured as the common ground terminal of the circuit in the backplate 11, serving as a current return path to ensure that the current in the display panel can form a complete loop, thereby maintaining the normal operation of the display panel. For example, the first signal line 111 is a VDD signal line, through which the cathode voltage (or ground voltage) is provided to the display panel.

[0072] In this embodiment, the display panel further includes a first metal layer 21, which is disposed on one side of the back panel 11. The first metal layer 21 extends from the display area AA to the first border area B1 and forms an electrical connection with the first signal line 111 within the first border area B1. Within the display area AA, the first metal layer 21 includes a plurality of metal patterns 213, with pixel openings formed between adjacent metal patterns 213. Pixel units are disposed within the pixel openings, and the cathode pattern 321 of the pixel unit is electrically connected to the metal patterns 213. In this embodiment, the resistance of the first metal layer 21 is less than the resistance of the cathode pattern 321. By setting the first metal layer 21, the metal pattern 213 in the display area AA and the cathode pattern 321 in the pixel unit directly contact each other to form an electrical connection. At the same time, the first metal layer 21 extends to the first border area B1 and directly contacts the first signal line 111 in the first border area B1 to form an electrical connection. This avoids the direct contact between the cathode pattern 321 and the first signal line 111. Instead, the electrical connection is achieved through the first metal layer 21 with lower resistance. When the display panel current passes through, the resistance of the material directly contacting the first signal line 111 is reduced, thereby effectively reducing the voltage drop of the first signal line 111.

[0073] In some optional embodiments, the first metal layer 21 includes a plurality of stacked metal sublayers, the materials of which include, but are not limited to, Ti and Al. For example, the first metal layer 21 includes a first metal sublayer, a second metal sublayer, and a third metal sublayer stacked together, with the second metal sublayer disposed between the first metal sublayer and the third metal sublayer, wherein the first metal sublayer and the third metal sublayer are made of Ti, and the second metal sublayer is made of Al.

[0074] In some alternative implementations, such as Figure 2As shown, the pixel unit includes a first pixel unit 311, a second pixel unit 312, and a third pixel unit 313. For example, the first pixel unit 311, the second pixel unit 312, and the third pixel unit 313 are combinations of red pixel units, green pixel units, and blue pixel units. It should be noted that the corresponding pixel color combination of the first pixel unit 311, the second pixel unit 312, and the third pixel unit 313 can be determined according to actual needs. For example, the first pixel unit 311, the second pixel unit 312, and the third pixel unit 313 can be red pixel units, green pixel units, and blue pixel units respectively, or the first pixel unit 311, the second pixel unit 312, and the third pixel unit 313 can be blue pixel units, red pixel units, and green pixel units respectively. This application embodiment does not have specific restrictions on the pixel color of each pixel unit.

[0075] Within the display area AA, each pixel unit includes a light-emitting layer. The light-emitting layer is disposed within a pixel opening on the side of the back plate 11 near the first metal layer 21, and is used to emit light of different colors. Specifically, the first pixel unit 311 includes a first light-emitting layer 3111, the second pixel unit 312 includes a second light-emitting layer 3121, and the third pixel unit 313 includes a third light-emitting layer 3131. The first light-emitting layer 3111, the second light-emitting layer 3121, and the third light-emitting layer 3131 are a combination of a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer.

[0076] In addition, the display panel also includes a cathode layer 32, which is located inside the display area AA. The cathode layer 32 is disposed on the side of the light-emitting layer away from the back plate 11. The cathode layer 32 is divided by the metal pattern 213 of the first metal layer 21 to form the cathode pattern 321 located in each pixel opening. In the pixel opening, the cathode pattern 321 covers the surface of the light-emitting layer away from the back plate 11.

[0077] In some alternative implementations, such as Figure 2As shown, the metal pattern 213 has an undercut structure, which includes a groove. The groove forms an opening on the side opposite to the back plate 11. In the second direction F2, the size of the groove opening is smaller than the size of the groove interior. The second direction F2 is the arrangement direction of the back plate 11 and the first metal layer 21. In the groove between adjacent metal patterns 213 of the first metal layer 21, the cathode pattern 213 in the pixel unit extends from the pixel opening into the groove of the undercut structure and directly contacts the sidewall of the metal pattern 213 inside the groove to form an electrical connection. In this embodiment, the cathode pattern 321 of the cathode layer 32 is disposed in each pixel opening. By directly contacting the sidewall of the metal pattern 213 to form an electrical connection, the cathode pattern 321 is disposed inside the display area AA. The first metal layer 21 extending to the first border area B1 achieves an electrical connection with the first signal line 111, effectively reducing the resistance of the first signal line 111 and reducing the voltage drop IR Drop of the first signal line 111.

[0078] In some optional embodiments, the display panel further includes: a first encapsulation layer 41, within the display area AA, the first encapsulation layer 41 being configured to at least cover the side surface of the cathode pattern of the first pixel unit facing away from the back plate, the first encapsulation layer 41 being used to protect the cathode pattern 321 and the first light-emitting layer 3111 in the first pixel unit 311; a second encapsulation layer 42, within the display area AA, the second encapsulation layer 42 being configured to at least cover the side surface of the cathode pattern 321 of the second pixel unit 312 facing away from the back plate 11, the second encapsulation layer 42 being used to protect the cathode pattern 321 and the second light-emitting layer 3121 in the second pixel unit 312; and a third encapsulation layer 43, within the display area AA, the third encapsulation layer 43 being configured to at least cover the side surface of the cathode pattern 321 of the third pixel unit 313 facing away from the back plate 11, the third encapsulation layer 43 being used to protect the cathode pattern 321 and the third light-emitting layer 3131 in the second pixel unit 312.

[0079] To ensure effective overlap between the cathode pattern 321 and the metal pattern 213 of each pixel unit during the formation of the cathode layer 32, a certain margin is required in the manufacturing process for the light-emitting layer, cathode pattern, and corresponding encapsulation layer of each pixel opening. Specifically, within the display area AA, the encapsulation layer (including the first encapsulation layer 41, the second encapsulation layer 42, and the third encapsulation layer 43) within each pixel opening extends from the side surface of the cathode pattern 321 facing away from the backplate along the sidewall of the metal pattern 213 to the side surface of the metal pattern 213 facing away from the backplate. The portion of the encapsulation layer on the side surface of the metal pattern 213 facing away from the backplate 11 is further layered with the cathode layer 32 and the light-emitting layer material between the encapsulation layer and the metal pattern 213. Furthermore, the first encapsulation layer 41, the second encapsulation layer 42, and the third encapsulation layer 43 are disposed in the same layer, and the encapsulation layers of adjacent pixel units are spaced apart from each other on the side surface of the metal pattern 213 facing away from the backplate 11 between the adjacent pixel units.

[0080] In some optional embodiments, to improve the encapsulation effect of the first encapsulation layer 41, the second encapsulation layer 42, and the third encapsulation layer 43 on the pixel units of the display area AA, the first encapsulation layer 41, the second encapsulation layer 42, and the third encapsulation layer 43 extend from the display area AA into the first border area B1. Specifically, Figure 5 This illustration shows a partially enlarged schematic diagram of a display panel according to an embodiment of this application, showing the portion near the display area when the first metal layer and the first signal line are fully overlapped within the first bezel region. Figure 5 As shown, within the first border area B1, the first encapsulation layer 41, the second encapsulation layer 42, and the third encapsulation layer 43 are sequentially stacked on the side of the first metal layer 21 away from the back plate 11. The first encapsulation layer 41 is disposed close to the first metal layer 21, and the third encapsulation layer 43 is disposed on the side of the second encapsulation layer 42 away from the back plate 11.

[0081] In this embodiment, the backplate 11 is further provided with a gate drive on array (GOA) 113. The gate drive on array 113 is disposed on the same layer as the first signal line 111, and is located on the side of the first signal line 111 near the display area AA. The gate drive on array 113 is configured to turn on the pixels of the display panel line by line and write the display signal into the pixel capacitor line by line. The first encapsulation layer 41 and the second encapsulation layer 42 are only used to encapsulate and protect the display area AA. Therefore, the boundaries of the first encapsulation layer 41 and the second encapsulation layer 42 within the first border area B1 are located on the side of the gate drive on array 113 near the display area AA. The orthographic projections of the first encapsulation layer 41 and the second encapsulation layer 42 on the backplate 11 do not overlap with the area where the gate drive on array 113 is located.

[0082] It is readily understood that the first light-emitting layer 3111, the second light-emitting layer 3121, the third light-emitting layer 3131, and the cathode layer 32 containing the cathode pattern 321 of each pixel unit also extend to the first border area B1. Specifically, the first light-emitting layer 3111 and the cathode layer 32 containing the cathode pattern 321 in the first pixel unit 311 are stacked between the first encapsulation layer 41 and the first metal layer 21; the second light-emitting layer 3121 and the cathode layer 32 containing the cathode pattern 321 in the second pixel unit 312 are stacked between the first encapsulation layer 41 and the second encapsulation layer 42; the third light-emitting layer 3131 and the cathode layer 32 containing the cathode pattern 321 in the third pixel unit 313 are stacked between the second encapsulation layer 42 and the third encapsulation layer 43. The first light-emitting layer 3111, the second light-emitting layer 3121, the third light-emitting layer 3131, and the cathode layer 32 where the cathode pattern 321 of each pixel unit is located are flush with the boundary of the first border area B1, and are all located on the side of the boundary between the first encapsulation layer 41 and the second encapsulation layer 42 that is close to the display area AA.

[0083] In some optional embodiments, within the first border area B1, the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42 are staggered. Specifically, the boundary of the first encapsulation layer 41 can be located on the side of the boundary of the second encapsulation layer 42 away from the display area AA, or the boundary of the first encapsulation layer 41 can be located on the side of the boundary of the second encapsulation layer 42 closer to the display area AA. In this embodiment, by staggering the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42, the boundaries of the first encapsulation layer 41 and the second encapsulation layer 42 within the first border area B1 are not flush, thereby avoiding a large step difference between the first encapsulation layer 41 and the second encapsulation layer at the boundary. This prevents other layer structures formed on the side of the first encapsulation layer 41 and the second encapsulation layer 42 away from the backplate 11 from breaking at the boundary of the first encapsulation layer 41 and the second encapsulation layer 42 due to excessive step difference during the manufacturing process.

[0084] Furthermore, in this embodiment of the application, in order to improve the chance of other layer structures on the side of the first encapsulation layer 41 and the second encapsulation layer 42 away from the backplate 11 breaking at the boundary of the first encapsulation layer 41 and the second encapsulation layer 42 during the manufacturing process, the slope of the first encapsulation layer 41 and the second encapsulation layer 42 at the inner boundary of the first border area B1 is set to a small slope value. For example, the slope of the first encapsulation layer 41 and the second encapsulation layer 42 at the inner boundary of the first border area B1 is less than or equal to 30 degrees.

[0085] Optionally, to ensure that the boundaries of the first encapsulation layer 41 and the second encapsulation layer 42 within the first border area B1 do not form an excessively large step difference, the distance between the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42 along the first direction F1 within the first border area B1 is greater than or equal to a first distance threshold. The first distance threshold is greater than or equal to 40 micrometers and less than or equal to 60 micrometers, where the first direction F1 is the direction from the display area AA to the first border area B1. For example, the first distance threshold can be 50 micrometers, meaning that the distance between the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42 along the first direction F1 within the first border area B1 is greater than or equal to 50 micrometers.

[0086] Optionally, in order to ensure that the first encapsulation layer 41 and the second encapsulation layer 42 encapsulate the display area AA well during the manufacturing process, within the first border area B1, the distance between the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42 and the display area AA along the first direction F1 is greater than or equal to 100 micrometers and less than or equal to 200 micrometers.

[0087] In some alternative implementations, Figure 4 This illustration shows a partially enlarged schematic diagram of a display panel according to an embodiment of this application, showing the portion of the panel away from the display area when the first metal layer and the first signal line are fully overlapped within the first bezel region. Figure 4 As shown, within the first border area B1, the display panel further includes a barrier dam 51. The barrier dam 51 is disposed on the side of the first metal layer 21 away from the display area AA. The barrier dam 51 is used to protect the structure of the display area AA and improve the reliability of the display panel. In this embodiment, the third encapsulation layer 43 is used to encapsulate and protect the entire display panel, that is, the third encapsulation layer 43 is used to encapsulate and protect the display area AA and the first border area B1. Therefore, within the first border area B1, the boundary of the third encapsulation layer 43 is disposed away from the display area AA relative to the boundary of the first encapsulation layer 41 and the boundary of the second encapsulation layer 42. Furthermore, in order to ensure that the third encapsulation layer 43 covers the structure within the first border area B1, the boundary of the third encapsulation layer 43 is disposed on the side of the barrier dam 51 away from the display area AA.

[0088] In some optional embodiments, the display panel further includes: a fourth encapsulation layer 44 disposed on the side of the third encapsulation layer 43 facing away from the backplate 11; and an organic encapsulation layer 45 disposed between the fourth encapsulation layer 44 and the third encapsulation layer 43, wherein the fourth encapsulation layer 44 and the organic encapsulation layer 45 cover the display area AA and extend from the display area AA to the first border area B1, thereby achieving overall encapsulation protection for the display panel. Within the first border area B1, the boundary of the fourth encapsulation layer 44 is disposed between the boundary of the barrier dam 51 and the boundary of the third encapsulation layer 43, and the boundary of the organic encapsulation layer 45 is disposed on the side of the barrier dam 51 closer to the display area AA.

[0089] In some optional embodiments, the display panel further includes a planarization layer 52 disposed on the side of the back panel 11 near the first metal layer 21. The planarization layer 52 covers the display area AA and extends into the first bezel area B1. The planarization layer 52 is disposed on the same layer as the barrier dam 51. Within the first bezel area B1, the boundary of the planarization layer 52 is located between the first encapsulation layer 41 and the first signal line 111.

[0090] In some alternative implementations, such as Figure 4As shown, within the first border area B1, the first metal layer 21 includes a first portion 211 and a second portion 212 connected to each other. The first portion 211 is disposed on the side of the planar layer 52 away from the back plate 11. The second portion 212 is disposed opposite the first portion 211 away from the display area AA. The second portion 212 is configured to directly contact the first signal line 111 to form an electrical connection. Specifically, the blocking dam 41 is disposed on the side of the second portion 212 away from the display area AA. The orthographic projection of the second portion 212 on the back plate 11 covers the first signal line 111. The orthographic projection of the blocking dam 41 on the back plate 11 does not overlap with the first signal line 111, thereby showing the complete overlap between the first metal layer 21 and the first signal line 111. In this embodiment, by setting the second part 212 of the first metal layer 21 to completely cover the surface of the first signal line 111, the second part 212 and the first signal line 111 are electrically connected through direct contact. At the same time, the first metal layer 21 covers the display area AA and is electrically connected through direct contact with the cathode pattern 321 in each pixel unit within the pixel opening. Thus, the first signal line 111 and the cathode layer 32 are electrically connected through the first metal layer 21, which greatly reduces the voltage drop of the first signal line 111 and effectively improves the display performance.

[0091] In some alternative implementations, Figure 6 This illustration shows a partially enlarged schematic diagram of a display panel according to an embodiment of this application, showing the portion of the display panel away from the display area when the first metal layer and the first signal line portion overlap within the first bezel region. Figure 6 As shown, since the first metal layer 21 is made of metal, its electrical connection with the first signal line 111 is independent of the overlap area. Therefore, in order to achieve a narrow bezel design for the display panel and reduce the width of the first bezel area B1 along the first direction F1, in this embodiment, the orthographic projection of the second part 212 on the back plate 11 partially overlaps with the first signal line 111, thereby effectively reducing the overlap area between the second part 212 and the first signal line 111. Simultaneously, the orthographic projection of the barrier dam 51 on the back plate 11 at least partially overlaps with the first signal line 111, thus achieving the narrow bezel design for the display panel. Furthermore, by setting the second part 212 to partially overlap with the first signal line 111 in this embodiment, moisture can be effectively prevented from entering the interior of the display panel along the second part 212.

[0092] In some optional embodiments, the display panel further includes a pixel defining layer 53 disposed between the planarization layer 52 and the first metal layer 21, the pixel defining layer 53 covering the display area AA, and within the display area AA, the pixel defining layer 53 is used to separate the light-emitting layers of adjacent pixel units; the pixel defining layer 53 extends from the display area AA to the first border area B1, and the pixel defining layer 53 covers the first border area.

[0093] In some optional embodiments, the pixel defining layer 53 is an inorganic material. During the display panel manufacturing process, the planarization layer 52 is prone to releasing air after absorbing moisture, which can lead to defects such as film cracking, adversely affecting the performance of the display panel. In the embodiments of this application, such as... Figure 3 As shown, the display panel has an opening area within the first bezel area B1. The orthogonal projection of the opening area onto the back panel 11 covers the area where the gate driving circuit 113 is located, and does not overlap with the area where the first signal line 111 is located. Multiple through-holes 61 are provided within the opening area. The orthogonal projection of the multiple through-holes 61 onto the back panel 11 is located inside the area where the gate driving circuit 113 is located. The multiple through-holes 61 are configured to penetrate the pixel defining layer 53 and the first metal layer 21. By providing multiple through-holes 61 within the opening area, the first metal layer 21 and the pixel defining layer 53 form a mesh within the opening area. When the planarization layer 52 releases gas, the gas can be released through the through-holes 61 in the opening area of ​​the first metal layer 21 and the pixel defining layer 53, preventing the gas from adversely affecting the formation of the display panel.

[0094] Optionally, the shape of the through hole 61 includes, but is not limited to, a circle, a regular polygon, etc. For example, the shape of the through hole 61 can be a circle, a square, or a regular hexagon. The plurality of through holes 61 can be randomly distributed within the opening area, with intervals between adjacent through holes 61, and the center distance between any two adjacent through holes 61 can be the same or different. The plurality of through holes 61 can also be arranged in an array within the opening area. For example, the plurality of through holes 61 are arranged in an array along the row and column directions within the opening area, with the through holes 61 in two adjacent columns aligned or at least partially staggered in the row direction. It should be noted that the shape and arrangement of the plurality of through holes 61 in this embodiment can be set according to actual needs, and this application does not impose any limitations on this.

[0095] In some alternative implementations, such as Figure 2 As shown, the display panel also includes an anode layer 33, which is disposed within the display area AA and between the pixel defining layer 53 and the planarization layer 52.

[0096] In some alternative implementations, such as Figure 1 As shown, the non-display area of ​​the display panel also includes a second border area B2 disposed on one side of the display area AA. The first border area B1 is disposed on both sides of the second border area B2. A chip is disposed within the second border area B2, which is typically used for bonding and connecting with the chip. Specifically, Figure 8 This illustration shows a schematic diagram of the structure of a display panel within the second bezel area according to an embodiment of this application, as shown below. Figure 8 As shown, within the second border area B2, the back plate 11 is provided with a second signal line 112. The boundary of the first metal layer 21 is located on the side of the second signal line 112 close to the display area AA, and the boundary of the first metal layer 21 is located on the side of the boundary of the first encapsulation layer 41 away from the display area AA. The orthographic projection of the first metal layer 21 on the back plate 11 does not overlap with the second signal line 112.

[0097] In some optional embodiments, the backplate 11 further includes a virtual pixel unit 114 in the non-display area (including the first border area B1 and the second border area B2). The boundary of the virtual pixel unit 114 in the non-display area is located on the side of the boundary of the light-emitting layer closer to the display area AA. The virtual pixel unit 114 is configured to ensure process accuracy and prevent electrostatic damage, as well as to match circuit performance and improve display effect.

[0098] This application provides a display panel and a display device. The display panel includes a display area and a first bezel area, with the first bezel area disposed on opposite sides of the display area. The display panel includes: a back plate, with a first signal line disposed within the first bezel area; and a first metal layer disposed on one side of the back plate, extending from the display area to the first bezel area and electrically connected to the first signal line within the first bezel area. Within the display area, the first metal layer includes multiple metal patterns, with pixel openings formed between adjacent metal patterns. Pixel units are disposed within the pixel openings, and the cathode patterns of the pixel units are electrically connected to the metal patterns. By providing a first metal layer that extends from the display area to the first bezel area and directly connects to the cathode patterns in the pixel units within the display area, while simultaneously directly connecting to the first signal line within the first bezel area, this application achieves the connection between the cathode and the first signal line through a first metal layer with lower resistance, effectively reducing the voltage drop of the first signal line and improving the display performance of the display panel.

[0099] Based on the same inventive concept, this application provides a display panel, which includes a display area AA and a first border area B1, wherein the first border area B1 is disposed on opposite sides of the display area AA. Figure 7 This illustration shows a partially enlarged schematic diagram of a display panel according to an embodiment of this application, showing the portion of the display panel away from the display area when the anode layer overlaps with the first signal line within the first bezel region. Figure 2 and Figure 7 As shown, the display panel includes: a back plate 11, wherein a first signal line 111 is disposed in the first border area B1; a first metal layer 21, wherein the first metal layer 21 is disposed on one side of the back plate 11 and extends from the display area AA to the first border area B1; within the display area AA, the first metal layer 21 includes a plurality of metal patterns 213, a pixel opening is formed between adjacent metal patterns 213, a pixel unit is disposed within the pixel opening, and the cathode pattern 321 of the pixel unit is electrically connected to the metal pattern 213.

[0100] In this embodiment, the display panel further includes an anode layer 33, which is disposed between the first metal layer 21 and the backplate 11. The anode layer 33 covers the display area AA and extends from the display area AA into the first bezel area B1. The first metal layer 21 is electrically connected to the first signal line 111 through the anode layer 33. Since the resistance of the anode layer 33 is less than the resistance of the cathode layer 32, and the thickness of the anode layer 33 along the second direction F2 is less than the thickness of the first metal layer 21 along the second direction F2, in this embodiment, by directly connecting the anode layer 33 to the first signal line 111, the voltage drop of the first signal line 111 can be reduced, and the overlap area with the first signal line 111 can be reduced. This is beneficial for further reducing the width of the first bezel area B1 along the first direction F1, thus achieving a narrow bezel design for the display panel.

[0101] Specifically, the display panel further includes a planarization layer 52 disposed between the back plate 11 and the first metal layer 21. Within the first bezel area B1, the first metal layer 21 is disposed on the surface of the planarization layer 52 facing away from the back plate 11. The anode layer 33 includes a third part 331 and a fourth part 332 connected to each other. The third part 331 is disposed on the side of the planarization layer 52 facing away from the back plate 11 and is in direct contact with the first metal layer 21 to form an electrical connection. The fourth part 332 is disposed away from the display area AA relative to the third part 331. The fourth part 332 is disposed on the side of the planarization layer 52 away from the display area AA. The orthographic projection of the fourth part 332 on the back plate 11 at least partially overlaps with the first signal line 111, and the fourth part 332 is in direct contact with the first signal line 111 to form an electrical connection.

[0102] In some alternative embodiments, the display panel further includes a blocking dam 51, which is disposed on the side of the first metal layer 21 away from the display area AA. The orthographic projection of the blocking dam 51 on the back panel 11 at least partially overlaps with the first signal line 111, thereby achieving a narrow bezel design for the display panel.

[0103] In one embodiment, within the first border area B1, the orthographic projection of the anode layer 33 onto the region where the first signal line 111 is located does not overlap with the orthographic projection of the barrier dam 51 onto the region where the first signal line 111 is located. In another embodiment, the anode layer 33 at least partially covers the side surface of the barrier dam 51 facing away from the backplate 11.

[0104] Based on the same inventive concept, this application discloses a display device, which includes the display panel described in the embodiments of this application.

[0105] It should be noted that since the display device provided in this application includes the display panel of the technical solution described in the embodiments of this application, the display device provided in this application has all the beneficial effects of the above-mentioned display panel, which will not be elaborated here.

[0106] In some optional embodiments, the display device includes, but is not limited to, any product or component with touch display function such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, virtual reality (VR) device, etc. Those skilled in the art can make appropriate selections according to the actual use of the display device, and this application will not elaborate further.

[0107] Based on the same inventive concept, this application discloses a method for manufacturing a display panel, which is used to manufacture the display panel described in this application embodiment. Figure 9 This illustration shows a schematic diagram of the structure for forming a first metal layer in a display panel fabrication method according to an embodiment of this application, as shown below. Figure 9 As shown, the fabrication method includes: providing a backplate 11; and sequentially forming a planarization layer 52, an anode layer 33, a pixel defining layer 53, and a first metal layer 21 on one side of the backplate 11.

[0108] Figure 10 This illustration shows a schematic diagram of the structure for forming a first pixel unit in a display panel fabrication method according to an embodiment of this application, as shown below. Figure 10 As shown, after the first metal layer 21 is formed, the first metal layer 21 and the pixel defining layer 53 in the area corresponding to the first pixel unit 311 are patterned; then the first light-emitting layer 3111, the cathode pattern 321 of the first pixel unit 311 and the first encapsulation layer 41 are sequentially stacked, and the first light-emitting layer 3111, the cathode pattern 321 of the first pixel unit 311 and the first encapsulation layer 41 are patterned to form the pixel structure in the area corresponding to the first pixel unit 311.

[0109] Figure 11 This illustration shows a schematic diagram of the structure for forming a second pixel unit in a display panel fabrication method according to an embodiment of this application. Figure 11 As shown, after the first pixel unit 311 is formed, the first metal layer 21 and the pixel defining layer 53 in the corresponding area of ​​the second pixel unit 312 are patterned; then, the second light-emitting layer 3121, the cathode pattern 321 of the second pixel unit 312 and the second encapsulation layer 42 are sequentially stacked and patterned to form the pixel structure in the corresponding area of ​​the second pixel unit 312.

[0110] Figure 12 This illustration shows a schematic diagram of the structure for forming a third pixel unit in a display panel fabrication method according to an embodiment of this application. Figure 12As shown, after the second pixel unit 312 is formed, the first metal layer 21 and the pixel defining layer 53 in the area corresponding to the third pixel unit 313 are patterned; then, the third light-emitting layer 3131, the cathode pattern 321 of the third pixel unit 313 and the third encapsulation layer 43 are sequentially stacked, and the third light-emitting layer 3131, the cathode pattern 321 of the third pixel unit 313 and the third encapsulation layer 43 are patterned to form the pixel structure in the area corresponding to the third pixel unit 313.

[0111] It should be noted that since the method for preparing the display panel provided in this application is used to prepare the display panel of the technical solution described in the embodiments of this application, the method for preparing the display panel provided in this application has all the beneficial effects of the above-mentioned display panel, and will not be elaborated here.

[0112] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0113] In the description of this specification, it should be understood that the terms "center", "thickness", "upper", "lower", "front", "rear", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0114] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0115] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0116] The foregoing application provides many different implementations or examples for carrying out different structures of this application. To simplify this application, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0117] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0118] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0119] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0120] The above provides a detailed description of a display panel and display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a first border area, the first border area being disposed on opposite sides of the display area, the display panel including: A backplate, wherein a first signal line is provided within the first frame area; A first metal layer is disposed on one side of the back panel, the first metal layer extends from the display area to the first bezel area, and forms an electrical connection with the first signal line within the first bezel area; Within the display area, the first metal layer includes multiple metal patterns, with pixel openings formed between adjacent metal patterns. Pixel units are disposed within the pixel openings, and the cathode pattern of the pixel unit is electrically connected to the metal patterns.

2. The display panel according to claim 1, characterized in that, The pixel unit includes a first pixel unit, a second pixel unit, and a third pixel unit, and the display panel further includes: A first encapsulation layer, within the display area, is configured to at least cover one surface of the cathode pattern of the first pixel unit facing away from the backplate. A second encapsulation layer, within the display area, is configured to at least cover the side surface of the cathode pattern of the second pixel unit facing away from the backplate. A third encapsulation layer, within the display area, is configured to at least cover the side surface of the cathode pattern of the third pixel unit facing away from the backplate.

3. The display panel according to claim 2, characterized in that, Within the first frame area, the first encapsulation layer and the second encapsulation layer are sequentially stacked on the side of the first metal layer away from the back plate, with the first encapsulation layer disposed close to the first metal layer. Within the first border area, the boundaries of the first encapsulation layer and the second encapsulation layer are staggered.

4. The display panel according to claim 2, characterized in that, Within the first bezel area, the back panel is further provided with a gate driving circuit, which is located on the side of the first signal line near the display area. The boundaries of the first encapsulation layer and the second encapsulation layer are located on the side of the gate driving circuit near the display area.

5. The display panel according to claim 3, characterized in that, Within the first border area, the distance between the boundary of the first encapsulation layer and the boundary of the second encapsulation layer along the first direction is greater than or equal to a first distance threshold, the first distance threshold is greater than or equal to 40 micrometers and less than or equal to 60 micrometers, and the first direction is the direction from the display area to the first border area.

6. The display panel according to claim 3, characterized in that, Within the first border area, the distance between the boundary of the first encapsulation layer and the boundary of the second encapsulation layer and the display area along the first direction is greater than or equal to 100 micrometers and less than or equal to 200 micrometers, respectively. The first direction is the direction from the display area to the first border area.

7. The display panel according to claim 2, characterized in that, Within the first border area, the third encapsulation layer is disposed on the side of the second encapsulation layer opposite to the backplate; The display panel also includes a barrier dam, which is disposed on the side of the first metal layer away from the display area, and the boundary of the third encapsulation layer is disposed on the side of the barrier dam away from the display area.

8. The display panel according to claim 1, characterized in that, The display panel further includes a planarization layer, which is disposed on the side of the back panel near the first metal layer; Within the first frame area, the first metal layer includes a first part and a second part that are connected to each other, wherein the first part is disposed on the side of the flat layer opposite to the back plate. The second part is disposed away from the display area relative to the first part, and the second part is disposed on the side of the flat layer away from the display area.

9. The display panel according to claim 8, characterized in that, The display panel also includes a barrier dam, which is disposed on the side of the second part away from the display area and is disposed on the same layer as the planarization layer; The second part's orthographic projection on the back plate covers the first signal line, and the orthographic projection of the blocking dam on the back plate does not overlap with the first signal line.

10. The display panel according to claim 8, characterized in that, The display panel also includes a barrier dam, which is disposed on the side of the second part away from the display area and is disposed on the same layer as the flat layer; The orthographic projection of the second part on the back plate partially overlaps with the first signal line, and the orthographic projection of the blocking dam on the back plate at least partially overlaps with the first signal line.

11. The display panel according to claim 8, characterized in that, The display panel further includes a pixel defining layer, which is disposed between the planarization layer and the first metal layer; Within the first border area, the display panel includes an opening area, in which a plurality of through holes are provided, the plurality of through holes being configured to penetrate the pixel defining layer and the first metal layer.

12. The display panel according to claim 11, characterized in that, The backplate is further provided with a gate driving circuit in the first frame area, and the gate driving circuit is located on the side of the first signal line near the display area. The orthographic projection of the plurality of vias on the backplate is located inside the region where the gate drive circuit is located.

13. The display panel according to claim 1, characterized in that, The metal pattern is an undercut structure, which includes a groove. The groove forms an opening on the side away from the back plate. In a second direction, the size of the groove opening is smaller than the size of the groove interior. The second direction is the arrangement direction of the back plate and the first metal layer.

14. The display panel according to claim 13, characterized in that, The cathode pattern extends from the pixel opening into the groove of the undercut structure and forms an electrical connection with the sidewall of the metal pattern inside the groove.

15. The display panel according to any one of claims 1-14, characterized in that, The display panel further includes a second border area disposed on one side of the display area, and the first border area is disposed on both sides of the second border area; Within the second frame area, the back panel is provided with a second signal line, and the boundary of the first metal layer is located on the side of the second signal line near the display area.

16. The display panel according to claim 15, characterized in that, The boundary of the first metal layer is located on the side of the boundary of the first encapsulation layer away from the display area.

17. A display panel, characterized in that, The display panel includes a display area and a first border area, the first border area being disposed on opposite sides of the display area, the display panel including: A backplate, wherein a first signal line is provided within the first frame area; A first metal layer is disposed on one side of the back panel, and the first metal layer extends from the display area to the first bezel area; Within the display area, the first metal layer includes multiple metal patterns, with pixel openings formed between adjacent metal patterns. Pixel units are disposed within the pixel openings, and the cathode pattern of the pixel unit is electrically connected to the metal patterns. An anode layer is disposed between the first metal layer and the back plate. Within the first frame area, the first metal layer is electrically connected to the first signal line through the anode layer.

18. The display panel according to claim 17, characterized in that, The display panel further includes a planarization layer disposed between the back panel and the first metal layer; Within the first frame area, the anode layer includes a third part and a fourth part that are interconnected, the third part being disposed on the side of the flat layer opposite to the back plate; The fourth part is disposed away from the display area relative to the third part, and the fourth part is disposed on the side of the flat layer away from the display area. The orthographic projection of the fourth part on the back plate at least partially overlaps with the first signal line.

19. The display panel according to claim 17 or 18, characterized in that, The thickness of the anode layer along the second direction is less than the thickness of the first metal layer along the second direction, where the second direction is the arrangement direction of the back plate and the first metal layer.

20. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-16, or the display device includes a display panel as described in any one of claims 17-19.

Images