Display device

Abstract

The invention relates to a display device. A display device according to one embodiment includes: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a first electrode disposed in each of the sub-pixels on the substrate; a bank disposed on the first electrode at a boundary between adjacent sub-pixels and overlapping a periphery of an upper surface of the first electrode; an organic layer on the first electrode and the bank; a second electrode on the organic layer; a color filter on the second electrode; and an optical member on the color filter, where the bank includes a black-based material, and the optical member includes a destructive interference layer and nanopatterns spaced apart from each other on the destructive interference layer.

Description

Technical Field

[0001] This specification relates to an apparatus, specifically, for example, but not limited to, a display apparatus. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices are being utilized.

[0003] The display device includes multiple pixels and multiple switching elements for driving and controlling the pixels.

[0004] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0005] The embodiments described in this specification are intended to provide a display device with increased flexibility by omitting the polarization unit.

[0006] Embodiments of this specification are also intended to provide a display device having a color filter and a dam comprising a black base material to improve external light reflection.

[0007] Embodiments of this specification also aim to provide a display device in which optical components are disposed on a color filter to improve the reflectivity of external light.

[0008] Embodiments of this specification are also intended to provide a display device in which, because the optical components include nanopatterns, the reflection of external light can be reduced or minimized and the travel angle of external light can be reduced.

[0009] Embodiments of this specification are also intended to provide a display device in which the reflection of external light can be reduced or minimized because the optical components include a destructive interference layer located beneath the nanopattern.

[0010] Embodiments of this specification are also intended to provide a low-reflection display device in which surface reflection of external light is enhanced and driven with low power.

[0011] The purpose of this specification is not limited to the above-described purposes, and other technical purposes can be inferred from the following embodiments.

[0012] According to one embodiment, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a first electrode disposed in each of the sub-pixels on the substrate; a dam disposed on the first electrode and overlapping the periphery of an upper surface of the first electrode; an organic layer disposed on the first electrode and the dam; a second electrode disposed on the organic layer; a color filter disposed on the second electrode; and an optical component disposed on the color filter, wherein the dam comprises a black base material, and the optical component includes an destructive interference layer and nanopatterns spaced apart from each other on the destructive interference layer.

[0013] According to another embodiment, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a light-emitting component disposed in each of the sub-pixels on the substrate; an optical component including an destructive interference layer disposed on the light-emitting component and nanopatterns spaced apart from each other on the destructive interference layer; and an upper planarization layer disposed on the optical component and filling between adjacent nanopatterns, wherein the nanopatterns alter the optical path of external light, and the destructive interference layer destructively interferes with the external light whose optical path has been altered.

[0014] Detailed descriptions of other embodiments are included in the detailed description and accompanying drawings.

[0015] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within the scope of this disclosure and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0016] It should be understood that both the foregoing general description and the following specific description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. In the drawings:

[0018] Figure 1 This is a plan view of a display device according to one embodiment.

[0019] Figure 2 This illustrates the implementation of the present disclosure. Figure 1 A cross-sectional view of the display panel in a bent state.

[0020] Figure 3 It is according to the embodiments of this disclosure along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0021] Figure 4 It is based on the embodiments of this disclosure. Figure 3 A detailed cross-sectional view of the light-emitting component.

[0022] Figure 5 This is a detailed cross-sectional view of the light-emitting component according to a modified embodiment of the present disclosure.

[0023] Figure 6 Based on the embodiments of this disclosure Figure 3 A cross-sectional view of the touch component.

[0024] Figure 7 It is according to the embodiments of this disclosure along Figure 1 A cross-sectional view of line B-B' in the diagram.

[0025] Figure 8 It is according to the embodiments of this disclosure along Figure 1 A cross-sectional view of line C-C' in the diagram.

[0026] Figure 9 It is based on the embodiments of this disclosure. Figure 3 An enlarged cross-sectional view of region Q1 in the image.

[0027] Figure 10 It is based on the embodiments of this disclosure. Figure 9 Enlarged cross-sectional view of region Q2 in the image.

[0028] Figure 11 It is based on the embodiments of this disclosure. Figure 9 Enlarged cross-sectional view of region Q3 in the image.

[0029] Figure 12 This illustrates a graph of reflectivity based on wavelength when no nanopattern is provided, according to an embodiment of the present disclosure.

[0030] Figure 13 This illustrates a graph of reflectivity based on wavelength when a nanopattern is provided, according to an embodiment of the present disclosure.

[0031] Figure 14It is a planar diagram of a nanopattern according to one embodiment.

[0032] Figure 15 This is a cross-sectional view of a display device according to another embodiment.

[0033] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment.

[0034] Figure 17 This is a cross-sectional view of a display device according to yet another embodiment.

[0035] Figure 18 This is a cross-sectional view of a display device according to yet another embodiment.

[0036] Figure 19 This is a cross-sectional view of a display device according to another embodiment.

[0037] Figure 20 This is a perspective view of a display device according to another embodiment.

[0038] Figure 21 It is according to another embodiment along Figure 20 A cross-sectional view of line D-D' in the diagram.

[0039] Explanation of reference numerals in the attached figures

[0040] 1: Display device

[0041] 100, 100_1, 100_2, 100_3, 100_4: Display panel

[0042] D1, D2: Dam Head Detailed Implementation

[0043] In the following description, embodiments will be described with reference to the accompanying drawings.

[0044] In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed when it is determined that such detailed descriptions unnecessarily obscure the inventive concept.

[0045] The advantages and features of this disclosure, as well as its implementation methods, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure sufficiently comprehensive and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0046] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, and convenience, the relative sizes and descriptions of these elements may be enlarged. The described progression of processing steps and / or operations is illustrative; however, the sequence of steps and / or operations is not limited to the sequence set forth herein, and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always denote the same elements. The names of the corresponding elements used in the following explanation are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0047] Any implementation described in this article as an "example" is not necessarily to be interpreted as superior to or better than other implementations.

[0048] The same reference numerals indicate the same components. Additionally, in the accompanying drawings, the thickness, scale, and dimensions of parts may be exaggerated for effective description. For ease of description, the dimensions of the components shown in the drawings differ from their actual dimensions, and therefore are not limited to the dimensions shown in the drawings.

[0049] Furthermore, when referring to any size, relative size, etc., even without a specific description, it should be assumed that the numerical values ​​of the component or feature or corresponding information (e.g., level, range, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "may".

[0050] In this specification, when a first component (or region, layer, section, etc.) is described as "on the second component", "connected" or "attached to" the second component, it means that the first component can be directly connected to / attached to the second component or that a third component can be placed therebetween.

[0051] The term "and / or" includes all one or more combinations that can be defined by the associated configuration.

[0052] Terms such as "first" and "second" can be used to describe various components, but these components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the implementation. Unless the context clearly indicates otherwise, the singular includes the plural.

[0053] Terms such as “below,” “under,” “above,” and “on top” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and describe the orientation relative to the markings in the drawings. For example, one or more other parts may be located between two parts, provided that “immediately adjacent” or “directly” is not used. Spatially relative terms such as “below or below,” “lower,” “above,” “upper,” etc., can be used to readily describe the relationship between one element or component as shown in the accompanying drawings and another element or component. Spatially relative terms should be understood to include terms that encompass different orientations of elements in use or operation other than those shown in the accompanying drawings. For example, in the case where the elements shown in the figures are inverted, an element described as being located “below” or “under” another element may be located “above” another element. Thus, the exemplary term “below” can include both downward and upward directions.

[0054] It should be understood that terms such as "comprising" or "having" are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and do not preclude the possibility of the existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Features of various embodiments of this specification may be partially or wholly linked or combined to enable interoperability and driving of various technologies, and embodiments may be implemented independently of each other or together in an associated relationship.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0056] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0057] The display device described herein will be described below with reference to the accompanying drawings and the following embodiments.

[0058] Figure 1 This is a plan view of a display device according to one embodiment.

[0059] Reference Figure 1According to one embodiment, the display device 1 may include a display panel 100. The display panel 100 may include a display area DA having a plurality of pixels PX and a non-display area NDA located around the display area DA. The flat surface shape of the display area DA may be rectangular. However, the embodiments of this specification are not limited to this, and the flat surface shape of the display area DA may be square, circular, elliptical, or other polygonal shapes. For example, the display area DA may have a rectangular shape including rounded corners, but is not limited to this, and may also have a rectangular shape including corners at a certain angle.

[0060] In the implementation, the first direction DR1 and the second direction DR2 are different directions and intersect each other, for example, perpendicularly intersecting directions in a plan view. Figure 1 In this embodiment, the first direction DR1 may be substantially the same as the extension direction of the short side of the display panel 100, and the second direction DR2 may be the same as or similar to the extension direction of the long side of the display panel 100. However, the directions described in the embodiment should be understood as indicating relative directions, and the embodiment is not limited to the described directions.

[0061] The display area DA may include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA may surround the display area DA. The non-display area NDA may be located on one side and the other side of the display area DA in the first direction DR1, and on one side and the other side of the display area DA in the second direction DR2.

[0062] The display panel 100 may further include a sensor non-display area NDA_S and sensor holes SH surrounded by the sensor non-display area NDA_S. In a plan view, sensor holes SH1 and SH2 may be surrounded by the display area NDA_S. The number of sensor holes SH1 and SH2 may be, for example, [missing information]. Figure 1 The two sensor holes SH1 and SH2 may each include a sensor hole for an infrared sensor and a sensor hole for a camera sensor, but the embodiments described herein are not limited to these. The sensor non-display area NDA_S may be located between the sensor holes SH1 and SH2 and the display area DA. The sensor non-display area NDA_S may completely surround the sensor holes SH1 and SH2. Pixel PX may not be located within the sensor non-display area NDA_S.

[0063] The gating drive unit GIP can be disposed in the non-display area NDA located on one side and the other side of the display area DA along the first direction DR1. The low-potential voltage line VSSL can be disposed outside the gating drive unit GIP on the non-display area NDA. For example, as... Figure 1 As shown, the low-potential voltage line VSSL can extend from the printed circuit board FPCB, through the sub-region SR and the curved region BR, and can be located outside the gating drive unit GIP on the non-display region NDA, and is configured to surround the display region DA.

[0064] The non-display area NDA, located on the other side of the display area DA in the second direction DR2, can extend further from the central portion of the other side of the display area DA in the second direction DR2 toward the other side. The width by which the non-display area NDA extends further from the central portion of the other side in the first direction DR1 toward the other side of the display area DA in the second direction DR2 can be less than the width of the non-display area NDA in the first direction DR1 adjacent to the other side of the display area DA in the second direction DR2.

[0065] Display device 1 may include a main region MR, a sub-region SR, and a curved region BR located between the main region MR and the sub-region SR. A display region DA and a non-display region NDA surrounding the four surfaces of the display region DA may form the main region MR, and a portion extending from the central portion on one side of the display region DA toward the other side in a second direction DR2 may form the curved region BR and the sub-region SR. The curved region BR may be disposed between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 located at the end portion on the other side of the sub-region SR in the second direction DR2. Display device 1 may also include a data driver unit DIC and a printed circuit board FPCB. The data driver unit DIC may be disposed in the first pad region PA1, and the printed circuit board FPCB may be attached to the second pad region PA2. A plurality of pads connected to the data driver unit DIC and the printed circuit board FPCB may be disposed in each of the first pad region PA1 and the second pad region PA2. The data driver unit DIC may be configured, for example, in the form of a driver chip (IC), but is not limited thereto. In one embodiment, a method for setting the data driving unit DIC by directly mounting it on a chip-on-plastic structure on the display panel 100 is described. However, the embodiments described herein are not limited to this, and the data driving unit DIC can also be set by a chip-on-glass or chip-on-film method.

[0066] According to one embodiment, the display panel 100 may also include a crack sensing pattern CSP surrounding a low-potential voltage line VSSL. For example... Figure 1As shown, the crack sensing pattern CSP can be configured to completely surround the display area DA. For example, the crack sensing pattern CSP can be positioned outside the low-potential voltage line VSSL. However, embodiments of this specification are not limited to this, and a portion of the crack sensing pattern CSP may not be positioned within the non-display area NDA on the other side of the display area DA in the second direction DR2.

[0067] Figure 2 This is an example based on Figure 1 A cross-sectional view of the display panel in a bent state.

[0068] Reference Figure 2 According to one embodiment, the curved region BR of the display panel 100 of the display device 1 can be curved in the thickness direction (or the third direction DR3). Therefore, the main region MR and the sub-region SR can overlap each other in the thickness direction. The display panel 100 can be curved such that the lower surface of the main region MR faces the upper surface of the sub-region SR. A printed circuit board FPCB can be attached to the end portion of the sub-region SR.

[0069] Figure 3 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0070] Reference Figure 3 The pixel count (PX) of the display panel 100 (see Figure 1 The pixel PX can include multiple sub-pixels PX1, PX2, and PX3. The first sub-pixel PX1 can be a red sub-pixel, the second sub-pixel PX2 can be a green sub-pixel, and the third sub-pixel PX3 can be a blue sub-pixel, but the embodiments described herein are not limited to this. In some embodiments, the pixel PX further includes a fourth sub-pixel, and the fourth sub-pixel can be a white sub-pixel, but the embodiments described herein are not limited to this. In some embodiments, the pixel can include one red sub-pixel, two green sub-pixels, and one blue sub-pixel, but the embodiments described herein are not limited to this. For example, the multiple sub-pixels PX1, PX2, and PX3 can be arranged in a stripe pattern on the first direction DR1, but are not limited to this, and can also be arranged in a pentile pattern.

[0071] The display panel 100 may include a substrate 101, a first thin-film transistor 120, a second thin-film transistor 130, a light-emitting component 150, an encapsulation component 170, a touch component 180, a color filter insulating layer 114, a black matrix BM, color filters 191, 192, and 193, and a planarization layer OC. The display panel 100 may include at least one panel insulating layer and at least one touch insulating layer located between the substrate 101 and the light-emitting component 150. The at least one panel insulating layer may include at least one of a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a 3-1 insulating layer 105-1, a 3-2 insulating layer 105-2, a fourth insulating layer 106, a fifth insulating layer 108, a sixth insulating layer 109, a first protective layer 111, and a second protective layer 112, and the at least one touch insulating layer may include at least one of a touch buffer layer 181, a first touch insulating layer 183, and a second touch insulating layer 184.

[0072] The substrate 101 may include one or more plastic materials. For example, the substrate 101 may be a multi-substrate comprising various plastic materials such as polyimide. For example, the substrate 101 may include a first substrate portion 101a and a second substrate portion 101b, each comprising a plastic material, and a third substrate portion 101c, comprising an inorganic insulating material, located between the first substrate portion 101a and the second substrate portion 101b, but the embodiments described herein are not limited thereto.

[0073] A buffer layer 102 can be disposed on the substrate 101. The buffer layer 102 can reduce, minimize, or delay the diffusion of moisture or oxygen through the substrate 101. The buffer layer 102 can be made of silicon nitride (SiN). x ) and silicon oxide (SiO) x The layers are alternately stacked at least once to form the structure, but the embodiments described herein are not limited to this.

[0074] The first light-shielding layer 126 may be disposed on the buffer layer 102. The first light-shielding layer 126 may reduce or prevent light from passing through the first semiconductor layer 123 of the first thin-film transistor 120. For example, the first semiconductor layer 123 may be configured to overlap with the first light-shielding layer 126. The first light-shielding layer 126 may be formed by a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, but the embodiments described herein are not limited thereto.

[0075] A first insulating layer 103 may be disposed on the buffer layer 102 and the first light-shielding layer 126. The first insulating layer 103 may reduce or prevent short circuits between components of the first thin-film transistor 120 and the first light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but embodiments described herein are not limited thereto. For example, the first insulating layer 103 may be made of materials such as silicon nitride (SiN). x ) or silicon oxide (SiO) x The inorganic insulating material is formed, but the embodiments described in this specification are not limited to this.

[0076] The first thin-film transistor 120 may be disposed on the first insulating layer 103. The first thin-film transistor 120 may include a first source electrode 121, a first gate electrode 122, a first semiconductor layer 123, and a first drain electrode 124.

[0077] The first semiconductor layer 123 may be disposed on the first insulating layer 103. The first semiconductor layer 123 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO) and silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon, but the embodiments described herein are not limited thereto. The first semiconductor layer 123 may include a channel region, a source region, and a drain region.

[0078] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, power consumption can be lower and reliability can be excellent. Therefore, driving transistors can be formed from polycrystalline semiconductor layers.

[0079] The second insulating layer 104 may be disposed on the first semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103 and may reduce or prevent short circuits between the first semiconductor layer 123 and another component of the first thin-film transistor 120.

[0080] The first gate electrode 122 may be disposed on the second insulating layer 104. The first gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the first semiconductor layer 123. The first gate electrode 122 may be formed by a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but the embodiments described herein are not limited thereto. The first gate electrode 122 may be disposed together with a gate line.

[0081] The third insulating layers 105-1 and 105-2 can be disposed on the first gate electrode 122. The third insulating layers 105-1 and 105-2 can be formed by alternating layers of silicon nitride (SiN). x ) and silicon oxide (SiO) xThe insulating layer 3-1 is formed at least once, but the embodiments described herein are not limited thereto. For example, the insulating layer 105-1 may include silicon oxide (SiO2). x Furthermore, the 3-2 insulating layer 105-2 may include silicon nitride (SiN). x However, the implementation methods described in this specification are not limited thereto.

[0082] The first source electrode 121 and the first drain electrode 124 can be disposed on the third insulating layers 105-1 and 105-2.

[0083] The first source electrode 121 and the first drain electrode 124 can be electrically connected to the first semiconductor layer 123 through contact holes. The first source electrode 121 and the first drain electrode 124 can be formed of a metallic material. For example, the first source electrode 121 and the first drain electrode 124 can be formed by a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), but the embodiments described in this specification are not limited thereto.

[0084] The first source electrode 121 and the first drain electrode 124 can be disposed together with the data line. For example, the data line can be formed of the same material as the first source electrode 121 and the first drain electrode 124, and formed on the same layer as the first source electrode 121 and the first drain electrode 124, but the embodiments described herein are not limited thereto.

[0085] The storage electrode 140 may be configured to be spaced apart from the first thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0086] The first storage electrode 141 may be formed of the same material as the first gate electrode 122 and disposed on the same layer as the first gate electrode 122, but the embodiments described herein are not limited thereto.

[0087] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layers 105-1 and 105-2, and the third insulating layers 105-1 and 105-2 located between the first storage electrode 141 and the second storage electrode 142 may serve as a dielectric to generate a capacitor. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but the embodiments described herein are not limited thereto.

[0088] The second thin-film transistor 130 may be configured to be spaced apart from the first thin-film transistor 120 and the storage electrode 140. The second thin-film transistor 130 may include a second source electrode 131, a second gate electrode 132, a second semiconductor layer 133, and a second drain electrode 134.

[0089] The second light-shielding layer 136 can be disposed on the same layer as the second storage electrode 142.

[0090] Similar to the first light-shielding layer 126, the second light-shielding layer 136 can reduce or prevent light from traveling to the second semiconductor layer 133, thereby extending the lifetime of the second thin-film transistor 130. For example, the second semiconductor layer 133 can be configured to overlap with the second light-shielding layer 136.

[0091] The fourth insulating layer 106 may be disposed on the second light-shielding layer 136. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104, or the third insulating layers 105-1 and 105-2, but the embodiments described herein are not limited thereto.

[0092] The second semiconductor layer 133 may be disposed on the fourth insulating layer 106. The second semiconductor layer 133 may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0093] The second semiconductor layer 133 may include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)) and silicon-based semiconductor materials (e.g., amorphous silicon, polycrystalline silicon, etc.), but the embodiments described herein are not limited thereto.

[0094] The fifth insulating layer 108 may be disposed on the second semiconductor layer 133. The fifth insulating layer 108 may be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2 or the fourth insulating layer 106, but the embodiments described herein are not limited thereto.

[0095] The second gate electrode 132 can be disposed on the fifth insulating layer 108.

[0096] The second gate electrode 132 may be formed of the same material as the first gate electrode 122. For example, the second gate electrode 132 may be formed by a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or compounds thereof, but the embodiments described herein are not limited thereto.

[0097] The sixth insulating layer 109 may be disposed on the second gate electrode 132. The sixth insulating layer 109 may be formed of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layers 105-1 and 105-2, the fourth insulating layer 106 or the fifth insulating layer 108, but the embodiments described herein are not limited thereto.

[0098] The first source electrode 121, the first drain electrode 124, the second source electrode 131, and the second drain electrode 134 can be disposed on the sixth insulating layer 109.

[0099] The second source electrode 131 and the second drain electrode 134 may be formed of the same material as the first source electrode 121 and the first drain electrode 124, and disposed on the same layer as the first source electrode 121 and the first drain electrode 124, but the embodiments described herein are not limited thereto. For example, the second source electrode 131 and the second drain electrode 134 may be formed by a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, but the embodiments described herein are not limited thereto. For example, the second source electrode 131 may be electrically connected to the second storage electrode 142. The second source electrode 131 may pass through the sixth insulating layer 109, the fifth insulating layer 108, and the fourth insulating layer 106, and may be electrically connected to the second storage electrode 142.

[0100] The first thin-film transistor 120 may be a driving transistor, and the second thin-film transistor 130 may be a switching transistor, but the embodiments described herein are not limited thereto.

[0101] The first protective layer 111 can be disposed on the first source electrode 121 and the first drain electrode 124.

[0102] The first protective layer 111 can planarize the upper part of the first thin-film transistor 120 and protect the first thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments in this specification are not limited thereto.

[0103] The second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but the embodiments described herein are not limited thereto.

[0104] In some embodiments, a third protective layer may be provided on the upper surface of the second protective layer 112, but the embodiments described herein are not limited thereto.

[0105] The connecting electrode 145 can be disposed between the first protective layer 111 and the second protective layer 112.

[0106] The connection electrode 145 can electrically connect the first thin-film transistor 120 to the light-emitting component 150. The connection electrode 145 can be formed of the same material as the first source electrode 121 and the first drain electrode 124, but the embodiments described herein are not limited thereto.

[0107] The connecting electrode 145 can be formed by a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments described herein are not limited thereto.

[0108] The light-emitting component 150 may be disposed on the second protective layer 112. The light-emitting component 150 may include a first electrode 151, an organic layer 152, and a second electrode 153. The first electrode 151 may be used as an anode, and the second electrode 153 may be used as a cathode.

[0109] The first electrode 151 may be disposed on the second protective layer 112. The first electrode 151 may be electrically connected to the first thin-film transistor 120 through a contact hole formed in the second protective layer 112. The first electrode 151 may be a reflective electrode that reflects light, but the embodiments described herein are not limited thereto. The first electrode 151 may comprise a metallic material with high reflectivity (e.g., a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy), and may be formed of a single layer or multiple layers, but the embodiments described herein are not limited thereto.

[0110] An organic layer 152 may be disposed on the first electrode 151. The organic layer 152 may include one or more light-emitting structures (or light-emitting elements or components) stacked on the first electrode 151 in the order of hole transport layer and electron transport layer, or in reverse order. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, a p-type charge generation layer, etc., but the embodiments described herein are not limited to these. For example, the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, an n-type charge generation layer, etc., but the embodiments described herein are not limited to these. The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a miniature light-emitting diode, etc., but the embodiments described herein are not limited to these. For example, the organic layer 152 of a display panel 100 according to one embodiment of this specification may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The organic layer 152 may be a white light-emitting layer, but the embodiments described herein are not limited to these. The specific structure of the organic layer 152 according to one embodiment will be described below.

[0111] Figure 4 yes Figure 3 A detailed cross-sectional view of the light-emitting component.

[0112] Reference Figure 4The light-emitting component 150 may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3.

[0113] The thickness of the light-emitting component 150 in each sub-pixel PX1, PX2 or PX3 may be different, but the embodiments described herein are not limited thereto, and the thickness of the light-emitting component 150 in each sub-pixel PX1, PX2 or PX3 may be the same.

[0114] Organic layer 152 may include a first organic layer 152a disposed in the first sub-pixel PX1, a second organic layer 152b disposed in the second sub-pixel PX2, and a third organic layer 152c disposed in the third sub-pixel PX3. The light-emitting layers EML1 of organic layer 152a, EML2 of organic layer 152b, and EML3 of organic layer 152c can be physically separated, but the lower and upper layers of light-emitting layers EML1, EML2, and EML3 can be integrally formed across sub-pixels PX1, PX2, and PX3. The thickness of each light-emitting layer EML1, EML2, or EML3 can be different. For example, the thickness of the first light-emitting layer EML1 can be the largest, the thickness of the second light-emitting layer EML2 can be the second largest, and the thickness of the third light-emitting layer EML3 can be the smallest, but the embodiments described in this specification are not limited thereto.

[0115] A hole injection layer HIL can be disposed on the first electrode 151. The hole injection layer HIL can be located between the first electrode 151 and the light-emitting layers EML1, EML2, and EML3. The hole injection layer HIL can be integrally formed across sub-pixels PX1, PX2, and PX3. For example, the hole injection layer HIL can be formed from a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(biphenyl-4-yl)-9,9-dimethyl-N-(4-(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine, etc., but the embodiments described in this specification are not limited to this.

[0116] The hole transport layer (HTL) can be disposed on the hole injection layer (HIL). The hole transport layer (HTL) can be located between the hole injection layer (HIL) and the light emission layers (EML1, EML2, and EML3). The hole transport layer (HTL) can be integrally formed across sub-pixels (PX1, PX2, and PX3). The hole transport layer (HTL) may be formed from one or more of the group consisting of aryl amine materials (e.g., NPB (N,N-naphthyl-N,N'-phenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), PPD, TTBND, FFD, p-dmDPS, and TAPC), star-shaped aromatic amine materials (e.g., TCTA, PTDATA, TDAPB, TDBA, 4-a, and TCTA), and spiro and step-type materials (e.g., spiro-TPD, spiro-mTTB, spiro-2, NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), s-TAD, and MTDATA (4,4',4”-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine)), but the embodiments described herein are not limited thereto.

[0117] The light-emitting layers EML1, EML2, and EML3 can be disposed on the hole transport layer HTL. The first light-emitting layer EML1 can be disposed in the first sub-pixel PX1, the second light-emitting layer EML2 can be disposed in the second sub-pixel PX2, and the third light-emitting layer EML3 can be disposed in the third sub-pixel PX3.

[0118] The thickness of each light-emitting layer EML1, EML2, or EML3 can be different. For example, the first light-emitting layer EML1 can be formed as follows: to The thickness of the second light-emitting layer EML2 can be formed as follows: to The thickness, and the third light-emitting layer EML3 can be formed as to The thickness is specified, but the embodiments described in this specification are not limited to this.

[0119] Each of the first luminescent layer EML1, the second luminescent layer EML2, and the third luminescent layer EML3 may include a material that can emit light in the visible light range by receiving and combining holes and electrons.

[0120] An electron blocking layer (EBL) can be applied to each emissive layer (EML1, EML2, or EML3). An EBL can also be integrated across sub-pixels PX1, PX2, and PX3.

[0121] An electron transport layer (ETL) can be disposed on an electron blocking layer (EBL). The ETL can be integrally disposed across sub-pixels PX1, PX2, and PX3. The ETL can be formed from anthracene derivatives and lithium quinoline (Liq), or from one or more of oxadiazole, triazole, phenanthrene, benzoxazole, benzothiazole, or benzimidazole (e.g., 2-[4-(9,10-di-2-naphthyl-2-anthrayl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described herein are not limited thereto.

[0122] The second electrode 153 can be disposed on the electron transport layer (ETL).

[0123] Figure 5 This is a detailed cross-sectional view of the light-emitting component based on the modified example.

[0124] Reference Figure 4 and Figure 5 The organic layer 152_1 may include a first organic layer 152a_1 disposed in the first sub-pixel PX1, a second organic layer 152b_1 disposed in the second sub-pixel PX2, and a third organic layer 152c_1 disposed in the third sub-pixel PX3.

[0125] The light-emitting layers of each organic layer 152a_1, 152b_1, or 152c_1 can be physically separated, but the lower and upper layers of the light-emitting layers can be integrally formed across sub-pixels PX1, PX2, and PX3. The thickness of each light-emitting layer can be different. For example, the thickness of the first light-emitting layer of the first sub-pixel can be the largest, the thickness of the second light-emitting layer of the second sub-pixel can be the second largest, and the thickness of the third light-emitting layer of the third sub-pixel can be the smallest, but the embodiments described in this specification are not limited to this. In addition, the light-emitting layers of each organic layer 152a_1, 152b_1, or 152c_1 can be configured as two or more light-emitting layers.

[0126] A hole injection layer HIL can be disposed on the first electrode 151. The hole injection layer HIL can be located between the first electrode 151 and the light-emitting layers EML1a, EML2a, and EML3a. The hole injection layer HIL can be integrally formed across sub-pixels PX1, PX2, and PX3. For example, the hole injection layer HIL can be formed from a hole injection material selected from MTDATA, CuPc, TCTA, NPB (NPD), HATCN, TDAPB, PEDOT / PSS, F4TCNQ, N-(biphenyl-4-yl)-9,9-dimethyl-N-(4-(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine, etc., but the embodiments described in this specification are not limited to this.

[0127] The first hole transport layer HTL1 can be disposed on the hole injection layer HIL. The first hole transport layer HTL1 can be located between the hole injection layer HIL and the light emission layers EML1a, EML2a and EML3a. The first hole transport layer HTL1 can be integrally formed across sub-pixels PX1, PX2 and PX3. The first hole transport layer HTL1 may be formed from one or more of the group consisting of aryl amine materials (e.g., NPB (N,N-naphthyl-N,N'-phenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N,N'-bis-(phenyl)-benzidine), PPD, TTBND, FFD, p-dmDPS, and TAPC), star-shaped aryl amine materials (e.g., TCTA, PTDATA, TDAPB, TDBA, 4-a, and TCTA), and spiro and step-type materials (e.g., spiro-TPD, spiro-mTTB, spiro-2, NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), s-TAD, and MTDATA (4,4',4”-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine)), but the embodiments described herein are not limited thereto.

[0128] Emitting layers EML1a, EML2a, and EML3a can be disposed on the first hole transport layer HTL1. Emitting layer EML1a (1-1) can be disposed in the first sub-pixel PX1, emitting layer EML2a (2-1) can be disposed in the second sub-pixel PX2, and emitting layer EML3a (3-1) can be disposed in the third sub-pixel PX3. Each of the emitting layers EML1a, EML2a, and EML3a can be coupled with… Figure 4 Each of the light-emitting layers EML1, EML2 and EML3 is the same or similar.

[0129] The thickness of each light-emitting layer EML1a, EML2a, or EML3a can be different. For example, the thickness of the 1-1 light-emitting layer EML1a can be formed as follows: to The thickness of the 2-1 light-emitting layer EML2a can be formed as to The thickness, and the 3-1 light-emitting layer EML3a can be formed as to The thickness is specified, but the embodiments described in this specification are not limited to this.

[0130] The hole blocking layer (HBL) can be set on each emissive layer EML1a, EML2a, or EML3a. The hole blocking layer (HBL) can be set uniformly across sub-pixels PX1, PX2, and PX3.

[0131] The first hole transport layer HTL1 can be disposed on the hole blocking layer HBL. The first electron transport layer ETL1 can be integrally formed across sub-pixels PX1, PX2, and PX3. The first electron transport layer ETL1 can be formed from anthracene derivatives and lithium quinoline (Liq), or from one or more of oxadiazole, triazole, phenanthroline, benzoxazole, benzothiazole, or benzimidazole (e.g., 2-[4-(9,10-di-2-naphthyl-2-anthrayl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described in this specification are not limited thereto.

[0132] A common charge layer CGL may be disposed on the first electron transport layer ETL1. The common charge layer CGL may be disposed between the first electron transport layer ETL1 and the second hole transport layer HTL2. The common charge layer CGL may include a conductive material, but embodiments of this disclosure are not limited thereto.

[0133] The second hole transport layer HTL2 can be disposed on the common charge layer CGL. The second hole transport layer HTL2 can be disposed between the hole blocking layer HBL and the light-emitting layers EML1b, EML2b, and EBL3b. The second hole transport layer HTL2 can be integrally formed across sub-pixels PX1, PX2, and PX3. The material of the second hole transport layer HTL2 can be the same as or similar to the material of the first hole transport layer HTL1, but the embodiments described in this specification are not limited thereto.

[0134] Emitting layers EML1b, EML2b, and EML3b can be disposed on the second hole transport layer HTL2. Emitting layer 1-2 EML1b can be disposed in the first sub-pixel PX1, emitting layer 2-2 EML2b can be disposed in the second sub-pixel PX2, and emitting layer 3-2 EML3b can be disposed in the third sub-pixel PX3. Each of emitting layers EML1b, EML2b, and EML3b can be the same as or similar to each of emitting layers EML1a, EML2a, and EML3a.

[0135] The thickness of each emissive layer EML1b, EML2b, or EML3b can be different. For example, 1-2 emissive layers EML1b can be formed as follows: to With a thickness of 2-2, the light-emitting layer EML2b can be formed as to The thickness, and the 3-2 light-emitting layer EML3b can be formed as to The thickness is specified, but the embodiments described in this specification are not limited to this.

[0136] An electron blocking layer (EBL) can be applied to each emissive layer (EML1b, EML2b, or EML3b). The EBL can also be integrated across sub-pixels PX1, PX2, and PX3.

[0137] The second electron transport layer ETL2 can be disposed on the electron blocking layer EBL. The second electron transport layer ETL2 can be integrally formed across sub-pixels PX1, PX2, and PX3. The second electron transport layer ETL2 can be formed from anthracene derivatives and lithium quinoline (Liq), or from one or more of oxadiazole, triazole, phenanthroline, benzoxazole, benzothiazole, or benzimidazole (e.g., 2-[4-(9,10-di-2-naphthyl-2-anthrayl)phenyl]-1-phenyl-1H-benzimidazole), but the embodiments described in this specification are not limited thereto.

[0138] The second electrode 153 can be disposed on the second electron transport layer ETL2.

[0139] Return to reference Figure 3 The second electrode 153 may be disposed on the organic layer 152. The second electrode 153 may be a transparent electrode that transmits light, but the embodiments described herein are not limited thereto. For example, the second electrode 153 may comprise a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or a metal that transmits visible light, but the embodiments described herein are not limited thereto.

[0140] The embankment 154 can be configured to expose the first electrode 151. The embankment 154 can define the openings (or light-emitting regions EA1, EA2, and EA3) of sub-pixels PX1, PX2, and PX3, and can be configured to cover the edge portion (or periphery) of the first electrode 151. That is, the first sub-pixel PX1 can include a first light-emitting region EA1 and a first non-light-emitting region NEA1 surrounding the first light-emitting region EA1, the second sub-pixel PX2 can include a second light-emitting region EA2 and a second non-light-emitting region NEA2 surrounding the second light-emitting region EA2, and the third sub-pixel PX3 can include a third light-emitting region EA3 and a third non-light-emitting region NEA3 surrounding the third light-emitting region EA3. That is, each non-light-emitting region NEA1, NEA2, or NEA3 can correspond to the boundary between adjacent sub-pixels PX1, PX2, and PX3.

[0141] The dam portion 154 may include a black base material. For example, the dam portion 154 may be formed of a material containing black pigment or an organic material (such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, etc.), but the embodiments described herein are not limited thereto. When the dam portion 154 is formed of a material containing black pigment or black dye, the dam portion 154 may be a black dam portion. When the dam portion 154 is formed of a material containing black pigment or black dye, it may block external light or light reflected from the outside, thereby further increasing the brightness of the display device.

[0142] The barrier RAS can also be installed on the embankment 154. For example... Figure 3 As shown, the barrier RAS can be disposed at all boundaries NEA1, NEA2, and NEA3 between sub-pixels PX1, PX2, and PX3, but the embodiments described herein are not limited to this. The barrier RAS can be disposed directly on the upper surface of the embankment 154, but the embodiments described herein are not limited to this. The barrier RAS can be used to separate the organic layer 152 from the boundaries of adjacent sub-pixels PX1, PX2, and PX3. In some embodiments, the barrier can be omitted or simply provided, and grooves can be formed in the embankment 154. The grooves can cause the embankment 154 to be recessed in the thickness direction.

[0143] Spacer 155 may also be disposed on the embankment 154. Spacer 155 may be formed of the same material as the embankment 154, but embodiments of this specification are not limited thereto. For example, spacer 155 may be a transparent embankment, but is not limited thereto, and spacer 155 may be formed of the same material as the embankment 154. For example, spacer 155 may be disposed on at least one boundary of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3, but embodiments of this specification are not limited thereto. Embankment 154 and spacer 155 may be formed of the same material and simultaneously formed through a halftone mask, but embodiments of this specification are not limited thereto.

[0144] The organic layer 152 can be disposed on the first electrode 151, the embankment 154, and the spacer 155. The second electrode 153 can be disposed on the organic layer 152.

[0145] Encapsulation component 170 may be disposed on the second electrode 153. Encapsulation component 170 may include one or more insulating layers. For example, encapsulation component 170 may include a first encapsulation layer 171, a second encapsulation layer 172 disposed on the first encapsulation layer 171, and a third encapsulation layer 173 disposed on the second encapsulation layer 172. Encapsulation component 170 may include one or more inorganic insulating material layers and one or more organic material layers. For example, the first encapsulation layer 171 and the third encapsulation layer 173 may include inorganic insulating materials, and the second encapsulation layer 172 may include organic materials, but the embodiments described herein are not limited thereto.

[0146] The touch component 180 may be disposed on the encapsulation component 170. The touch component 180 may include a touch buffer layer 181, a first touch conductive layer, a first touch insulating layer 183, a second touch insulating layer 184, and a second touch conductive layer. In some embodiments, one or more touch organic layers may also be disposed on the second touch conductive layer, but the embodiments described herein are not limited thereto.

[0147] Figure 6 It is based on Figure 3 A cross-sectional view of the touch component.

[0148] Reference Figure 3 and Figure 6 The touch buffer layer 181 may be disposed on the encapsulation component 170. For example, the touch buffer layer 181 may be disposed on the third encapsulation layer 173. The touch buffer layer 181 may be formed of the same material as the buffer layer 102, but the embodiments described herein are not limited thereto.

[0149] A first touch conductive layer may be disposed on the touch buffer layer 181. The first touch conductive layer may include a bridging electrode 182. The bridging electrode 182 and sensor electrode 185, which will be described below, may be disposed at each of the boundaries between adjacent sub-pixels PX1, PX2, and PX3. For example, the bridging electrode 182 and sensor electrode 185 may be disposed in non-light-emitting regions NEA1, NEA2, and NEA3. The bridging electrode 182 and sensor electrode 185 may overlap with the black matrix BM, which will be described below, in the thickness direction. The black matrix BM may cover the bridging electrode 182 and sensor electrode 185. Therefore, the visibility of the bridging electrode 182 and sensor electrode 185 from the outside can be reduced or prevented.

[0150] A first touch insulating layer 183 and a second touch insulating layer 184 disposed on the first touch insulating layer 183 can be disposed on the first touch conductive layer. The first touch insulating layer 183 and the second touch insulating layer 184 disposed on the first touch insulating layer 183 can reduce or prevent short circuits between the first touch conductive layer and the second touch conductive layer. The first touch insulating layer 183 can be made of silicon oxide (SiO2). x ), silicon nitride (SiN) x The second touch insulating layer 184 may be formed in multiple layers, but the embodiments described herein are not limited thereto. The second touch insulating layer 184 may include an organic insulating material, but the embodiments described herein are not limited thereto, and the second touch insulating layer 184 may include the same material as the first touch insulating layer 183.

[0151] The second touch conductive layer may be disposed on the second touch insulating layer 184. The second touch conductive layer may include a first sensor electrode 185a and a second sensor electrode 185b. The sensor electrode 185a may be disposed in a first direction DR1 (see...). Figure 1 The first sensor electrode 185a extends on the first direction DR1 and in the second direction DR2 (see [reference]). Figure 1 The second sensor electrode 185b extends from the top.

[0152] The bridging electrode 182 can be electrically connected to the first sensor electrode 185a through contact holes formed in the first touch insulating layer 183 and the second touch insulating layer 184. For example, the first sensor electrode 185a and the bridging electrode 182 can be connected in a first direction DR1 (see...). Figure 1 Extending upwards.

[0153] The sensor electrode 185 and the bridging electrode 182 may comprise metallic materials. For example, the sensor electrode 185 and the bridging electrode 182 may be formed of titanium (Ti), nickel (Ni), aluminum (Al), or alloys thereof, and may be formed of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments described herein are not limited thereto.

[0154] Return to reference Figure 3 The color filter insulating layer 114 can be disposed on the second touch conductive layer. The color filter insulating layer 114 can be made of an inorganic insulating material (e.g., silicon nitride (SiN)). x ) or silicon oxide (SiO) x However, the implementation methods described in this specification are not limited to this.

[0155] A black matrix BM can be disposed on the color filter insulating layer 114. The black matrix BM can include a black base material. For example, the black matrix BM can include a light-blocking material or a light-absorbing material. For example, the black matrix BM can be formed from a material including black pigments, black dyes, etc. The black matrix BM can cover the bridging electrode 182 and the sensor electrode 185. Therefore, the visibility of the bridging electrode 182 and the sensor electrode 185 from the outside can be reduced or prevented. For example, the width of the black matrix BM can be smaller than the width of the embankment 154.

[0156] For example, the distance between the end of the black matrix BM and the boundary between the luminous regions EA1, EA2, and EA3 and the non-luminous regions NEA1, NEA2, and NEA3 can be longer than the distance between the end of the embankment 154 and the boundary between the luminous regions EA1, EA2, and EA3 and the non-luminous regions NEA1, NEA2, and NEA3. The end of the embankment 154 can be aligned with the boundary between the luminous regions EA1, EA2, and EA3 and the non-luminous regions NEA1, NEA2, and NEA3, but the embodiments described herein are not limited to this. In the case of the display panel 100 according to one embodiment, since the embankment 154 may include a black base material and the spacing between the ends of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA1, NEA2, and NEA3 can be longer than the spacing between the ends of the embankment 154 and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA1, NEA2, and NEA3, light emitted from the light-emitting areas EA1, EA2, and EA3 can be emitted upward at an angle as large as the spacing between the ends of the black matrix BM and the boundaries between the light-emitting areas EA1, EA2, and EA3 and the non-light-emitting areas NEA1, NEA2, and NEA3. Therefore, brightness reduction can be minimized depending on the viewing angle. However, when the distance between the ends of the black matrix BM and the boundaries between the light-emitting regions EA1, EA2, and EA3 and the non-light-emitting regions NEA1, NEA2, and NEA3 can be longer than the distance between the ends of the dam 154 and the boundaries between the light-emitting regions EA1, EA2, and EA3 and the non-light-emitting regions NEA1, NEA2, and NEA3, and the dam 154 is formed only of transparent material, light incident from the outside may be reflected by the dam 154, resulting in a visible ring-shaped light spot. However, in the case of the display panel 100 according to one embodiment, light incident from the outside can be absorbed or blocked by the dam 154, which includes a black base material, thereby reducing or preventing the occurrence of the ring-shaped light spot.

[0157] Color filters 191, 192, and 193 can be disposed on the black matrix BM. Color filters 191, 192, and 193 can be disposed on the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3, respectively, and can block specific colors of light emitted from the light-emitting area EA1 of sub-pixel PX1, the light-emitting area EA2 of sub-pixel PX2, and the light-emitting area EA3 of sub-pixel PX3. The first color filter 191 can be configured to block light of colors other than red (R) light. In this case, the first color filter 191 can be configured as a red color filter. The second color filter 192 can be configured to block light of colors other than green (G) light. In this case, the second color filter 192 can be configured as a green color filter. The third color filter 193 disposed in the third sub-pixel PX3 can be configured to block light of colors other than blue (B) light. In this case, the third color filter 193 can be configured as a blue color filter. However, the embodiments described in this specification are not limited to these.

[0158] For example, each color filter 191, 192, or 193 may be in direct contact with the side and top surfaces of the black matrix BM. For example, each color filter 191, 192, or 193 may be spaced apart from the boundaries of adjacent sub-pixels PX1, PX2, and PX3, but the embodiments described herein are not limited thereto, and color filters 191, 192, and 193 may overlap each other in the thickness direction.

[0159] A planarization layer OC can be disposed on color filters 191, 192, and 193. The planarization layer OC can be used to flatten the steps formed by color filters 191, 192, and 193. For example, the planarization layer OC may include an organic insulating material.

[0160] The optical component LSP can be disposed on the planarization layer OC. The optical component LSP can be used to improve the reflectivity of external light incident from the top of the display panel 100. The optical component LSP will be described in detail below.

[0161] The upper planarization layer OCR can be disposed on the optical component LSP. For example, the upper planarization layer OCR may include an organic insulating material.

[0162] The cover layer CG can be disposed on the upper planarization layer OCR. The cover layer CG can be formed of glass materials including glass, quartz, etc., but the embodiments described herein are not limited to this, and the cover layer CG can also be formed of plastic materials. The cover layer CG can be disposed above the display panel 100 to protect the components disposed below the cover layer CG from external influences. The cover layer CG can be a cover layer formed by chemical reinforcement, but the embodiments described herein are not limited to this. The cover layer CG can be a cover window, a window cover, or a cover component, but the embodiments described herein are not limited to this.

[0163] An anti-reflective layer that can reduce the reflectivity of external light can be added to the cover CG, but the implementation method described in this specification is not limited to this.

[0164] Figure 7 It is along Figure 1 A cross-sectional view of line B-B' in the diagram.

[0165] Reference Figure 7 At least one of the inorganic layers 102, 103, 104, 105-1, 105-2, 106, 108, and 109 of the panel may not extend to the end of the substrate 101. That is, at least one of the inorganic layers 102, 103, 104, 105-1, 105-2, 106, 108, and 109 of the panel may expose the end portion of the substrate 101, but the embodiments described in this specification are not limited thereto.

[0166] According to one embodiment, the display panel 100 may further include a crack sensing pattern CSP, a low-potential voltage line VSSL, and a gating drive unit GIP. For example... Figure 1 As shown, the low-potential voltage line VSSL can be located between the crack sensing pattern CSP and the display area DA, and the gating drive unit GIP can be located between the low-potential voltage line VSSL and the display area DA.

[0167] For example, such as Figure 7 As shown, the gate drive unit GIP can be connected to the first gate electrode 122 (see...). Figure 3 The conductive layer located on the same layer as the second light-shielding layer 136 (see...) Figure 3 The conductive layer located on the same layer as the first source electrode 121 or the conductive layer located on the same layer as the first source electrode 121 is formed, but the embodiments described in this specification are not limited to this.

[0168] For example, a crack sensing pattern CSP can be disposed between the first dam D1 and the second dam D2. The crack sensing pattern CSP can be formed by the first gate electrode 122 (see...). Figure 3 The conductive layer located on the same layer or the second light-shielding layer 136 (see...) Figure 3 A conductive layer may be formed on the same layer as the first source electrode 121, but the embodiments described herein are not limited thereto. For example, the crack sensing pattern CSP may include a conductive layer on the same layer as the first source electrode 121, but the embodiments described herein are not limited thereto.

[0169] A low-potential voltage line VSSL can be disposed between the crack sensing pattern CSP and the gating drive unit GIP. The low-potential voltage line VSSL can be formed from a conductive layer located on the same layer as the first source electrode 121, but the embodiments described in this specification are not limited thereto.

[0170] The first protective layer 111 may cover the gated drive unit GIP, partially cover one end portion of the low-potential voltage line VSSL, and expose the other end portion of the low-potential voltage line VSSL. In this specification, one end portion may refer to the area of ​​a particular component located in the direction from the non-display area NDA toward the display area DA, and the other end portion may refer to the area of ​​a particular component located in the direction from the display area DA toward the non-display area NDA.

[0171] A first connecting electrode CNE1, located on the same layer as connecting electrode 145, may be disposed on the first protective layer 111. The first connecting electrode CNE1 may be directly connected to the area of ​​the low-potential voltage line VSSL that exposes the first protective layer 111. The first connecting electrode CNE1 may cover the other end portion of the low-potential voltage line VSSL, but the embodiments described in this specification are not limited thereto.

[0172] The second protective layer 112 may be disposed on the first connecting electrode CNE1. The second protective layer 112 may directly contact and cover one end portion of the first connecting electrode CNE1, and expose the other end portion of the first connecting electrode CNE1. The second protective layer 112 may form a first layer of the first dam D1 and a first layer of the second dam D2. The second dam D2 may, for example, overlap with and cover the other end portion of the low-potential voltage line VSSL. The second dam D2 may directly contact the first connecting electrode CNE1 and cover the other end portion of the first connecting electrode CNE1. The second protective layer 112 forming the first layer of the first dam D1 may directly contact the exposed side surface of at least one of the inorganic layers 102, 103, 104, 105, 106, 107, and 109 of the panel, and may directly contact the upper surface of the substrate 101, but embodiments described herein are not limited thereto. The second protective layer 112 may overlap with the gated drive unit GIP. In this specification, the dam section is, for example, set as two dam sections, but the dam section can be set as three or more dam sections or one dam section.

[0173] With the first electrode 151 (see Figure 3 A low-potential connection electrode 151' located on the same layer can be disposed on the first connection electrode CNE1 exposed through the second protective layer 112. The low-potential connection electrode 151' can be electrically connected to the first connection electrode CNE1 exposed through the second protective layer 112. The low-potential connection electrode 151' can be electrically connected to the electrode above it. Figure 3 The second electrode 153 described in [the text] (see [the text]). Figure 3 ).

[0174] A dam portion 154 may be disposed on the low-potential connection electrode 151' and the second protective layer 112. The dam portion 154 may overlap with the gate drive unit GIP, overlap with the low-potential connection electrode 151', and cover the other end portion of the low-potential connection electrode 151'. The dam portion 154 may completely cover the low-potential connection electrode 151', but embodiments described herein are not limited thereto. The dam portion 154 may expose the central portion and the other end portion of the first connection electrode CNE1, but embodiments described herein are not limited thereto. The dam portion 154 may form a second layer of the first dam portion D1 and a second layer of the second dam portion D2. In each dam portion D1 or D2, the dam portion 154 may overlap with and completely cover the second protective layer 112 forming the first layer, but embodiments described herein are not limited thereto. In the second dam portion D2, the dam portion 154 may contact the side surface of the second protective layer 112 and the upper surface of the substrate 101, but embodiments described herein are not limited thereto.

[0175] Spacer 155 may be disposed on dam 154. Spacer 155 may overlap with gate drive unit GIP. Spacer 155 may form a third layer of dam sections D1 and D2. Spacer 155 forming the third layer of each dam section D1 or D2 may overlap with and completely cover dam section 154 forming the second layer, but the embodiments described herein are not limited thereto. In the second dam section D2, spacer 155 may contact the side surface of dam section 154 and the upper surface of substrate 101, but the embodiments described herein are not limited thereto.

[0176] Encapsulation component 170 may be disposed on spacer 155. First encapsulation layer 171 may extend to the gate drive unit GIP, low-potential voltage line VSSL, first dam D1 and second dam D2, and cover the outer surface of second dam D2. Second encapsulation layer 172 may terminate at first dam D1. Second encapsulation layer 172 may overlap with gate drive unit GIP and low-potential voltage line VSSL. Third encapsulation layer 173 may extend to gate drive unit GIP, low-potential voltage line VSSL, first dam D1 and second dam D2, and directly contact the first encapsulation layer 171 on second dam D2, crack sensing pattern CSP, and first dam D1.

[0177] The touch buffer layer 181 and the first touch insulating layer 183 may extend to the gating drive unit GIP, the low-potential voltage line VSSL, the first dam D1 and the second dam D2, and cover the outer surface of the second dam D2. The second touch insulating layer 184 may extend to the gating drive unit GIP, the low-potential voltage line VSSL, the first dam D1 and the crack sensing pattern CSP, and terminate at the second dam D2, but the embodiments described herein are not limited thereto.

[0178] The color filter insulating layer 114 may extend to the gate drive unit GIP, the low potential voltage line VSSL, the first dam D1 and the second dam D2, and directly contact the outer surface of the second touch insulating layer 184, but the embodiments described herein are not limited thereto.

[0179] Figure 8 It is along Figure 1 A cross-sectional view of line C-C' in the diagram.

[0180] Reference Figure 3 , Figure 7 and Figure 8 The bending region BR can be set between the sub-region SR and the crack sensing pattern CSP. In the bending region BR, the inorganic layers 102, 103, 104, 105, 106, 107 and 109 of the panel can be removed to expose the upper surface of the substrate 101.

[0181] In the first pad area PA1, a connection can be made with the first source electrode 121 (see...). Figure 3 The pad electrode PAD is disposed on the same layer, and can be disposed on the crack sensing pattern CSP with the first source electrode 121 (see [reference]). Figure 3 The third connecting electrode CNE3 is set on the same layer.

[0182] The first protective layer 111 can be disposed on the pad electrode PAD and the third connection electrode CNE3. The first protective layer 111 can be disposed in the bending region BR, and the first protective layer 111 can be in direct contact with the upper surface of the substrate 101 and located in the bending region BR. The first protective layer 111 can be in direct contact with the side surfaces of the inorganic layers 102, 103, 104, 105, 106, 107 and 109 of the panel.

[0183] The second connecting electrode CNE2 can be disposed on the first protective layer 111, and the second connecting electrode CNE2 can be disposed on the same layer as the connecting electrode 145 (see [reference]). Figure 3 The second connecting electrode CNE2 can electrically connect the pad electrode PAD to the third connecting electrode CNE3. The second connecting electrode CNE2 can be disposed on the bending region BR, and can also be disposed on the first pad region PA1 and the crack sensing pattern CSP.

[0184] A data drive unit (DIC) can be disposed on a pad electrode (PAD). The DIC may include a bump (BUMP). An anisotropic conductive film (ACF) can be disposed between the pad electrode (PAD) and the bump (BUMP), and the ACF can electrically connect the pad electrode (PAD) to the bump (BUMP). The ACF may include a resin (SR) and multiple conductive balls (CBs) dispersed in the resin (SR). The pad electrode (PAD) and the bump (BUMP) can be electrically connected through the conductive balls (CBs).

[0185] The second protective layer 112 can be disposed on the second connection electrode CNE2. The second protective layer 112 can expose the pad electrode PAD.

[0186] The first encapsulation layer 171 and the third encapsulation layer 173 of the encapsulation component 170 may extend up to the bending region BR. For example, the first encapsulation layer 171 and the third encapsulation layer 173 may extend up to the crack sensing pattern CSP, but the embodiments described herein are not limited thereto, and the first encapsulation layer 171 and the third encapsulation layer 173 may also overlap with the crack sensing pattern CSP. The first encapsulation layer 171 and the third encapsulation layer 173 may not be provided in the bending region BR.

[0187] The touch buffer layer 181 and the first touch insulating layer 183 may extend up to the bending region BR. For example, the touch buffer layer 181 and the first touch insulating layer 183 may extend up to the crack sensing pattern CSP, but the embodiments described herein are not limited thereto, and the touch buffer layer 181 and the first touch insulating layer 183 may also overlap with the crack sensing pattern CSP. The touch buffer layer 181 and the first touch insulating layer 183 may not be provided in the bending region BR.

[0188] The second touch insulating layer 184 may overlap with the first dam D1 and the second dam D2. The second touch insulating layer 184 may not be disposed outside the second dam D2, but the embodiments described herein are not limited thereto.

[0189] Touch connection cable 185' can be electrically connected to the second connection electrode CNE2. Touch connection cable 185' can be used to provide signals applied from the pad electrode PAD and the second connection electrode CNE2 to the surface above. Figure 3 The first sensor electrode 185a or the second sensor electrode 185b described herein. The touch connection line 185' can connect to the second touch conductive layer ( Figure 3 The first sensor electrode 185a) is located on the same layer, but the embodiments described in this specification are not limited thereto, and the touch connection line 185' can be connected to the first touch conductive layer ( Figure 3The bridging electrode 182 is located in the same layer or is formed by two first touch conductive layers and a second touch conductive layer, but the embodiments described herein are not limited thereto.

[0190] The color filter insulation layer 114 can be disposed on the touch connection line 185', and the color filter insulation layer 114 may not be disposed in the bending area BR.

[0191] Figure 9 yes Figure 3 An enlarged cross-sectional view of region Q1 in the image.

[0192] exist Figure 9 In the example, only the first sub-pixel PX1 is shown. See reference... Figure 3 and Figure 9 The optical component LSP may include a destructive interference layer DL and nanopatterns NP located on the destructive interference layer DL. The nanopatterns NP may be configured as multiple nanopatterns. The multiple nanopatterns NP may be spaced apart from each other. The multiple nanopatterns NP may be disposed in both a first emitting region EA1 and a first non-emitting region NEA1. However, embodiments of this specification are not limited thereto, and the nanopatterns NP may be disposed only in the first emitting region EA1, and may not be disposed in the first non-emitting region NEA1. An upper planarization layer OCR may be disposed on the optical component LSP. The upper planarization layer OCR may be in direct contact with each nanopattern NP. The upper planarization layer OCR may be in direct contact with the upper surface and side surfaces of the nanopattern NP, and directly in contact with the upper surface of the destructive interference layer DL exposed through the nanopattern NP.

[0193] The destructive interference layer DL may include multiple destructive interference layers DL1 and DL2. For example, the destructive interference layer DL may include a first destructive interference layer DL1 located on the planarization layer OC and a second destructive interference layer DL2 located on the first destructive interference layer DL1. For example, the refractive index of the first destructive interference layer DL1 may be less than the refractive index of the second destructive interference layer DL2. That is, the refractive index of the second destructive interference layer DL2 may be greater than the refractive index of the first destructive interference layer DL1. For example, the first destructive interference layer DL1 may include silicon oxide, and the second destructive interference layer DL2 may include titanium oxide, but the embodiments described herein are not limited thereto. For example, the refractive index of the first destructive interference layer DL1 may be in the range of about 1.4 to about 1.8, and the refractive index of the second destructive interference layer DL2 may be in the range of about 2.4 to about 2.8, but the embodiments described herein are not limited thereto. For example, the first destructive interference layer DL1 and the second destructive interference layer DL2 may be provided as multiple destructive interference layers, and disposed alternately and repeatedly upwards. Figure 9 An example is illustrated where there are two destructive interference layers DL1 and DL2, but the implementation of this specification is not limited to this.

[0194] According to one embodiment, the nanopattern NP can be integrally formed with the destructive interference layer DL. For example, the nanopattern NP can be integrally formed with the second destructive interference layer DL2. The nanopattern NP can be directly connected to the second destructive interference layer DL2 and can include the same material as the second destructive interference layer DL2. However, the nanopattern NP can include a material different from the second destructive interference layer DL2.

[0195] Multiple nanopatterns NP can be used to reduce the travel angle of the first light L1 (or external light) incident from the top of the capping layer CG. Additionally, the multiple nanopatterns NP, together with the adjacent upper planarization layer OCR, can form a gradient refractive index from top to bottom, thereby suppressing surface reflection of the first light L1. When the optical component LSP is not provided (the upper planarization layer OCR is also omitted or can be simply provided), the first light L1 can pass through the capping layer CG, the planarization layer OC, and color filters 191, 192, and 193 from the top (see...). Figure 3 Furthermore, the refractive indices of the planarization layer OC and color filters 191, 192, and 193 can vary depending on the surrounding environment (e.g., temperature). Therefore, even when the planarization layer OC and color filters 191, 192, and 193 are designed not to have substantially different refractive indices in order to suppress reflection of the first light L1 from the interface between the planarization layer OC and the color filters 191, 192, and 193, the refractive indices of the planarization layer OC and the color filters 191, 192, and 193 still vary depending on the surrounding environment, thus inevitably causing surface (or interface) reflection of the first light L1 at the interface between the planarization layer OC and the color filters 191, 192, and 193. The interface reflectivity can be proportional to the difference in refractive index at the interface.

[0196] However, the main objective of one implementation is to eliminate the first light L1 before it reaches the color filters 191, 192 and 193, and to this end, by utilizing the nanopattern NP and the upper planarization layer OCR to form multiple layers with a gradient refractive index from top to bottom “optically”, interface reflections that may occur during the process of the first light L1 reaching the destructive interference layer DL can be suppressed as much as possible.

[0197] Therefore, the second light L2 that has passed through the nanopattern NP and the upper planarization layer OCR can be eliminated by the destructive interference layer DL. Thus, the display panel 100 can significantly reduce the reflection of external light. The following will explain... Figure 10 and Figure 11 A more detailed description is given in the text.

[0198] According to one embodiment of the display panel, since color filters 191, 192 and 193 and a black matrix BM can be used (see... Figure 3) and / or dike section 154 (see Figure 3 (or black embankment) to reduce or prevent the reflection of external light (or surface reflection), thus the polarization unit can be removed and thinning can be achieved. In addition, when surface reflection occurs from the surfaces of color filters 191, 192 and 193, optical components LSP provided on color filters 191, 192 and 193 can be used to reduce or prevent color conversion.

[0199] Figure 10 yes Figure 9 Enlarged cross-sectional view of region Q2 in the image.

[0200] Reference Figure 9 and Figure 10 The planarization layer OCR between the nanopatterned NP and adjacent nanopatterned NPs can be formed in multiple layers F1 to FS with gradient refractive indices. In this specification, when multiple layers F1 to FS have gradient refractive indices, this does not mean that each layer is actually changed to a different material than the nanopatterned NP and the planarization layer OCR, but rather that the first light L1 (see...) Figure 9 The upper planarization layer can be identified by OCR as multiple layers F1 to FS with gradient refractive indices “optically”.

[0201] In order to make the first light L1 (see Figure 9 To identify the upper planarization layer as multiple layers F1 to FS with gradient refractive index "optically", the following conditions must be met.

[0202] first condition

[0203] The first condition is that the refractive index of the nanopatterned NP needs to be greater than the refractive index of the upper planarization layer OCR. As described above, since the nanopatterned NP is formed using the same process as the second destructive interference layer DL2, which has a large refractive index, the nanopatterned NP can have a larger refractive index than the upper planarization layer OCR. For example, the refractive index of the upper planarization layer OCR varies depending on the surrounding environment, but can be in the range of about 1.5 to about 1.6. For example, the refractive index of the nanopatterned NP can be in the range of about 2.4 to about 2.8, but the embodiments described in this specification are not limited to this.

[0204] The refractive index of each layer F1 to FS can be calculated using the following formula.

[0205] [Formula 1]

[0206]

[0207] In Equation 1, n represents the refractive index of the specific layers F1 to FS to be calculated, nocr represents the refractive index of the upper planarization layer OCR, nnp represents the refractive index of the nanopattern NP, t represents the thickness of the nanopattern NP, h represents the height from the lower end of the nanopattern NP to the surface of the specific layers F1 to FS to be calculated, W1 represents the width of the lower surface of the nanopattern NP, and W2 represents the width of the upper surface of the nanopattern NP.

[0208] Second condition

[0209] Subsequently, the second condition is that, since the refractive index of each layer F1 to FS is calculated based on the density of the nanopattern NP and the upper planarization layer OCR in each layer F1 to FS as shown in Equation 1, the density of the nanopattern NP needs to increase as it decreases (F1→F2……→FS).

[0210] The increase in the density of the nanopatterned NP is related to the shape of the nanopatterned NP, and the cross-sectional shape of the nanopatterned NP can be such that the width W1 of the lower surface is greater than the width W2 of the upper surface and the side surfaces of the nanopatterned NP are conical. For example, the cross-sectional shape of the nanopatterned NP can be trapezoidal or triangular, but the embodiments described herein are not limited to this. The three-dimensional shape of the nanopatterned NP can be a cylinder or cone with conical side surfaces reflecting the cross-sectional shape of a trapezoid or triangle, but the embodiments described herein are not limited to this.

[0211] Figure 11 yes Figure 9 Enlarged cross-sectional view of region Q3 in the image.

[0212] Reference Figure 11 The second beam L2, which has passed through the nanopattern NP and the upper planarization layer OCR, can be destructively interfered with by the destructive interference layer DL. The refractive index of the second destructive interference layer DL2 can be greater than that of the first destructive interference layer DL1. The first destructive interference layer DL1 and the second destructive interference layer DL2 can be set as multiple destructive interference layers, and they can be alternately and repeatedly set upwards.

[0213] For example, some light L2a of the second light L2 can be reflected at the boundary (or interface) between the uppermost second destructive interference layer DL2 and the first destructive interference layer DL1 directly below the second destructive interference layer DL2, and other light L2b of the second light L2 can be reflected at the boundary (or interface) between the second destructive interference layer DL2 below the first destructive interference layer DL1 and the first destructive interference layer DL1 directly below the second destructive interference layer DL2. When the destructive interference condition is met, some light L2a and other light L2b can cancel each other out and be eliminated.

[0214] According to one embodiment, the thicknesses of the first destructive interference layer DL1 and the second destructive interference layer DL2 can be set to satisfy the destructive interference condition. For example, the destructive interference condition of the first destructive interference layer DL1 and the second destructive interference layer DL2, as well as the thickness satisfying the destructive interference condition, can be determined based on the incident angle (or travel angle) of the second light L2, and can generally be determined within a low incident angle range. As described above, since the nanopattern NP is used to reduce the interference from the capping layer CG (see... Figure 9 The angle of travel of the external light (or the first light L1) incident on the top of the destructive interference layer DL is such that the second light L2 incident on the destructive interference layer DL is likely to be destructively interfered by the destructive interference layer DL.

[0215] Figure 12 This is an example of a graph showing the reflectivity based on wavelength when no optical components are present. Figure 13 This is an example of a graph showing the reflectivity based on wavelength when optical components are installed. Figure 12 It is from Figure 9 The curve when the nanopattern NP is omitted is shown in the figure, and Figure 13 Is when structure and Figure 9 A graph showing the same or similar structures. Figure 12 and Figure 13 In the figure, the horizontal axis represents the wavelength (nm) of external light incident at 6°, 20°, 40° and 60° (e.g., the wavelength of the incident external light), and the vertical axis represents the reflectance (reflectance, %) of external light incident at 6°, 20°, 40° and 60°.

[0216] like Figure 12 and Figure 13 As shown, nanopatterned NPs can reduce the reflectivity of external light across all wavelength bands at various travel angles (6°, 20°, 40°, and 60°). As described above, multiple nanopatterned NPs can reduce the reflectivity of light from the capping layer CG (see [link to capping layer]). Figure 9 The angle of travel of external light incident on the top of the destructive interference layer DL. Therefore, external light incident on the destructive interference layer DL is likely to be destructively interfered with by the destructive interference layer DL. In addition, due to the nanopattern NP and the adjacent upper planarization layer OCR (see Figure 11 Together, they form a gradient refractive index from top to bottom, thus suppressing surface reflection of external light so that most of the external light incident on the nanopattern NP and the upper planarization layer OCR can reach the destructive interference layer DL without surface reflection.

[0217] Figure 14 It is a planar diagram of a nanopattern according to one embodiment.

[0218] Reference Figure 14 According to one embodiment, the nanopatterns NP can be configured to be spaced apart from each other in a planar diagram. Figure 14An example is illustrated by a nanopattern NP arranged in a matrix manner along a first direction DR1 and a second direction DR2. However, the embodiments described in this specification are not limited to this, and the nanopattern NP can be arranged in various ways, as long as they satisfy the above requirements. Figure 11 Equation 1 as described in the text.

[0219] For example, the flat surface shape of the nanopattern NP can be circular, but the embodiments described herein are not limited to this, and the flat surface shape of the nanopattern NP can be elliptical, rectangular, square or other polygonal.

[0220] In the following description, a display device according to other embodiments will be described. In the following embodiments, details will be omitted or may be briefly provided. Figures 1 to 14 The detailed description of the reference numerals or components described in the figures may be omitted or may be briefly repeated.

[0221] Figure 15 This is a cross-sectional view of a display device according to another embodiment.

[0222] Reference Figure 15 The display panel 100_1 of the display device according to this embodiment and the display panel 100_1 according to this embodiment Figure 3 The difference in the display panel 100 is that the optical component LSP can be disposed only in the light-emitting areas EA1, EA2, and EA3, and can be omitted from the non-light-emitting areas NEA1, NEA2, and NEA3. The upper surface of the planarization layer OC exposed through the optical component LSP can be in direct contact with the upper planarization layer OCR.

[0223] According to this embodiment, as described above, the optical component LSP is used to improve surface reflection of external light, and the embankment 154 capable of providing surface reflection of external light is provided in the non-light-emitting regions NEA1, NEA2, and NEA3. Therefore, by arranging the optical component LSP only in the light-emitting regions EA1, EA2, and EA3, there is an advantage of cost reduction.

[0224] Since the above has already been... Figure 3 The remaining parts are described in the text, so their specific descriptions will be omitted or can be provided briefly.

[0225] Figure 16 This is a cross-sectional view of a display device according to yet another embodiment. Figure 17 This is a cross-sectional view of a display device according to yet another embodiment. Figure 18 This is a cross-sectional view of a display device according to yet another embodiment.

[0226] Reference Figures 16 to 18 The display panel 100_2 of the display device according to this embodiment and the display panel 100_2 according to this embodiment Figure 3 , Figure 7 and Figure 8 The difference between the display panel 100 and the display panel 100_2 is that the display panel 100_2 may also include a third protective layer 113 located on the second protective layer 112.

[0227] More specifically, the display panel 100_2 according to this embodiment may further include a third protective layer 113 located between the second protective layer 112 and the first electrode 151. The material of the third protective layer 113 may include at least one of the materials exemplified by the material of the second protective layer 112, but the embodiments described herein are not limited thereto.

[0228] like Figure 17 and Figure 18 As shown, each of the first dam section D1_1 and the second dam section D2_1 may include a third protective layer 113 as the first layer, and may not include the second protective layer 112, but the embodiments described herein are not limited thereto.

[0229] Since the above has already been... Figure 3 , Figure 7 and Figure 8 The remaining components are described in the previous section, so their detailed descriptions will be omitted below.

[0230] Figure 19 This is a cross-sectional view of a display device according to another embodiment.

[0231] Reference Figure 19 According to this embodiment, the color filters 191_1, 192_1, and 193_1 of the display panel 100_3 of the display device are consistent with those of the display device according to this embodiment. Figure 3 The difference with the display panels 100 is that they can overlap each other in the non-light-emitting areas NEA1, NEA2 and NEA3.

[0232] Figure 19 The example shows a second color filter 192_1 located at the top, a first color filter 191_1 located below the second color filter 192_1, and finally, a third color filter 193_1 located at the bottom in each non-luminescent region NEA1, NEA2, or NEA3. However, the stacking order of color filters 191_1, 192_1, and 193_1 in the non-luminescent regions NEA1, NEA2, and NEA3 can vary depending on the process sequence.

[0233] Since the above has already been... Figure 3 The remaining parts are described in the text, so their specific descriptions will be omitted or can be provided briefly.

[0234] Figure 20 This is a perspective view of a display device according to another embodiment. Figure 21 It is along Figure 20 A cross-sectional view of line D-D' in the diagram.

[0235] Reference Figure 20 and Figure 21 The display device 2 according to this embodiment and the display device 2 according to this embodiment Figure 1 The difference between display device 1 and display device 2 is that display device 2 is a foldable display device.

[0236] In this specification, the display device 2 along its folding axis A1 may be the same as or similar to the second direction DR2.

[0237] The top frame TF is located at the top of the display device 2. Relative to the folding axis A1, the top frame TF includes a first top frame TF1 located on one side and a second top frame TF2 located on the other side. The top frame TF can be configured to cover the edge of the display panel 100_4. The top frame TF can protect the display panel 100_4 from external impacts. The top frame TF can form the bezel of the display device 2.

[0238] The capping CG can be placed below the top frame TF. The capping CG can also be placed above the display panel 100_4.

[0239] The cover CG can be positioned above the display panel 100_4 to protect the components positioned below the cover CG from external influences.

[0240] The panel assembly is located below the cover layer CG. The panel assembly includes a display panel 100_4 and a board PLT. The display panel 100_4 may be substantially the same as one of the aforementioned display panels 100, 100_1, 100_2 and 100_3.

[0241] The plate PLT can be disposed below the display panel 100_4 and can include various plates for supporting the display panel 100_4. For example, one or more plates may include a back plate for supporting the display panel 100_4, a top plate disposed below the back plate and made of stainless steel (SUS) material, a bottom plate disposed below the top plate and having a pattern formed on the folding portion and made of SUS material, a heat sink for performing heat dissipation function, an intermediate plate for covering the non-flattened flat surface caused by various components of the hinge assembly, etc.

[0242] A slit pattern PTN can be formed in the plate PLT. The slit pattern PTN can be formed at a position corresponding to the folding area FA of the display panel 100_4. The slit pattern PTN can be a slit-shaped etched portion formed in the plate PLT. For example, the plate PLT can be formed of a metal such as SUS material, but the rigidity of the metal may cause limitations when folding or unfolding the plate PLT. The slit pattern PTN can supplement the flexibility of the plate PLT.

[0243] The intermediate plate MST is positioned below the panel assembly. The intermediate plate MST supports the upwardly positioned assembly. Additionally, the hinge assembly 200 and the cover frame CF are positioned downwards from the intermediate plate MST, and their upper surfaces may be uneven. The intermediate plate MST can flatten the uneven lower surface. The intermediate plate MST can be formed of a material such as plastic, polyimide, or metal to increase the rigidity of the display device 2. For example, the intermediate plate MST may include aluminum or SUS, but is not limited to these.

[0244] The intermediate plate MST may include a first intermediate plate portion MSTH1 disposed in the first unfolded region NFA1 and a second intermediate plate portion MSTH2 disposed in the second unfolded region NFA2.

[0245] The hinge assembly 200 is disposed below the panel assembly. The hinge assembly 200 is disposed below the folding area FA. The hinge assembly 200 may have a shape extending along the folding axis A1. The hinge assembly 200 can perform a folding movement, wherein one side and the other side rotate about the folding axis A1.

[0246] The cover frame CF is disposed below the hinge assembly 200. A receiving groove for accommodating a portion of the hinge assembly 200 can be formed in the upper surface of the cover frame CF. Relative to the folding axis A1, the cover frame CF includes a first cover frame CF1 disposed on one side and a second cover frame CF2 disposed on the other side. The cover frame CF can be a housing for defining the side and rear surfaces of the display device 2. The cover frame CF can protect the display device 2 from external impacts. The cover frame CF can be coupled to the hinge assembly 200. Folding and unfolding of the display device 2 can be achieved by rotating the cover frames CF1 and CF2.

[0247] Connecting members BM1, BM2, and BM3 for connecting adjacent members MST, PLT, PNL, and CG can also be disposed between adjacent members. In each of the unfolded areas NFA1 and NFA2, the first connecting member BM1 can connect the intermediate plate portions MSTH1 and MSTH2 to the plate PLT disposed above the intermediate plate portions MSTH1 and MSTH2; the second connecting member BM2 can connect the plate PLT and the slit pattern PTN to the display panel 100_4 disposed above the plate PLT and the slit pattern PTN; and the third connecting member BM3 can connect the display panel 100_4 to the cover layer CG.

[0248] The connected plate PLT and intermediate plate MST can be mounted on the cover frames CF1 and CF2. The display device 2 can be folded and unfolded via the hinge assembly 200 provided on the cover frames CF1 and CF2.

[0249] Since the display panel 100_4 has already been described above, its specific description will be omitted below.

[0250] The display device according to various embodiments of this specification can be described as follows.

[0251] According to embodiments of this specification, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a first electrode disposed in each of the sub-pixels on the substrate; a dam disposed on the first electrode, located at the boundary between adjacent sub-pixels and overlapping the periphery of the upper surface of the first electrode; an organic layer disposed on the first electrode and the dam; a second electrode disposed on the organic layer; a color filter disposed on the second electrode; and an optical component disposed on the color filter, wherein the dam comprises a black base material, and the optical component includes an destructive interference layer and nanopatterns spaced apart from each other on the destructive interference layer.

[0252] In the display device according to the embodiments of this specification, the destructive interference layer and the nanopattern can be directly connected.

[0253] In a display device according to an embodiment of this specification, the destructive interference layer may include a first destructive interference layer and a second destructive interference layer located on the first destructive interference layer, and the refractive index of the second destructive interference layer may be greater than the refractive index of the first destructive interference layer.

[0254] In the display device according to embodiments of this specification, the second phase-deinterference layer may include the same material as the nanopattern.

[0255] In the display device according to the embodiments of this specification, the first anti-interference layer and the second anti-interference layer may be alternately and repeatedly provided.

[0256] In the display device according to the embodiments of this specification, the width of the lower surface of the nanopattern may be greater than the width of the upper surface of the nanopattern.

[0257] The display device according to embodiments of this specification may further include an upper planarization layer located on the nanopattern, wherein the upper planarization layer may be in direct contact with the upper surface and side surface of the nanopattern.

[0258] In the display device according to the embodiments of this specification, the upper planarization layer may be filled between adjacent nanopatterns.

[0259] In the display device according to the embodiments of this specification, the refractive index of the nanopattern can be greater than the refractive index of the upper planarization layer.

[0260] In a display device according to an embodiment of this specification, a plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and an organic layer may be disposed across the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0261] In a display device according to an embodiment of this specification, the organic layer may include a first light-emitting layer located on a first sub-pixel, a second light-emitting layer located on a second sub-pixel, and a third light-emitting layer located on a third sub-pixel.

[0262] In a display device according to an embodiment of this specification, in each sub-pixel, each of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer may be stacked in two or more layers.

[0263] The display device according to the embodiments of this specification may further include a black matrix located between adjacent sub-pixels between the second electrode and the color filter, wherein the width of the black matrix may be smaller than the width of the embankment.

[0264] In a display device according to an embodiment of this specification, the end portion of the black matrix may be closer to the boundary between adjacent sub-pixels than the end portion of the embankment.

[0265] The display device according to the embodiments of this specification may further include a touch component located between the second electrode and the color filter, wherein the touch component may include a bridging electrode and a sensor electrode located on the bridging electrode, and the black matrix may overlap with the bridging electrode and the sensor electrode.

[0266] The display device according to embodiments of this specification may further include: a first transistor located between a substrate and a first electrode; and a second transistor located between the first transistor and the first electrode, wherein the semiconductor layer of the first transistor may include polysilicon, and the semiconductor layer of the second transistor may include oxide.

[0267] According to embodiments of this specification, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a light-emitting unit disposed in each of the sub-pixels on the substrate; an optical component including an destructive interference layer disposed on the light-emitting component and nanopatterns spaced apart from each other on the destructive interference layer; and an upper planarization layer disposed on the optical component and filling between adjacent nanopatterns, wherein the nanopatterns alter the optical path of external light, and the destructive interference layer destructively interferes with the external light whose optical path has been altered.

[0268] In the display device according to the embodiments of this specification, the destructive interference layer and the nanopattern can be directly connected.

[0269] In a display device according to an embodiment of this specification, the destructive interference layer may include a first destructive interference layer and a second destructive interference layer located on the first destructive interference layer. The refractive index of the second destructive interference layer may be greater than the refractive index of the first destructive interference layer, and the second destructive interference layer may include the same material as the nanopattern.

[0270] In the display device according to the embodiments of this specification, the width of the lower surface of the nanopattern may be greater than the width of the upper surface of the nanopattern, and the refractive index of the nanopattern may be greater than the refractive index of the upper planarization layer.

[0271] According to embodiments of this specification, by omitting the polarization unit, the display device can have improved flexibility and can be applied to foldable products where the display area is folded.

[0272] According to embodiments of this specification, external light reflection can be improved by arranging color filters and a dam comprising a black base material.

[0273] According to the embodiments of this specification, since color filters, black matrices, and / or black embankments can be used to reduce or prevent external light reflection, polarization units can be eliminated and thinning can be achieved. Furthermore, when surface reflection occurs from the surface of the color filter, optical components disposed on the color filter according to the embodiments of this specification can be used to reduce or prevent color conversion caused by surface reflection.

[0274] According to the embodiments described in this specification, the reflectivity of external light can be improved by arranging optical components.

[0275] According to embodiments of this specification, since the optical components include nanopatterns, the reflection of external light can be reduced or minimized, and the travel angle of external light can be reduced.

[0276] According to embodiments of this specification, since the optical component includes a destructive interference layer beneath the nanopattern, the reflection of external light can be reduced or minimized.

[0277] According to the embodiments described herein, surface reflection of external light can be improved to provide a low-reflection display device, thereby achieving low power consumption.

[0278] However, the effects that can be obtained from this specification are not limited to those described above, and based on the description, those skilled in the art to which this specification pertains will be able to clearly understand other effects not mentioned.

[0279] Although embodiments of the present disclosure have been described above with reference to the accompanying drawings, those skilled in the art will understand that the above-described technical configurations of the present disclosure can be implemented in other specific forms without altering its technical concept or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all respects. Furthermore, the scope of the present disclosure is defined by the described claims rather than the specific description. Additionally, the meaning and scope of the claims, as well as all changes or modifications derived from equivalent concepts, should be construed as being included within the scope of this disclosure.

[0280] Cross-references to related applications

[0281] This application claims priority to Korean Patent Application No. 10-2024-0130563, filed on September 26, 2024, the entire contents of which are expressly incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; A first electrode is disposed in each of the sub-pixels on the substrate; A dam portion is disposed on the first electrode and overlaps with the periphery of the upper surface of the first electrode; An organic layer is disposed on the first electrode and the embankment; The second electrode is located on the organic layer; A color filter, wherein the color filter is disposed on the second electrode; as well as Optical components, the optical components being located on the color filter, The embankment comprises a black base material, and The optical component includes a destructive interference layer and nanopatterns spaced apart from each other on the destructive interference layer.

2. The display device according to claim 1, wherein, The destructive interference layer is directly connected to the nanopattern.

3. The display device according to claim 1, wherein, The destructive interference layer includes a first destructive interference layer and a second destructive interference layer located on the first destructive interference layer, wherein the refractive index of the second destructive interference layer is greater than the refractive index of the first destructive interference layer.

4. The display device according to claim 3, wherein, The second destructive interference layer comprises the same material as the nanopattern.

5. The display device according to claim 3, wherein, The first destructive interference layer and the second destructive interference layer are alternately and repeatedly disposed.

6. The display device according to claim 1, wherein, The width of the lower surface of the nanopattern is greater than the width of the upper surface of the nanopattern.

7. The display device according to claim 6, further comprising an upper planarization layer located on the nanopattern, wherein, The upper planarization layer is in direct contact with the upper and side surfaces of the nanopattern.

8. The display device according to claim 7, wherein, The upper planarization layer fills the spaces between adjacent nanopatterns.

9. The display device according to claim 8, wherein, The refractive index of the nanopattern is greater than that of the upper planarization layer.

10. The display device according to claim 1, wherein, The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the organic layer is disposed across the first sub-pixel to the third sub-pixel.

11. The display device according to claim 10, wherein, The organic layer includes a first light-emitting layer located on the first sub-pixel, a second light-emitting layer located on the second sub-pixel, and a third light-emitting layer located on the third sub-pixel.

12. The display device according to claim 11, wherein, In each sub-pixel, each of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer is stacked as two or more layers.

13. The display device according to claim 1, further comprising a black matrix, the black matrix being located at the boundary between adjacent sub-pixels between the second electrode and the color filter, wherein, The width of the black matrix is ​​smaller than the width of the embankment.

14. The display device according to claim 13, wherein, The ends of the black matrix are closer to the boundaries between adjacent sub-pixels than the ends of the dike.

15. The display device according to claim 13, further comprising a touch component located between the second electrode and the color filter, wherein, The touch component includes a bridging electrode and a sensor electrode located on the bridging electrode, and the black matrix overlaps with the bridging electrode and the sensor electrode.

16. The display device according to claim 1, further comprising: A first transistor, wherein the first transistor is located between the substrate and the first electrode; and a second transistor located between the first transistor and the first electrode, wherein the semiconductor layer of the first transistor comprises polysilicon, and the semiconductor layer of the second transistor comprises oxide.

17. The display device according to claim 1, wherein, The embankment is located at the boundary between adjacent sub-pixels.

18. A display device, the display device comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; A light-emitting component, wherein the light-emitting component is disposed in each of the sub-pixels on the substrate; An optical component, the optical component comprising an destructive interference layer located on the light-emitting component and nanopatterns spaced apart from each other on the destructive interference layer; as well as An upper planarization layer is disposed on the optical component and fills the spaces between adjacent nanopatterns.

19. The display device according to claim 18, wherein, The nanopatterns alter the optical path of external light, and The destructive interference layer destructively interferes with the external light whose optical path has been altered.

20. The display device according to claim 19, wherein, The destructive interference layer and the nanopattern are directly connected.

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