Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device may include: a first anode electrode, a second anode electrode, and a third anode electrode; a pixel defining layer including a first pixel opening, a second pixel opening and a third pixel opening disposed on the first anode electrode, the second anode electrode and the third anode electrode, respectively, each having a circular shape and extending to a portion of the first anode electrode to a portion of the third anode electrode, respectively; an emission layer disposed on the first to third anode electrodes in the first to third pixel openings; a cathode electrode covering the pixel defining layer and the first to third emission layers; and a light blocking layer disposed on the cathode electrode and including a circular opening. The third anode electrode may include a flat portion and an inclined portion. The centers of the first to third pixel openings coincide with the centers of the first to third openings. A radius of the third opening may be less than a radius of the third pixel opening.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0131043, filed on September 26, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Various embodiments of this disclosure relate to a display device and an electronic device including the display device. Background Technology

[0003] With the development of information technology, the importance of display devices, which serve as a connection medium between users and information, has increased. To better fulfill their function as a connection medium, the use of display devices such as organic light-emitting diode (OLED) displays is on the rise. Summary of the Invention

[0004] Various embodiments of this disclosure relate to a display device with enhanced design flexibility and improved light output efficiency.

[0005] Embodiments of this disclosure may provide a display device comprising: a first anode electrode, a second anode electrode, and a third anode electrode, spaced apart from each other; a pixel defining layer including a first pixel opening, a second pixel opening, and a third pixel opening respectively disposed on the first anode electrode, the second anode electrode, and the third anode electrode, each of the first pixel opening, the second pixel opening, and the third pixel opening having a circular shape in a plan view and extending to a portion of the first anode electrode, a portion of the second anode electrode, and a portion of the third anode electrode, respectively; a first emitting layer, a second emitting layer, and a third emitting layer disposed on the first anode electrode, the second anode electrode, and the third anode electrode respectively in the first pixel opening, the second pixel opening, and the third pixel opening; a cathode electrode covering the pixel defining layer and the first emitting layer, the second emitting layer, and the third emitting layer; and a light blocking layer disposed on the cathode electrode, and including the first opening, the second opening, and the third opening, each having a circular shape in a plan view. The third anode electrode may include a flat portion and a sloping portion around the flat portion in the region overlapping with the third pixel opening. The centers of the first pixel opening, the second pixel opening, and the third pixel opening may coincide with the centers of the first opening, the second opening, and the third opening, respectively. The radius of the third opening can be smaller than the radius of the third pixel opening.

[0006] In this embodiment, the radius of the first opening may be larger than the radius of the first pixel opening. The radius of the second opening may be larger than the radius of the second pixel opening.

[0007] In an embodiment, the radius of the third pixel opening can be greater than the radius of the first pixel opening and the radius of the second pixel opening.

[0008] In an embodiment, the radius of the first pixel opening can be larger than the radius of the second pixel opening.

[0009] In an embodiment, the difference between the radius of the first opening and the radius of the first pixel opening can be equal to the difference between the radius of the second opening and the radius of the second pixel opening.

[0010] In an embodiment, in a cross-sectional view, the acute angle formed by the upper surface of the inclined portion relative to a plane parallel to the upper surface of the flat portion can be about 15 degrees or greater and about 45 degrees or less.

[0011] In an embodiment, in a cross-sectional view, the distance in the thickness direction between the upper surface of the third anode electrode overlapping the flat surface of the pixel defining layer and the upper surface of the flat portion can be about 0.5 micrometers or more and about 3 micrometers or less.

[0012] In an embodiment, in a cross-sectional view, the orthogonal projection of the edge of the third opening in the thickness direction may be located on the inclined portion.

[0013] In an embodiment, the display device may further include: a first color filter disposed in a first opening; a second color filter disposed in a second opening; and a third color filter disposed in a third opening.

[0014] Embodiments of this disclosure may provide a display device comprising: a first anode electrode including a first flat portion and a first inclined portion surrounding the first flat portion; a second anode electrode including a second flat portion and a second inclined portion surrounding the second flat portion; a third anode electrode including a third flat portion and a third inclined portion surrounding the third flat portion; a pixel defining layer including a first pixel opening exposing the first flat portion and the first inclined portion and having a circular shape in a plan view, a second pixel opening exposing the second flat portion and the second inclined portion and having a circular shape in a plan view, and a third pixel opening exposing the third flat portion and the third inclined portion and having a circular shape in a plan view; a first emitting layer, a second emitting layer, and a third emitting layer disposed on the first anode electrode, the second anode electrode, and the third anode electrode respectively in the first pixel opening, the second pixel opening, and the third pixel opening; a cathode electrode covering the pixel defining layer and the first emitting layer, the second emitting layer, and the third emitting layer; and a light blocking layer disposed on the cathode electrode and including a first opening, a second opening, and a third opening, all having a circular shape in a plan view. The centers of the first pixel opening, the second pixel opening, and the third pixel opening may coincide with the centers of the first opening, the second opening, and the third opening, respectively.

[0015] In an embodiment, in a planar view, the radius of the first opening may be smaller than the radius of the first pixel opening. The radius of the second opening may be smaller than the radius of the second pixel opening. The radius of the third opening may be smaller than the radius of the third pixel opening.

[0016] In an embodiment, in a planar view, the first difference between the radius of the first pixel opening and the radius of the first opening, the second difference between the radius of the second pixel opening and the radius of the second opening, and the third difference between the radius of the third pixel opening and the radius of the third opening can be different from each other.

[0017] In an embodiment, in a planar view, the radius of the third pixel opening can be greater than the radius of the first pixel opening and the radius of the second pixel opening.

[0018] In an embodiment, the radius of the first pixel opening can be larger than the radius of the second pixel opening.

[0019] In an embodiment, in a cross-sectional view, the orthogonal projection of the edge of the first opening in the thickness direction may be located on the first inclined portion. In a cross-sectional view, the orthogonal projection of the edge of the second opening in the thickness direction may be located on the second inclined portion. In a cross-sectional view, the orthogonal projection of the edge of the third opening in the thickness direction may be located on the third inclined portion.

[0020] In an embodiment, in a cross-sectional view, the first acute angle between the upper surface of the first inclined portion and the plane parallel to the upper surface of the first flat portion, the second acute angle between the upper surface of the second inclined portion and the plane parallel to the upper surface of the second flat portion, and the third acute angle between the upper surface of the third inclined portion and the plane parallel to the upper surface of the third flat portion can all be about 15 degrees or greater and about 45 degrees or less.

[0021] In an embodiment, the first acute angle, the second acute angle, and the third acute angle may be different from each other in the cross-sectional view.

[0022] In an embodiment, in a cross-sectional view, each of the following distances in the thickness direction—a first distance between the upper surface of the first anode electrode stacked with the pixel-defining layer and the upper surface of the first flat portion, a second distance in the thickness direction between the upper surface of the second anode electrode stacked with the pixel-defining layer and the upper surface of the second flat portion, and a third distance in the thickness direction between the upper surface of the third anode electrode stacked with the pixel-defining layer and the upper surface of the third flat portion—may be about 0.5 micrometers or greater and about 3 micrometers or less.

[0023] In an embodiment, the first distance, the second distance, and the third distance may be different from each other in the cross-sectional view.

[0024] Embodiments of this disclosure can provide an electronic device including a display device for displaying images. The display device may include: a first anode electrode, a second anode electrode, and a third anode electrode, spaced apart from each other; a pixel defining layer including a first pixel opening, a second pixel opening, and a third pixel opening extending respectively into portions of the first anode electrode, a portion of the second anode electrode, and a portion of the third anode electrode, each of the first pixel opening, the second pixel opening, and the third pixel opening having a circular shape in a plan view; a first emitting layer, a second emitting layer, and a third emitting layer disposed on the first anode electrode, the second anode electrode, and the third anode electrode respectively in the first pixel opening, the second pixel opening, and the third pixel opening; a cathode electrode covering the pixel defining layer and the first emitting layer, the second emitting layer, and the third emitting layer; and a light blocking layer disposed on the cathode electrode, and including the first opening, the second opening, and the third opening, each having a circular shape in a plan view. The third anode electrode includes a flat portion and a sloped portion surrounding the flat portion in the region overlapping with the third pixel opening. The centers of the first pixel opening, the second pixel opening, and the third pixel opening may coincide with the centers of the first opening, the second opening, and the third opening, respectively. The radius of the third opening may be smaller than the radius of the third pixel opening. Attached Figure Description

[0025] Figure 1 This is a block diagram used to describe a display device according to embodiments of the present disclosure.

[0026] Figure 2 It is used to describe including Figure 1 A block diagram of any one of the subpixels in a display device.

[0027] Figure 3 It is used to describe the composition Figure 1 A plan view of the display panel of the display device.

[0028] Figure 4 It is used to describe Figure 3 A cross-sectional view of an embodiment of the display panel.

[0029] Figure 5 It is used to describe Figure 3 A cross-sectional view of another embodiment of the display panel.

[0030] Figure 6 and Figure 7 It is used to describe including Figure 3 A plan view of an embodiment of any one of the pixels in the display panel.

[0031] Figure 8 It is along Figure 7 A sectional view taken from line I1-I1'.

[0032] Figure 9 It is along Figure 7 A sectional view taken from line I2-I2'.

[0033] Figure 10 It is shown Figure 9 A magnified planar view of the third sub-pixel region.

[0034] Figure 11 and Figure 12 It is used to describe including Figure 3 A plan view of another embodiment of any one of the pixels in the display panel.

[0035] Figure 13 It is along Figure 12 A sectional view taken from line I3-I3'.

[0036] Figure 14 It is shown Figure 13 A magnified planar view of the first sub-pixel region.

[0037] Figure 15 It is shown Figure 13 A magnified planar view of the 2-1 sub-pixel region.

[0038] Figure 16 It is along Figure 12 A sectional view taken from line I4-I4'.

[0039] Figure 17 It is shown Figure 16 An enlarged cross-sectional view of the 2nd-2nd sub-pixel region.

[0040] Figure 18 It is shown Figure 16 An enlarged cross-sectional view of the third sub-pixel region.

[0041] Figure 19 This is a block diagram of an electronic device according to an embodiment.

[0042] Figure 20 Schematic diagrams of various embodiments of the electronic device are shown. Detailed Implementation

[0043] In the following description, embodiments of the invention will be described in detail with reference to the accompanying drawings. In the description below, only the parts necessary for understanding operation according to this disclosure will be described, and explanations of other parts will be omitted. Therefore, this disclosure is not limited to the embodiments set forth herein and can be implemented in variations. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the spirit of the disclosed technology to those skilled in the art.

[0044] It will be understood that when an element is referred to as being “joined” or “connected” to another element, it may be directly joined or directly connected to said other element, or indirectly joined or indirectly connected to said other element with an intermediary element between them. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In the specification, when an element is referred to as “comprising” or “including” a component, it does not exclude another component, but may include other components, unless the context clearly indicates otherwise. “At least one of X, Y, and Z” and “at least one selected from an array of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items.

[0045] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element. Furthermore, there may be multiple “first” elements and / or multiple “second” elements.

[0046] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, then an element described as “below” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0047] Various embodiments will be described with reference to the accompanying drawings, which illustrate preferred embodiments. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments disclosed herein should not be construed as limited to a specific shape of the illustrated area, but rather include shape deviations due to, for example, manufacturing processes. Thus, the shapes shown in the drawings may not show the exact shape of an area of ​​the device, and are not intended to be limiting.

[0048] Figure 1 This is a block diagram for describing a display device DD according to embodiments of the present disclosure.

[0049] Reference Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0050] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm, where m is a natural number greater than 0. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn, where n is a natural number greater than 0.

[0051] Subpixels (SPs) can generate light of two or more colors. For example, each subpixel SP can generate light of colors such as red, green, blue, cyan, magenta, or yellow.

[0052] Two or more subpixels in subpixel SP can form a pixel PXL. For example, as Figure 1 As shown, pixel PXL can include four sub-pixels. Depending on the combination of light emitted from the sub-pixels included in pixel PXL, pixel PXL can emit light of various colors and brightness.

[0053] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0054] Gate driver 120 may be disposed on a first side of display panel DP. However, embodiments are not limited to the foregoing examples. For example, gate driver 120 may be divided into two or more drivers that are physically and / or logically separated from each other. Drivers may be disposed on a first side of display panel DP and a second side of display panel DP opposite to the first side. Thus, gate driver 120 may be disposed around display panel DP in various forms depending on the embodiment.

[0055] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include source start signal, source shift clock signal, source output enable signal, etc.

[0056] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 through the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 through the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 through DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0057] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0058] Voltage generator 140 can operate in response to a voltage control signal VCS provided from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of display device DD (such as gate driver 120, data driver 130, and controller 150). Voltage generator 140 can receive input voltages from external devices of display device DD and generate multiple voltages by adjusting the received voltages.

[0059] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The generated first and second electrical voltages can be provided to the sub-pixel SP via power line PL. In another embodiment, at least one of the first and second electrical voltages can be provided from an external device of the display device DD.

[0060] Furthermore, voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages to be applied to sub-pixel SP. For example, during sensing operations for sensing the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, a specific reference voltage can be applied to each of the first data lines DL1 to the nth data line DLn. Voltage generator 140 can generate a reference voltage and transmit the reference voltage to data driver 130. For example, during display operations for displaying an image on display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide the pixel control signal to sub-pixel SP via pixel control line PXCL. Although in Figure 1 The illustration shows a pixel control line PXCL connected between the voltage generator 140 and the display panel DP, but the embodiment is not limited to this. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, the pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0061] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and the corresponding control signal CTRL from an external device. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0062] The controller 150 can convert the input image data IMG into a format suitable for a display device DD or a display panel DP, and then output image data DATA. In one embodiment, the controller 150 can align the input image data IMG line by line to fit the sub-pixels SP, and then output image data DATA.

[0063] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component separate from the driver integrated circuit (DIC).

[0064] Figure 2 It is used to describe including Figure 1A block diagram of any subpixel in the subpixel SP of the display device DD. Figure 2 In, it is shown Figure 1 The sub-pixel SPij is set in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixel SP.

[0065] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0066] The light-emitting element (LD) can be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be connected to... Figure 1 One of the power lines PL is used to receive the first power voltage. The second power voltage node VSSN can be connected to... Figure 1 The first power line (PL) is another power line to receive a second power voltage. The first power voltage may have a higher voltage level than the second power voltage.

[0067] The light-emitting element (LD) can be connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD is configured to emit light based on the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0068] Sub-pixel circuits (SPCs) can be connected to Figure 1 The first gate line GL1 to the m-th gate line GLm, and connected to the i-th gate line GLi. Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to a gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC can control the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to... Figure 1 The pixel control line PXCL. In this case, the sub-pixel circuit SPC can also control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0069] For the above operations, the sub-pixel circuit SPC may include circuit elements (e.g., transistors and one or more capacitors).

[0070] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0071] Figure 3 It is used to describe the composition Figure 1 A plan view of the display panel DP of the display device DD.

[0072] Reference Figure 3 The display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. The non-display area NDA can be positioned around the display area DA.

[0073] The display panel DP may include subpixels SP disposed in the display area DA. The subpixels SP may be arranged on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the subpixels SP may be arranged in a matrix pattern on the first direction DR1 and the second direction DR2. For example, the subpixels SP may be arranged in a zigzag pattern on the first direction DR1 and the second direction DR2. The arrangement of the subpixels SP may vary depending on the embodiment. The first direction DR1 may refer to the row direction, and the second direction DR2 may refer to the column direction.

[0074] Two or more subpixels in subpixel SP can form a pixel PXL. Although Figure 3 The illustration shows that pixel PXL comprises four sub-pixels SP1, SP2a, SP2b, and SP3, but the embodiment is not limited thereto. For example, pixel PXL may include two sub-pixels. In the following text, for ease of explanation, it is assumed that pixel PXL comprises a first sub-pixel SP1, a second-first sub-pixel SP2a, a second-second sub-pixel SP2b, and a third sub-pixel SP3. As used herein, the second-first sub-pixel SP2a and the second-second sub-pixel SP2b are collectively referred to as "second sub-pixel SP2". A portion X of the second sub-pixel SP2 will also be collectively referred to as "second" X, and it is understood that there may be more than one "second" X.

[0075] Each of the first sub-pixel SP1, the second-first sub-pixel SP2a, the second-second sub-pixel SP2b, and the third sub-pixel SP3 can generate light of one of various colors, such as red, green, blue, cyan, magenta, and yellow. In the following description, for clarity and conciseness, it is assumed that the first sub-pixel SP1 is configured to generate red light, each of the second-first sub-pixels SP2a and SP2b is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0076] Each of the first sub-pixel SP1, the second-first sub-pixel SP2a, the second-second sub-pixel SP2b, and the third sub-pixel SP3 may include at least one light-emitting element (LD) configured to generate light. In an embodiment, the light-emitting elements (LDs) of the first sub-pixel SP1, the second-first sub-pixel SP2a, the second-second sub-pixel SP2b, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements (LDs) of the first sub-pixel SP1, the second-first sub-pixel SP2a, the second-second sub-pixel SP2b, and the third sub-pixel SP3 may generate red light, green light, green light, and blue light, respectively.

[0077] As a display panel DP, for example, a self-emitting display panel, such as an organic light-emitting display (OLED) panel that uses organic light-emitting diodes as light-emitting elements, can be used.

[0078] The components used to control the subpixel SP can be located in the non-display area NDA. Lines connected to the subpixel SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be set in the non-display area NDA.

[0079] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 can be disposed in the non-display area NDA. In this case, the data driver 130, voltage generator 140, and controller 150 can be implemented as follows: Figure 1 The driver integrated circuit (DIC) is separate from the display panel (DP). The driver integrated circuit (DIC) can be connected to a line disposed in the non-display area (NDA). In other embodiments, the gate driver 120, together with the data driver 130, voltage generator 140, and controller 150, can be implemented as a single integrated circuit separate from the display panel (DP).

[0080] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, ellipses, etc.

[0081] In one embodiment, the display panel DP may have a flat display surface. In another embodiment, the display panel DP may have a display surface that is at least partially rounded. In yet another embodiment, the display panel DP is flexible, foldable, or rollable. In the foregoing cases, the display panel DP and / or its substrate may comprise a material with flexible properties.

[0082] Figure 4 It is used to describe Figure 3 A cross-sectional view of an embodiment of the display panel DP.

[0083] Reference Figure 4 The display panel DP may include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL sequentially stacked on the substrate SUB on a third direction DR3 that intersects the first direction DR1 and the second direction DR2.

[0084] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate. In another example, the substrate SUB may include a polyimide (PI) substrate. In yet another example, the substrate SUB may include a silicon wafer substrate formed by semiconductor processes.

[0085] In embodiments, the substrate SUB may be made of a flexible material to be bent or foldable, and may have a single-layer or multi-layer structure. Examples of flexible materials include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments are not limited thereto.

[0086] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The PCL may include an insulating layer and semiconductor and conductive patterns disposed between the insulating layers. The conductive patterns of the PCL can be used as circuit elements, lines, etc.

[0087] The circuit elements of the pixel circuit layer PCL can be formed Figure 3 Each of the sub-pixels SP has a sub-pixel circuit SPC. In other words, the circuit elements of the pixel circuit layer PCL can be configured as transistors and one or more capacitors in the sub-pixel circuit SPC.

[0088] The lines in the pixel circuit layer (PCL) may include lines connected to the sub-pixels (SP). The lines in the pixel circuit layer (PCL) may also include various signal lines and / or voltage lines required to drive the display element layer (DPL).

[0089] The display element layer (DPL) can be set on the pixel circuit layer (PCL). The display element layer (DPL) may include the light-emitting elements (LDs) of the sub-pixels (SPs).

[0090] A light functional layer (LFL) may be disposed on a display element layer (DPL). The LFL may include a light conversion pattern with color conversion particles and / or scattering particles. For example, the color conversion particles may include quantum dots. Quantum dots can convert the wavelength (or color) of light emitted from the display element layer (DPL). The LFL may also include a light scattering pattern with scattering particles. In embodiments, the light conversion pattern and light scattering pattern may be omitted.

[0091] The optical functional layer (LFL) may also include a color filter layer containing color filters. Each of the color filters can selectively transmit light of a specific wavelength (or a specific color). In embodiments, the color filter layer may be omitted.

[0092] A window can be installed on the light functional layer (LFL) to protect the exposed surface (or top surface) of the display panel (DP). The window protects the display panel (DP) from external impacts. The window can be attached to the light functional layer (LFL) using an optically transparent adhesive (or bonding agent). The window can have a multi-layer structure selected from glass substrates, plastic films, and plastic substrates. The multi-layer structure can be formed through a continuous process or an adhesive process using adhesive layers. The window, either entirely or partially, can be flexible.

[0093] Figure 5 It is used to describe Figure 3 A cross-sectional view of another embodiment of the display panel DP.

[0094] Reference Figure 5 The display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL. The substrate SUB, pixel circuit layer PCL, display element layer DPL, and light function layer LFL can be aligned with previously referenced... Figure 4 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and optical function layer (LFL) are constructed in essentially the same (or similar) manner. Therefore, redundant explanations will be omitted.

[0095] The input sensing layer (ISL) can sense user input on the upper surface (or display surface) of the display panel (DP). The input sensing layer (ISL) may include components suitable for sensing external objects such as a user's hand or a pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0096] Figure 6 and Figure 7 It is used to describe including Figure 3 A plan view of an embodiment of any one of the pixels PXL in the display panel DP.

[0097] Reference Figure 6 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0098] The first sub-pixel SP1 may include a first anode electrode AE1. The first anode electrode AE1 may be configured as a sub-pixel circuit SPC connected to the first sub-pixel SP1 (see reference). Figure 2 The anode electrode AE ​​of ) (refer to Figure 2 ).

[0099] The second sub-pixel SP2 may include a second anode electrode AE2 spaced apart from the first anode electrode AE1. The second anode electrode AE2 may be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the second sub-pixel SP2.

[0100] In an embodiment, the second sub-pixel SP2 may include a second-first sub-pixel SP2a and a second-second sub-pixel SP2b. The second-first sub-pixel SP2a may include a second-first anode electrode AE2a. The second-first anode electrode AE2a may be configured as the anode electrode AE ​​connected to the sub-pixel circuit SPC of the second-first sub-pixel SP2a. The second-second sub-pixel SP2b may include a second-second anode electrode AE2b spaced apart from the second-first anode electrode AE2a. The second-second anode electrode AE2b may be configured as the anode electrode AE ​​connected to the sub-pixel circuit SPC of the second-second sub-pixel SP2b.

[0101] The third sub-pixel SP3 may include a third anode electrode AE3 spaced apart from the first anode electrode AE1 and the second anode electrode AE2. The third anode electrode AE3 may be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the third sub-pixel SP3.

[0102] Pixel PXL may include a pixel defining layer PDL. The pixel defining layer PDL may include a first pixel opening PXO1, a second pixel opening PXO2, and a third pixel opening PXO3 that respectively expose a portion of a first anode electrode AE1, a portion of a second anode electrode AE2, and a portion of a third anode electrode AE3.

[0103] The first pixel opening PXO1 may expose a portion of the first anode electrode AE1. The first pixel opening PXO1 may be circular in the planar view. In this case, the center of the first pixel opening PXO1 (i.e., the center of the circle) may be the first center C1. The radius of the first pixel opening PXO1 (i.e., the radius of the circle) may be the first pixel radius X1.

[0104] The second pixel opening PXO2 may include the second-first pixel opening PXO2a and the second-second pixel opening PXO2b.

[0105] The 2-1 pixel opening PXO2a can expose a portion of the 2-1 anode electrode AE2a. The 2-1 pixel opening PXO2a can be circular in the planar view. In this case, the center of the 2-1 pixel opening PXO2a can be the 2-1 center C2a. The radius of the 2-1 pixel opening PXO2a can be the 2-1 pixel radius X2a.

[0106] The 2-2 pixel opening PXO2b can expose a portion of the 2-2 anode electrode AE2b. The 2-2 pixel opening PXO2b can be circular in the planar view. In this case, the center of the 2-2 pixel opening PXO2b can be the 2-2 center C2b. The radius of the 2-2 pixel opening PXO2b can be the 2-2 pixel radius x 2b.

[0107] In an embodiment, the radius of the second-1st pixel X2a can be substantially the same as the radius of the second-2nd pixel X2b.

[0108] The third pixel opening PXO3 can expose a portion of the third anode electrode AE3. The third pixel opening PXO3 can be circular in the planar view. In this case, the center of the third pixel opening PXO3 can be the third center C3. The radius of the third pixel opening PXO3 can be the third pixel radius x3.

[0109] In an embodiment, the third pixel radius X3 can be greater than each of the first pixel radius X1, the (2-1)th pixel radius X2a, and the (2-2)th pixel radius X2b. The first pixel radius X1 can be greater than the (2-1)th pixel radius X2a and the (2-2)th pixel radius X2b.

[0110] Reference Figure 7 Pixel PXL may include a light-blocking layer BM disposed on the pixel definition layer PDL. The light-blocking layer BM may include a first opening OPN1, a second opening OPN2, and a third opening OPN3.

[0111] The first opening OPN1 can be circular in the planar view. In this case, the center of the first opening OPN1 can correspond to the first center C1, which is the center of the first pixel opening PXO1. The radius of the first opening OPN1 can be a first opening radius Y1. In an embodiment, the first opening radius Y1 can be greater than the first pixel radius X1.

[0112] The second opening OPN2 may include the second-first opening OPN2a and the second-second opening OPN2b.

[0113] The second-first opening OPN2a can be circular in the planar view. In this case, the center of the second-first opening OPN2a can correspond to the second-first center C2a, which is the center of the second-first pixel opening PXO2a. The radius of the second-first opening OPN2a can be the second-first opening radius Y2a. In an embodiment, the second-first opening radius Y2a can be greater than the second-first pixel radius X2a.

[0114] The second-second opening OPN2b can be circular in the planar view. In this case, the center of the second-second opening OPN2b can correspond to the second-second center C2b, which is the center of the second-second pixel opening PXO2b. The radius of the second-second opening OPN2b can be the second-second opening radius Y2b. In an embodiment, the second-second opening radius Y2b can be greater than the second-second pixel radius X2b.

[0115] The third opening OPN3 can be circular in the planar view. In this case, the center of the third opening OPN3 can correspond to the third center C3, which is the center of the third pixel opening PXO3. The radius of the third opening OPN3 can be the third opening radius Y3. In an embodiment, the third opening radius Y3 can be smaller than the third pixel radius X3.

[0116] In an embodiment, the difference between the first opening radius Y1 of the first opening OPN1 and the first pixel radius X1 of the first pixel opening PXO1 can be substantially the same as the difference between the second-first opening radius Y2a of the second-first opening OPN2a and the second-first pixel radius X2a of the second-first pixel opening PXO2a, and can be substantially the same as the difference between the second-second opening radius Y2b of the second-second opening OPN2b and the second-second pixel radius X2b of the second-second pixel opening PXO2b.

[0117] Figure 8 It is along Figure 7 A sectional view taken along line I1-I1'. Figure 8 The image shows the first sub-pixel SP1 and the second-to-first sub-pixel SP2a.

[0118] Reference Figures 6 to 8The pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL, which are sequentially stacked on the third-party DR3.

[0119] The pixel circuit layer PCL may include a first sub-pixel circuit SPC1 and a second-to-first sub-pixel circuit SPC2a. The first sub-pixel circuit SPC1 may be configured as the sub-pixel circuit SPC of the first sub-pixel SP1 (see reference). Figure 2 The 2-1st sub-pixel circuit SPC2a can be set as the sub-pixel circuit SPC of the 2-1st sub-pixel SP2a (refer to...). Figure 2 ).

[0120] The display element layer (DPL) may include a via layer (VIA), a first anode electrode (AE1), a second-first anode electrode (AE2a), a pixel limiting layer (PDL), a first emitter layer (EL1), a second-first emitter layer (EL2a), a cathode electrode (CE), and a packaging layer (TFE).

[0121] The via layer VIA can be disposed on the pixel circuit layer PCL. The via layer VIA can have a single-layer structure or a multi-layer structure comprising inorganic and / or organic materials. In an embodiment, in the region where the first sub-pixel SP1 and the second-first sub-pixel SP2a are disposed, the upper surface of the via layer VIA can be substantially flat.

[0122] The first anode electrode AE1 can be disposed on the via layer VIA. The first anode electrode AE1 can be connected to the first sub-pixel circuit SPC1 through vias penetrating the via layer VIA and one or more insulating layers constituting the pixel circuit layer PCL. In an embodiment, the upper surface of the first anode electrode AE1 can be substantially flat.

[0123] The second-first anode electrode AE2a can be disposed on the via layer VIA. The second-first anode electrode AE2a can be connected to the second-first sub-pixel circuit SPC2a through vias penetrating the via layer VIA and one or more insulating layers constituting the pixel circuit layer PCL. In an embodiment, the upper surface of the second-first anode electrode AE2a can be substantially flat.

[0124] A pixel defining layer (PDL) may be disposed on the via layer (VIA), the first anode electrode AE1, and the second-first anode electrode AE2a. The PDL may include a first pixel opening (PXO1) exposing a portion of the first anode electrode AE1 and a second pixel opening (PXO2a) exposing a portion of the second-first anode electrode AE2a. The PDL may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In embodiments, the PDL may include an organic material. For example, the PDL may include an organic insulating material made of materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0125] The first emitting layer EL1 can be disposed on the first anode electrode AE1 in the first pixel opening PXO1. The first emitting layer EL1 may include an organic emitting material formed to generate red light.

[0126] The second-first emitting layer EL2a can be disposed on the second-first anode electrode AE2a within the second-first pixel opening PXO2a. The second-first emitting layer EL2a may include an organic emitting material formed to generate green light.

[0127] The cathode electrode CE may cover the pixel defining layer PDL, the first emitter layer EL1, and the second-first emitter layer EL2a. The cathode electrode CE may be electrically connected to... Figure 2 The second power voltage node VSSN. The cathode electrode CE can be constructed to be substantially transparent or translucent to meet a certain transmittance. For example, the cathode electrode CE can include at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0128] The encapsulation layer TFE can be disposed across the entire surface of the cathode electrode CE. The encapsulation layer TFE can be used to protect the component disposed under the encapsulation layer TFE from external moisture or gases. In an embodiment, the encapsulation layer TFE may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on a third-direction DR3.

[0129] An input sensing layer (ISL) may be disposed on a display element layer (DPL). The input sensing layer (ISL) may include a sensing electrode (YMTL). The sensing electrode (YMTL) may be used to sense external objects such as a user's hand or a pen. In an embodiment, the sensing electrode (YMTL) may be superimposed on a pixel definition layer (PDL), but may not be superimposed on a first pixel opening (PXO1) and a second-to-first pixel opening (PXO2a).

[0130] The light functional layer LFL may include a light blocking layer BM, a first color filter CF1, and a second-first color filter CF2a.

[0131] The light-blocking layer BM may include a first opening OPN1 and a second-first opening OPN2a. The light-blocking layer BM may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In one embodiment, the light-blocking layer BM may include a material substantially the same as that of the pixel defining layer PDL. In another embodiment, the light-blocking layer BM may be configured as a multilayer structure formed by stacking at least two color filters. For example, the light-blocking layer BM between the first color filter CF1 and the second-first color filter CF2a may be configured as a multilayer structure formed by stacking the first color filter CF1 and the second-first color filter CF2a. In one embodiment, the light-blocking layer BM may be stacked with a sensing electrode YMTL.

[0132] A first color filter CF1 can be disposed on the input sensing layer ISL within the first opening OPN1. The first color filter CF1 selectively allows red light to pass through. For example, the first color filter CF1 can be a red color filter.

[0133] The second-first color filter CF2a can be disposed on the input sensing layer ISL within the second-first opening OPN2a. The second-first color filter CF2a allows green light to pass selectively. For example, the second-first color filter CF2a can be a green color filter.

[0134] Figure 9 It is along Figure 7 A sectional view taken by line I2-I2'. Figure 9 The image shows the second-to-second sub-pixel SP2b and the third sub-pixel SP3.

[0135] Reference Figure 6 , Figure 7 and Figure 9 The pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL, which are sequentially stacked on the third-party DR3.

[0136] The pixel circuit layer PCL may include a second-to-second sub-pixel circuit SPC2b and a third sub-pixel circuit SPC3. The second-to-second sub-pixel circuit SPC2b may be configured as the sub-pixel circuit SPC of the second-to-second sub-pixel SP2b (see reference). Figure 2 The third sub-pixel circuit SPC3 can be configured as the sub-pixel circuit SPC of the third sub-pixel SP3 (see reference). Figure 2 ).

[0137] The display element layer (DPL) may include a via layer (VIA), a second-second anode electrode (AE2b), a third anode electrode (AE3), a pixel limiting layer (PDL), a second-second emitter layer (EL2b), a third emitter layer (EL3), a cathode electrode (CE), and a packaging layer (TFE).

[0138] In an embodiment, the upper surface of the via layer VIA can be substantially flat in the region where the second-second sub-pixel SP2b is located. Unlike the above, the upper surface of the via layer VIA may not be substantially flat in the region where the third sub-pixel SP3 is located. In the region where the third sub-pixel SP3 is located, the via layer VIA may include a recess GR recessed in the direction opposite to the third-direction DR3. In an embodiment, the recess GR may be stacked with the third pixel opening PXO3. The recess GR may be formed as part of the upper surface of the pixel circuit layer PCL.

[0139] The second-2 anode electrode AE2b can be disposed on the via layer VIA. The second-2 anode electrode AE2b can be connected to the second-2 sub-pixel circuit SPC2b through vias penetrating the via layer VIA and one or more insulating layers constituting the pixel circuit layer PCL. In an embodiment, the upper surface of the second-2 anode electrode AE2b can be substantially flat.

[0140] The third anode electrode AE3 can be disposed on the via layer VIA. The third anode electrode AE3 can be connected to the third sub-pixel circuit SPC3 through vias penetrating the via layer VIA and one or more insulating layers constituting the pixel circuit layer PCL. A portion of the third anode electrode AE3 can be positioned in the recess GR. Therefore, a portion of the third anode electrode AE3 can be configured as a sloped surface. (Refer to the following...) Figure 10 To describe the details of the aforementioned content.

[0141] The pixel definition layer (PDL) can be disposed on the via layer (VIA), the second-second anode electrode (AE2b), and the third anode electrode (AE3). The pixel definition layer (PDL) may include a second-second pixel opening (PXO2b) that exposes a portion of the second-second anode electrode (AE2b) and a third pixel opening (PXO3) that exposes a portion of the third anode electrode (AE3).

[0142] The second-2 emitting layer EL2b can be disposed on the second-2 anode electrode AE2b within the second-2 pixel opening PXO2b. The second-2 emitting layer EL2b may comprise an organic emitting material formed to generate green light. In an embodiment, the second-2 emitting layer EL2b may comprise a material substantially the same as the second-1 emitting layer EL2a.

[0143] The third emitting layer EL3 can be disposed on the third anode electrode AE3 within the third pixel opening PXO3. The third emitting layer EL3 may include an organic emitting material formed to generate blue light.

[0144] The cathode electrode CE can cover the pixel limiting layer PDL, the second-second emitter layer EL2b, and the third emitter layer EL3. The encapsulation layer TFE can be disposed across the entire surface of the cathode electrode CE.

[0145] The input sensing layer ISL can be disposed on the display element layer DPL and can include a sensing electrode YMTL. In an embodiment, the sensing electrode YMTL can be stacked with the pixel defining layer PDL, but can be separate from the second-second pixel opening PXO2b and the third pixel opening PXO3.

[0146] The light functional layer LFL may include a light blocking layer BM, a second-second color filter CF2b, and a third color filter CF3.

[0147] The light-blocking layer BM may include a second-second opening OPN2b and a third opening OPN3. The light-blocking layer BM may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In an embodiment, the light-blocking layer BM between the second-second color filter CF2b and the third color filter CF3 may be configured as a multilayer structure formed by stacking the second-second color filter CF2b and the third color filter CF3. In an embodiment, the light-blocking layer BM may be stacked with the sensing electrode YMTL.

[0148] The second-second color filter CF2b can be disposed on the input sensing layer ISL within the second-second opening OPN2b. The second-second color filter CF2b allows green light to pass selectively. For example, the second-second color filter CF2b can be a green color filter.

[0149] A third color filter CF3 can be disposed on the input sensing layer ISL within the third opening OPN3. The third color filter CF3 allows blue light to pass through selectively. For example, the third color filter CF3 can be a blue color filter.

[0150] Figure 10 It is shown Figure 9 A magnified planar view of the third sub-pixel region AR_SP3.

[0151] Reference Figure 6 , Figure 7 , Figure 9 and Figure 10 The image shows a magnified view of the third sub-pixel region AR_SP3.

[0152] In an embodiment, a portion of the third anode electrode AE3 may be disposed in the groove GR in the region overlapping with the third pixel opening PXO3. Therefore, as seen in the plan view, the third anode electrode AE3 may include a flat portion S1_AE3 and a sloping portion S2_AE3 surrounding the flat portion S1_AE3. For example, the flat portion S1_AE3 may be circular in the plan view. The center of the flat portion S1_AE3 (i.e., the center of the circle) may be... Figure 6 The third center C3. The slanted portion S2_AE3 can also be circular in the planar view. In this case, in the planar view, the slanted portion S2_AE3 can surround the flat portion S1_AE3, and the edge of the slanted portion S2_AE3 furthest from the base SUB can coincide with the edge of the third pixel opening PXO3. As used here, A and B “coinciding” means that A and B are aligned in the third direction so that they appear as a point or a line in the planar view.

[0153] In an embodiment, the acute angle ANG formed by the upper surface of the inclined portion S2_AE3 relative to a plane parallel to the upper surface of the flat portion S1_AE3 can be about 15 degrees or greater and about 45 degrees or less. In an embodiment, in a cross-sectional view, the distance T_GR between the upper surface of the flat portion S1_AE3 and the upper surface of the third anode electrode AE3 stacked with the pixel defining layer PDL on the third direction DR3 can be about 0.5 micrometers or greater and about 3 micrometers or less.

[0154] In this configuration, the third emitting layer EL3, disposed on the third anode electrode AE3 within the third pixel opening PXO3, can have contours corresponding to the flat portion S1_AE3 and the inclined portion S2_AE3 in a cross-sectional view. In other words, the third emitting layer EL3 can have an inclined surface corresponding to the inclined portion S2_AE3 and a flat surface corresponding to the flat portion S1_AE3. Because the third emitting layer EL3 has an inclined surface, the lateral visibility of light generated from the third sub-pixel SP3 can be further improved.

[0155] In an embodiment, the orthogonal projection of the edge EG_OPN3 of the third opening OPN3 onto the third direction DR3 can be located on the inclined portion S2_AE3. In this case, the distance W in the first direction DR1 between the edge EG_OPN3 of the third opening OPN3 and the edge EG3 of the flat portion S1_AE3 can be, for example, about 2 micrometers.

[0156] Refer again Figures 1 to 10 In a display device DD including pixel PXL according to an embodiment of the present disclosure, unlike the first sub-pixel SP1 and the second sub-pixel SP2, the third aperture radius Y3 in the third sub-pixel SP3 can be smaller than the third pixel radius X3. Therefore, as Figure 7 As shown, this ensures that the light-blocking layer BM has a sufficient width W_BM in the first direction DR1 between the second-2 center C2b and the third center C3 (see reference). Figure 9 Similarly, it can be ensured that the light-blocking layer BM has sufficient width in the second direction DR2 between the second-1 center C2a and the third center C3. In this case, if the pixels per inch (ppi) of the pixel PXL increases (i.e., if the resolution is higher), sufficient process margin can be ensured during the formation of the light-blocking layer BM, which can reduce the difficulty of the process of forming the light-blocking layer BM. In addition, due to the light-blocking layer BM, external light reflected from the cathode electrode CE set on the inclined portion S2_AE3 can be effectively blocked, which can enhance the visibility of the cutoff state.

[0157] In the above embodiment, the tilted portion S2_AE3 of the third anode electrode AE3 can prevent excessive blocking of light emitted from the third emitting layer EL3 due to the relatively small third opening radius Y3. More specifically, since the third anode electrode AE3 includes the tilted portion S2_AE3, the third emitting layer EL3 can have a tilted surface corresponding to the tilted portion S2_AE3. Light emitted from the tilted surface of the third emitting layer EL3 can pass sufficiently through the third opening OPN3, which has a relatively small third opening radius Y3. In other words, the light output efficiency of the third sub-pixel SP3 can be improved.

[0158] Figure 11 and Figure 12 It is used to describe including Figure 3 A plan view of another embodiment of any one of the pixels PXL in the display panel DP.

[0159] Reference Figure 11 Pixel PXL' may include subpixels SP1', SP2a', SP2b', and SP3'. The first subpixel SP1' is configured to generate red light, the second subpixel SP2' (which includes subpixels SP2a' and SP2b') is configured to generate green light, and the third subpixel SP3' is configured to generate blue light.

[0160] The first sub-pixel SP1' may include a first anode electrode AE1'. The first anode electrode AE1' may be configured to be connected to the sub-pixel circuit SPC (see reference) of the first sub-pixel SP1'. Figure 2 The anode electrode AE ​​of ) (refer to Figure 2 ).

[0161] The second sub-pixel SP2' may include a second anode electrode AE2' spaced apart from the first anode electrode AE1'. The second anode electrode AE2' may be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the second sub-pixel SP2'.

[0162] In an embodiment, the second sub-pixel SP2' may include a second-first sub-pixel SP2a' and a second-second sub-pixel SP2b'. The second-first sub-pixel SP2a' may include a second-first anode electrode AE2a'. The second-first anode electrode AE2a' may be configured as an anode electrode AE ​​connected to the sub-pixel circuit SPC of the second-first sub-pixel SP2a'. The second-second sub-pixel SP2b' may include a second-second anode electrode AE2b' spaced apart from the second-first anode electrode AE2a'. The second-second anode electrode AE2b' may be configured as an anode electrode AE ​​connected to the sub-pixel circuit SPC of the second-second sub-pixel SP2b'.

[0163] The third sub-pixel SP3' may include a third anode electrode AE3' spaced apart from the first anode electrode AE1' and the second anode electrode AE2'. The third anode electrode AE3' may be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the third sub-pixel SP3'.

[0164] Pixel PXL' may include a pixel defining layer PDL'. The pixel defining layer PDL' may include a first pixel opening PXO1', a second pixel opening PXO2', and a third pixel opening PXO3' that respectively expose a portion of a first anode electrode AE1', a portion of a second anode electrode AE2', and a portion of a third anode electrode AE3'.

[0165] The first pixel opening PXO1' can expose a portion of the first anode electrode AE1'. The first pixel opening PXO1' can be circular in the planar view. In this case, the center of the first pixel opening PXO1' can be a first center C1'. The radius of the first pixel opening PXO1' can be a first pixel radius X1'.

[0166] The second pixel opening PXO2' may include the second-first pixel opening PXO2a' and the second-second pixel opening PXO2b'.

[0167] The 2-1 pixel opening PXO2a' can expose a portion of the 2-1 anode electrode AE2a'. The 2-1 pixel opening PXO2a' can be circular in the planar view. In this case, the center of the 2-1 pixel opening PXO2a' can be the 2-1 center C2a'. The radius of the 2-1 pixel opening PXO2a' can be the 2-1 pixel radius X2a'.

[0168] The 2-2 pixel opening PXO2b' can expose a portion of the 2-2 anode electrode AE2b'. The 2-2 pixel opening PXO2b' can be circular in the planar view. In this case, the center of the 2-2 pixel opening PXO2b' can be the 2-2 center C2b'. The radius of the 2-2 pixel opening PXO2b' can be the 2-2 pixel radius X2b'.

[0169] In an embodiment, the radius of the second-1st pixel X2a' can be substantially the same as the radius of the second-2nd pixel X2b'.

[0170] The third pixel opening PXO3' can expose a portion of the third anode electrode AE3'. The third pixel opening PXO3' can be circular in the planar view. In this case, the center of the third pixel opening PXO3' can be the third center C3'. The radius of the third pixel opening PXO3' can be the third pixel radius x 3'.

[0171] In this embodiment, the radius of the third pixel X3' can be greater than the radius of the first pixel X1', greater than the radius of the (2-1)th pixel X2a', and greater than the radius of the (2-2)th pixel X2b'. The radius of the first pixel X1' can be greater than the radius of the (2-1)th pixel X2a' and greater than the radius of the (2-2)th pixel X2b'.

[0172] Reference Figure 12 Pixel PXL' may include a light-blocking layer BM' disposed on pixel definition layer PDL'. Light-blocking layer BM' may include a first opening OPN1', a second opening OPN2', and a third opening OPN3'.

[0173] The first opening OPN1' can be circular in the planar view. In this case, the center of the first opening OPN1' can correspond to the first center C1', which is the center of the first pixel opening PXO1'. The radius of the first opening OPN1' can be the first opening radius Y1'. In an embodiment, the first opening radius Y1' can be smaller than the first pixel radius X1'.

[0174] The second opening OPN2' may include the second-first opening OPN2a' and the second-second opening OPN2b'.

[0175] The second-first opening OPN2a' can be circular in the planar view. In this case, the center of the second-first opening OPN2a' can correspond to the second-first center C2a', which is the center of the second-first pixel opening PXO2a'. The radius of the second-first opening OPN2a' can be the second-first opening radius Y2a'. In an embodiment, the second-first opening radius Y2a' can be smaller than the second-first pixel radius X2a'.

[0176] The second-second opening OPN2b' can be circular in the planar view. In this case, the center of the second-second opening OPN2b' can correspond to the second-second center C2b', which is the center of the second-second pixel opening PXO2b'. The radius of the second-second opening OPN2b' can be the second-second opening radius Y2b'. In an embodiment, the second-second opening radius Y2b' can be smaller than the second-second pixel radius X2b'.

[0177] The third opening OPN3' can be circular in the planar view. In this case, the center of the third opening OPN3' can correspond to the third center C3', which is the center of the third pixel opening PXO3'. The radius of the third opening OPN3' can be the third opening radius Y3'. In an embodiment, the third opening radius Y3' can be smaller than the third pixel radius X3'.

[0178] In this embodiment, the differences between the first pixel radius X1' of the first pixel opening PXO1' and the first opening radius Y1' of the first opening OPN1', the differences between the second-first pixel radius X2a' of the second-first pixel opening PXO2a' and the second-first opening radius Y2a' of the second-first pixel opening OPN2a', and the differences between the third pixel radius X3' of the third pixel opening PXO3' and the third opening radius Y3' of the third opening OPN3' can be different from each other. Here, the difference between the second-first pixel radius X2a' of the second-first pixel opening PXO2a' and the second-first opening radius Y2a' of the second-first pixel opening OPN2a' can be substantially the same as the difference between the second-second pixel radius X2b' of the second-second pixel opening PXO2b' and the second-second opening radius Y2b' of the second-second pixel opening OPN2b'.

[0179] Figure 13 It is along Figure 12 A sectional view taken along line I3-I3'. Figure 13 The image shows the first sub-pixel SP1' and the second-to-first sub-pixel SP2a'.

[0180] Reference Figures 11 to 13 Pixel PXL' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL, which are sequentially stacked on the third-party DR3.

[0181] The pixel circuit layer PCL may include a first sub-pixel circuit SPC1' and a second-to-first sub-pixel circuit SPC2a'. The first sub-pixel circuit SPC1' may be configured as the sub-pixel circuit SPC of the first sub-pixel SP1' (see reference). Figure 2 The 2-1st sub-pixel circuit SPC2a' can be set as the sub-pixel circuit SPC of the 2-1st sub-pixel SP2a' (refer to...). Figure 2 ).

[0182] The display element layer (DPL) may include a via layer (VIA'), a first anode electrode (AE1'), a second-first anode electrode (AE2a'), a pixel limiting layer (PDL'), a first emission layer (EL1'), a second-first emission layer (EL2a'), a cathode electrode (CE'), and an encapsulation layer (TFE').

[0183] A via layer VIA' can be disposed on the pixel circuit layer PCL. The via layer VIA' can have a single-layer or multi-layer structure comprising inorganic and / or organic materials. In an embodiment, in the region where the first sub-pixel SP1' is disposed, the via layer VIA' can include a first recess GR1' recessed in a direction opposite to the third direction DR3. The first recess GR1' can be superimposed on the first pixel opening PXO1'. In an embodiment, in the region where the second-first sub-pixel SP2a' is disposed, the via layer VIA' can include a second-first recess GR2a' recessed in a direction opposite to the third direction DR3. The second-first recess GR2a' can be superimposed on the second-first pixel opening PXO2a'.

[0184] The first anode electrode AE1' can be disposed on the via layer VIA'. The first anode electrode AE1' can be connected to the first sub-pixel circuit SPC1' through vias penetrating the via layer VIA' and one or more insulating layers constituting the pixel circuit layer PCL. A portion of the first anode electrode AE1' can be positioned in the first recess GR1'. Therefore, a portion of the first anode electrode AE1' can be configured as an inclined surface. (Refer to the following...) Figure 14 To describe the details of the aforementioned content.

[0185] The 2-1 anode electrode AE2a' can be disposed on the via layer VIA'. The 2-1 anode electrode AE2a' can be connected to the 2-1 sub-pixel circuit SPC2a' through through-holes penetrating the via layer VIA' and one or more insulating layers constituting the pixel circuit layer PCL. A portion of the 2-1 anode electrode AE2a' can be positioned in the 2-1 recess GR2a'. Therefore, a portion of the 2-1 anode electrode AE2a' can be configured as a sloped surface. (Refer to the following...) Figure 15 To describe the details of the aforementioned content.

[0186] A pixel defining layer PDL' may be disposed on a via layer VIA', a first anode electrode AE1', and a second-first anode electrode AE2a'. The pixel defining layer PDL' may include a first pixel opening PXO1' exposing a portion of the first anode electrode AE1' and a second-first pixel opening PXO2a' exposing a portion of the second-first anode electrode AE2a'. The pixel defining layer PDL' may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In embodiments, the pixel defining layer PDL' may include an organic material. For example, the pixel defining layer PDL' may include an organic insulating material made of materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0187] The first emitting layer EL1' can be disposed on the first anode electrode AE1' within the first pixel opening PXO1'. The first emitting layer EL1' may include an organic emitting material formed to generate red light.

[0188] The second-first emitting layer EL2a' can be disposed on the second-first anode electrode AE2a' within the second-first pixel opening PXO2a'. The second-first emitting layer EL2a' may include an organic emitting material formed to generate green light.

[0189] The cathode electrode CE' may cover the pixel-defining layer PDL', the first emission layer EL1', and the second-first emission layer EL2a'. The cathode electrode CE' may be electrically connected to... Figure 2 The second power voltage node VSSN. The cathode electrode CE' can be constructed to be substantially transparent or translucent to meet a certain transmittance. For example, the cathode electrode CE' can include at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0190] The encapsulation layer TFE' can be disposed across the entire surface of the cathode electrode CE'. The encapsulation layer TFE' can be used to protect the components disposed under the encapsulation layer TFE' from external moisture or gases. In an embodiment, the encapsulation layer TFE' may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on a third-direction DR3.

[0191] An input sensing layer (ISL) may be disposed on a display element layer (DPL). The input sensing layer (ISL) may include sensing electrodes (YMTL'). The sensing electrodes (YMTL') may be used to sense external objects such as a user's hand or a pen. In an embodiment, the sensing electrodes (YMTL') may be superimposed on a pixel definition layer (PDL'), but may not be superimposed on the first pixel opening (PXO1') and the second-to-first pixel opening (PXO2a').

[0192] The light functional layer LFL may include a light blocking layer BM', a first color filter CF1', and a second-first color filter CF2a'.

[0193] The light-blocking layer BM' may include a first opening OPN1' and a second opening OPN2'. The light-blocking layer BM' may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In one embodiment, the light-blocking layer BM' may include a material substantially the same as that of the pixel defining layer PDL'. In another embodiment, the light-blocking layer BM' may be configured as a multilayer structure formed by stacking at least two color filters. For example, the light-blocking layer BM' between the first color filter CF1' and the second-first color filter CF2a' may be configured as a multilayer structure formed by stacking the first color filter CF1' and the second-first color filter CF2a'. In one embodiment, the light-blocking layer BM' may be stacked with a sensing electrode YMTL'.

[0194] A first color filter CF1' can be disposed on the input sensing layer ISL within the first opening OPN1'. The first color filter CF1' allows red light to pass through selectively. For example, the first color filter CF1' can be a red color filter.

[0195] The second-first color filter CF2a' can be disposed on the input sensing layer ISL within the second-first opening OPN2a'. The second-first color filter CF2a' allows green light to pass through selectively. For example, the second-first color filter CF2a' can be a green color filter.

[0196] Figure 14 It is shown Figure 13 A magnified planar view of the first sub-pixel region AR_SP1'.

[0197] Reference Figures 11 to 14 This shows a magnified view of the first sub-pixel region AR_SP1'.

[0198] In an embodiment, a portion of the first anode electrode AE1' may be disposed in the first groove GR1' in the region overlapping with the first pixel opening PXO1' in a planar view. Therefore, in a planar view, the first anode electrode AE1' may include a first flat portion S1_AE1' and a first inclined portion S2_AE1' surrounding the first flat portion S1_AE1'. For example, the first flat portion S1_AE1' may be circular in a planar view. The center of the first flat portion S1_AE1' (i.e., the center of the circle) may be... Figure 11The first center C1' in the first planar view. The first inclined portion S2_AE1' can also be circular in the planar view. In this case, in the planar view, the first inclined portion S2_AE1' can surround the first flat portion S1_AE1', and the edge of the first inclined portion S2_AE1' farthest from the base SUB can coincide with the edge of the first pixel opening PXO1'.

[0199] In an embodiment, the first acute angle ANG1' formed by the upper surface of the first inclined portion S2_AE1' relative to a plane parallel to the upper surface of the first flat portion S1_AE1' can be about 15 degrees or greater and about 45 degrees or less. In an embodiment, in a cross-sectional view, the first distance T_GR1' between the upper surface of the first flat portion S1_AE1' and the upper surface of the first anode electrode AE1' superimposed on the pixel defining layer PDL' in the third direction DR3 can be about 0.5 micrometers or greater and about 3 micrometers or less.

[0200] In this case, the first emitting layer EL1' disposed on the first anode electrode AE1' in the first pixel opening PXO1' can have a profile in cross-sectional view corresponding to the first flat portion S1_AE1' and the first inclined portion S2_AE1'. In other words, the first emitting layer EL1' can have an inclined surface corresponding to the first inclined portion S2_AE1' and a flat surface corresponding to the first flat portion S1_AE1'. Since the first emitting layer EL1' has an inclined surface, the lateral visibility of light generated from the first sub-pixel SP1' can be further improved.

[0201] In an embodiment, the orthogonal projection of the edge EG_OPN1' of the first opening OPN1' onto the third direction DR3 can lie on the first inclined portion S2_AE1'. In this case, the distance W1' between the edge EG_OPN1' of the first opening OPN1' and the edge EG1' of the first flat portion S1_AE1' on the first direction DR1 can be, for example, about 3 micrometers.

[0202] Since the first sub-pixel SP1' is constructed as described above, sufficient process margin can be ensured during the formation of the light-blocking layer BM', which reduces the difficulty of forming the light-blocking layer BM'. Furthermore, due to the light-blocking layer BM', external light reflected from the cathode electrode CE' disposed on the first inclined portion S2_AE1' can be effectively blocked, which enhances the visibility of the cutoff state. Moreover, due to the inclined surfaces of the first inclined portion S2_AE1' of the first anode electrode AE1' and the first emitting layer EL1' corresponding to the first inclined portion S2_AE1', light emitted from the first emitting layer EL1' can pass sufficiently through the first opening OPN1'. In other words, the light output efficiency of the first sub-pixel SP1' can be improved.

[0203] Figure 15 It is shown Figure 13 A magnified planar view of the 2-1 sub-pixel region AR_SP2a'.

[0204] Reference Figures 11 to 13 as well as Figure 15 The image shown is an enlarged view of the 2-1 sub-pixel region AR_SP2a'.

[0205] In an embodiment, a portion of the second-1 anode electrode AE2a' may be disposed in the second-1 groove GR2a' in the region overlapping with the second-1 pixel opening PXO2a'. Therefore, in a planar view, the second-1 anode electrode AE2a' may include a second-1 flat portion S1_AE2a' and a second-1 inclined portion S2_AE2a' surrounding the second-1 flat portion S1_AE2a'. For example, the second-1 flat portion S1_AE2a' may be circular in a planar view. The center of the second-1 flat portion S1_AE2a' (i.e., the center of the circle) may be... Figure 11 The second-1 center C2a' in the diagram. The second-1 inclined portion S2_AE2a' can also be circular in the planar view. In this case, in the planar view, the second-1 inclined portion S2_AE2a' can surround the second-1 flat portion S1_AE2a', and the edge of the second-1 inclined portion S2_AE2a' farthest from the base SUB can coincide with the edge of the second-1 pixel opening PXO2a'.

[0206] In an embodiment, the second-first acute angle ANG2a' formed by the upper surface of the second-first inclined portion S2_AE2a' relative to a plane parallel to the upper surface of the second-first flat portion S1_AE2a' can be approximately 15 degrees or greater and approximately 45 degrees or less. In an embodiment, the size of the second-first acute angle ANG2a' can be different from the first acute angle ANG1' (refer to...). Figure 14 ) size.

[0207] In an embodiment, in a cross-sectional view, the second-first distance T_GR2a' in the third direction DR3 between the upper surface of the second-1 flat portion S1_AE2a' and the upper surface of the second-1 anode electrode AE2a' superimposed on the pixel defining layer PDL' can be about 0.5 micrometers or greater and about 3 micrometers or less. In an embodiment, the second-first distance T_GR2a' can be different from the first distance T_GR1' (refer to...). Figure 14 ).

[0208] In this case, in the cross-sectional view, the second-first emitting layer EL2a' disposed on the second-first anode electrode AE2a' in the second-first pixel opening PXO2a' can have a contour corresponding to the second-first flat portion S1_AE2a' and the second-first tilted portion S2_AE2a'. In other words, the second-first emitting layer EL2a' can have a tilted surface corresponding to the second-first tilted portion S2_AE2a' and a flat surface corresponding to the second-first flat portion S1_AE2a'. Since the second-first emitting layer EL2a' has a tilted surface, the lateral visibility of the light generated from the second-first sub-pixel SP2a' can be further improved.

[0209] In an embodiment, the orthogonal projection of the edge EG_OPN2a' of the second-1 opening OPN2a' onto the third direction DR3 can lie on the second-1 inclined portion S2_AE2a'. In this case, the distance W2a' between the edge EG_OPN2a' of the second-1 opening OPN2a' and the edge EG2a' of the second-1 flat portion S1_AE2a' on the first direction DR1 can be, for example, about 3.5 micrometers.

[0210] Since the 2-1 sub-pixel SP2a' is constructed as described above, sufficient process margin can be ensured during the formation of the light-blocking layer BM', which reduces the difficulty of forming the light-blocking layer BM'. Furthermore, due to the light-blocking layer BM', external light reflected from the cathode electrode CE' disposed on the 2-1 inclined portion S2_AE2a' can be effectively blocked, which enhances the visibility in the cutoff state. Moreover, due to the inclined surfaces of the 2-1 inclined portion S2_AE2a' of the 2-1 anode electrode AE2a' and the 2-1 emitting layer EL2a' corresponding to the 2-1 inclined portion S2_AE2a', light emitted from the 2-1 emitting layer EL2a' can pass sufficiently through the 2-1 opening OPN2a'. In other words, the light output efficiency of the 2-1 sub-pixel SP2a' can be improved.

[0211] Figure 16 It is along Figure 12 A sectional view taken along line I4-I4'. Figure 16 The image shows the second-to-second sub-pixel SP2b' and the third sub-pixel SP3'.

[0212] Reference Figure 11 , Figure 12 and Figure 16 Pixel PXL' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL, which are sequentially stacked on the third-party DR3.

[0213] The pixel circuit layer PCL may include a second-second sub-pixel circuit SPC2b' and a third sub-pixel circuit SPC3'. The second-second sub-pixel circuit SPC2b' may be configured as the sub-pixel circuit SPC of the second-second sub-pixel SP2b' (see reference). Figure 2 The third sub-pixel circuit SPC3' can be set as the sub-pixel circuit SPC of the third sub-pixel SP3' (see reference). Figure 2 ).

[0214] The display element layer (DPL) may include a via layer (VIA'), a second-second anode electrode (AE2b'), a third anode electrode (AE3'), a pixel limiting layer (PDL'), a second-second emission layer (EL2b'), a third emission layer (EL3'), a cathode electrode (CE'), and an encapsulation layer (TFE').

[0215] In an embodiment, in the region where the second-2nd sub-pixel SP2b' is provided, the via layer VIA' may include a second-2nd recess GR2b' recessed in a direction opposite to the third-direction DR3. The second-2nd recess GR2b' may be aligned with the second-1st recess GR2a' (see reference). Figure 13 They are constructed in basically the same way.

[0216] In an embodiment, in the region where the third sub-pixel SP3' is located, the via layer VIA' may include a third recess GR3' recessed in a direction opposite to the third-direction DR3. In an embodiment, the third recess GR3' may be stacked with the third pixel opening PXO3'. The third recess GR3' may be formed as part of the upper surface of the pixel circuit layer PCL.

[0217] The 2-2 anode electrode AE2b' can be disposed on the via layer VIA'. The 2-2 anode electrode AE2b' can be connected to the 2-2 sub-pixel circuit SPC2b' through vias penetrating the via layer VIA' and one or more insulating layers constituting the pixel circuit layer PCL. A portion of the 2-2 anode electrode AE2b' can be positioned in the 2-2 recess GR2b'. Therefore, a portion of the 2-2 anode electrode AE2b' can be configured as a sloped surface. (Refer to the following...) Figure 17 To describe the details of the aforementioned content.

[0218] The third anode electrode AE3' can be disposed on the via layer VIA'. The third anode electrode AE3' can be connected to the third sub-pixel circuit SPC3' through vias penetrating the via layer VIA' and one or more insulating layers constituting the pixel circuit layer PCL. A portion of the third anode electrode AE3' can be positioned in the third recess GR3'. Therefore, a portion of the third anode electrode AE3' can be configured as an inclined surface. (Refer to the following...) Figure 18 To describe the details of the aforementioned content.

[0219] The pixel defining layer PDL' can be disposed on the via layer VIA', the second-second anode electrode AE2b', and the third anode electrode AE3'. The pixel defining layer PDL' may include a second-second pixel opening PXO2b' that exposes a portion of the second-second anode electrode AE2b' and a third pixel opening PXO3' that exposes a portion of the third anode electrode AE3'.

[0220] The second-2 emitting layer EL2b' can be disposed on the second-2 anode electrode AE2b' within the second-2 pixel opening PXO2b'. The second-2 emitting layer EL2b' may include an organic emitting material formed to generate green light. In an embodiment, the second-2 emitting layer EL2b' may include a material substantially the same as that of the second-1 emitting layer EL2a'.

[0221] The third emitting layer EL3' can be disposed on the third anode electrode AE3' within the third pixel opening PXO3'. The third emitting layer EL3' may include an organic emitting material formed to generate blue light.

[0222] The cathode electrode CE' may cover the pixel limiting layer PDL', the second-second emission layer EL2b', and the third emission layer EL3'. The encapsulation layer TFE' may be disposed across the entire surface of the cathode electrode CE'.

[0223] The light functional layer LFL may include a light blocking layer BM', a second-second color filter CF2b', and a third color filter CF3'.

[0224] The light-blocking layer BM' may include a second-second opening OPN2b' and a third opening OPN3'. The light-blocking layer BM' may include a light-blocking material and may be used to prevent light mixing between adjacent sub-pixels. In an embodiment, the light-blocking layer BM' between the second-second color filter CF2b' and the third color filter CF3' may be configured as a multilayer structure formed by stacking the second-second color filter CF2b' and the third color filter CF3'. In an embodiment, the light-blocking layer BM' may be stacked with the sensing electrode YMTL'.

[0225] The second-second color filter CF2b' can be disposed on the input sensing layer ISL within the second-second opening OPN2b'. The second-second color filter CF2b' allows green light to pass selectively. For example, the second-second color filter CF2b' can be a green color filter.

[0226] A third color filter CF3' can be disposed on the input sensing layer ISL within the third opening OPN3'. The third color filter CF3' allows blue light to pass through selectively. For example, the third color filter CF3' can be a blue color filter.

[0227] Figure 17 It is shown Figure 16 An enlarged cross-sectional view of the 2nd-2nd sub-pixel region AR_SP2b'.

[0228] Reference Figure 11 , Figure 12 , Figure 16 and Figure 17 The image shows a magnified view of the 2-2 sub-pixel region AR_SP2b'.

[0229] In an embodiment, a portion of the second-2 anode electrode AE2b' may be disposed in the second-2 recess GR2b' in the region overlapping with the second-2 pixel opening PXO2b'. Therefore, the second-2 anode electrode AE2b' may include a second-2 flat portion S1_AE2b' and a second-2 inclined portion S2_AE2b' surrounding the second-2 flat portion S1_AE2b'. For example, the second-2 flat portion S1_AE2b' may be circular in a planar view. The center of the second-2 flat portion S1_AE2b' (i.e., the center of the circle) may be... Figure 11 The 2-2 center C2b' in the diagram. The 2-2 inclined portion S2_AE2b' can also be circular in the planar view. In this case, in the planar view, the 2-2 inclined portion S2_AE2b' can surround the 2-2 flat portion S1_AE2b', and the edge of the 2-2 inclined portion S2_AE2b' farthest from the base SUB can coincide with the edge of the 2-2 pixel opening PXO2b'.

[0230] In an embodiment, the second acute angle ANG2b' formed by the upper surface of the second-2 inclined portion S2_AE2b' relative to a plane parallel to the upper surface of the second-2 flat portion S1_AE2b' can be approximately 15 degrees or greater and approximately 45 degrees or less. In an embodiment, the size of the second acute angle ANG2b' can be the same as that of the second acute angle ANG2a' (refer to...). Figure 15 The sizes are basically the same.

[0231] In an embodiment, in a cross-sectional view, the second-2 distance T_GR2b' between the upper surface of the second-2 flat portion S1_AE2b' and the upper surface of the second-2 anode electrode AE2b' superimposed on the pixel defining layer PDL' in the third direction DR3 can be about 0.5 micrometers or greater and about 3 micrometers or less. In an embodiment, the second-2 distance T_GR2b' can be the same as the second-1 distance T_GR2a' (refer to...). Figure 15 They are basically the same.

[0232] In this case, in the cross-sectional view, the second-second emitting layer EL2b' disposed on the second-second anode electrode AE2b' in the second-second pixel opening PXO2b' can have a contour corresponding to the second-second flat portion S1_AE2b' and the second-second tilted portion S2_AE2b'. In other words, the second-second emitting layer EL2b' can have a tilted surface corresponding to the second-second tilted portion S2_AE2b' and a flat surface corresponding to the second-second flat portion S1_AE2b'. Since the second-second emitting layer EL2b' has a tilted surface, the lateral visibility of the light generated from the second-second sub-pixel SP2b' can be further improved.

[0233] In an embodiment, the orthogonal projection of the edge EG_OPN2b' of the second-2 opening OPN2b' onto the third direction DR3 can lie on the second-2 inclined portion S2_AE2b'. In this case, the distance W2b' between the edge EG_OPN2b' of the second-2 opening OPN2b' and the edge EG2b' of the second-2 flat portion S1_AE2b' on the first direction DR1 can be, for example, about 3.5 micrometers.

[0234] Since the 2-2 sub-pixel SP2b' is constructed as described above, sufficient process margin can be ensured during the formation of the light-blocking layer BM', which reduces the difficulty of forming the light-blocking layer BM'. Furthermore, due to the light-blocking layer BM', external light reflected from the cathode electrode CE' disposed on the 2-2 inclined portion S2_AE2b' can be effectively blocked, which enhances the visibility in the cutoff state. Moreover, due to the inclined surfaces of the 2-2 inclined portion S2_AE2b' of the 2-2 anode electrode AE2b' and the 2-2 emitting layer EL2b' corresponding to the 2-2 inclined portion S2_AE2b', light emitted from the 2-2 emitting layer EL2b' can pass sufficiently through the 2-2 opening OPN2b'. In other words, the light output efficiency of the 2-2 sub-pixel SP2b' can be improved.

[0235] Figure 18 It is shown Figure 16 An enlarged cross-sectional view of the third sub-pixel region AR_SP3'.

[0236] Reference Figure 11 , Figure 12 , Figure 16 and Figure 18 The image shows a magnified view of the third sub-pixel region AR_SP3'.

[0237] In an embodiment, a portion of the third anode electrode AE3' may be disposed in the third recess GR3' in the region overlapping with the third pixel opening PXO3'. Therefore, in a planar view, the third anode electrode AE3' may include a third flat portion S1_AE3' and a third inclined portion S2_AE3' surrounding the third flat portion S1_AE3'. For example, the third flat portion S1_AE3' may be circular in a planar view. The center of the third flat portion S1_AE3' (i.e., the center of the circle) may be... Figure 11 The third center C3' in the diagram. The third inclined portion S2_AE3' can also be circular in the planar view. In this case, in the planar view, the third inclined portion S2_AE3' can surround the third flat portion S1_AE3', and the edge of the third inclined portion S2_AE3' farthest from the base SUB can coincide with the edge of the third pixel opening PXO3'.

[0238] In an embodiment, the third acute angle ANG3' formed by the upper surface of the third inclined portion S2_AE3' relative to a plane parallel to the upper surface of the third flat portion S1_AE3' can be approximately 15 degrees or greater and approximately 45 degrees or less. In an embodiment, the size of the third acute angle ANG3' can be different from the first acute angle ANG1' (see reference). Figure 14 The size of ) and may also differ from the 2-1 acute angle ANG2a' (see reference). Figure 15 ).

[0239] In an embodiment, in a cross-sectional view, the third distance T_GR3' in the third direction DR3 between the upper surface of the third flat portion S1_AE3' and the upper surface of the third anode electrode AE3' superimposed on the pixel defining layer PDL' can be about 0.5 micrometers or greater and about 3 micrometers or less. In an embodiment, the third distance T_GR3' can be different from the first distance T_GR1' (refer to...). Figure 14 ), and may also differ from the 2-1 distance T_GR2a' (see reference) Figure 15 ).

[0240] In this case, the third emitting layer EL3' disposed on the third anode electrode AE3' in the third pixel opening PXO3' can have a profile in cross-section corresponding to the third flat portion S1_AE3' and the third inclined portion S2_AE3'. In other words, the third emitting layer EL3' can have an inclined surface corresponding to the third inclined portion S2_AE3' and a flat surface corresponding to the third flat portion S1_AE3'. Since the third emitting layer EL3' has an inclined surface, the lateral visibility of light generated from the third sub-pixel SP3' can be further improved.

[0241] In an embodiment, the orthogonal projection of the edge EG_OPN3' of the third opening OPN3' onto the third direction DR3 can be located on the third inclined portion S2_AE3'. In this case, the distance W3' between the edge EG_OPN3' of the third opening OPN3' and the edge EG3' of the third flat portion S1_AE3' on the first direction DR1 can be, for example, about 2 micrometers.

[0242] Since the third sub-pixel SP3' is constructed as described above, sufficient process margin can be ensured during the formation of the light-blocking layer BM', which reduces the difficulty of forming the light-blocking layer BM'. Furthermore, due to the light-blocking layer BM', external light reflected from the cathode electrode CE' disposed on the third inclined portion S2_AE3' can be effectively blocked, which enhances the visibility of the cutoff state. Moreover, due to the third inclined portion S2_AE3' of the third anode electrode AE3' and the inclined surface of the third emitting layer EL3' corresponding to the third inclined portion S2_AE3', light emitted from the third emitting layer EL3' can pass sufficiently through the third opening OPN3'. In other words, the light output efficiency of the third sub-pixel SP3' can be improved.

[0243] The display device according to embodiments of the present disclosure may include a first anode electrode, a second anode electrode and a third anode electrode spaced apart from each other, a pixel defining layer including a first pixel opening to a third pixel opening, and a light blocking layer including a first opening to a third opening.

[0244] The radius of the third opening can be smaller than the radius of the third pixel opening. Thus, because the radius of the third opening is designed to be small, sufficient process margin can be ensured during the formation of the light-blocking layer. Therefore, the process difficulty of forming the light-blocking layer can be reduced, and the design freedom of the display device can be improved.

[0245] The third anode electrode may include a flat portion and a sloping portion around the flat portion in the area overlapping with the third pixel opening in the planar diagram. Since the third anode electrode includes the sloping portion, the third emission layer disposed on the third anode electrode may have a sloping surface corresponding to the sloping portion. Light emitted from the sloping surface of the third emission layer can pass through the third opening with a small radius. Therefore, light output efficiency can be enhanced.

[0246] The display device according to the embodiments can be applied to various types of electronic devices. In the embodiments, the electronic device includes the above-described display device, and may also include other modules or devices with additional functions in addition to the display device.

[0247] Figure 19 This is a block diagram of the electronic device 10 according to an embodiment. (Refer to...) Figure 19The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0248] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0249] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0250] The power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module. The power conversion module converts the power supplied by the power supply module and generates power to operate the electronic device 10.

[0251] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the embodiment described above. Furthermore, in terms of functionality, some of the modules included in a single module may be included in the display device, while other modules may be disposed separately from the display device. For example, the display module 11 may be included in the display device, while the processor 12, memory 13, and power module 14 may not be included in the display device but may be disposed separately in the electronic device 10.

[0252] Figure 20 Schematic diagrams of various embodiments of the electronic device are shown.

[0253] Reference Figure 20 Various types of electronic devices applied to embodiments of the display device may include electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and automotive electronic devices 10_3 including display modules (such as central information displays (CIDs) and interior mirror displays located on the dashboard, center instrument panel, and dashboard of a vehicle).

[0254] Although embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure as claimed in the appended claims.

Claims

1. A display device, the display device comprising: The first anode electrode, the second anode electrode, and the third anode electrode are spaced apart from each other; A pixel defining layer includes a first pixel opening, a second pixel opening, and a third pixel opening respectively disposed on the first anode electrode, the second anode electrode, and the third anode electrode. Each of the first pixel opening, the second pixel opening, and the third pixel opening has a circular shape in a plan view. The first pixel opening, the second pixel opening, and the third pixel opening extend to a portion of the first anode electrode, a portion of the second anode electrode, and a portion of the third anode electrode, respectively. The first emission layer, the second emission layer, and the third emission layer are respectively disposed on the first anode electrode, the second anode electrode, and the third anode electrode in the first pixel opening, the second pixel opening, and the third pixel opening; A cathode electrode covers the pixel defining layer, the first emission layer, the second emission layer, and the third emission layer; as well as A light-blocking layer is disposed on the cathode electrode and includes a first opening, a second opening, and a third opening, each having a circular shape in the plan view. The third anode electrode includes a flat portion and a sloping portion around the flat portion in the region overlapping with the third pixel opening. Wherein, the centers of the first pixel opening, the second pixel opening, and the third pixel opening coincide with the centers of the first opening, the second opening, and the third opening, respectively, and The radius of the third opening is smaller than the radius of the third pixel opening.

2. The display device according to claim 1, in, The radius of the first opening is larger than the radius of the first pixel opening, and The radius of the second opening is larger than the radius of the second pixel opening.

3. The display device according to claim 1, wherein, The radius of the third pixel opening is greater than the radius of the first pixel opening and the radius of the second pixel opening.

4. The display device according to claim 3, wherein, The radius of the first pixel opening is greater than the radius of the second pixel opening.

5. The display device according to claim 1, wherein, The difference between the radius of the first opening and the radius of the first pixel opening is equal to the difference between the radius of the second opening and the radius of the second pixel opening.

6. The display device according to claim 1, wherein, In the sectional view, the acute angle formed by the upper surface of the inclined portion relative to a plane parallel to the upper surface of the flat portion is 15 degrees or greater and 45 degrees or less.

7. The display device according to claim 1, wherein, In the cross-sectional view, the distance in the thickness direction between the upper surface of the third anode electrode, which overlaps with the flat surface of the pixel defining layer, and the upper surface of the flat portion is 0.5 micrometers or greater and 3 micrometers or less.

8. The display device according to claim 1, wherein, In the cross-sectional view, the orthogonal projection of the edge of the third opening in the thickness direction lies on the inclined portion.

9. The display device according to claim 1, further comprising: A first color filter is disposed in the first opening; A second color filter is disposed in the second opening; as well as A third color filter is disposed in the third opening.

10. A display device, the display device comprising: The first anode electrode includes a first flat portion and a first inclined portion surrounding the first flat portion; The second anode electrode includes a second flat portion and a second inclined portion surrounding the second flat portion; The third anode electrode includes a third flat portion and a third inclined portion surrounding the third flat portion; A pixel-defining layer includes a first pixel opening that exposes the first flat portion and the first inclined portion and has a circular shape in a planar view, a second pixel opening that exposes the second flat portion and the second inclined portion and has a circular shape in a planar view, and a third pixel opening that exposes the third flat portion and the third inclined portion and has a circular shape in a planar view. The first emission layer, the second emission layer, and the third emission layer are respectively disposed on the first anode electrode, the second anode electrode, and the third anode electrode in the first pixel opening, the second pixel opening, and the third pixel opening; A cathode electrode covers the pixel defining layer, the first emission layer, the second emission layer, and the third emission layer; as well as A light-blocking layer is disposed on the cathode electrode and includes a first opening, a second opening, and a third opening, each having a circular shape in the plan view. The centers of the first pixel opening, the second pixel opening, and the third pixel opening coincide with the centers of the first opening, the second opening, and the third opening, respectively.

11. The display device according to claim 10, in, The radius of the first opening is smaller than the radius of the first pixel opening. Wherein, the radius of the second opening is smaller than the radius of the second pixel opening, and The radius of the third opening is smaller than the radius of the third pixel opening.

12. The display device according to claim 10, wherein, In the planar diagram, the first difference between the radius of the first pixel opening and the radius of the first opening, the second difference between the radius of the second pixel opening and the radius of the second opening, and the third difference between the radius of the third pixel opening and the radius of the third opening are different from each other.

13. The display device according to claim 10, wherein, In the planar view, the radius of the third pixel opening is greater than the radius of the first pixel opening and the radius of the second pixel opening.

14. The display device according to claim 13, wherein, The radius of the first pixel opening is greater than the radius of the second pixel opening.

15. The display device according to claim 10, in, In the cross-sectional view, the orthogonal projection of the edge of the first opening in the thickness direction lies on the first inclined portion. In the cross-sectional view, the orthogonal projection of the edge of the second opening in the thickness direction lies on the second inclined portion, and In the sectional view, the orthogonal projection of the edge of the third opening in the thickness direction is located on the third inclined portion.

16. The display device according to claim 10, wherein, In the cross-sectional view, the first acute angle between the upper surface of the first inclined portion and the plane parallel to the upper surface of the first flat portion, the second acute angle between the upper surface of the second inclined portion and the plane parallel to the upper surface of the second flat portion, and the third acute angle between the upper surface of the third inclined portion and the plane parallel to the upper surface of the third flat portion are all 15 degrees or greater and 45 degrees or less.

17. The display device according to claim 16, wherein, In the sectional view, the first acute angle, the second acute angle, and the third acute angle are different from each other.

18. The display device according to claim 10, wherein, In the cross-sectional view, each of the following distances in the thickness direction—a first distance between the upper surface of the first anode electrode stacked with the pixel defining layer and the upper surface of the first flat portion, a second distance in the thickness direction between the upper surface of the second anode electrode stacked with the pixel defining layer and the upper surface of the second flat portion, and a third distance in the thickness direction between the upper surface of the third anode electrode stacked with the pixel defining layer and the upper surface of the third flat portion—is 0.5 micrometers or greater and 3 micrometers or less.

19. The display device according to claim 18, wherein, In the cross-sectional view, the first distance, the second distance, and the third distance are different from each other.

20. An electronic device, the electronic device comprising a display means for displaying an image, in, The display device includes: The first anode electrode, the second anode electrode, and the third anode electrode are spaced apart from each other; A pixel defining layer includes a first pixel opening, a second pixel opening, and a third pixel opening, each having a circular shape in a planar view. The first pixel opening, the second pixel opening, and the third pixel opening extend to a portion of the first anode electrode, a portion of the second anode electrode, and a portion of the third anode electrode, respectively. The first emission layer, the second emission layer, and the third emission layer are respectively disposed on the first anode electrode, the second anode electrode, and the third anode electrode in the first pixel opening, the second pixel opening, and the third pixel opening; A cathode electrode, covering the pixel defining layer and the first emission layer, the second emission layer, and the third emission layer; and A light-blocking layer is disposed on the cathode electrode and includes a first opening, a second opening, and a third opening, each having a circular shape in the plan view. The third anode electrode includes a flat portion and a sloping portion around the flat portion in the region overlapping with the third pixel opening. Wherein, the centers of the first pixel opening, the second pixel opening, and the third pixel opening coincide with the centers of the first opening, the second opening, and the third opening, respectively, and The radius of the third opening is smaller than the radius of the third pixel opening.

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