Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, the semiconductor structure comprises a plurality of semiconductor devices arranged in parallel, each semiconductor device comprises at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, and the metal interconnection structure is arranged in a dielectric layer; the second well region is arranged in the substrate between the first well regions of the adjacent semiconductor devices; the insulating layer is arranged on the dielectric layer between the adjacent semiconductor devices and extends to the two sides to a part of the metal interconnection structure; the passivation layer is arranged on the insulating layer; the first groove is formed in the surface of the metal interconnection structure and exposes part of the metal interconnection structure; and the second groove surrounds the first groove and is arranged on the metal interconnection structure, and a part of the insulating layer is exposed. According to the semiconductor structure and the preparation method thereof provided by the invention, the influence of environment humidity on junction leakage current measurement can be reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In semiconductor devices, when measuring the junction leakage current between N-wells and P-wells, the passivation layer between the two electrodes being tested is easily affected by ambient humidity, and a microscopic water film is easily formed. This microscopic water film forms an additional conductive path, introducing additional leakage current. As a result, the actual measured value includes both the junction leakage current and the water film leakage current, thus interfering with the accurate measurement of the junction leakage current. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure and its preparation method that can reduce the influence of ambient humidity on junction leakage current measurement, thereby improving the accuracy of electrical measurement.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0005] This invention provides a semiconductor structure comprising at least: A plurality of semiconductor devices arranged in parallel, each semiconductor device including at least one first well region disposed in a substrate and a metal interconnect structure disposed on the substrate, the metal interconnect structure being disposed in a dielectric layer; The second well region is disposed within the substrate between the first well regions adjacent to the semiconductor device; An insulating layer is disposed on the dielectric layer between adjacent semiconductor devices and extends laterally onto portions of the metal interconnect structure; A passivation layer is disposed on the insulating layer; A first groove is provided on the surface of the metal interconnect structure and exposes a portion of the metal interconnect structure; and A second groove is disposed on the metal interconnect structure surrounding the first groove, and exposes a portion of the insulating layer.

[0006] In one embodiment of the present invention, the ratio between the circumferential width of the second groove and the inward recess depth of the second groove is (5-50):1.

[0007] In one embodiment of the present invention, the ratio between the distance between the first groove and the second groove and the depth of the inward recess of the second groove is greater than 1.

[0008] In one embodiment of the present invention, the thickness of the passivation layer is greater than 100 nm, and the thickness of the insulating layer is less than the thickness of the passivation layer.

[0009] This invention provides a method for fabricating a semiconductor structure, comprising at least the following steps: A plurality of semiconductor devices are provided in parallel, each semiconductor device including at least one first well region disposed in a substrate and a metal interconnect structure disposed on the substrate, the metal interconnect structure being disposed in a dielectric layer; A second well region is formed in the substrate between the first well regions of adjacent semiconductor devices; An insulating layer is formed on the dielectric layer between adjacent semiconductor devices, and the insulating layer extends laterally onto portions of the metal interconnect structure; A passivation layer is formed on the insulating layer; A first groove is formed on the surface of the metal interconnect structure, the first groove exposing a portion of the metal interconnect structure; and A second groove is formed around the first groove on the metal interconnect structure, and the second groove exposes a portion of the insulating layer.

[0010] In one embodiment of the present invention, when forming the first groove and the second groove, a first photoresist layer is first formed on the passivation layer, and a first opening and a second opening are formed in the first photoresist layer. The first opening exposes a portion of the passivation layer on the metal interconnect structure, and the second opening is disposed around the first opening and exposes a portion of the passivation layer on the metal interconnect structure. The width of the first opening is greater than the circumferential width of the second opening.

[0011] In one embodiment of the present invention, after the first opening and the second opening are formed, the first photoresist layer is used as a mask and the insulating layer under the first opening is used as an etching stop layer to etch the passivation layer exposed by the first opening and the second opening to form a first recess and a second recess. The second recess is recessed inward from the passivation layer to the surface of the insulating layer. The first recess is disposed around the second recess and is recessed inward from the passivation layer.

[0012] In one embodiment of the present invention, after forming the first recess and the second recess, the insulating layer exposed in the second recess is selectively etched away to form the first groove, and then the passivation layer on the bottom of the first recess is selectively removed to form the second groove.

[0013] In one embodiment of the present invention, when forming the first groove and the second groove, a second photoresist layer is first formed on the passivation layer, and a third opening is formed in the second photoresist layer. The third opening exposes part of the passivation layer on the metal interconnect structure. Then, using the second photoresist layer as a mask and the metal interconnect structure as a stop layer, the passivation layer and the insulating layer exposed by the third opening are etched away to form the first groove.

[0014] In one embodiment of the present invention, after the first groove is formed, a third photoresist layer is formed on the passivation layer and in the first groove, and a fourth opening is formed in the third photoresist layer. The fourth opening is disposed on the passivation layer around the first groove. Then, using the third photoresist layer as a mask and the insulating layer as a stop layer, the passivation layer exposed by the fourth opening is etched to form the second groove.

[0015] As described above, the present invention provides a semiconductor structure and its fabrication method. An unexpected technical advantage of this invention is its ability to reduce the impact of ambient humidity on leakage current measurement, thereby improving the accuracy of electrical measurements. Furthermore, the semiconductor structure and fabrication method provided by this invention allow for the simultaneous formation of two different depths of grooves using only one photomask etching operation, thus reducing the frequency of photomask usage, lowering fabrication costs, and improving fabrication efficiency.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure forming an insulating layer and a passivation layer in one embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure for forming the first photoresist layer in one embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the etched passivation layer in one embodiment of the present invention.

[0022] Figure 5This is a schematic diagram of the structure forming the first groove in one embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure forming the second groove in one embodiment of the present invention.

[0024] Figure 7 for Figure 6 A top view of the semiconductor structure.

[0025] Figure 8 This is a schematic diagram of the structure for forming the second photoresist layer in another embodiment of the present invention.

[0026] Figure 9 This is a schematic diagram of the structure forming the first groove in another embodiment of the present invention.

[0027] Figure 10 This is a schematic diagram of the structure for forming the third photoresist layer in another embodiment of the present invention.

[0028] In the figure: 10, substrate; 11, semiconductor device; 111, first sub-well region; 112, second sub-well region; 113, first interconnect structure; 1131, first conductive plug; 1132, first metal layer; 114, second interconnect structure; 1141, second conductive plug; 1142, second metal layer; 115, first dielectric layer; 116, second dielectric layer; 117, third dielectric layer; 118, fourth dielectric layer; 12, second well region; 13, shallow trench isolation structure; 14, insulating layer; 15, passivation layer; 16, first photoresist layer; 161, first opening; 162, second opening; 17, first recess; 18, second recess; 19, first groove; 20, second groove; 21, second photoresist layer; 211, third opening; 22, third photoresist layer; 221, fourth opening. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figures 6 to 7As shown, the present invention provides a semiconductor structure, including at least a semiconductor device 11, a second well region 12, a shallow trench isolation structure 13, an insulating layer 14, a passivation layer 15, a first trench 19, and a second trench 20. The semiconductor device 11 may be multiple, arranged side-by-side. Each semiconductor device 11 includes at least one first well region disposed within a substrate 10 and at least one metal interconnect structure disposed on the substrate 10. The metal interconnect structure is disposed within a dielectric layer. The second well region 12 is disposed within the substrate 10 between the first well regions of two adjacent semiconductor devices 11. The insulating layer 14 is disposed on the dielectric layer between adjacent semiconductor devices 11 and extends laterally to portions of the metal interconnect structure. The passivation layer 15 is disposed on the insulating layer 14. The first trench 19 is disposed on the surface of the metal interconnect structure and exposes a portion of the metal interconnect structure. The second trench 20 surrounds the first trench 19 and is disposed on the metal interconnect structure, exposing a portion of the insulating layer 14. Due to the influence of ambient humidity, a water film is easily formed on the passivation layer 15. The water film forms an additional conductive path, introducing additional leakage current, which interferes with the accurate measurement of junction leakage current. Therefore, in the semiconductor structure provided by the present invention, by setting the second groove 20 around the first groove 19, the transmission of leakage current in the water film can be physically blocked, reducing the influence of ambient humidity on junction leakage current measurement, thereby improving the accuracy of electrical measurement.

[0031] Please see Figure 1 As shown, the present invention also provides a method for fabricating a semiconductor structure. First, a substrate 10 is provided. The substrate 10 can be any material suitable for forming a semiconductor structure, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials. It also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator. The substrate 10 can be an intrinsic semiconductor, or ions can be implanted into the substrate 10 to form an N-type semiconductor or a P-type semiconductor. Furthermore, the present invention does not limit the thickness of the substrate 10. In this embodiment, a silicon wafer substrate 10 is used as an example to illustrate the method for fabricating the semiconductor structure.

[0032] Please see Figure 1 As shown, in one embodiment of the present invention, a first ion is implanted into a substrate 10 to form at least one second well region 12, and the second well region 12 maintains a first distance from the surface of the substrate 10. The first ion is, for example, a p-type ion such as boron (B) or indium (In). When there are multiple second well regions 12, they are arranged side-by-side and spaced apart within the substrate 10. In this embodiment, for example, one second well region 12 is shown.

[0033] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the second well region 12, semiconductor devices 11 are formed side-by-side on both sides of the second well region 12. In this embodiment, for example, two semiconductor devices 11 are shown, which are arranged side-by-side on and within the substrate 10 on both sides of the second well region 12. The fabrication process is described using a single semiconductor device 11 as an example. Specifically, ions are first implanted into the substrate 10 to form a first well region. There are, for example, at least two first well regions. In this embodiment, for example, two first well regions are shown, namely a first sub-well region 111 and a second sub-well region 112. Specifically, when forming the first sub-well region 111 and the second sub-well region 112, second ions are implanted into the substrate 10 to form the first sub-well region 111, which maintains a second distance from the surface of the substrate 10. The second ion is of the opposite type to the first ion; the second ion is, for example, an N-type ion such as phosphorus (P) or arsenic (As), and the second distance is, for example, smaller than the first distance.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the first sub-well region 111, the substrate 10 on the second well region 12 is etched to form a shallow trench (not shown in the figure). Then, an insulating medium is filled into the shallow trench to form a shallow trench isolation structure 13. The shallow trench isolation structure 13 extends from the surface of the substrate 10 into the substrate 10 to the surface of the second well region 12. The insulating medium material includes at least one of silicon oxide or silicon oxynitride. The present invention does not limit the method of forming the insulating medium; for example, it can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD).

[0035] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 13, third ions are implanted into the first sub-well regions 111 on both sides of the shallow trench isolation structure 13 to form a second sub-well region 112. The second sub-well region 112 extends from the surface of the substrate 10 into the first sub-well region 111. The third ion and the second ion are of the same type, but the doping concentration of the second sub-well region 112 is greater than the doping concentration of the first sub-well region 111.

[0036] Please see Figure 1As shown, in one embodiment of the present invention, after forming the second sub-well region 112, a metal interconnect structure is formed on the second sub-well region 112. The metal interconnect structure may be at least one. In this embodiment, for example, there are two metal interconnect structures, such as a first interconnect structure 113 and a second interconnect structure 114. The first interconnect structure 113 is disposed on the second sub-well region 112, and the second interconnect structure 114 is disposed on the first interconnect structure 113. Specifically, when forming the first interconnect structure 113 and the second interconnect structure 114, a first dielectric layer 115 is first formed on the surface of the substrate 10. Then, a portion of the first dielectric layer 115 on the second sub-well region 112 is etched to form a first via (not shown in the figure). Then, conductive material is filled into the first via to obtain a first conductive plug 1131. The first conductive plug 1131 extends from the surface of the first dielectric layer 115 into the first dielectric layer 115 and then to the surface of the second sub-well region 112. Next, a second dielectric layer 116 is formed on the first dielectric layer 115 and the first conductive plug 1131. Then, the second dielectric layer 116 on the first conductive plug 1131 is etched, and the etched window extends to both sides of the second dielectric layer 116 on both sides of the first conductive plug 1131 to form a first trench (not shown in the figure). Then, conductive metal is filled into the first trench to form a first metal layer 1132. The first metal layer 1132 extends from the first conductive plug 1131 to both sides, and the two ends of the first metal layer 1132 are aligned with the two ends of the first sub-well region 111. The first metal layer 1132 and the first conductive plug 1131 constitute a first interconnect structure 113. The materials of the first conductive plug 1131 and the first metal layer 1132 are each selected from at least one material such as tungsten and copper, and the first dielectric layer 115 and the second dielectric layer 116 are each selected from at least one insulating material such as silicon oxide and silicon nitride.

[0037] Please see Figure 1As shown, in one embodiment of the present invention, after forming the first interconnect structure 113, a third dielectric layer 117 is formed on the first metal layer 1132 and the second dielectric layer 116. Then, the third dielectric layer 117 on the first metal layer 1132 is etched to form a second through hole (not shown in the figure). Then, conductive material is filled into the second through hole to obtain a second conductive plug 1141. The second conductive plug 1141 extends from the surface of the third dielectric layer 117 into the third dielectric layer 117 to the surface of the first metal layer 1132. Next, a fourth dielectric layer 118 is formed on the third dielectric layer 117 and the second conductive plug 1141. Then, the fourth dielectric layer 118 on the second conductive plug 1141 is etched, and the etched window extends to both sides of the fourth dielectric layer 118 on both sides of the second conductive plug 1141 to form a second trench (not shown in the figure). Then, conductive metal is filled into the second trench to form a second metal layer 1142. The second metal layer 1142 extends from the second conductive plug 1141 to both sides, and the two ends of the second metal layer 1142 are aligned with the two ends of the first metal layer 1132. The second conductive plug 1141 and the second metal layer 1142 constitute a second interconnect structure 114. The materials of the second conductive plug 1141 and the second metal layer 1142 are each selected from at least one material such as tungsten and copper, and the third dielectric layer 117 and the fourth dielectric layer 118 are each selected from at least one insulating material such as silicon oxide and silicon nitride.

[0038] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, after forming a metal interconnect structure, a semiconductor device 11 is obtained. The semiconductor device 11 includes at least a first sub-well region 111, a second sub-well region 112, a first interconnect structure 113, and a second interconnect structure 114. Then, an insulating layer 14 is formed on the metal interconnect structure in the semiconductor device 11, and the insulating layer 14 extends to both sides onto the metal interconnect structure of adjacent semiconductor devices 11. Specifically, in this embodiment, the insulating layer 14 is disposed on the second metal layer 1142 and the fourth dielectric layer 118. The material of the insulating layer 14 includes, for example, silicon oxide, to cover the second metal layer 1142, thereby preventing unnecessary electrical conduction between the second metal layer 1142 and other conductive structures, avoiding short circuits or signal crosstalk, ensuring the normal implementation of circuit logic functions, and also preventing the second metal layer 1142 from oxidizing in air, maintaining the conductivity of the metal, and ensuring the stability of signal transmission.

[0039] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after forming the insulating layer 14, a passivation layer 15 is formed on the insulating layer 14. The material of the passivation layer 15 includes, for example, silicon nitride, which can prevent external factors such as moisture, dust, and static electricity from damaging the semiconductor device 11, thereby improving the reliability and service life of the semiconductor device 11. The thickness of the passivation layer 15 is, for example, greater than 100 nm, specifically, 500 nm, 600 nm, or 700 nm, and the thickness of the passivation layer 15 is, for example, greater than the thickness of the insulating layer 14.

[0040] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the passivation layer 15, a photoresist layer is formed on the passivation layer 15. The photoresist layer is patterned through processes such as exposure and development to form a first photoresist layer 16. A first opening 161 and a second opening 162 are formed within the first photoresist layer 16. The first opening 161 exposes a portion of the passivation layer 15 on the second metal layer 1142. The second opening 162 surrounds the first opening 161 and also exposes a portion of the passivation layer 15 on the second metal layer 1142. The width of the first opening 161 is greater than the circumferential width of the second opening 162.

[0041] Please see Figure 3 , Figure 4 and Figure 6 As shown, in one embodiment of the present invention, after the first photoresist layer 16 is formed, the first photoresist layer 16 is used as a mask and the insulating layer 14 under the first opening 161 is used as an etching stop layer. For example, the passivation layer 15 exposed by the first opening 161 and the second opening 162 is etched by dry etching, and then the first photoresist layer 16 is removed. In this embodiment, because the width of the first opening 161 is greater than the annular width of the second opening 162, there is a larger contact area between the etching gas and the passivation layer 15 under the first opening 161. Therefore, the etching gas has a greater etching rate on the passivation layer 15 under the first opening 161. Consequently, when the insulating layer 14 under the first opening 161 is etched, the passivation layer 15 under the second opening 162 is not yet completely etched. Thus, after etching, a first recess 17 and a second recess 18 are formed within the passivation layer 15. The second recess 18 is recessed inward from the passivation layer 15 to the surface of the insulating layer 14. The first recess 17 surrounds the second recess 18 and is recessed inward from the passivation layer 15, with its bottom located within the passivation layer 15. Specifically, in this embodiment, the etching gas includes at least one of CH4, CHF3, CH3F, CF4, O2, and H2. By using the first photoresist layer 16 as a mask and performing etching only once, two different depths of the first recess 17 and the second recess 18 can be formed simultaneously, laying the foundation for the subsequent formation of the first groove 19 and the second groove 20 of different depths. This can save the frequency of photomask use, reduce manufacturing costs, and improve manufacturing efficiency.

[0042] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after forming the first recess 17 and the second recess 18, the exposed insulating layer 14 in the second recess 18 is selectively etched away to form a first groove 19. The first groove 19 is recessed inward from the passivation layer 15 on a portion of the metal interconnect structure to the surface of the metal interconnect structure. Specifically, in this embodiment, the first groove 19 is recessed inward from the passivation layer 15 on the second metal layer 1142 to the surface of the second metal layer 1142. The method for selectively etching away the insulating layer 14 is, for example, dry etching or wet etching. The etching gas in dry etching includes, for example, fluorine-based gases and auxiliary gases. The fluorine-based gas includes, for example, trifluoromethane. The auxiliary gas includes, for example, at least one of oxygen and argon. The etching solution in wet etching includes, for example, at least one of hydrofluoric acid and ammonium fluoride. By setting the first groove 19 as a window for connecting the external metal pin to the semiconductor device 11, a voltage difference can be applied to the second sub-well region 112 in two adjacent semiconductor devices 11 through the metal interconnect structure, so that the PN junction formed between the second sub-well region 112 and the second well region 12 is reverse biased, and then the current between the second sub-well regions 112 in the adjacent semiconductor devices 11 is tested, that is, the junction leakage current is measured.

[0043] Please see Figures 5 to 7As shown, in one embodiment of the present invention, after forming the first groove 19, the passivation layer 15 on the bottom of the first groove 17 is selectively removed, for example, by wet etching, to form a second groove 20. The second groove 20 is disposed around the first groove 19 and maintains a distance from the first groove 19. The second groove 20 is recessed inward from the passivation layer 15 on a portion of the metal interconnect structure to the surface of the insulating layer 14. In this embodiment, the second groove 20 is disposed around the first groove 19 on the second metal layer 1142, and the ratio between the circumferential width of the second groove 20 and the depth of the second groove 20 recessed into the passivation layer 15 is, for example, (5-50):1, to balance the ease of etching the passivation layer 15 and reduce the footprint; the ratio between the distance between the second groove 20 and the first groove 19 and the depth of the second groove 20 recessed into the passivation layer 15 is, for example, greater than 1, to ensure the physical stability of the semiconductor structure. Specifically, when etching away the passivation layer 15, an etching solution is first applied to the bottom of the first recess 17. The etching solution reacts with the passivation layer 15 at the bottom of the first recess 17 to remove the passivation layer 15. The etching solution may be, for example, hot phosphoric acid, with a temperature of, for example, 150°C-165°C and a concentration of, for example, 85wt%-90wt%. Due to the influence of ambient humidity, a microscopic water film can easily form on the passivation layer 15 between two adjacent first recesses 19. This microscopic water film forms an additional conductive path, introducing additional leakage current and thus interfering with the accurate measurement of junction leakage current. Therefore, in this application, by providing a second recess 20 around the first recess 19, the transmission of leakage current in the water film can be physically blocked, reducing the influence of ambient humidity on junction leakage current measurement and thus improving the accuracy of electrical measurements. Furthermore, since the passivation layer 15 and the insulating layer 14 are made of different materials, the thickness of the water film formed on the insulating layer 14 is less than the thickness of the water film formed on the passivation layer 15. If the second groove 20 is not provided, a continuous and thick water film is easily formed on the passivation layer 15 between two adjacent first grooves 19. However, by providing the second groove 20, the thickness of the water film formed on the insulating layer 14 in the second groove 20 is smaller, thereby reducing the overall thickness of the passivation layer 15 and the water film formed on the insulating layer 14 between two adjacent first grooves 19, weakening the leakage path, and further improving the accuracy of electrical measurement.

[0044] Please see Figure 2 , Figure 8 and Figure 9As shown, in another embodiment of the present invention, after the passivation layer 15 is formed, a photoresist layer is formed on the passivation layer 15. The photoresist layer is patterned by processes such as exposure and development to form a second photoresist layer 21. A third opening 211 is formed in the second photoresist layer 21. The third opening 211 exposes part of the passivation layer 15 on the second metal layer 1142. Then, using the second photoresist layer 21 as a mask and the second metal layer 1142 as a stop layer, the passivation layer 15 and the insulating layer 14 exposed by the third opening 211 are etched away. Alternatively, a first groove 19 can be formed. The first groove 19 is recessed inward from the passivation layer 15 on the second metal layer 1142 to the surface of the second metal layer 1142.

[0045] Please see Figure 6 , Figures 9 to 10 As shown, in another embodiment of the present invention, after the first groove 19 is formed, a photoresist layer is formed on the passivation layer 15 and inside the first groove 19. The photoresist layer is patterned through processes such as exposure and development to form a third photoresist layer 22. A fourth opening 221 is formed inside the third photoresist layer 22. The fourth opening 221 is disposed around the first groove 19 on the passivation layer 15. Then, using the third photoresist layer 22 as a mask and the insulating layer 14 as a stop layer, the passivation layer 15 exposed by the fourth opening 221 is etched. Alternatively, a second groove 20 can be formed. The second groove 20 is disposed around the first groove 19 and exposes part of the insulating layer 14 on the second metal layer 1142.

[0046] In summary, this invention provides a semiconductor structure and its fabrication method. By setting a second groove around a first groove, the unexpected technical effect of this invention is that it can reduce the influence of ambient humidity on leakage current measurement, thereby improving the accuracy of electrical measurement. Furthermore, the semiconductor structure and fabrication method provided by this invention can simultaneously form two grooves of different depths using only one etching operation on a single photomask, thus reducing the frequency of photomask use, saving fabrication costs, and improving fabrication efficiency.

[0047] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized by, At least comprising: a plurality of semiconductor devices arranged side by side, each of the semiconductor devices comprising at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, the metal interconnection structure being arranged in a dielectric layer; a second well region arranged in the substrate between the first well regions of adjacent semiconductor devices; an insulating layer arranged on the dielectric layer between adjacent semiconductor devices and extending to part of the metal interconnection structure on both sides; a passivation layer arranged on the insulating layer; a first recess arranged on a surface of the metal interconnection structure and exposing part of the metal interconnection structure; and a second recess arranged on the metal interconnection structure around the first recess and exposing part of the insulating layer. A ratio between a ring width of the second recess and a depth of the second recess inwardly recessed is (5-50):

1.

2. The semiconductor structure of claim 1, wherein, A ratio between a distance between the first recess and the second recess and the depth of the second recess inwardly recessed is greater than 1.

3. The semiconductor structure of claim 1, wherein, A thickness of the passivation layer is greater than 100 nm and a thickness of the insulating layer is less than the thickness of the passivation layer.

4. The semiconductor structure of claim 1, wherein, At least comprising the following steps:

5. A method of fabricating a semiconductor structure, characterized by, providing a plurality of semiconductor devices arranged side by side, each of the semiconductor devices comprising at least one first well region arranged in a substrate and a metal interconnection structure arranged on the substrate, the metal interconnection structure being arranged in a dielectric layer; forming a second well region in the substrate between the first well regions of adjacent semiconductor devices; forming an insulating layer on the dielectric layer between adjacent semiconductor devices and extending to part of the metal interconnection structure on both sides; forming a passivation layer on the insulating layer; forming a first recess on a surface of the metal interconnection structure, the first recess exposing part of the metal interconnection structure; and forming a second recess on the metal interconnection structure around the first recess, the second recess exposing part of the insulating layer. When forming the first recess and the second recess, first, a first photoresist layer is formed on the passivation layer, a first opening and a second opening are formed in the first photoresist layer, the first opening exposes part of the passivation layer on the metal interconnection structure, the second opening is arranged around the first opening and exposes part of the passivation layer on the metal interconnection structure, and a width of the first opening is greater than a ring width of the second opening. After forming the first opening and the second opening, the passivation layer exposed by the first opening and the second opening is etched with the first photoresist layer as a mask and the insulating layer under the first opening as an etching stop layer to form a first recess portion and a second recess portion, the second recess portion is recessed inwardly from the passivation layer to a surface of the insulating layer, and the first recess portion is arranged around the second recess portion and recessed inwardly from the passivation layer.

6. The production method according to claim 5, wherein After forming the first recess portion and the second recess portion, the insulating layer exposed in the second recess portion is selectively etched to form the first recess, and then the passivation layer on a bottom of the first recess portion is selectively removed to form the second recess.

7. The production method according to claim 6, wherein ​ 8. The production method according to claim 7, characterized by, ​ 9. The preparation method according to claim 5, characterized in that, When the first recess and the second recess are formed, a second photoresist layer is first formed on the passivation layer, a third opening is formed in the second photoresist layer, the third opening exposes part of the passivation layer on the metal interconnection structure, then the second photoresist layer is used as a mask, the metal interconnection structure is used as a stop layer, the passivation layer and the insulating layer exposed by the third opening are etched to form the first recess.

10. The method of claim 9, wherein, After the first recess is formed, a third photoresist layer is formed on the passivation layer and in the first recess, a fourth opening is formed in the third photoresist layer, the fourth opening is arranged on the passivation layer around the first recess, then the third photoresist layer is used as a mask, the insulating layer is used as a stop layer, the passivation layer exposed by the fourth opening is etched to form the second recess.

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