Testing method of semiconductor structure

Abstract

The invention provides a test method of a semiconductor structure. The test method comprises the following steps: providing a substrate on which a dielectric layer with a predetermined thickness is formed; first treatment is carried out on the substrate at least once to remove part of the dielectric layer, and the first treatment comprises the steps that etching gas is introduced into a chemical vapor decomposition machine table at a first flow speed, and purging gas is introduced into the chemical vapor decomposition machine table; etching gas is continuously introduced into the chamber at a second flow rate, the remaining dielectric layer is subjected to second processing, the remaining dielectric layer is removed, the second flow rate is greater than the first flow rate, and the time length of introducing the etching gas during the second processing is greater than the time length of introducing the etching gas during the first processing; dropping the extracting liquid drop on the substrate with the dielectric layer removed, and rolling the extracting liquid drop on the substrate to obtain a liquid drop to be detected; and analyzing the to-be-detected liquid drops to obtain the content of the metal ions in the to-be-detected liquid drops. The pretreatment of VPD is divided into a low-flow-rate treatment stage and a high-flow-rate treatment stage, so that the silicon content in the to-be-tested liquid can be effectively reduced, and the accuracy of metal ion testing is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a testing method of semiconductor structure. BACKGROUND

[0002] In the process of preparing semiconductor devices, such as the process of preparing BCD (Bipolar-CMOS-DMOS) devices, the introduction of metal ions can cause various defects affecting the service life of chips, and therefore the content of metal ions directly affects the yield of chips.

[0003] In related technologies, inductively coupled plasma mass spectrometry (ICP-MS) is widely used in the testing of metal ions on the surface of substrates in the semiconductor field. The testing of metal ions on the surface of substrates by using an inductively coupled plasma mass spectrometer mainly includes using vapor phase decomposition (VPD) to pretreat the metal ions on the substrate to extract a test solution containing metal ions and using an inductively coupled plasma mass spectrometer to analyze the content of metal ions in the test solution. However, when the oxide layer deposited on the surface of the substrate is thick (for example, the thickness of the oxide layer reaches about 1000 angstroms), VPD cannot directly extract the metal ions on the surface of the substrate, and HF needs to be used to etch the oxide layer. Fluorosilicic acid is generated in the etching process, and VPD will collect water droplets containing high-concentration fluorosilicic acid during the extraction process. Silicon will interfere with the sensitivity of ICP-MS, and thus affect the results of the testing of metal ions, so it is necessary to reduce or even eliminate the interference of silicon to ensure the accuracy of the testing of metal ions. SUMMARY

[0004] A series of concepts in simplified form are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solutions, nor to attempt to determine the protection scope of the claimed technical solutions.

[0005] In view of the existing problems, the present application provides a testing method of semiconductor structure, the testing method comprises: providing a substrate, a medium layer with a predetermined thickness is formed on the substrate; placing the substrate on a chemical vapor deposition machine, and performing at least one first treatment on the substrate to remove part of the medium layer, the first treatment comprising: introducing etching gas into a chamber of the chemical vapor deposition machine at a first flow rate to etch the medium layer, and then introducing a purge gas into the chamber to perform first purging on the substrate; The etching gas is continued to be introduced into the chamber at a second flow rate to perform a second treatment on the remaining dielectric layer and remove the remaining dielectric layer. The second flow rate is greater than the first flow rate, and the duration of the etching gas being introduced during the second treatment is greater than the duration of the etching gas being introduced during the first treatment. An extraction droplet is applied to a substrate on which the dielectric layer has been removed, and the extraction droplet is rolled on the substrate to obtain a test droplet; The test droplet was subjected to inductively coupled plasma mass spectrometry analysis to obtain the metal ion content in the test droplet.

[0006] In one embodiment, the first process is performed on the substrate three times.

[0007] In one embodiment, after the second treatment and before applying the extracted droplets to the substrate on which the dielectric layer has been removed, the manufacturing method further includes introducing a purge gas into the chamber to perform a second purging of the substrate, wherein the duration of the purge gas during the second purging is greater than the duration of the purge gas during the first purging.

[0008] In one embodiment, the operating temperature range of the chemical vapor decomposition machine is 20°C-30°C.

[0009] In one embodiment, during the first process, the duration of the purge gas is greater than the duration of the etching gas.

[0010] In one embodiment, the first flow rate ranges from 0.8 L / min to 1.2 L / min, the second flow rate ranges from 1.8 L / min to 2.2 L / min, and the purge gas flow rate ranges from 0.8 L / min to 1.2 L / min.

[0011] In one embodiment, the duration of introducing the etching gas during the first process is 1 min to 2 min, and the duration of introducing the etching gas during the second process is 5 min to 7 min.

[0012] In one embodiment, the dielectric layer is formed by deposition using a high-density plasma process.

[0013] In one embodiment, the etching gas includes HF, the purging gas includes nitrogen, and the dielectric layer is made of silicon oxide.

[0014] In one embodiment, the extraction droplet is a mixed solution of HF, H2O2, and H2O.

[0015] The semiconductor structure testing method of this application embodiment divides the VPD pretreatment into segments. In the first stage, an etching gas is introduced at a low flow rate to reduce the reaction rate between the dielectric layer and the etching gas, resulting in small droplet sizes. Then, a purge gas is introduced for the first purge, thereby effectively removing water droplet residues on the substrate surface after etching. In the second stage, the flow rate of the etching gas is increased and the reaction time is extended. This ensures that the dielectric layer is completely removed and avoids the formation of large droplets when reacting at high flow rates. As a result, the silicon content in the extracted test solution can be effectively reduced, the interference of silicon on ICP-MS testing is reduced, and the accuracy of metal ion testing is improved. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image: Figure 1 A flowchart illustrating a testing method for a semiconductor structure according to a specific embodiment of this application is shown; Figures 2A-2C This illustration shows a partial cross-sectional view of a substrate obtained by sequentially performing a test method for a semiconductor structure according to a specific embodiment of this application. Detailed Implementation

[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In the semiconductor device manufacturing process, the introduction of metal ions may lead to various defects that affect the chip's lifespan. Therefore, the content of metal ions directly affects the chip's yield.

[0025] In related technologies, inductively coupled plasma mass spectrometry (ICP-MS) is widely used in the semiconductor field for the testing of metal ions on substrate surfaces. Testing metal ions on substrate surfaces using ICP-MS mainly involves two steps: first, pretreatment of the substrate using vapor phase decomposition (VPD) to extract the analyte containing metal ions; and second, analysis of the metal ion content in the analyte using ICP-MS. However, when the oxide layer deposited on the substrate surface is thick (e.g., approximately 1000 angstroms thick), VPD cannot directly extract metal ions from the substrate surface, requiring HF etching of the oxide layer first.

[0026] During the etching process, silicon dioxide and HF react to form water and silicon tetrafluoride. Due to the thick and dense oxide layer, the reaction between HF and silicon dioxide is vigorous, resulting in large, visible granular water droplets. Silicon tetrafluoride dissolves rapidly in the water droplets to form fluorosilicic acid. During extraction, the VPD collects these water droplets containing a high concentration of fluorosilicic acid. Silicon affects the sensitivity of ICP-MS and increases the PM frequency of the instrument's sample introduction system, reducing uptime and thus impacting the results of metal ion testing. Therefore, it is necessary to reduce or even eliminate silicon interference to ensure the accuracy of metal ion testing.

[0027] Therefore, in view of the aforementioned technical problems, this application proposes a testing method for semiconductor structures. This method can be used to test the metal ion content on the wafer surface, and can also be used in other suitable testing scenarios; this application makes no limitations on this.Figure 1 As shown, it mainly includes the following steps: Step S110: Provide a substrate on which a dielectric layer of predetermined thickness is formed; Step S120: Place the substrate on a chemical vapor decomposition machine and perform at least one first process on the substrate to remove part of the dielectric layer. The first process includes: introducing an etching gas into the chamber of the chemical vapor decomposition machine at a first flow rate to etch the dielectric layer, and then introducing a purge gas into the chamber to purge the substrate for the first time. Step S130: Continue to introduce the etching gas into the chamber at a second flow rate to perform a second treatment on the remaining dielectric layer and remove the remaining dielectric layer. The second flow rate is greater than the first flow rate, and the duration of introducing the etching gas during the second treatment is greater than the duration of introducing the etching gas during the first treatment. Step S140: Apply the extraction droplet to the substrate on which the dielectric layer has been removed, and roll the extraction droplet on the substrate to obtain the droplet to be tested; Step S150: Perform inductively coupled plasma mass spectrometry analysis on the droplet to be tested to obtain the metal ion content in the droplet.

[0028] The semiconductor structure testing method of this application embodiment divides the VPD pretreatment into stages. In the first stage, an etching gas is introduced at a low flow rate to reduce the reaction rate between the dielectric layer and the etching gas, resulting in small droplet sizes. Then, a purge gas is introduced for the first purge, thereby effectively removing water droplet residues on the substrate surface after etching. In the second stage, the flow rate of the etching gas is increased and the reaction time is extended. This ensures that the dielectric layer is completely removed and avoids the formation of large droplets at high flow rates. As a result, the silicon content in the extracted test solution is effectively reduced, the interference of silicon on ICP-MS testing is reduced, and the accuracy of metal ion testing is improved.

[0029] Below, for reference Figure 1 as well as Figures 2A-2C The testing method for the semiconductor structure of this application is described in detail, wherein, Figure 1 A flowchart illustrating a testing method for a semiconductor structure according to a specific embodiment of this application is shown; Figures 2A-2C This illustration shows a partial cross-sectional view of a substrate obtained by sequentially performing a test method for a semiconductor structure according to a specific embodiment of this application.

[0030] For example, the semiconductor structure testing method of this application includes the following steps: First, such as Figure 1 As shown, step S110 provides a substrate on which a dielectric layer of predetermined thickness is formed.

[0031] For example, such as Figure 2A As shown, a substrate 200 is provided, on which a dielectric layer 201 is deposited using a high-density plasma process. The dielectric layer 201 is made of materials including, but not limited to, silicon oxide. Metal ions may be, but are not limited to, ions doped into the dielectric layer 201 during the process of forming the dielectric layer 201. Exemplarily, the thickness of the dielectric layer ranges from 800 angstroms to 1200 angstroms, for example, the thickness of the dielectric layer is 800 angstroms, 1000 angstroms, or 1200 angstroms.

[0032] For example, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or it can be at least one of the following materials: Si, SiGe, SiC, SiGeC or other suitable III / V compound semiconductors, including multilayer structures made of these semiconductor materials, or it can be silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeOI) and germanium on insulator (GeOI), or it can be double-side polished wafers (DSP), etc.

[0033] It should be noted that the term "substrate" in the context of this application is a relative concept, and it can also refer to a substrate on which a semiconductor structure (such as an isolation layer, gate structure, transistor, interconnect line or basic structure) has been pre-formed.

[0034] Then, continue as follows Figure 1 As shown, in step S120, the substrate is placed on a chemical vapor deposition (CVD) machine, and a first treatment is performed on the substrate at least once to remove a portion of the dielectric layer. The first treatment includes: introducing an etching gas into the chamber of the CVD machine at a first flow rate to etch the dielectric layer, and then introducing a purge gas into the chamber to purge the substrate for a first purging. In some examples, the operating temperature range of the CVD machine is 20°C-30°C, for example, 20°C, 25°C, or 30°C. Within this operating temperature range, the standard operating temperature of the CVD machine is typically 15°C. Due to the large difference between the machine temperature and room temperature, the gaseous HF settles quickly, accelerating the reaction rate between the gaseous HF and the oxides on the substrate surface, which easily leads to the formation of large droplets. By increasing the operating temperature of the machine to reduce the difference from room temperature, the gaseous HF settles more slowly, allowing the etching gas to remain in a stable gaseous state, thereby reducing the reaction rate between the gaseous HF and the oxides on the substrate surface and decreasing the formation of byproduct water droplets.

[0035] For example, firstly, the substrate 200 is placed on a chemical vapor deposition apparatus (not shown), such as...Figure 2B As shown, an etching gas, such as gaseous HF, is introduced into the chamber of a chemical vapor deposition apparatus at a relatively slow first flow rate. The HF reacts with the dielectric layer (e.g., SiO2) to etch the dielectric layer 201. Because the inflow of HF is slow, the reaction rate between HF and SiO2 is also slow, resulting in very small droplet sizes of the generated byproducts. Exemplarily, the first flow rate ranges from 0.8 L / min to 1.2 L / min, or other flow rates that maintain the formed droplets at a small size, such as 0.8 L / min, 1 L / min, or 1.2 L / min.

[0036] Next, after introducing HF for a predetermined duration, a purge gas, such as N2, is introduced into the chamber. This purge gas performs a first purging of the dielectric layer 201. Since the droplets of byproducts generated by the etching reaction are very small, purging with the purge gas effectively removes any remaining droplets. This completes the first treatment, removing a portion of the dielectric layer 201. Figure 2C As shown. For example, the flow rate of the purge gas is in the range of 0.8 L / min to 1.2 L / min, such as 0.8 L / min, 1 L / min or 1.2 L / min.

[0037] In practical tests, after depositing a dielectric layer of approximately 1000 angstroms using a high-density plasma process, its outermost layer is typically purplish-red. This purplish-red oxide reacts violently with HF. In some examples, the substrate is cycled through three first treatments to ensure complete reaction of the surface purplish-red oxide, thereby removing it. It is worth noting that this number of cycles is merely an example; other suitable cycle numbers may also be applicable to this application.

[0038] In some examples, to more thoroughly remove residual water droplets, the duration of the purge gas introduction in the first process is longer than the duration of the etching gas introduction. For example, the duration of the etching gas introduction in the first process ranges from 1 min to 2 min, such as 1 min, 1.5 min, or 2 min, while the duration of the purge gas introduction ranges from 2 min to 3 min, such as 2 min, 2.5 min, or 3 min. In a specific embodiment, gaseous HF is introduced into the chamber at a first flow rate of 1 L / min. The introduced HF reacts with the oxide on the substrate surface to form an etching reaction. After 1 min of reaction, the gaseous HF introduction is stopped, and N2 is introduced into the chamber at a flow rate of 1 L / min. The dielectric layer is then purged with N2 for 2 min, thereby removing part of the dielectric layer and removing residual water droplets.

[0039] Then, continue as follows Figure 1As shown, in step S130, the etching gas is continuously introduced into the chamber at a second flow rate to perform a second treatment on the remaining dielectric layer, removing the remaining dielectric layer. The second flow rate is greater than the first flow rate, and the duration of the etching gas introduction during the second treatment is greater than the duration of the etching gas introduction during the first treatment. For example, the range of the second flow rate is 1.8 L / min to 2.2 L / min, the duration of the etching gas introduction during the first treatment is 1 min to 2 min, and the duration of the etching gas introduction during the second treatment is 5 min to 7 min. More specifically, the second flow rate is 1.8 L / min, 2 L / min, or 2.2 L / min, and the duration of the etching gas introduction during the second treatment is 5 min, 6 min, or 7 min.

[0040] For example, next, a purge gas is introduced into the chamber to perform a second purging of the substrate, wherein the duration of the purge gas during the second purging is longer than the duration of the purge gas during the first purging. For example, the duration of the purge gas during the second purging is in the range of 5 min to 7 min, more specifically, the duration of the purge gas during the second purging is 5 min, 6 min, or 7 min. It is worth mentioning that the flow rate of the purge gas during the second purging can be equal to the flow rate of the purge gas during the first purging.

[0041] In a specific example, after step 120, the second flow rate is set to 2 L / min, and gaseous HF is introduced into the chamber for a reaction time of 5 min. Then, the gaseous HF is stopped, and N2 is introduced into the chamber at a flow rate of 1 L / min to purge the substrate for 5 min. By increasing the flow rate of the etching gas and the reaction time, it is ensured that the dielectric layer on the substrate surface is completely reacted, thereby removing the remaining dielectric layer. It is worth mentioning that after the outermost purplish-red oxide layer is reacted, the reaction between HF and silicon oxide at a high flow rate does not produce obvious large-diameter water droplets, and the purge gas introduced into the chamber can also remove the small-diameter water droplets remaining after the etching reaction.

[0042] After the dielectric layer is subjected to the first and second treatments, the dielectric layer on the substrate is removed, and the metal ions in the dielectric layer are exposed on the substrate surface. Then, step S140 is performed to extract the test droplet containing the metal ions.

[0043] Continue as Figure 1 As shown, in step S140, the extraction droplet is applied to the substrate on which the dielectric layer has been removed, and the extraction droplet is rolled on the substrate to obtain the droplet to be tested.

[0044] For example, such as Figure 2CAs shown, an extraction droplet 202 of a mixed solution of HF, H2O2, and H2O is placed on a substrate 200. The substrate 200 is then tilted to allow the extraction droplet to scan its surface. As the extraction droplet moves across the substrate surface, it collects dissolved SiO2 and all metal ions. In one specific embodiment, a pump draws in 120 μL of scanning liquid, then moves the pump nozzle 1 mm directly above the substrate, ejecting 100 μL of scanning liquid to form a suspended extraction droplet. The extraction droplet makes point contact with the substrate due to surface tension. The nozzle moves the extraction droplet along a path from the center of the substrate to the edge and back to the center, causing the droplet to roll on the substrate. Once the droplet reaches its endpoint, i.e., the center of the substrate, the pump reverses, and the droplet is drawn back along the same path, thus obtaining the test droplet.

[0045] Then, continue as follows Figure 1 Figure 1 As shown, step 150 is performed to analyze the test droplet using inductively coupled plasma mass spectrometry (ICP-MS) to obtain the metal ion content in the test droplet. The test droplet is transferred to the ICP-MS instrument, which performs calculations and analyses on the test droplet to obtain the metal ion content.

[0046] The same sample was tested using the test methods of this application and related technologies. The metal content in the untested sample was used as a reference value. The metal content of the sample was tested using the test methods of related technologies and the test methods of this application, respectively. Table 1 is a comparison table of metal ion content tested using the test methods of related technologies and the test methods of this application. The specified acceptable range for the test results of the sample is 80-120 ppt.

[0047] Table 1 Comparison of test results between the test methods of related technologies and the test methods of this application.

[0048] Table 1 shows that the test results of some metal contents using the related technologies were outside the acceptable range and differed significantly from the standard values, with water droplets remaining on the substrate surface. However, the test method of this application showed no water droplet residue on the substrate surface, and all test results were within the acceptable range and closer to the standard values. This demonstrates that this application can effectively reduce interference caused by silicon and improve test accuracy. Furthermore, in actual experiments, it was found that the related technologies required periodic maintenance of the ICP-MS for every 10 wafers tested, while this application only requires periodic maintenance for more than 50 wafers tested. This shows that the test method of this application can reduce the frequency of periodic maintenance, significantly reduce the silicon content entering the ICP-MS, extend the cleanliness of the instrument, and greatly prolong the performance stability period, thereby significantly improving analytical throughput and efficiency while reducing operating costs. Therefore, the test method of this application is more robust and instrument-friendly compared to the related technologies.

[0049] This concludes the description of the key steps in the semiconductor structure testing method of this application embodiment. The complete semiconductor structure testing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0050] The semiconductor structure testing method of this application embodiment divides the VPD pretreatment into segments. In the first stage, an etching gas is introduced at a low flow rate to reduce the reaction rate between the dielectric layer and the etching gas, resulting in small droplet sizes. Then, a purge gas is introduced for the first purge, thereby effectively removing water droplet residues on the substrate surface after etching. In the second stage, the flow rate of the etching gas is increased and the reaction time is extended. This ensures that the dielectric layer is completely removed and avoids the formation of large droplets when reacting at high flow rates. As a result, the silicon content in the extracted test solution can be effectively reduced, the interference of silicon on ICP-MS testing is reduced, and the accuracy of metal ion testing is improved.

[0051] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for testing semiconductor structures, characterized in that, The testing method includes: A substrate is provided on which a dielectric layer of predetermined thickness is formed; The substrate is placed on a chemical vapor deposition apparatus and subjected to at least one first process to remove a portion of the dielectric layer. The first process includes: introducing an etching gas into the chamber of the chemical vapor deposition apparatus at a first flow rate to etch the dielectric layer, and then introducing a purge gas into the chamber to purge the substrate for a first purge. The etching gas is continued to be introduced into the chamber at a second flow rate to perform a second treatment on the remaining dielectric layer to remove the remaining dielectric layer. The second flow rate is greater than the first flow rate, and the duration of the etching gas being introduced during the second treatment is greater than the duration of the etching gas being introduced during the first treatment. An extraction droplet is applied to a substrate on which the dielectric layer has been removed, and the extraction droplet is rolled on the substrate to obtain a test droplet; The test droplet was subjected to inductively coupled plasma mass spectrometry analysis to obtain the metal ion content in the test droplet.

2. The test method as described in claim 1, characterized in that, The first process is performed three times on the substrate.

3. The test method as described in claim 1, characterized in that, After the second treatment and before applying the extracted droplets to the substrate on which the dielectric layer has been removed, the process further includes: introducing a purge gas into the chamber to perform a second purging of the substrate, wherein the duration of the purge gas during the second purging is greater than the duration of the purge gas during the first purging.

4. The test method as described in claim 1, characterized in that, The operating temperature range of the chemical vapor decomposition machine is 20℃-30℃.

5. The test method as described in claim 1, characterized in that, In the first process, the duration of the purge gas is longer than the duration of the etching gas.

6. The test method as described in claim 1, characterized in that, The first flow rate ranges from 0.8 L / min to 1.2 L / min, the second flow rate ranges from 1.8 L / min to 2.2 L / min, and the purge gas flow rate ranges from 0.8 L / min to 1.2 L / min.

7. The test method as described in claim 1, characterized in that, The duration of the etching gas during the first process is 1 min to 2 min, and the duration of the etching gas during the second process is 5 min to 7 min.

8. The test method as described in claim 1, characterized in that, The dielectric layer is formed by deposition using a high-density plasma process.

9. The test method as described in claim 1, characterized in that, The etching gas includes HF, the purging gas includes nitrogen, and the dielectric layer is made of silicon oxide.

10. The test method as described in claim 1, characterized in that, The extraction droplets are a mixed solution of HF, H2O2 and H2O.

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