Semiconductor element and method of forming feedby-

Abstract

The present disclosure describes a semiconductor element and a method of forming a feedthrough via. A method of forming a longitudinal feedthrough via on a substrate includes exposing a portion of a semiconductor fin in a micro-motion region on a front side of the substrate. The exposed portion of the semiconductor fin is removed to create a first trench. The first trench is filled with at least one dielectric material to form a dielectric trench. The dielectric trench is etched to an intermediate depth to form a second trench within the dielectric trench. The second trench is filled with a conductive material. The dielectric trench is etched from the back side of the substrate to form a back side volume that exposes the conductive material in the second trench. The back side volume is filled with additional conductive material to form a longitudinal feedthrough via. The longitudinal feedthrough vias are perpendicular to the cut metal gate trenches.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming feedthrough vias. Background Technology

[0002] Integrated circuits are formed on semiconductor wafers. The lithography patterning process uses ultraviolet light to transfer the desired photomask pattern onto a photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to a layer beneath the photoresist. This process is repeated multiple times using different patterns to create different layers on the wafer substrate and fabricate useful components. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for forming a feedthrough via includes exposing portions of semiconductor fins in a micromotion region on the front side of a substrate. Etching is performed to remove the exposed portions of the semiconductor fins and create a first trench in the substrate. The first trench is filled with at least one dielectric material to form a dielectric trench. The dielectric trench is etched to an intermediate depth to form a second trench within the dielectric trench. The second trench is filled with a conductive material. The dielectric trench is etched from the rear side of the substrate to form a rear volume, the rear volume exposing the conductive material in the second trench. The rear volume is filled with the conductive material to form a continuous polysilicon feedthrough via on a diffusion edge.

[0004] According to one embodiment of this disclosure, a method for forming a feedthrough via includes receiving a substrate having a semiconductor fin on its front side, the semiconductor fin extending longitudinally and changing width in a micromotion region. A diced metal gate trench is formed, extending longitudinally on one side of the micromotion region. A gate region extending laterally in the micromotion region is removed to expose portions of the semiconductor fin. The exposed portions of the semiconductor fin are etched to create a first trench in the substrate. The first trench is filled with at least one dielectric material to form a dielectric trench. The dielectric trench and the diced metal gate trench are etched to an intermediate depth to form a second trench within the dielectric trench and a third trench within the diced metal gate trench. The second and third trenches are filled with a conductive material. The rear side of the substrate is planarized to expose the depth of the diced metal gate trench. Dielectric trenches are etched on the back side of the substrate, and metal gate trenches are cut to form a back side volume and a metal gate back side volume is cut. The back side volume exposes conductive material in a second trench, and the cut metal gate back side volume exposes conductive material in a third trench. The back side volume is filled with conductive material to form a lateral feedthrough via. The cut metal gate back side volume is also filled with conductive material to form a longitudinal feedthrough via.

[0005] According to one embodiment of this disclosure, a semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, and a feedthrough via. The first semiconductor fin is located on the front side of the substrate in a first region, and the second semiconductor fin is located on the front side of the substrate in a second region. The first and second semiconductor fins are in contact with each other in a micro-motion region. The feedthrough via is surrounded by a dielectric structure within the micro-motion region, and the dielectric structure electrically isolates the first and second regions. Attached Figure Description

[0006] This disclosure will be best understood by reading the following embodiments in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A as well as Figure 1B Together, they form a flowchart illustrating a method for forming a continuous polysilicon feedthrough via on a diffusion edge between the front and rear sides of a semiconductor element according to a partial embodiment;

[0008] Figures 2A to 2E To illustrate the completed substrate at the beginning Figure 1A as well as Figure 1B Different views before the method; Figure 2A It is a floor plan; Figure 2B Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 2C Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 2D Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 2E Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0009] Figures 3A to 3D To illustrate different views of the substrate after applying a hard photomask layer and a graphic layer; Figure 3A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 3B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 3C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 3D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0010] Figures 4A to 4D To illustrate different views of the substrate behind the patterned hard photomask layer; Figure 4A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 4B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 4C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 4D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0011] Figures 5A to 5D To illustrate different views of the substrate after trenches have been formed in the exposed area; Figure 5A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 5B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 5C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 5D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0012] Figures 6A to 6D Different views are shown after the substrate is filled with dielectric material to form dielectric trenches; Figure 6A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 6B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 6C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 6D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0013] Figures 7A to 7D To illustrate different views of the front side of the substrate after it has been flattened; Figure 7A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 7B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 7C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 7D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0014] Figures 8A to 8DTo illustrate different views of the substrate after the second trench is formed within the dielectric trench; Figure 8A Is the substrate along Figure 2A The first X-axis view of the line X1-X1; Figure 8B Is the substrate along Figure 2A The second X-axis view of the line X2-X2; Figure 8C Is the substrate along Figure 2A The first Y-axis view of the line Y1-Y1; Figure 8D Is the substrate along Figure 2A The second Y-axis view of the line Y2-Y2;

[0015] Figures 9A to 9E Different views showing the second trench of the substrate after it has been filled with conductive material; Figure 9A It's a floor plan, again as shown Figure 2A The lines X1-X1, X2-X2, Y1-Y1, and Y2-Y2 are drawn in the middle. Figure 9B This is the first X-axis view of the substrate along the scribing line X1-X1; Figure 9C This is the second X-axis view of the substrate along the scribing line X2-X2; Figure 9D This is the first Y-axis view of the substrate along the scribing line Y1-Y1; Figure 9E This is the second Y-axis view of the substrate along the scribing line Y2-Y2;

[0016] Figures 10A to 10D To illustrate different views of the front side of the substrate after the winding is formed; Figure 10A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 10B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 10C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 10D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0017] Figures 11A to 11D To illustrate the different views after the substrate is flipped; Figure 11A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 11B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 11C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 11D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0018] Figures 12A to 12DTo illustrate different views after the back side of the substrate is planarized to expose the cut metal gate trenches; Figure 12A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 12B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 12C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 12D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0019] Figures 13A to 13D To illustrate the different views of the hard photomask layer of the substrate after it has been patterned and etched; Figure 13A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 13B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 13C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 13D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0020] Figures 14A to 14D Different views are shown after the dielectric trench etching of the substrate is used to form the back volume and expose the second trench. Figure 14A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 14B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 14C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 14D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0021] Figures 15A to 15D Different views are shown to illustrate the back side of the substrate's volumetric dielectric trench filled with conductive material to form a continuous polysilicon feedthrough via on the diffusion edge. Figure 15A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 15B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 15C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 15D Is the substrate along Figure 9AThe second Y-axis view of the line Y2-Y2;

[0022] Figures 16A to 16D To illustrate different views after the back side of the substrate has been flattened to remove excess material; Figure 16A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 16B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 16C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 16D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0023] Figures 17A to 17D Different views are shown to illustrate the windings formed on the rear side of the substrate; Figure 17A Is the substrate along Figure 9A The first X-axis view of the line X1-X1; Figure 17B Is the substrate along Figure 9A The second X-axis view of the line X2-X2; Figure 17C Is the substrate along Figure 9A The first Y-axis view of the line Y1-Y1; Figure 17D Is the substrate along Figure 9A The second Y-axis view of the line Y2-Y2;

[0024] Figure 18A To illustrate the substrate of a semiconductor device along Figure 9A X-axis view of the first embodiment with scribe lines X1-X1; in this embodiment, the source / drain regions can be contacted from either side of the substrate;

[0025] Figure 18B To illustrate the substrate of a semiconductor device along Figure 9A The X-axis view of the second embodiment with scribbled X2-X2; in this embodiment, the additional feedthrough via is formed through the source / drain region;

[0026] Figure 18C To illustrate the substrate of a semiconductor device along Figure 9A The Y-axis view of the third embodiment with scribe line Y1-Y1; in this embodiment, multiple feedthrough holes are formed through dielectric trenches in the micro-motion region;

[0027] Figure 18D It is a floor plan, and Figure 18E To illustrate the substrate of a semiconductor device along Figure 18D The Y-axis view of the fourth embodiment with scribing line X2-X2; in this embodiment, the continuous polysilicon feedthrough vias on the diffusion edge are larger and replace the portion of the semiconductor fins;

[0028] Figures 19A to 19E Different views illustrating how the size of the continuous polysilicon feedthrough via on the diffusion edge of the semiconductor device is changed in a fourth embodiment; Figure 19A To illustrate Figure 2A A plan view of the substrate with the scribed lines X1-X1 and Y1-Y1 partially completed; Figure 19B The first X-axis view along scribing line X1-X1 is used to illustrate the partially completed substrate. Figure 19C To illustrate the second X-axis view along the scribing line X1-X1 after the formation of continuous polysilicon feedthrough vias on the diffusion edge; Figure 19D A first Y-axis view along scribing line Y1-Y1, showing the partially completed substrate; Figure 19E To illustrate the second Y-axis view along the doodled line Y1-Y1 after the formation of continuous polysilicon feedthrough vias on the diffusion edge;

[0029] Figures 20A to 20F Different views are shown for illustrating a fifth embodiment of a semiconductor device forming a feedthrough via by cutting a metal gate trench (e.g., cutting a metal gate feedthrough via); Figure 20A To illustrate Figure 2A A plan view of the substrate with the scribed lines X1-X1 and Y1-Y1 partially completed; Figure 20B The first X-axis view along scribing line X1-X1 is used to illustrate the partially completed substrate. Figure 20C To illustrate the second X-axis view along the scribing line X1-X1 after the formation of continuous polysilicon feedthrough vias on the diffusion edge;

[0030] Figure 20D A first Y-axis view along scribing line Y1-Y1, showing the partially completed substrate; Figure 20E To illustrate the second Y-axis view along the scribing line Y1-Y1 after the substrate forms the cut metal gate volume within the cut metal gate trench; Figure 20F To illustrate the third Y-axis view along the scribing line Y1-Y1 after the substrate has been formed with a cut metal gate feedthrough via; the cut metal gate feedthrough via extends longitudinally (e.g., along the X-axis);

[0031] Figure 20G A plan view illustrating another embodiment in which multiple cut metal gate feedthrough vias are formed in a cut metal gate trench; in this embodiment, there are three cut metal gate feedthrough vias in the cut metal gate trench; similarly, depending on the size of the cut metal gate trench and the desired application, any number of feedthrough vias may exist, including zero, one, two, three or more;

[0032] Figures 21A to 21CTo illustrate three different combinations of semiconductor fins (singular / plural) joined together in the micro-motion region; this embodiment illustrates three different combinations; Figure 21A In the middle, two fins of different widths join together in the micro-motion zone; Figure 21B In the middle, one side of the fin joins with multiple fins in the micro-motion zone; in Figure 21C In the middle, two fins with the same width are offset from each other in the micro-motion zone;

[0033] Figure 21D to Figure 21I To illustrate six different combinations of micro-motion graphics containing multiple micro-motion zones; Figure 21D to Figure 21F illustrates three different symmetrical micro-motion patterns; Figures 21G to... Figure 21I To illustrate three different asymmetric micro-motion patterns;

[0034] Figure 22A To illustrate the plan view of the front side of the wafer, cut metal gate feedthrough vias for wired to the source or drain metal contacts and continuous polysilicon feedthrough vias on the diffusion edge are shown on the front side.

[0035] Figure 22B To illustrate the plan view of the back side of the wafer, cut metal gate feedthrough vias for wired to the source or drain metal contacts and continuous polysilicon feedthrough vias on the diffusion edge are shown on the back side.

[0036] Figure 23A A plan view illustrating a first embodiment of a micro-motion pattern that can serve as a feedthrough unit;

[0037] Figure 23B A plan view illustrating a second embodiment of a micro-motion pattern that can serve as a feedthrough unit;

[0038] Figure 24A A plan view of a first embodiment of a micro-motion pattern that can serve as a feedthrough unit and a continuous polysilicon structure on a connected diffusion edge to disable surrounding transistors along an axis.

[0039] Figure 24B A plan view of a first embodiment of a micro-motion pattern that can serve as a feedthrough unit and a continuous polysilicon structure on a connected diffusion edge to disable surrounding transistors along an axis.

[0040] Figure 25A A plan view of a first embodiment of a micro-motion pattern that can serve as a feedthrough unit and a continuous polysilicon structure on a disconnected diffusion edge to disable surrounding transistors along an axis.

[0041] Figure 25BA plan view of a first embodiment of a micro-motion pattern that can serve as a feedthrough unit and a continuous polysilicon structure on a disconnected diffusion edge to disable surrounding transistors along an axis.

[0042] Figure 26 A plan view of a first embodiment of a micro-motion pattern that can serve as a feedthrough unit and a continuous polysilicon structure on a disconnected diffusion edge to disable surrounding transistors along two axes.

[0043] Figure 27A A plan view illustrating a micro-motion pattern that can serve as a feedthrough unit, a continuous polysilicon structure on a connected diffusion edge to disable surrounding transistors along an axis, and a first embodiment of a cut metal gate trench.

[0044] Figure 27B A plan view illustrating a micro-motion pattern that can serve as a feedthrough unit, a continuous polysilicon structure on a connected diffusion edge to disable surrounding transistors along an axis, and a first embodiment of a cut metal gate trench.

[0045] Figure 28 A plan view illustrating a micro-motion pattern that can serve as a feedthrough unit, a continuous polysilicon structure on the diffusion edge to disable surrounding transistors along two axes, and a first embodiment of a cut metal gate trench.

[0046] Figure 29A To illustrate the micro-motion pattern that can serve as a feedthrough unit, the micro-motion pattern does not have a plan view of the first embodiment of the source / drain region formed around its periphery;

[0047] Figure 29B To illustrate the micro-motion pattern that can serve as a feedthrough unit, a plan view of the second embodiment is provided, which does not have the source / drain regions formed around its periphery.

[0048] Figure 30A To illustrate the micro-motion pattern that can serve as a feedthrough unit, a plan view of the first embodiment is provided, which does not have a source / drain region or semiconductor channel formed around its periphery.

[0049] Figure 30B A plan view of a second embodiment of a micro-motion pattern that can serve as a feedthrough unit, which does not have a source / drain region or semiconductor channel formed around its periphery.

[0050] Figures 31A to 31G A general method for reducing layout dependency effects and parasitic capacitance in transistors / integrated circuits disclosed herein, according to a partial implementation, is illustrated.

[0051] [Symbol Explanation]

[0052] 100,400: Method

[0053] 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,146,148,150,152,154,156,158,160,402,404,406,408,410,412,414: Steps

[0054] 200: Integrated Circuits

[0055] 202: Substrate

[0056] 203: Front

[0057] 204: Shallow trench isolation layer / area

[0058] 205: Rear side

[0059] 210, 211, 426, 428: Source / Drain Regions

[0060] 218: Internal dielectric spacers

[0061] 220, 221: Interlayer dielectric layer / region

[0062] 222: Interlayer dielectric trench

[0063] 224: Low-k dielectric layer / spacer

[0064] 226: Continuous Etching Termination Layer

[0065] 230: Gate dielectric layer

[0066] 240: Cutting metal gate trenches

[0067] 241: Cutting depth / length of metal gate

[0068] 243,253,263,265,267,269,271,W1,W2,W3: Width

[0069] 250,432: Gate electrode

[0070] 251: Length

[0071] 260: Semiconductor fins

[0072] 262: First fin section / First semiconductor fin

[0073] 264: Second fin section / Second semiconductor fin

[0074] 266: Third fin section / Third semiconductor fin

[0075] 268: Fourth fin section / Fourth semiconductor fin

[0076] 270: Fifth fin section / Fifth semiconductor fin

[0077] 280: Micro-motion zone

[0078] 282: Zone 1

[0079] 284: Second Zone / Middle Zone

[0080] 286: Third District

[0081] 290: First trench

[0082] 291: Depth

[0083] 292: Dielectric trench

[0084] 294: Second trench

[0085] 295: Intermediate Depth

[0086] 296: Rear volume

[0087] 297: Source / Drain Backside Volume

[0088] 298: Third trench

[0089] 300: Stacking

[0090] 302: Semiconductor Nanosheets

[0091] 310: Hard photomask layer

[0092] 315: Thickness

[0093] 320: Bottom layer

[0094] 322: Intermediate Layer

[0095] 324: Photoresist layer

[0096] 330: Front winding

[0097] 332, 352: Etching stop layer

[0098] 334, 354: Interlayer dielectric layer

[0099] 340: Hard photomask layer

[0100] 342, 344, 346: Feedthrough holes

[0101] 350: Rear winding

[0102] 356: Feedthrough unit

[0103] 360:Contact

[0104] 362: Electrical connection

[0105] 364, 366: Continuous polysilicon dielectric structure on the diffusion edge

[0106] 365: Area

[0107] 367: Cutting metal gate structure

[0108] 420, 422: Semiconductor Channels

[0109] 424: Virtual Gate

[0110] 430, 436: Dielectric structure

[0111] 434: Dielectric spacer

[0112] 438: Dielectric-cut metal gate trench

[0113] D: Offset difference

[0114] N: Quantity

[0115] X1, X2, Y1, Y2: Draw lines Detailed Implementation

[0116] The following disclosure provides many different implementations or embodiments to carry out the various features of this disclosure. The specific implementations or embodiments of the composition or arrangement described below are intended to simplify this disclosure. Of course, these are merely embodiments and are not intended to limit this disclosure. For example, in the description below, the first feature is formed on or above the second feature, which may include an implementation where the formed first feature and the second feature are in direct contact, and may also include an implementation where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and does not in itself specify the relationship between the various implementations and / or configurations.

[0117] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower," "above," and "upper" may be used in this disclosure to facilitate the description of the relationship between one element or feature and another element or feature as shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive symbols used in this disclosure may be interpreted accordingly.

[0118] The numerical values ​​in this disclosure and claims should be understood to include the same numerical values ​​when the important figures are reduced to the same number, and the differences between the values ​​are less than the experimental errors of the type of conventional measurement technique used in this disclosure to determine the values. All scopes of this disclosure include the enumerated endpoints.

[0119] The term "approximately" can be used to include any numerical value that can be changed without altering its fundamental function. When used with a range, "approximately" also reveals a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also reveals a range "from 2 to 4". The term "approximately" can also mean plus or minus 10% of a specified numerical value.

[0120] This disclosure relates to structures composed of different layers. When the terms "on" or "above" are used to refer to two different layers (including the substrate), they simply mean that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of the structure can be considered to be "on" the substrate, even if they are not in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other without any layers in between. Furthermore, when referring to performing process steps on the substrate, this should be understood to mean that, depending on the context, these steps are also performed on any layers that may be present on the substrate.

[0121] The terms “feedthrough via”, “FTV”, “feedthrough cell”, “FTC”, “silicon through-hole”, and “TSV” are used interchangeably to refer to a structure that extends from the front side to the back side of a wafer substrate.

[0122] It should be noted that the term “groove” as used in this article refers to a volume that can be empty or filled, and it should be clear from the context of the discussion that the volume is empty or filled.

[0123] This disclosure relates to a method and apparatus for forming a communication channel between the front and back sides of a wafer substrate or semiconductor device, particularly for a full-around gate transistor. The full-around gate transistor can use nanosheets as the semiconductor channel, and the number and width of the nanosheets can be varied to obtain desired performance characteristics.

[0124] Micromotion design, where the structure in a given layer has a non-linear shape, can significantly improve the efficiency of area utilization. In this disclosure, continuous polysilicon feedthrough vias or feedthrough cells are formed on the diffusion edge within or adjacent to the micromotion region to form a communication channel between the front and back sides of the wafer substrate. Continuous polysilicon feedthrough vias on the diffusion edge are formed by etching away one or more semiconductor fins, forming trenches in the substrate, filling the trenches with a dielectric material, forming a second trench within the dielectric trench, and filling the second trench with a conductive material. This creates one or more vias with low parasitic capacitance between the front and back sides of the wafer substrate in an area-efficient manner.

[0125] Figure 1A as well as Figure 1B Together they form a flowchart illustrating a method 100 for forming a continuous polysilicon feedthrough via on a diffusion edge on a substrate according to a partial embodiment. Figures 2A to 17D To illustrate the various steps of the method, these figures provide different views for better understanding. While the method steps are discussed below in terms of forming one micro-motion region, and are illustrated as forming two micro-motion regions, this discussion should also be broadly interpreted as applying to the simultaneous formation of multiple consecutive polysilicon feedthrough vias on diffusion edges in a substrate. It should be noted that not all steps shown in the flowcharts are necessary, nor are all method steps described in the flowcharts.

[0126] initial, Figures 2A to 2E To illustrate Figure 1A The transistors or integrated circuits 200 partially completed on the wafer substrate 202 received in step 102 are in their initial state before the method steps are executed. First, refer to... Figure 2A Floor plan Figure 2A To illustrate a set of gate electrodes 250. Between each pair of gate electrodes 250 are a pair of gate dielectric layers 230, a pair of dielectric spacers 224, a pair of continuous etch stop layers 226, and an interlayer dielectric layer 220.

[0127] The dashed lines indicate the locations of the semiconductor fins beneath the gate electrode 250 and other layers 230, 224, 226, and 220. As shown in this embodiment, the first fin portion 262 and the second fin portion 264 are located in the first region 282 of the substrate. The third fin portion 266 is located in the second region or intermediate region 284 of the substrate. Finally, the fourth fin portion 268 and the fifth fin portion 270 are located in the third region 286 of the substrate.

[0128] As shown in the figure, region 282 is adjacent to region 284. Similarly, region 284 is adjacent to region 286, separating region 286 from region 282. However, it should be noted that these terms are merely identification labels for these regions. Therefore, any one of the three regions 282, 284, and 286 can be designated as region 1, region 2, etc. Micro-motion region 280 is located between regions 282 and 284, and between regions 284 and 286. In other words, each micro-motion region contains a portion of two regions or overlaps with two regions.

[0129] The first fin portion 262 has a width of 263. The second fin portion 264 has a width of 265. The third fin portion 266 has a width of 267. The fourth fin portion 268 has a width of 269. The fifth fin portion 270 has a width of 271. The width of each fin portion is independent of the widths of the other fin portions. As shown in the figure, the width 267 of the third fin portion is greater than the widths 263, 265, 269, and 271 of the other fin portions.

[0130] Before forming continuous polysilicon feedthrough vias on the diffusion edge, the fifth fin portions are connected together and can be considered as forming a single semiconductor fin 260 extending in the longitudinal direction (e.g., along the X-axis). Alternatively, each fin portion can be considered a semiconductor fin on its own. As a second alternative, the fin portions in each region can be considered together as semiconductor fins in that region, since the current density in that region is proportional to the sum of the widths of the fin portions in that region. The locations where the fin portions intersect can be called micro-regions 280, and two such micro-regions are indicated here by a rectangle. It should be noted that, for simplicity, micro-regions are shown as having a 90° intersection between the fin portions, but their intersection angle can be lower. For example, a single semiconductor fin can be described as having a varying width within the micro-region.

[0131] Now refer to Figure 2B , Figure 2B A cross-sectional view is provided. The integrated circuit is constructed on a substrate 202 having a front side 203 and a back side 205. The substrate is typically a wafer made of a semiconductor material. This material may contain silicon, such as crystalline silicon or polycrystalline silicon. In alternative embodiments, the substrate may be made of other semiconductor elements, such as germanium, or may contain semiconductor compounds such as silicon carbide, gallium arsenide, gallium carbide, gallium phosphide, indium arsenide, indium phosphide, silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In a particular embodiment, the wafer substrate is silicon.

[0132] Next, a shallow trench isolation region or layer 204 is present on the front side of the substrate 202 surrounding the fin portions. The dielectric material in the shallow trench isolation layer is typically silicon dioxide, but other dielectric materials may also be used, such as undoped polysilicon, silicon oxide (e.g., silicon dioxide), silicon nitride, silicon oxynitride, fluorine-doped silicon glass, or other low-k dielectric materials. Deposition can be performed using physical vapor deposition, chemical vapor deposition, or spin coating processes known in the art, or by oxidation growth. The shallow trench isolation layer is typically deposited before the layers of semiconductor fins 260 / fin portions 262, 264, 266, 268, 270 are constructed on the front side of the substrate. If desired, the dielectric material can be deposited above the substrate level and then recessed back to the desired height.

[0133] At Figure 2B In the view along the X-axis (X1-X1), the first fin portion 262 and the fourth fin portion 268 are visible. Figure 2C In the middle, the third fin portion 266 is visible in the X-axis view along the scribing line X2-X2. Figure 2D In the view along the Y-axis (Y1-Y1), the first fin portion 262 and the second fin portion 264 are visible. Figure 2E In the middle, the third fin portion 266 is visible in the Y-axis view along the scribing line Y2-Y2.

[0134] like Figure 2C Most readily apparent is that each fin portion comprises a stack 300 formed of alternating layers of semiconductor nanosheets 302 and a sacrificial layer (no longer present). These layers can be fabricated using chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, or any other suitable process. Each semiconductor nanosheet layer can be, for example, silicon or other suitable substrate material. The sacrificial layer can be made of any suitable material that can be selectively etched compared to other materials to be used in the transistor, such as silicon-germanium.

[0135] The concurrently existing source / drain regions 210 are located within the fin portion. In certain embodiments, these regions are formed from epitaxial silicon using chemical vapor deposition, metal-organic vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, and ultra-high vacuum chemical vapor deposition. They may also be doped with suitable dopants, such as boron, gallium, or indium; or phosphorus or arsenic. Internal dielectric spacers 218 separate the semiconductor nanosheets 302 from each other.

[0136] Next, the interlayer dielectric region 220 and the gate electrode 250 are placed alternately on the substrate. For example... Figure 2B as well as Figure 2C As shown, the interlayer dielectric region 220 is aligned with and placed on the source / drain region 210.

[0137] The interlayer dielectric region electrically isolates the source / drain regions from the gate electrode. The interlayer dielectric region can be formed of any dielectric material and does not need to be a high-k dielectric. The interlayer dielectric can be deposited using any suitable method, such as chemical vapor deposition. The interlayer dielectric region 220 is surrounded on both sides by a continuous etch stop layer 226, and then by a low-k dielectric spacer 224. The continuous etch stop layer is made of a different material than the interlayer dielectric region 220 and the low-k dielectric spacer 224, and is typically silicon nitride. The dielectric constant of the low-k dielectric layer 224 is equal to or less than the dielectric constant of silicon nitride (~7). Suitable materials can include various nitrides or oxides.

[0138] Gate electrode 250 is located between interlayer dielectric regions. Gate dielectric layer 230 exists on three sides of each gate electrode. Continuous polysilicon feedthrough vias on the diffusion edges are typically formed at the locations of the gate electrodes.

[0139] Finally, two diced metal gate trenches 240 are shown on both sides of the semiconductor fin 260. (See diagram below.) Figure 2A As shown, two diced metal gate trenches 240 extend along the X-axis (i.e., the longitudinal direction), and the gate electrode 250 extends along the Y-axis (i.e., the lateral direction). A micro-motion region 280 is located between the diced metal gate trenches 240. Figure 2D as well as Figure 2E As shown, the cut metal gate trench 240 extends into the shallow trench isolation layer 204, and thus electrically isolates the gate electrode 250 between them.

[0140] An integrated circuit 200 partially completed on a wafer substrate 202 can be fabricated by first etching the substrate to define trenches for a shallow trench isolation layer 204. The trenches are then filled with a dielectric material to form a shallow trench isolation layer. Next, a fin stack 300 is formed by depositing alternating layers of semiconductor nanosheets 302 and a sacrificial layer on the substrate. A hard photomask is applied and the fin stack is etched to obtain fin portions of the semiconductor fins at desired locations. Anisotropic etching of the sacrificial layer is performed, and internal dielectric spacers 218 are formed at these etched locations on the exposed outer walls of the fin stack. The fin stack is then etched to create trenches at desired locations in the source / drain regions 210. Another anisotropic etching is performed on the newly exposed surfaces of the sacrificial layer within these trenches, and internal dielectric spacers 218 are again formed at the newly etched locations. A dummy oxide layer is then formed on the exposed silicon surface. Epitaxial silicon is then deposited into the trenches to form the source / drain regions 210. A dummy gate material, such as polysilicon, is then deposited over the substrate. Another photomask is applied and a dummy gate material is etched to create trenches on the source / drain regions and form the dummy gate regions. A low-k dielectric spacer 224 is then applied to the vertical surfaces exposed by the dummy gate regions. An interlayer dielectric region 220 is then formed on the source / drain regions. A sequential etch stop layer 226 is then applied to the three sides exposed by the interlayer dielectric regions. The dummy gate regions are then removed to expose the sacrificial layer, which is etched away. A gate dielectric layer, comprising a semiconductor nanosheet, is applied to the exposed surfaces. The dummy gate regions are then filled to form the gate electrode 250. A metal gate trench 240 is then diced across the gate electrode 250 to form the dummy gate region. This yields... Figures 2A to 2E The partially completed substrate. If the partially completed substrate does not include diced metal gate trenches, then in Figure 1A In step 104, the substrate is etched to form an empty trench, and then the empty trench is filled with a dielectric material to obtain a cut metal gate trench, thereby forming a cut metal gate trench in the substrate.

[0141] Now refer to the example Figures 3A to 3D Illustration Figure 1A In step 106, a hard photomask layer 310 having a thickness of 315 is applied to the gate electrode 250 and the interlayer dielectric region 220. In some embodiments, the thickness of the hard photomask layer 315 ranges from about 600 angstroms to about 900 angstroms, or from about 700 angstroms to about 800 angstroms.

[0142] At Figure 1A In optional step 108, the underlayer 320 and / or intermediate layer 322 may be applied onto the hard photomask layer 310. Spin-coated carbon material is suitable for the underlayer. Spin-coated glass material is typically used for the intermediate layer. In use, the combination of the hard photomask layer, the underlayer, and the intermediate layer forms a three-layer patterned etching system, which allows for better control of subsequent etching. Then, in Figure 1AIn step 110, the photoresist layer 324 is applied and patterned. In a particular embodiment, extreme ultraviolet light with a wavelength of approximately 13.5 nm is used for patterning because this allows for smaller feature sizes. If no underlayer and intermediate layers are used, the photoresist layer is applied directly to the hard photomask layer 310. Figures 3A to 3D The resulting structure is illustrated. It can be seen that the photoresist layer 324 is patterned to expose the second region 284 (i.e., along...). Figure 2A The two gate electrodes 250 within or adjacent to the micro-motion region 280 (marked by line Y2-Y2). For example... Figure 3C As seen, the first fin portion 262 and the second fin portion 264 are exposed. (As...) Figure 3D As seen, the third fin portion 266 is exposed.

[0143] Next, at Figure 1A In step 112, the hard mask layer 310 is patterned. This can be done, for example, by dry etching. This can be called a hard mask open (HMO). When present, the intermediate layer 322 and the bottom layer 320 are first etched using a suitable etchant. After removing the bottom layer, intermediate layer, and photoresist layer, the resulting structure is as follows: Figures 4A to 4D As can be seen, the hard photomask layer 310 is patterned to expose the second region 284 (i.e., along...). Figure 2A The two gate electrodes 250 within or adjacent to the micro-motion region 280 (the scribed line Y2-Y2).

[0144] Next, at Figure 1A In step 114, etching is performed to remove gate material from any gate region within or adjacent to the micromotion region 280. Any existing gate dielectric material is also removed. Here, the gate region is the removed gate electrode 250. Figure 1A In step 116, as shown, at least one semiconductor fin portion in the micro-motion region is exposed. For example... Figure 4C As seen, the first fin portion 262 and the second fin portion 264 in the micro-motion region are exposed after the gate electrode 250 is removed. Similarly, as Figure 4D As seen, the third fin portion 266 in the micromotion region is exposed after the gate electrode 250 is removed. These fin portions are located on the front side of the substrate.

[0145] Then, in step 118, the exposed semiconductor fins are also etched away. Therefore, as... Figures 5A to 5D As seen, the first groove 290 is formed in the micro-motion region. Two first grooves 290 are shown here; the first groove 290 is either empty or hollow. (See reference...) Figure 5CThe first trench 290 has a depth 291. The diced metal gate trench 240 has a diced metal gate depth 241. In certain embodiments, the first trench depth 291 is equal to or greater than the diced metal gate depth 241, and in more specific embodiments it is greater than the diced metal gate depth 241. It should be particularly noted that etching occurs only within or adjacent to the micromotion regions 280 (singular / plural) (see...). Figure 2A Furthermore, this will not occur over the entire second region 284. Additionally, although the first trench is depicted as having a uniform depth, this is not necessary and may not occur due to the use of multiple etching steps on different layers.

[0146] Then, at Figure 1A In step 120, the first trench 290 (singular / plural) is filled (or refilled) with at least one dielectric material to form a dielectric trench 292. This may be performed, for example, by deposition. The resulting structure is illustrated in... Figures 6A to 6D In the middle. Through comparison Figure 6C as well as Figure 6D As can be seen, the fin portions 262 and 264 in the first region are now electrically isolated from the fin portion 266 in the second region by a dielectric trench 292, which extends beyond the sides of the fin portions 262 and 264.

[0147] Then next, at Figure 1A In step 122, the substrate is planarized to remove excess dielectric material and the hard photomask layer 310. The resulting structure is illustrated in... Figures 7A to 7D The remaining gate electrodes 250 in the first region 282, the second region 284, and the third region 286 are now exposed.

[0148] Next, at Figure 1A In step 124, the second trench 294 is etched into at least one dielectric trench 292. The resulting structure is illustrated in... Figures 8A to 8D As shown in the figure, the dielectric trench 292 is still present on all sides of the second trench 294, but this is not necessary.

[0149] Reference Figure 8C The dielectric trench 292 also has a depth 291, the diced metal gate trench 240 has a diced metal gate depth 241, and the second trench 294 has an intermediate depth 295. In a particular embodiment, the intermediate depth 295 is less than the diced metal gate depth 241. Therefore, the intermediate depth 295 is also less than the dielectric trench depth 291.

[0150] Although not depicted here, Figure 1A In optional step 126, a third trench is etched into at least one cut metal gate trench 240. The third trench is also etched to an intermediate depth 295.

[0151] At Figure 1A In optional step 128, and as follows Figure 8B The portions of one or more interlayer dielectric regions 220 shown can also be etched to form interlayer dielectric trenches 222. Figure 8B In the middle, interlayer dielectric trenches 222 are formed on one or more source / drain regions 210, but not on their sides, such as Figure 8A The continued presence of the interlayer dielectric region 220 is shown. In other embodiments, the interlayer dielectric region on one side of the semiconductor fin may be etched away alternatively or together with the interlayer dielectric region on the source / drain region, as needed, to form an interlayer dielectric trench. This can be achieved by appropriate patterning prior to etching. It should be noted that steps 126 and 128 may be performed simultaneously with step 124 when the dielectric trench 292 is etched, particularly if the dielectric trench 292, the diced metal gate trench 240, and the interlayer dielectric region 220 (singular / plural) are made of the same material. This can be achieved by appropriate patterning prior to etching.

[0152] Although not depicted here, Figure 1A In optional step 130, etching may be performed to remove the exposed source / drain regions 210 and form source / drain trenches. (See reference...) Figure 8B The source / drain trench will be located below the interlayer dielectric trench 222.

[0153] Next, as Figures 9A to 9E As illustrated, conductive material is deposited to fill each trench and begin to form one or more feedthrough vias. Figure 1A In step 132, conductive material fills the second trench 294. In optional step 134, conductive material fills the interlayer dielectric trench 222 and the source / drain trench. In optional step 136, conductive material fills the third trench in the cleaved metal gate trench. Steps 132, 134, and 136 can be performed simultaneously. The conductive material is typically metal. The dielectric trench 292 still separates the metal-filled second trench from the substrate to reduce metal migration into the substrate.

[0154] If desired, planarization can be performed again to remove excess material. Then, at Figure 1A In step 138 and as follows Figures 10A to 10D The diagram illustrates a front-side winding 330 formed on the front side 203 of a substrate. The front-side winding 330 is shown here as a series of alternating etch-stop layers 332 and interlayer dielectric layers 334. The front-side winding 330 electrically connects to a second trench 294 (singular / plural), an interlayer dielectric trench 222 (singular / plural), and a third trench (singular / plural) within a diced metal gate trench.

[0155] Next, at Figure 1A In step 140 and as follows Figures 11A to 11D The flipped wafer substrate 202 is illustrated. This can be accomplished by attaching a carrier wafer (not shown) to the front winding. Figure 11A The front side 203 and the rear side 205 are shown in the figure.

[0156] At Figure 1A In step 142 and as follows Figures 12A to 12D The rear side 205 of the planarized substrate 202 is illustrated to expose the diced metal gate trench 240. In other words, as shown... Figure 12D As shown, the back side is planarized to a cut metal gate depth of 241. This can be accomplished, for example, by chemical mechanical polishing or grinding. It should be noted that in some embodiments, the chemical mechanical polishing termination layer can be formed, for example, from silicon-germanium. As illustrated herein, depending on the depth of the cut metal gate trench, the substrate may no longer be continuous or may exist throughout the entire semiconductor device.

[0157] Then, at Figure 1A In step 144 and as follows Figures 13A to 13D The hard photomask 340 is illustrated and patterned on the rear side 205. Here, the hard photomask 340 is patterned to expose the second trench 294 (singular / plural) and one of the source / drain regions 210 is located between the second trenches (singular / plural).

[0158] Now refer to Figures 14A to 14D ,At Figure 1A In step 146, dielectric trench 292 is etched from the back side 205 to expose second trench 294. Back side volume 296 is formed. In optional step 148, back side 205 is etched to expose one or more source / drain regions 210. Source / drain back side volume 297 is thus formed. In optional step 150, diced metal gate trench is etched from the back side to expose third trench. Diced metal gate back side volume is thus formed. These steps 146, 148, and 150 can be performed simultaneously if desired. They can be performed using the same photomask or different photomasks.

[0159] Now refer to Figures 15A to 15D ,At Figure 1A In step 150, conductive material fills the back volume. In optional step 152, conductive material fills the source / drain back volume 297. In optional step 154, conductive material fills the diced metal gate back volume. These steps 152, 154, and 156 can be performed simultaneously if desired. As seen here, a continuous polysilicon feedthrough via 342 on the diffusion edge is thus formed in the micromotion region 280 (see also...). Figure 9A The continuous polysilicon feedthrough vias on the diffusion edge extend in the lateral direction (i.e., along the Y-axis).

[0160] Next, at Figure 1A In step 158 and as follows Figures 16A to 16D The back side 205 of the substrate is shown being planarized to remove excess conductive material. The hard photomask layer 340 does not need to be completely removed and is shown to remain after planarization.

[0161] Next, at Figure 1A In the steps and such Figures 17A to 17D The diagram illustrates a rear-side routing 350 formed on the rear side 205 of the substrate. The rear-side routing 350 is illustrated here as a series of alternating etch-stop layers 352 and interlayer dielectric layers 354. A front-side routing 330 is electrically connected to the rear-side routing 350 via a continuous polysilicon feedthrough 342 on the diffusion edge. The semiconductor device or integrated circuit 200 thus forms a feedthrough 342 extending from the front side to the rear side of the substrate.

[0162] Special attention should be paid to Figure 1A The methods and Figures 2A to 17D To illustrate the substrate where the gate electrode has already been formed. This method may also be performed on a partially completed substrate having a dummy gate that has not yet been replaced by the gate electrode. In this case, steps 106 to 120 will be performed and a dielectric trench will be formed. Specifically, in step 114, the gate material removed will be the dummy gate and any dummy gate oxide material. After completing step 120, the dummy gate will be removed and replaced by the gate electrode. Then, a metal gate trench 240 will be formed and filled with a conductive material. Steps 122 to 160 can then be performed. Similarly, an implementation that forms only a continuous polysilicon feedthrough via on the diffusion edge of a micro-motion region is considered to be within the scope of this disclosure.

[0163] It should also be noted that, generally, steps 124, 132, 146, and 152 describe replacing a portion of the dielectric trench from the front side and then replacing the remaining portion from the rear side to form a continuous polysilicon feedthrough via 342 on the diffusion edge by replacing the dielectric trench with metal. However, this is not necessary. The dielectric trench can be completely replaced from the front side or completely replaced from the rear side. Therefore, in step 124 (see...) Figures 8A to 8D The second trench can be etched to the cut metal gate depth 241 instead of the intermediate depth 295, and steps 146 and 152 will not be performed. Alternatively, steps 124 or 132 need not be performed, and in step 146 (see...) Figures 14A to 14D The dielectric trench can be etched to the etch stop layer of the front winding 330.

[0164] Figure 18A This is the X-axis view of the first deformation of the semiconductor device, which is drawn as follows. Figure 9AThe substrate is scribed along line X1-X1. In this embodiment, the source / drain region 211 can be contacted from either side of the substrate, as indicated by the presence of the interlayer dielectric region 220 contacting the front winding 330 and the interlayer dielectric region 221 contacting the rear winding 350.

[0165] Figure 18B This is the X-axis view of the second deformation of the semiconductor device, which is drawn as follows. Figure 9A The substrate along the scribing line X2-X2. In this embodiment, Figure 1A Step 130 is performed to remove the source / drain region 210. Therefore, a region is formed through... Figure 1A Another feedthrough via 344 is provided in the semiconductor fin 260. Depending on the size of the semiconductor fin 260, more than one such feedthrough via 344 can be formed by removing the source / drain regions.

[0166] Figure 18C This is the Y-axis view of the third deformation of the semiconductor device, which is drawn as follows. Figure 9A The substrate along the scribed line Y1-Y1. Refer back to the original text. Figure 7C as well as Figure 8C Instead of forming a single second trench 294 within the dielectric trench 292, multiple second trenches are formed. Therefore, once filled with a conductive material, such as Figure 18C As shown, multiple feedthrough vias 342 are formed in the micro-motion region 280, passing through the dielectric trench 292. Three feedthrough vias are shown here, but any number of feedthrough vias can be formed depending on the size of the dielectric trench.

[0167] Figure 18D as well as Figure 18E The fourth variation of the semiconductor device is illustrated here. As shown, other elements within the semiconductor fin portion 266 have been completely removed, and a continuous polysilicon feedthrough via 342 on the diffusion edge extends through at least one micro-motion region and through the semiconductor fin portion 266. In other words, the continuous polysilicon feedthrough via 342 on the diffusion edge fills portion 266, or the portion with the maximum width. It is contemplated that the various structures 210, 218, 220, 224, 226, 250, 302 illustrated in the previous figures for this portion can be removed by etching, or intentionally not formed in this portion beforehand.

[0168] The size of the continuous polysilicon feedthrough via 342 on the diffusion edge can be varied as desired. Figures 19A to 19E It illustrates the comparison with Figure 1AThe design incorporates a larger gate electrode 250 within a micromotion region 280 formed between semiconductor fin portions 262, 264, and 266. The gate electrode 250 has a length 251 along the X-axis and a width 253 along the Y-axis. The length is measured between low-k dielectric spacers 224 on either side of the gate electrode 250. The width 253 is measured between diced metal gate trenches 240. The length and width can vary independently, and the length does not need to be greater than the width. In some specific embodiments, the length 251 is 20 nm or higher, possibly up to 200 nm. In some specific embodiments, the width 253 is 40 nm or higher, possibly up to 200 nm. Other ranges and values ​​are also within the scope of this disclosure. Higher dimensions reduce resistance.

[0169] Figure 19B as well as Figure 19C All of these are X-axis views taken along the line X1-X1. Figure 19B The partially completed substrate 202 is shown, while Figure 19C The substrate is illustrated after the formation of continuous polysilicon feedthrough vias 342 on the diffusion edge. Figure 19D as well as Figure 19E These are all Y-axis views taken along the line Y1-Y1. Figure 19D The partially completed substrate 202 is shown, while Figure 19E The substrate after the formation of continuous polysilicon feedthrough vias 342 on the diffusion edge is illustrated. Front winding 330 and rear winding 350 are also illustrated.

[0170] The dimensions of the cut metal gate trench 240 can be varied as desired. Figures 20A to 20E An enlarged view of a cut-metal gate trench 240 including a cut-metal gate feedthrough via 346 is shown. The cut-metal gate trench has a length 241 along the X-axis and a width 243 along the Y-axis. The length and width can vary independently, and the length does not need to be greater than the width. The cut-metal gate trench 240 is located between two semiconductor fins 260 and separates the gate electrode 250 into two portions, such that each semiconductor fin operates as an individual transistor. Dielectric material fills the cut-metal gate trench 240.

[0171] Figure 20B as well as Figure 20C They are all along Figure 20A The X-axis view is captured by the line X1-X1 in the diagram. Figure 20B The partially completed substrate 202 is illustrated. Here, the shallow trench isolation layer 204 is visible on the substrate 202. Interlayer dielectric regions 220 and gate electrodes 250 alternate on the shallow trench isolation layer. Figure 20CThe substrate after forming the cut metal gate feedthrough via 346 is illustrated. The cut metal gate trench 240 separates the feedthrough via 346 from the interlayer dielectric region 220. The front winding 330 and the rear winding 350 are also illustrated.

[0172] Figures 20D to 20F It is along Figure 20A The Y-axis view is shown by the scribing line Y1-Y1, illustrating the formation of the cut metal gate feedthrough via 346. Figure 20D The partially completed substrate 202 is shown. A gate electrode 250 is present between two semiconductor fins 260.

[0173] Figure 20E The illustration shows the execution Figure 1A Following step 126, a substrate 202 is formed within the diced metal gate trench 240 to create a third trench 298. Dielectric material for the diced metal gate trench is present on all sides of the empty third trench. The third trench 298 is etched to an intermediate depth 295.

[0174] Figure 20F The illustration shows the execution Figure 1A Following steps 136, 150, and 156, a substrate is formed within the cut metal gate trench 240 to create a cut metal gate feedthrough via 346. Front winding 330 and rear winding 350 are also shown.

[0175] Figure 20G Another variation is illustrated. Here, multiple cut-metal gate feedthrough vias 346 are formed within a single cut-metal gate trench 240. This can be accomplished through appropriate patterning, etching, and filling.

[0176] Now refer to Figures 21A to 21C The method disclosed herein can be applied to any combination of different semiconductor fins / fin portions. Three different combinations are illustrated here.

[0177] At Figure 21A In the diagram, the first semiconductor fin 262 has nanosheets with a width of W1. These nanosheets are connected to a second semiconductor fin 264 in a micromotion region 280. The second semiconductor fin has nanosheets with a different width W2 (W1 > W2). A dielectric trench 292 passing through the first semiconductor fin 262 and its nanosheets is also illustrated here. The dielectric trench may alternatively pass through the second semiconductor fin 264, or through both fins.

[0178] Figure 21BThe diagram illustrates a configuration where a semiconductor fin is connected to multiple semiconductor fins. Here, a first semiconductor fin 262 is connected at one end to a second semiconductor fin 264 and a third semiconductor fin 266. Alternatively, a semiconductor fin 262 may be divided into multiple portions 264, 266 in a first region 282 within a micro-motion region 280, each portion 264, 266 having a width smaller than that of portion 262 of the fin in the second region 284. Here, a dielectric trench 292 is shown passing through the second semiconductor fin 264 and the third semiconductor fin 266.

[0179] The first semiconductor fin 262 and its nanosheets have a width W1. Similarly, the second semiconductor fin 264 is specified to have a width W2, and the third semiconductor fin 266 is specified to have a width W3. Here, W1 ≥ (W2 + W3). Generally, the number of multiple semiconductor fins is N ≥ 2.

[0180] Figure 21C The diagram illustrates a configuration where the first semiconductor fin 262 and the second semiconductor fin 264 have the same width (W1=W2), and the two fins are offset from each other in the micro-motion region 280. The offset difference is denoted by the letter D. The dielectric trench 292 is shown here passing through both the first semiconductor fin 262 and the second semiconductor fin 264.

[0181] Figure 21D to Figure 21F illustrates three different symmetrical micro-motion patterns that can be formed. In Figure 21D, the first semiconductor fin 262 and the third semiconductor fin 266 have the same width. They are on opposite sides of the second semiconductor fin 264 (along the X-axis) and connected at the center of the second semiconductor fin.

[0182] In Figure 21E, the first semiconductor fin 262 and the second semiconductor fin 264 have the same width. They are both located to the left of the third semiconductor fin 266 and are connected at opposite ends of the third semiconductor fin (along the Y-axis). The fourth semiconductor fin 268 and the fifth semiconductor fin 270 have the same width. They are both located to the right of the third semiconductor fin 266 and are connected at opposite ends of the third semiconductor fin. The first semiconductor fin 262 and the fourth semiconductor fin 268 have the same width and are both located at the same end of the third semiconductor fin. The second semiconductor fin 264 and the fifth semiconductor fin 270 have the same width and are both located at the same end of the third semiconductor fin.

[0183] In Figure 21F, the first semiconductor fin 262 and the third semiconductor fin 266 have the same width. They are on opposite sides of the second semiconductor fin 264 and are both connected to the same end of the second semiconductor fin.

[0184] Figure 21G to Figure 21IThree different symmetrical micro-motion patterns that can be formed are illustrated. In Figure 21G, the first semiconductor fin 262 and the third semiconductor fin 266 have different widths. They are on opposite sides of the second semiconductor fin 264 and connected at the center of the second semiconductor fin.

[0185] In Figure 21H, the first semiconductor fin 262 and the second semiconductor fin 264 have the same width. They are both on the left side of the third semiconductor fin 266 and connected to opposite ends of the third semiconductor fin. The fourth semiconductor fin 268 and the fifth semiconductor fin 270 have the same width. They are both on the right side of the third semiconductor fin 266 and connected to opposite ends of the third semiconductor fin. The first semiconductor fin 262 and the fourth semiconductor fin 268 have different widths, and they are both at the same end of the third semiconductor fin. The second semiconductor fin 264 and the fifth semiconductor fin 270 have different widths, and they are both at the same end of the third semiconductor fin.

[0186] At Figure 21I In this configuration, the first semiconductor fin 262 and the third semiconductor fin 266 have the same width. They are located on opposite sides of the second semiconductor fin 264 and are connected to different ends of the second semiconductor fin.

[0187] Figure 22A This is a plan view of the front side 203 of the wafer, and Figure 22B This is a plan view of the back side 205 of the wafer. On the front side 203, contacts 360 can connect to the source or drain regions, while on the back side 205, contacts 360 can connect to the source region. Electrical connections 362 are shown as either continuous polysilicon feedthrough vias 342 or diced metal gate feedthrough vias 346 through the diffusion edge to each contact 360. For devices parallel to continuous polysilicon feedthrough vias 342 on the diffusion edge, electrical connections through continuous polysilicon feedthrough vias 342 on the diffusion edge are more efficient. Similarly, for devices parallel to diced metal gate feedthrough vias 346, electrical connections through diced metal gate feedthrough vias 346 are more efficient.

[0188] Figure 23A as well as Figure 23B These are two different planar schematic diagrams of the wafer substrate 202. In each diagram, six horizontal columns extend, containing five source / drain regions 210, and four gate electrodes 250 extend vertically. The source / drain regions 210 are isolated by shallow trench isolation regions 204. Therefore, there are 24 possible transistors in each diagram. Figure 23AThe diagram illustrates a feedthrough cell 356 occupying the space of two source / drain regions. The feedthrough cell is formed by replacing the shown volume with a dielectric material. The source / drain regions, gate electrode, semiconductor material, and interlayer dielectric are not present within the feedthrough cell. The only micro-motion region within the feedthrough cell is shown as a continuous polysilicon feedthrough via 342 on the diffusion edge. The dielectric trench 292 still fills another micro-motion region (which is not further processed into a continuous polysilicon feedthrough via on the diffusion edge). Figure 23B In the diagram, feedthrough cell 356 occupies the space of six source / drain regions. Continuous polysilicon feedthrough vias 342 on the two diffusion edges are also shown within the feedthrough cell. This reduces layout dependency and increases pattern density.

[0189] Figure 24A as well as Figure 24B These are two different planar schematic diagrams of the wafer substrate 202. Each diagram includes six columns of five source / drain regions 210, four gate electrodes 250, and a shallow trench isolation region 204. Figure 24A In this configuration, the feedthrough cell 356 occupies the space of three source / drain regions and cuts through all four gate electrodes 250. A continuous polysilicon feedthrough via 342 on the diffusion edges fills the feedthrough cell. Furthermore, eight continuous polysilicon dielectric structures 364 on the diffusion edges are physically connected to the feedthrough cell 356. These eight continuous polysilicon dielectric structures on the diffusion edges replace the gate electrodes and disable the transistors in region 365. Figure 24B A similar structure is illustrated, but with a larger feedthrough unit 356. Furthermore, the continuous polysilicon feedthrough via 342 on the diffusion edges is illustrated as extending into the continuous polysilicon dielectric structure 364 on the four diffusion edges. Generally, the continuous polysilicon feedthrough via on the diffusion edges can be extended to any number of continuous polysilicon dielectric structures on the diffusion edges and at any location, as desired.

[0190] Figure 25A as well as Figure 25B These are two different planar schematic diagrams of the wafer substrate 202. These diagrams are similar to... Figure 24A and Figure 24B Except for the continuous polysilicon dielectric structure 364 on the diffusion edge, which has no physical connection to the feedthrough unit 356, the transistor is still disabled in region 365.

[0191] Figure 26 This is another planar schematic diagram of the wafer substrate 202. However, Figures 24A to 25B The continuous polysilicon dielectric structure 364 on the diffusion edge is located above or below the feedthrough unit 356. In this figure, there are also two continuous polysilicon dielectric structures 366 on the diffusion edge located on each side of the feedthrough unit 356. The transistors directly above, directly below, and on each side of the feedthrough unit are disabled, but the diagonal transistors are not disabled as they are. Figures 24A to 25B It is disabled in China.

[0192] Figure 27A as well as Figure 27B These are two other different planar schematic diagrams of the wafer substrate 202. These diagrams are similar to... Figure 24A and Figure 24B However, it also includes a diced metal gate structure 367 at the distal end of the continuous polysilicon dielectric structure 364 on the diffusion edge. This diced metal gate structure can be used to remove high-k dielectric material from the sidewalls of the continuous polysilicon dielectric structure on the diffusion edge to reduce parasitic capacitance in the continuous polysilicon dielectric structure on the diffusion edge.

[0193] Figure 28 This is another planar schematic diagram of the wafer substrate 202. This diagram is similar to... Figure 26 However, it also includes six diced metal gate structures 367 at the far end of the continuous polysilicon dielectric structure 364 on the diffusion edge. Again, the transistors directly above, directly below, and on each side of the feedthrough unit are disabled, but the diagonal transistors are not as they are. Figures 24A to 25B It is disabled in China.

[0194] Figure 29A as well as Figure 29B These are two other different planar schematic diagrams of the wafer substrate 202. In these diagrams, the source / drain regions 210 are not formed around the feedthrough cells 356. Here, the semiconductor fins 260 are visible in the columns above and below the feedthrough cells 356. This also disables the transistors in the region 365 surrounding the feedthrough cells. From a vertical perspective, it is particularly noteworthy that the surrounding area is still filled with the interlayer dielectric region 220.

[0195] Figure 30A as well as Figure 30B These are two other different planar schematic diagrams of the wafer substrate 202. In these diagrams, the source / drain regions 210 and semiconductor fins are not formed around the feedthrough cells 356. This also disables the transistors in the region 365 surrounding the feedthrough cells. Again, from a vertical perspective, it is particularly noteworthy that the surrounding area is still filled with the interlayer dielectric region 220. Figure 30A In the diagram, the continuous polysilicon feedthrough vias 342 on the diffusion edge are also depicted as having different sizes and surface areas. Figure 30B In the diagram, the continuous polysilicon feedthrough vias 342 on the diffusion edge are also depicted as filled feedthrough cells 356.

[0196] Figures 31A to 31G A general method 400 for reducing layout-dependent effects and parasitic capacitance during the manufacture of the transistors / integrated circuits disclosed herein is illustrated.

[0197] At Figure 31AIn step 402, a semiconductor channel is formed in the substrate. Here, a P-type metal-oxide-semiconductor (MOSFET) channel 420 and an N-type MOSFET channel 422 are illustrated. Figure 31B In step 404, a virtual gate 424 is formed.

[0198] At Figure 31C In step 406, source / drain regions 426, 428 are formed on either side of semiconductor channels 420, 422 and dummy gate 424. This can be accomplished, for example, by deposition or appropriate doping of epitaxial silicon.

[0199] At Figure 31D In optional step 408, one or more portions of the dummy gate 424 may be replaced by a dielectric structure 430 to disable a transistor that would otherwise be formed at the given location. This dielectric structure extends along the same axis as the dummy gate 424. However, using the dielectric structure 430 increases the risk of metal gate tilting, which can occur due to metal gate bending.

[0200] At Figure 31E In step 410, the dummy gate is removed and replaced by a gate electrode 432. The gate electrode is typically metal. Furthermore, dielectric spacers 434 are formed on all sides of the metal gate. If a dielectric structure 430 is formed, the dielectric spacers 434 directly contact the dielectric structure 430 (see enlarged view). Metal boundary effects thus occur, which can lead to undesirable voltage shifts.

[0201] At Figure 31F In step 412, the dielectric structure 436 is formed by replacing the gate electrode to disable the transistor formed at a given location. The dielectric structure extends along the same axis as the gate electrode 432. When these dielectric structures are formed alternatively, the dielectric spacers 434 are present only on both sides of the gate electrode 432, and there is no dielectric spacer between the gate electrode 432 and the dielectric structure 436 (see enlarged view).

[0202] At Figure 31G In the illustrated optional step 414, a dielectrically cleaved metal gate trench 438 is formed together with the dielectric structure 430. The cleaved metal gate trench is formed perpendicular to the axis of the gate electrode 432. Alternatively, the formation of the cleaved metal gate trench can reduce or eliminate metal boundary effects that would otherwise occur. In the enlarged view, there is no dielectric spacer between the gate electrode 432 and the dielectric structure 430 (see enlarged view).

[0203] It should be noted that some routine steps are not fully described in every instance in the following discussion, and their results should be considered only. For example, a pattern / structure can be formed on a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching it, but the following discussion may only involve patterning the given layer. For completeness, some of these different steps are now described.

[0204] Generally, photoresist layers can be applied by methods such as spin coating, spraying, roller coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating table, which may include vacuum chucks to hold the substrate in place. The photoresist mixture is then applied to the center of the substrate. The speed of the rotating table is then increased to evenly distribute the photoresist from the center of the substrate to its surrounding area. The rotation speed of the table is then fixed, which controls the final thickness of the photoresist layer.

[0205] Next, the photoresist mixture is baked or cured to remove the solvent and harden the photoresist layer. In a particular embodiment, baking occurs at a temperature of about 90°C to about 110°C. Baking can be performed using a hot plate, oven, or other similar equipment. As a result, a photoresist layer is formed on the substrate.

[0206] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the desired photomask pattern. In a particular embodiment, extreme ultraviolet light with a wavelength of approximately 13.5 nm is used for patterning because this allows for a smaller feature size. This results in some portions of the photoresist layer being exposed to radiation, while other portions remain unexposed. This exposure causes some portions of the photoresist to become soluble in the developer while other portions remain insoluble.

[0207] Following exposure to radiation, an additional photoresist baking step (post-exposure baking) may occur. For example, this could help release acid leaving groups (ALGs) or other molecules that are significant in chemically amplified photoresist.

[0208] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. The soluble portion of the photoresist layer is dissolved and washed away during the development step, leaving the photoresist pattern. A common example of a developer is an aqueous solution of tetramethylamine hydroxide. Other developers may include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl 2-hydroxyisobutyrate, ethyl lactate or propylene glycol methyl ether acetate, n-amyl acetate, butyl propionate, n-hexyl acetate, butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanediol, 2,6-dimethyl-4-heptanone, propyl 2-methylpropionate, or isobutyl propionate. Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" is performed after development to stabilize the photoresist pattern, thereby achieving optimal performance in subsequent steps.

[0209] Next, the area of ​​the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example using various solvents such as N-methylpyrrolidone or alkaline media or other stripping agents at elevated temperatures, or by dry etching using oxygen plasma.

[0210] Generally, any etching steps used herein can be performed using wet etching, dry etching, or plasma etching processes such as reactive ion etching, inductively coupled plasma, or combinations thereof, depending on the application. Etching can be anisotropic. Depending on the material, the etchant may contain carbon tetrafluoride, hexafluoroethane, octafluoropropane, trifluoromethane, difluoromethane, fluoromethane, trifluoromethane, fluorinated carbon, nitrogen, hydrogen, oxygen, argon, xenon, xenon difluoride, helium, carbon monoxide, carbon dioxide, fluorine, chlorine, oxygen, hydrogen bromide, hydrofluoric acid, nitrogen trifluoride, sulfur hexafluoride, boron trichloride, ammonia, bromine, nitrogen trifluoride, etc., or various combinations thereof in different proportions. For example, hydrofluoric acid and ammonium fluoride can be used for wet etching of silicon dioxide. Alternatively, various mixtures of trifluoromethane, oxygen, carbon tetrafluoride, and / or hydrogen can be used for dry etching of silicon dioxide.

[0211] Planarization can be performed to obtain a flat surface. Planarization can be performed using processes such as chemical mechanical polishing (CMP). Generally, CMP is performed using a rotating stage with an attached polishing pad. The substrate is attached to a rotating carrier. A slurry or solvent containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier rotate, inducing mechanical and chemical action on the surface of the wafer substrate and / or its top layer, removing unwanted material and creating a high-level surface. A post-CMP cleaning step is then performed using a rotating scrubbing brush and cleaning solution to clean one or both sides of the wafer substrate.

[0212] Finally, a cleaning step, such as a wet wash, can be performed between the various processing steps. The cleaning solution will depend on the etching formulation and the exposed layers. Examples of cleaning solutions may include deionized water, diluted hydrogen fluoride, or other conventional solutions.

[0213] The methods and systems disclosed herein encompass several different dielectric structures. These dielectric structures can be made from any suitable combination of dielectric materials, examples of which include silicon dioxide, silicon nitride, silicon carbide, hafnium dioxide, zirconium dioxide, aluminum oxide, silicon oxynitride, hafnium oxynitride, or zirconium oxynitride, or hafnium silicate, zirconium silicate, silicon carbonitride, or hexagonal boron nitride. Other dielectric materials may include tantalum oxide, nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass, fluorosilicate glass, undoped silicate glass, high-stress undoped silicate glass, and borosilicate glass.

[0214] Any conductive material discussed herein can generally be any conductive metal or any conductive oxide. Examples of suitable metals include copper, aluminum, nickel, chromium, gold, germanium, silver, titanium, tungsten, platinum, tantalum, ruthenium, cobalt, rhenium, palladium, or zirconium; composite materials such as titanium nitride, tungsten nitride, or tantalum nitride; or alloys thereof, such as copper and aluminum. Examples of suitable conductive oxides include indium tin oxide, zinc oxide, tin oxide, zinc aluminum oxide, indium oxide, or cadmium oxide. Metals or oxides can be deposited via methods such as evaporation or sputtering, electroplating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods.

[0215] The method disclosed herein has several advantages. First, the resulting feedthrough vias have high area efficiency. Second, they also have low parasitic capacitance. They enable efficient and effective electrical signal communication for components perpendicular to the metal gate electrode, providing good communication in the second axis. Third, wiring is thus simplified. Fourth, lower-resistance metal contacts can be formed, improving electrical signal communication. Fifth, layout dependence effects can be reduced by appropriately disabling adjacent transistors. Sixth, no new photomask is required to implement the method described herein. Other advantages may also exist in the method and layout described herein.

[0216] Additional processing steps may be performed to obtain a semiconductor device comprising a transistor with a micro-motion region having continuous polysilicon feedthrough vias on a diffusion edge. The semiconductor device can be used in a variety of applications, such as bipolar-CMOS-DMOS circuits for driving discrete high-voltage components; drivers for liquid crystal displays, organic light-emitting diodes (OLEDs), active-matrix OLEDs, and quantum dot OLED display panels; image sensors for systems such as mobile phones, facial recognition systems, or as motion sensors for automotive applications, security applications, energy efficiency, etc.; power management devices for controlling power flow; and / or image signal processors.

[0217] Therefore, in some embodiments, this disclosure relates to a method for forming continuous polysilicon feedthrough vias on a diffusion edge in a substrate. A portion of a semiconductor fin in a micromotion region on the front side of the substrate is exposed. Etching is performed to remove the exposed portion of the semiconductor fin and create a first trench in the substrate. The first trench is filled with at least one dielectric material to form a dielectric trench. The dielectric trench is then etched to an intermediate depth to form a second trench within the dielectric trench. The second trench is filled with a conductive material. The dielectric trench is then etched from the back side of the substrate to form a back volume exposing the conductive material in the second trench. Additional conductive material fills the back volume to form continuous polysilicon feedthrough vias on the diffusion edge.

[0218] In one embodiment, the micro-motion region is located between two diced metal gate trenches. In one embodiment, the two diced metal gate trenches extend to the diced metal gate depth, and the first trench has a depth equal to or greater than the diced metal gate depth. In one embodiment, the intermediate depth is less than the diced metal gate depth. In one embodiment, the method further includes planarizing the back side of the substrate to the diced metal gate depth to expose the diced metal gate trenches before etching the dielectric trenches from the back side of the substrate. In one embodiment, the method further includes etching each diced metal gate trench to form a third trench within the diced metal gate trench. Each third trench is filled with a conductive material. Each diced metal gate trench is etched from the back side of the substrate to form a diced metal gate volume, the diced metal gate volume exposing the conductive material in the third trench. And each diced metal gate volume is filled with a conductive material to form a diced metal gate feedthrough via. In one embodiment, when the dielectric trench is etched to an intermediate depth, at least one dielectric layer on the source / drain region is also etched, and this further includes etching to remove the source / drain region before filling the rear volume with conductive material. In one embodiment, this further includes forming at least one winding layer on the front side of the substrate. In one embodiment, this further includes forming at least one winding layer on the rear side of the substrate. In one embodiment, the portion of the semiconductor fin in the micromotion region is exposed by removing the gate region. In one embodiment, the micromotion region is located between a first region and a second region of the substrate. In one embodiment, the portion of the semiconductor fin in the first region has a width greater than the portion of the semiconductor fin in the second region. In one embodiment, the portion of the semiconductor fin in the first region is offset by the portion of the semiconductor fin in the second region. In one embodiment, the semiconductor fin in the first region is divided into multiple portions, each portion having a width smaller than that of the semiconductor fin in the second region.

[0219] Various embodiments also disclose methods for forming longitudinal feedthrough vias and lateral feedthrough vias. A substrate having semiconductor fins on its front side is received, the semiconductor fins extending longitudinally and varying in width in a micromotion region. A diced metal gate trench extending longitudinally is formed on one side of the micromotion region. A gate region extending laterally in the micromotion region is removed to expose the semiconductor fin portion. Etching is performed to remove the exposed portion of the semiconductor fin and create a first trench in the substrate. The first trench is filled with at least one dielectric material to form a dielectric trench. The dielectric trench and the diced metal gate trench are etched to an intermediate depth to form a second trench within the dielectric trench and a third trench within the diced metal gate trench. The second and third trenches are filled with a conductive material. The rear side of the substrate is planarized to the depth exposing the diced metal gate trench. The dielectric trench and the diced metal gate trench are etched from the rear side of the substrate to form a rear volume, the rear volume exposing the conductive material in the second trench and the diced metal gate rear volume exposing the conductive material in the third trench. Conductive material is used to fill the back volume to form a lateral feedthrough via. Conductive material is used to fill the back volume of a cut metal gate to form a longitudinal feedthrough via.

[0220] In one embodiment, when the dielectric trench is etched to an intermediate depth, at least one dielectric layer on the source / drain region is also etched, and further includes etching to remove the source / drain region before filling the back volume with conductive material.

[0221] Various embodiments also disclose semiconductor devices comprising a substrate. The substrate has a first semiconductor fin in a first region and a second semiconductor fin in a second region. The first and second semiconductor fins are in contact with each other in a micro-motion region. A feedthrough via exists within the micro-motion region. A dielectric structure surrounds the feedthrough via, electrically isolating the first and second regions.

[0222] In one embodiment, the micro-motion region is located between two diced metal gate trenches. In one embodiment, a feedthrough via is further included in at least one of the two diced metal gate trenches. In one embodiment, the first semiconductor fin and the second semiconductor fin are offset from each other.

[0223] The foregoing outlines several features of the embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a feedthrough aperture, characterized in that, Include: A portion of a semiconductor fin is exposed in a micro-motion region on a front side of a substrate; Etching is used to remove the exposed portion of the semiconductor fin and create a first trench in the substrate; The first trench is filled with at least one dielectric material to form a dielectric trench; The dielectric trench is etched to an intermediate depth to form a second trench within the dielectric trench; The second trench is filled with a conductive material; The dielectric trench is etched from one rear side of the substrate to form a rear volume, the rear volume exposing the conductive material in the second trench; as well as The conductive material is used to fill the rear volume to form a continuous polysilicon feedthrough via on the diffusion edge.

2. The method as described in claim 1, characterized in that, The micro-motion region is located between two cut metal gate trenches.

3. The method as described in claim 2, characterized in that, The two diced metal gate trenches extend to a diced metal gate depth, and the first trench has a depth equal to or greater than the diced metal gate depth.

4. The method as described in claim 3, characterized in that, The intermediate depth is less than the depth of the cut metal gate.

5. The method as described in claim 3, characterized in that, The method further includes planarizing the back side of the substrate to the cut metal gate depth to expose the cut metal gate trench before etching the dielectric trench from the back side of the substrate.

6. The method as described in claim 5, characterized in that, Further includes: Etch each of the cut metal gate trenches to form a third trench within the cut metal gate trench; The conductive material is used to fill each of the third trenches; Each of the cut metal gate trenches is etched from the rear side of the substrate to form a cut metal gate volume, the cut metal gate volume exposing the conductive material in the third trench; as well as The conductive material is used to fill each of the cut metal gate volumes to form a cut metal gate feedthrough via.

7. The method as described in claim 1, characterized in that, When the dielectric trench is etched to the intermediate depth, at least one dielectric layer on a source / drain region is also etched, and further includes: The source / drain region is removed by etching before the conductive material is filled into the back volume.

8. A method for forming a feedthrough aperture, characterized in that, Include: A substrate is received, the substrate having a semiconductor fin on a front side, the semiconductor fin extending along a longitudinal direction and changing its width in a micro-motion region; A cut metal gate trench is formed, which extends along the longitudinal direction on one side of the micro-motion region; Remove a gate region that extends laterally within the micro-motion region to expose a portion of the semiconductor fin; Etching is used to remove the exposed portion of the semiconductor fin and to create a first trench in the substrate; The first trench is filled with at least one dielectric material to form a dielectric trench; The dielectric trench and the cut metal gate trench are etched to an intermediate depth to form a second trench in the dielectric trench and a third trench in the cut metal gate trench. The second trench and the third trench are filled with a conductive material; Planarize a rear side of the substrate to expose a depth of the cut metal gate trench; The dielectric trench and the cut metal gate trench are etched on the back side of the substrate to form a back side volume and a cut metal gate back side volume. The back side volume exposes the conductive material in the second trench, and the cut metal gate back side volume exposes the conductive material in the third trench. The rear volume is filled with the conductive material to form a lateral feedthrough via; as well as The conductive material is used to fill the volume behind the cut metal gate to form a longitudinal feedthrough via.

9. The method as described in claim 8, characterized in that, When the dielectric trench is etched to the intermediate depth, at least one dielectric layer on a source / drain region is also etched, and further includes: The source / drain region is removed by etching before the conductive material is filled into the back volume.

10. A semiconductor element, characterized in that, Include: One substrate; A first semiconductor fin and a second semiconductor fin, the first semiconductor fin being located on a front side of a substrate in a first region, and the second semiconductor fin being located on a front side of the substrate in a second region, wherein the first semiconductor fin and the second semiconductor fin are in contact with each other in a micro-motion region; and A feedthrough is provided within the micro-motion region and surrounded by a dielectric structure that electrically isolates the first region from the second region.

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