Semiconductor device and manufacturing method thereof
By constructing porous layers and alloy self-healing layers on semiconductor substrates, combined with gradient nitrogen doping of the gate dielectric layer, the electromigration problem of copper interconnect structures was solved, thereby improving the reliability and performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-27
AI Technical Summary
During the miniaturization of integrated circuit process nodes, copper interconnect structures are prone to voids or whiskers caused by electromigration. Furthermore, low dielectric constant dielectric materials have poor adhesion to copper, which increases the risk of interconnect structure failure. Existing metal diffusion barrier layers are difficult to completely block metal diffusion and introduce additional resistance.
A porous layer and an alloy self-healing layer are formed on a semiconductor substrate. A diffusion barrier layer is formed on the inner surface of the via, and an electric field is used to guide the directional growth of the metal-organic framework porous layer. The alloy is melted at high temperature to repair defects in the metal interconnect structure. At the same time, gradient nitrogen doping is introduced in the gate dielectric layer to strengthen the interface.
It effectively repairs electromigration damage in metal interconnect structures, improves the reliability and interconnect performance of semiconductor devices, reduces resistivity, and increases interface strength.
Smart Images
Figure CN121752046A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] As integrated circuit process nodes continue to shrink to the nanoscale, complementary metal-oxide-semiconductor (CMOS) devices face severe reliability challenges.
[0003] In the later stages of the process, driven by high current density, copper atoms in the copper interconnect structure undergo directional migration along the direction of electron flow, a phenomenon known as electromigration. Electromigration can lead to the formation of voids or whiskers within the copper interconnect structure, increasing resistivity. Furthermore, the low-dielectric-constant dielectric materials introduced to reduce parasitic capacitance typically have poor adhesion to copper, making them prone to interfacial delamination under thermal or mechanical stress, further exacerbating the risk of interconnect failure.
[0004] To address these challenges, the industry primarily relies on inserting a metal diffusion barrier layer between the copper and the surrounding dielectric layer. However, these barrier layers are difficult to completely block metal diffusion and introduce additional resistance, which is detrimental to further improvements in interconnect performance. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor, the method comprising: Provide semiconductor substrates; An interlayer dielectric layer is formed covering the semiconductor substrate, and through-holes are formed in the interlayer dielectric layer; A self-healing layer is formed on the inner surface of the through hole, the self-healing layer comprising a porous layer and an alloy filling the pores of the porous layer; A metal layer is filled into the through-hole to form a metal interconnect structure, and the alloy is used to melt when heated to repair defects in the metal interconnect structure.
[0007] In one embodiment, the porous layer comprises a metal-organic framework porous layer; the formation of a self-healing layer on the inner surface of the through-hole comprises: A diffusion barrier layer is formed on the inner surface of the through hole; The porous metal-organic framework layer is directionally grown on the surface of the diffusion barrier layer using an electric field; The alloy is injected into the pores of the metal-organic framework porous layer.
[0008] In one embodiment, the alloy has a melting point of 60°C-200°C, and the alloy comprises an indium-tin alloy.
[0009] In one embodiment, prior to forming the interlayer dielectric layer, the method further includes: A gate structure is formed on the semiconductor substrate. The gate structure includes a gate dielectric layer and a gate electrode layer, wherein the nitrogen doping concentration in the gate dielectric layer decreases in a gradient along the direction from the semiconductor substrate to the gate electrode layer.
[0010] In one embodiment, the step of forming the gate dielectric layer includes: An oxide layer is deposited on the surface of the semiconductor substrate using an atomic layer deposition process. During the deposition process, a nitrogen-containing process gas is introduced, and the radio frequency power of the atomic layer deposition process is adjusted to form a gradient-reduced nitrogen doping concentration in the grown gate dielectric layer.
[0011] In one embodiment, during the first stage of the atomic layer deposition process, a first partial gate dielectric layer having a first nitrogen doping concentration is formed using a first radio frequency power. In the second stage of the atomic layer deposition process, a second portion of the gate dielectric layer with a second nitrogen doping concentration is formed using a second radio frequency power, wherein the first radio frequency power is higher than the second radio frequency power and the first nitrogen doping concentration is higher than the second nitrogen doping concentration.
[0012] Another aspect of the present invention provides a semiconductor device, comprising: Semiconductor substrate; An interlayer dielectric layer covering the semiconductor substrate; A self-healing encapsulation structure is formed in the interlayer dielectric layer, the self-healing encapsulation structure including a metal interconnect structure and a self-healing layer formed between the metal interconnect structure and the interlayer dielectric layer, the self-healing layer including a porous layer and an alloy filling the pores of the porous layer, the alloy being used to melt upon heating to repair defects in the metal interconnect structure.
[0013] In one embodiment, the porous layer comprises a metal-organic framework porous layer.
[0014] In one embodiment, the alloy has a melting point of 60°C-200°C, and the alloy comprises an indium-tin alloy.
[0015] In one embodiment, the semiconductor device further includes: A gate structure is formed on the semiconductor substrate, the gate structure including a gate dielectric layer and a gate electrode layer, wherein the nitrogen doping concentration in the gate dielectric layer decreases in a gradient along the direction from the semiconductor substrate to the gate electrode layer.
[0016] According to the semiconductor device and manufacturing method provided in the embodiments of this application, a self-healing layer composed of a porous layer and an alloy is formed on the inner wall of the through hole, which can actively repair electromigration damage in the metal interconnect structure. Attached Figure Description
[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0018] In the attached image: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 2A-2F This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation
[0019] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.
[0020] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the widths of layers and regions, as well as their relative widths, may be exaggerated. The same reference numerals denote the same elements throughout.
[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0022] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0024] In view of the aforementioned technical problems, this application provides a semiconductor device and a method for manufacturing the same. The semiconductor device in this application includes, but is not limited to, a CMOS device. Below, reference is made to... Figures 1 to 2F The method for fabricating the semiconductor device according to the embodiments of this application is described in detail, wherein, Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figures 2A-2F A cross-sectional view of a semiconductor device obtained by implementing a manufacturing method according to a specific embodiment of this application is shown.
[0025] First, execute step S101, as follows: Figure 2A As shown, a semiconductor substrate 200 is provided.
[0026] For example, the material of the semiconductor substrate 200 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon on dielectric (S-SiGeOI), silicon on dielectric (SiGeOI), and germanium on dielectric (GeOI).
[0027] Next, optionally, a gate structure is formed on the semiconductor substrate 200.
[0028] Specifically, firstly, a gate dielectric layer 201 with a gradient nitrogen doping concentration is formed on a semiconductor substrate 200, wherein the nitrogen doping concentration in the gate dielectric layer 201 decreases gradually along the direction from the semiconductor substrate 200 to the gate electrode layer 202. The gradient nitrogen doping concentration enables interface strengthening, overcomes the limitations of traditional uniform nitriding, reduces threshold voltage (Vt) drift caused by hot carrier effect (HCI), improves time breakdown (TDDB) lifetime, and enhances the reliability of the gate dielectric layer.
[0029] During the formation of the gate dielectric layer 201, a plasma-assisted oxidation-nitridation (PAON) process can be used to simultaneously achieve oxidation and nitrogen doping, avoiding lattice damage associated with conventional annealing. Specifically, an oxide layer is deposited on the surface of the semiconductor substrate 200 using atomic layer deposition (ALD). During the deposition process, a nitrogen-containing process gas is introduced, and the radio frequency power of the ALD process is adjusted to create a gradient-decreasing nitrogen doping concentration in the grown gate dielectric layer 201.
[0030] Exemplarily, firstly, a semiconductor substrate 200 is placed in a reaction chamber for an atomic layer deposition process. The chamber temperature is set and stabilized at 300°C to 400°C. High-purity oxygen is introduced into the chamber at a flow rate of 100 to 200 sccm. Simultaneously, low-frequency radio frequency power below 15 MHz is applied to excite the oxygen into oxygen plasma. Under this low-temperature plasma environment, an initial silicon oxide layer with a thickness of 1 nm to 2 nm is grown on the surface of the semiconductor substrate 200. This low-temperature process avoids excessive densification of the oxide layer caused by high temperatures, creating favorable conditions for subsequent nitrogen gradient doping.
[0031] After the initial silicon oxide layer is grown, the process gas is switched. A nitrogen-containing process gas, such as a mixture of ammonia (NH3) and nitrogen (N2), is introduced into the chamber, with the NH3 to N2 flow rate ratio being, for example, 1:3, and the total flow rate being, for example, approximately 50 sccm. Simultaneously, a high-frequency radio frequency source with a frequency higher than 2 GHz is turned on.
[0032] This stage achieves a gradient distribution of nitrogen concentration by adjusting the high-frequency radio frequency power in stages. Specifically, in the first stage, a first portion of the gate dielectric layer with a first nitrogen doping concentration is formed using a first radio frequency power; in the second stage, a second portion of the gate dielectric layer with a second nitrogen doping concentration is formed using a second radio frequency power. The first radio frequency power is higher than the second radio frequency power, and the first nitrogen doping concentration is higher than the second nitrogen doping concentration.
[0033] Specifically, the first stage accounts for approximately 30% of the total time of the two stages. The applied first radio frequency power is, for example, 300W. This high power generates a high-energy nitrogen plasma, which has sufficient kinetic energy to penetrate the initial silicon oxide layer and reach and primarily act on the interface region between the silicon oxide and the semiconductor substrate, forming a first nitrogen doping concentration in this region, with a nitrogen atom percentage concentration ranging from 5% to 8%, for example, 7%, thereby constituting a high-nitrogen interface layer.
[0034] The second stage accounts for approximately 70% of the total time of the two stages. In the second stage, the radio frequency power is reduced from the first radio frequency power to a second radio frequency power, for example, 100W. This lower power generates a lower-energy nitrogen plasma, which mildly dopes the main region of the silicon oxide layer, forming a second nitrogen doping concentration with a nitrogen atom percentage concentration ranging from 2% to 3%.
[0035] Through the above dynamic power regulation, a nitrogen doping concentration distribution with a gradient decreasing from the semiconductor substrate 200 upwards is finally formed in the grown gate dielectric layer 201.
[0036] For example, after the gradient nitriding stage, the nitrogen-containing process gas is stopped, and an inert gas (such as argon) is introduced into the chamber. The semiconductor device is then subjected to rapid thermal annealing under this inert atmosphere. The annealing temperature is controlled at 600°C to 700°C, and the annealing time is maintained at 10 to 30 seconds. The annealing process serves three purposes: first, it activates the incorporated nitrogen atoms, placing them in electrically active positions; second, it repairs lattice damage that may be introduced by the plasma process; and third, through short-duration high-temperature treatment, it optimizes interface characteristics while locking in the established nitrogen concentration gradient distribution, preventing the gradient from homogenizing due to nitrogen atom diffusion during subsequent thermal processes.
[0037] Subsequently, a gate electrode layer 202 is formed on the gate dielectric layer 201. For example, a polysilicon layer can be deposited as the gate electrode layer 202 using a low-pressure chemical vapor deposition process. Then, as... Figure 2B As shown, the gate electrode layer 202 and the gate dielectric layer 201 are patterned by photolithography and dry etching processes to form a gate structure.
[0038] After the gate structure is formed, conventional semiconductor front-end processes can be performed, such as lightly doped drain implantation, sidewall formation, heavily doped source / drain implantation, and rapid thermal annealing, to form source and drain regions in the semiconductor substrate, which will not be elaborated here.
[0039] Next, proceed to step S102, as follows: Figure 2C As shown, an interlayer dielectric layer 203 is formed covering the semiconductor substrate, and vias 205 are formed in the interlayer dielectric layer 203. The interlayer dielectric layer 203 also covers the gate structure formed on the semiconductor substrate 200. Figure 2C The semiconductor substrate and gate structure in the front-end process are omitted.
[0040] For example, silicon dioxide or a low-k dielectric material (such as carbon-doped silicon oxide) can be deposited as an interlayer dielectric layer 203 using plasma-enhanced chemical vapor deposition (PECVD). Then, vias 205 for forming metal interconnect structures are etched into the interlayer dielectric layer 203 using photolithography and reactive ion etching (RIE) processes. These vias 205 can connect to the underlying metal layer 204, or to the active region of a gate structure or semiconductor substrate. Figure 2C The image shows a through-hole formed using a double damask process to connect to the lower metal layer 204.
[0041] Next, a self-healing layer is formed on the inner surface of the via. The self-healing layer includes a porous layer and an alloy filling the pores of the porous layer. When the temperature rises above the melting point of the alloy, the alloy melts to fill the electromigration voids in the metal interconnect structure, thereby achieving self-healing of defects in the metal interconnect structure.
[0042] The porous layer includes, but is not limited to, metal-organic framework (MOF) porous layers. MOF porous layers can be formed using electrochemical self-assembly processes. Specifically, firstly, as... Figure 2D As shown, a diffusion barrier layer 206 is formed on the entire inner surface of the via (including the bottom and sidewalls). Exemplarily, a diffusion barrier layer 206 with a thickness of approximately 5 nm is conformally deposited using physical vapor deposition or atomic layer deposition processes. The material of the diffusion barrier layer 206 includes tantalum, tantalum nitride, or cobalt. The following description uses tantalum nitride as an example.
[0043] Next, as Figure 2E As shown, an electric field guides the directional growth of a porous metal-organic framework (MOF) layer on the surface of a diffusion barrier layer. Exemplarily, the semiconductor device, having undergone the aforementioned steps, is immersed in a MOF precursor solution. Electrodes are placed in the solution to apply a bias voltage of 0.5-2V, specifically 1V. Under the influence of the electric field, organic ligands in the MOF precursor solution are directionally guided to the surface of the tantalum nitride layer and undergo a coordination self-assembly reaction with tantalum electrochemically activated and released from the tantalum nitride layer surface, thereby forming a porous MOF layer with a thickness of approximately 8-10 nm and uniform nanopores on the inner surface of the via.
[0044] Next, the alloy is injected into the pores of the metal-organic framework porous layer to obtain the self-healing layer 207. The alloy can be a low-melting-point alloy with a melting point between 60°C and 200°C, and it can be an indium-tin alloy, a bismuth-based alloy, a gallium-based alloy, or other low-melting-point alloys.
[0045] For example, a vacuum melt implantation process is used, in which a semiconductor device is placed in a vacuum chamber and heated to above the melting point of the alloy, for example, to about 150°C for an indium tin alloy with a melting point of about 118°C. Under vacuum, the molten indium tin alloy is drawn into the pores of the metal-organic framework porous layer. Subsequently, the semiconductor device is cooled to room temperature, and the alloy in the pores solidifies, forming a self-healing layer 207 filled with the alloy.
[0046] Next, as Figure 2F As shown, a metal layer is filled in the through-hole to form a metal interconnect structure 208.
[0047] For example, an electrochemical electroplating process is used to fill copper in the vias having a self-healing layer 207 to form a copper interconnect structure. Then, a chemical mechanical polishing process is performed to remove excess copper and diffusion barrier material from the surface, planarizing the surface and achieving isolation between the metal interconnect structures 208. Once voids or whiskers caused by electromigration occur in the metal interconnect structure 208, the alloy stored in the pores of the self-healing layer 207 can achieve in-situ repair of electromigration damage, similar to the self-repair mechanism of biological tissue.
[0048] In one embodiment, the metal interconnect structure 208 has a wavy topology, thereby reducing the current density gradient.
[0049] Thus, the process steps of the semiconductor device manufacturing method according to the first aspect embodiment of this application are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.
[0050] According to the semiconductor device manufacturing method provided in the embodiments of this application, by introducing gradient nitrogen doping into the gate dielectric layer, the interface is effectively strengthened and hot carrier degradation is suppressed; by constructing a self-healing layer composed of a porous layer and an alloy on the inner wall of the back-end via, the metal interconnect is provided with the ability to actively repair electromigration damage. The two work synergistically to systematically improve the reliability of the semiconductor device from both the front and back ends.
[0051] This application also provides a semiconductor device, which can be prepared by the methods described in the foregoing embodiments, but is not limited thereto.
[0052] The semiconductor device of this application will be described in detail below. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the description in Embodiment 1.
[0053] Specifically, such as Figure 2F As shown, the semiconductor device of this application embodiment includes: a semiconductor substrate (not shown); an interlayer dielectric layer 203 covering the semiconductor substrate; a self-healing packaging structure formed in the interlayer dielectric layer 203, the self-healing packaging structure including a metal interconnect structure 208, and a self-healing layer 207 formed between the metal interconnect structure 208 and the interlayer dielectric layer 203, the self-healing layer 207 including a porous layer and an alloy filling the pores of the porous layer, the alloy being used to melt upon heating to repair defects in the metal interconnect structure 208.
[0054] In one embodiment, the porous layer comprises a metal-organic framework porous layer, and the alloy is a low-melting-point alloy with a melting point of 60°C-200°C, such as an indium-tin alloy.
[0055] In one embodiment, such as Figure 2B As shown, it also includes a gate structure formed on the semiconductor substrate 200. The gate structure includes a gate dielectric layer 201 and a gate electrode layer 202, wherein the nitrogen doping concentration in the gate dielectric layer 201 decreases in a gradient along the direction from the semiconductor substrate 200 to the gate electrode layer 202.
[0056] The semiconductor device of this application effectively strengthens the interface and suppresses hot carrier degradation by introducing gradient nitrogen doping into the gate dielectric layer; and provides the metal interconnect with the ability to actively repair electromigration damage by constructing a self-healing layer composed of a porous layer and an alloy on the inner wall of the back-end via. These two aspects work synergistically to systematically improve the reliability of the semiconductor device from both the front and back ends.
[0057] This application also provides an electronic device, including the aforementioned semiconductor device, which can be prepared according to the aforementioned method.
[0058] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment, due to the use of the aforementioned semiconductor devices, has better performance.
[0059] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Provide semiconductor substrates; An interlayer dielectric layer is formed covering the semiconductor substrate, and through-holes are formed in the interlayer dielectric layer; A self-healing layer is formed on the inner surface of the through hole, the self-healing layer comprising a porous layer and an alloy filling the pores of the porous layer; A metal layer is filled into the through-hole to form a metal interconnect structure, and the alloy is used to melt when heated to repair defects in the metal interconnect structure.
2. The method according to claim 1, characterized in that, The porous layer includes a metal-organic framework porous layer; the formation of a self-healing layer on the inner surface of the through-hole includes: A diffusion barrier layer is formed on the inner surface of the through hole; The porous metal-organic framework layer is directionally grown on the surface of the diffusion barrier layer using an electric field; The alloy is injected into the pores of the metal-organic framework porous layer.
3. The method according to claim 1, characterized in that, The alloy has a melting point of 60℃-200℃, and the alloy includes an indium-tin alloy.
4. The method according to claim 1, characterized in that, Before forming the interlayer dielectric layer, the method further includes: A gate structure is formed on the semiconductor substrate. The gate structure includes a gate dielectric layer and a gate electrode layer, wherein the nitrogen doping concentration in the gate dielectric layer decreases in a gradient along the direction from the semiconductor substrate to the gate electrode layer.
5. The method according to claim 4, characterized in that, The step of forming the gate dielectric layer includes: An oxide layer is deposited on the surface of the semiconductor substrate using an atomic layer deposition process. During the deposition process, a nitrogen-containing process gas is introduced, and the radio frequency power of the atomic layer deposition process is adjusted to form a gradient-reduced nitrogen doping concentration in the grown gate dielectric layer.
6. The method according to claim 5, characterized in that, In the first stage of the atomic layer deposition process, a first partial gate dielectric layer with a first nitrogen doping concentration is formed using a first radio frequency power. In the second stage of the atomic layer deposition process, a second portion of the gate dielectric layer with a second nitrogen doping concentration is formed using a second radio frequency power, wherein the first radio frequency power is higher than the second radio frequency power and the first nitrogen doping concentration is higher than the second nitrogen doping concentration.
7. A semiconductor device, characterized in that, include: Semiconductor substrate; An interlayer dielectric layer covering the semiconductor substrate; A self-healing encapsulation structure is formed in the interlayer dielectric layer, the self-healing encapsulation structure including a metal interconnect structure and a self-healing layer formed between the metal interconnect structure and the interlayer dielectric layer, the self-healing layer including a porous layer and an alloy filling the pores of the porous layer, the alloy being used to melt upon heating to repair defects in the metal interconnect structure.
8. The semiconductor device according to claim 7, characterized in that, The porous layer includes a metal-organic framework porous layer.
9. The semiconductor device according to claim 7, characterized in that, The alloy has a melting point of 60℃-200℃, and the alloy includes an indium-tin alloy.
10. The semiconductor device according to claim 7, characterized in that, Also includes: A gate structure is formed on the semiconductor substrate, the gate structure including a gate dielectric layer and a gate electrode layer, wherein the nitrogen doping concentration in the gate dielectric layer decreases in a gradient along the direction from the semiconductor substrate to the gate electrode layer.