Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the cellular structure is located on a part of the surface of the substrate; the scribing channel structure is located on the remaining part of the surface of the substrate and makes contact with the side wall of the cellular structure, the scribing channel structure is made of a low-K dielectric material and / or a high-heat-conduction dielectric material, the relative dielectric constant of the low-K dielectric material is smaller than 3.9, and the heat conductivity of the high-heat-conduction dielectric material is larger than 10 W / mK. The problem that in the prior art, the scribing channel of a traditional SiC MOS device is poor in reliability is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a semiconductor device. Background Technology

[0002] Silicon-based IGBTs dominate high-voltage, high-current applications, but they cannot withstand high-frequency operation and have high power consumption. SiC, on the other hand, with its high voltage and high temperature resistance, allows it to achieve the same voltage withstand capability as silicon-based IGBTs using simpler MOSFET devices, while avoiding their high energy consumption. Under the same conditions, silicon carbide MOSFETs reduce energy loss by 66% compared to silicon-based IGBTs of the same specifications, primarily due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used in inverters for driving and controlling motors, on-board chargers, and fast-charging piles. In photovoltaic power generation, leading photovoltaic inverter companies have already adopted SiC power devices to replace silicon devices. In semiconductor manufacturing, the dicing track is the area on the wafer used to cut and separate chips; the dicing track of traditional SiC MOS devices has poor reliability. Summary of the Invention

[0003] The main objective of this application is to provide a semiconductor structure and semiconductor device to solve the problem of poor reliability of the dicing traces in traditional SiC MOS devices in the prior art.

[0004] To achieve the above objectives, according to one aspect of this application, a semiconductor structure is provided, comprising: a substrate; a cell structure located on a portion of the surface of the substrate; and a scribe line structure located on the remaining portion of the surface of the substrate and in contact with the sidewalls of the cell structure, wherein the material of the scribe line structure comprises a low-k dielectric material and / or a high thermal conductivity dielectric material, wherein the relative permittivity of the low-k dielectric material is less than 3.9, and the thermal conductivity of the high thermal conductivity dielectric material is greater than 10 W / mK.

[0005] Optionally, the dicing channel structure includes: a dicing channel body located on the substrate; a trench located in the dicing channel body; and a filling layer located in the trench, wherein the surface of the filling layer away from the substrate is flush with the surface of the dicing channel structure away from the substrate, and the material of the filling layer includes the low-k dielectric material or the high thermal conductivity dielectric material.

[0006] Optionally, the sidewall of the trench has a plurality of steps connected in sequence, at least two of the steps having different widths in a first direction, the first direction intersecting the thickness direction of the substrate.

[0007] Optionally, the difference in width between any two steps in the first direction is 2μm-20μm.

[0008] Optionally, the filling layer is made of the low-K dielectric material, and the sidewalls of the trench have a plurality of sequentially connected steps, the number of which is 2-5, and the depth of the steps in a second direction is 5μm-30μm, the second direction being parallel to the thickness direction of the substrate.

[0009] Optionally, the filling layer is made of the high thermal conductivity medium material, and the sidewall of the trench has a plurality of steps connected in sequence, the number of steps being 3-5, and the depth of the steps in a second direction being 10μm-50μm, the second direction being parallel to the thickness direction of the substrate.

[0010] Optionally, the filler layer is made of the low-k dielectric material, and the dicing track body is made of the high thermal conductivity dielectric material or silicon carbide; or, the filler layer is made of the high thermal conductivity dielectric material, and the dicing track body is made of the low-k dielectric material or silicon carbide.

[0011] Optionally, the groove extends through the dicing channel body, the filling layer is made of the high thermal conductivity medium material, and the dicing channel body is made of the low K medium material.

[0012] Optionally, the width of the trench in the second direction is 1 / 3 to 2 / 3 of the width of the dicing structure in the second direction, and the second direction is parallel to the thickness direction of the substrate.

[0013] According to another aspect of this application, a semiconductor device is provided, comprising: any of the semiconductor structures described herein.

[0014] The semiconductor structure using the technical solution of this application includes a substrate, a cell structure located on the substrate, and a scribe line structure. The scribe line structure is in contact with the sidewalls of the cell structure. The material of the scribe line structure includes a low-k dielectric material and / or a high thermal conductivity dielectric material. Compared with the poor reliability of the scribe line in traditional SiC MOS devices in the prior art, this application uses a low-k dielectric material to fill the area where the scribe line is located, which can significantly reduce signal interference and crosstalk during transmission. The low dielectric constant material helps to reduce the coupling effect of the electric field, thereby reducing mutual interference between signals. This is crucial for high-frequency, high-density integrated circuits, improving the stability and reliability of the device. By using a high thermal conductivity dielectric material in the scribe line structure, the thermal conductivity performance of the semiconductor device can be effectively improved. The introduction of high thermal conductivity material helps to quickly dissipate the heat generated during chip operation, avoiding local overheating, thereby extending the chip's lifespan and improving the stability and reliability of the device. Attached Figure Description

[0015] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown;

[0017] Figure 2 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown;

[0018] Figure 3 A cross-sectional schematic diagram of another semiconductor structure provided according to an embodiment of this application is shown.

[0019] The above figures include the following reference numerals:

[0020] 10. Substrate; 11. Cell structure; 12. Dicing channel structure; 121. Dicing channel body; 122. Filler layer; 123. Step. Detailed Implementation

[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0022] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As described in the background section, the dicing reliability of traditional SiC MOS devices in the prior art is poor. To solve the above problems, embodiments of this application provide a semiconductor structure and a semiconductor device.

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] This application provides a semiconductor structure, such as... Figures 1 to 3 As shown, it includes:

[0028] Substrate 10;

[0029] Cellular structure 11 is located on a portion of the surface of the substrate 10;

[0030] The dicing channel structure 12 is located on the remaining surface of the substrate 10 and is in contact with the sidewall of the cell structure 11. The material of the dicing channel structure 12 includes a low-k dielectric material and / or a high thermal conductivity dielectric material. The relative permittivity of the low-k dielectric material is less than 3.9, and the thermal conductivity of the high thermal conductivity dielectric material is greater than 10 W / mK.

[0031] In practical applications, those skilled in the art can flexibly select appropriate low-K dielectric materials and high thermal conductivity dielectric materials according to actual needs, and this application does not impose specific restrictions in this regard.

[0032] For example, the low-k dielectric material is preferably fluorinated silica or porous silica with a kJ / kJ of 2.5-3.5; the high thermal conductivity dielectric can be boron nitride or alumina, preferably an epoxy resin composite material of boron nitride.

[0033] In the above embodiments, the semiconductor structure includes a substrate, a cell structure located on the substrate, and a scribe line structure. The scribe line structure is in contact with the sidewalls of the cell structure. The material of the scribe line structure includes a low-k dielectric material and / or a high thermal conductivity dielectric material. Compared with the poor reliability of the scribe line in conventional SiC MOS devices in the prior art, this application uses a low-k dielectric material to fill the area where the scribe line is located, which can significantly reduce signal interference and crosstalk during transmission. The low dielectric constant material helps to reduce the coupling effect of the electric field, thereby reducing mutual interference between signals. This is crucial for high-frequency, high-density integrated circuits, improving the stability and reliability of the device. By using a high thermal conductivity dielectric material in the scribe line structure, the thermal conductivity performance of the semiconductor device can be effectively improved. The introduction of high thermal conductivity material helps to quickly dissipate the heat generated during chip operation, avoiding local overheating, thereby extending the chip's lifespan and improving the stability and reliability of the device.

[0034] In one alternative, such as Figures 1 to 3 As shown, the dicing channel structure 12 includes: a dicing channel body 121 located on the substrate 10; a trench (not shown) located in the dicing channel body 121; and a filler layer 122 located in the trench. The surface of the filler layer 122 away from the substrate 10 is flush with the surface of the dicing channel structure 12 away from the substrate 10. The material of the filler layer 122 includes the low-k dielectric material or the high thermal conductivity dielectric material. In this embodiment, by designing and forming trenches in the dicing channel body and filling the trenches with low-k dielectric material or high thermal conductivity dielectric material, the reliability of the dicing channel can be further improved.

[0035] Specifically, the filling layer completely filled the aforementioned trench.

[0036] Specifically, Figures 1 to 3 In the first direction, there are two cell structures 11, and the slicing channel structure 12 is located between the two cell structures 11.

[0037] According to some exemplary embodiments of this application, such as Figure 1 and Figure 2As shown, the sidewalls of the aforementioned trench have multiple sequentially connected steps 123, with at least two steps 123 having different widths in a first direction, which intersects the thickness direction of the substrate 10. In this embodiment, the use of stepped trenches can effectively disperse stress generated under high temperature and high pressure environments, reducing the formation and propagation of cracks. This structural change makes the stress distribution more uniform, thereby improving the reliability and stability of the device under extreme conditions. By using stepped trenches and then filling them with a high thermal conductivity medium, the heat conduction path of the device is optimized. The high thermal conductivity medium filling these steps can form a multi-layer thermally conductive structure, effectively improving heat conduction efficiency and dissipating the heat generated during chip operation more quickly, avoiding the temperature rise caused by heat accumulation inside the chip.

[0038] Specifically, the trench is a stepped trench; the bottom surface of the step closest to the middle of the trench in the first direction can be flush with the surface of the scribe line structure near the substrate (i.e., the trench penetrates the scribe line body), or it can be not flush (i.e., the trench does not penetrate the scribe line body). This application does not impose any specific restrictions on this.

[0039] It should be noted that the width of multiple steps in the first direction can be the same, or at least two steps can have different widths in the first direction. Those skilled in the art can flexibly set the width of each step according to actual needs, and this application does not impose specific restrictions on this.

[0040] According to some other exemplary embodiments of this application, the width difference between any two of the above-mentioned steps in the first direction is 2μm-20μm. In this embodiment, the width difference between any two steps in the first direction is set to 2μm to 20μm, which ensures that the structural change of the stepped groove is gradual, further dispersing the stress concentration in the dicing area. Especially under high temperature and high pressure working environment, it can further reduce the risk of crack propagation. By adjusting the difference in step width, the stress distribution is further optimized, and the device damage caused by thermal expansion coefficient mismatch is further reduced, thereby further improving the reliability and yield of the device.

[0041] In other embodiments, the filling layer is made of the low-k dielectric material, and the sidewalls of the trench have multiple sequentially connected steps, the number of which is 2-5. The depth of each step in a second direction is 5μm-30μm, and the second direction is parallel to the thickness direction of the substrate. In this embodiment, the trench sidewalls are designed with 2 to 5 sequentially connected steps, each step having a depth ranging from 5μm to 30μm in the second direction. This structure can further effectively disperse stress concentration in the dicing area and further reduce the risk of crack propagation, especially under harsh testing conditions of high temperature and high pressure.

[0042] According to some other exemplary embodiments of this application, the material of the filling layer includes the aforementioned high thermal conductivity dielectric material. The sidewalls of the trenches have multiple sequentially connected steps, the number of which is 3-5. The depth of the steps in a second direction is 10μm-50μm, and the second direction is parallel to the thickness direction of the substrate. In this embodiment, the depth of the steps (10μm to 50μm) and the presence of multiple steps provide more surface area, which is beneficial for the contact and distribution of the high thermal conductivity dielectric material. The high thermal conductivity dielectric material is filled in these trenches, which can greatly improve the heat transfer efficiency, allowing heat to dissipate more quickly from the chip surface to the surrounding environment, reducing the chip's operating temperature, and improving the stability and lifespan of the device.

[0043] In some other alternatives to this application, such as Figures 1 to 3 As shown, the material of the filling layer 122 includes the low-K dielectric material, and the material of the dicing track body 121 includes the high thermal conductivity dielectric material or silicon carbide; or, the material of the filling layer 122 includes the high thermal conductivity dielectric material, and the material of the dicing track body 121 includes the low-K dielectric material or silicon carbide. In this embodiment, the trenches are filled with a low-k dielectric material, which reduces signal interference and crosstalk in the scribe line area, improving the electrical performance and signal integrity of the device. The scribe line body uses a high thermal conductivity dielectric material or silicon carbide, which increases thermal conductivity, improves the heat dissipation capacity of the device, reduces heat accumulation during long-term high-temperature testing, thereby reducing the risk of device damage due to overheating and improving the reliability and lifespan of the device. The trenches are filled with a high thermal conductivity dielectric material, which optimizes the heat conduction path, accelerates the conduction of heat energy from the chip surface to the heat sink, reduces the chip operating temperature, and improves thermal management capabilities. The use of a low-k dielectric material or silicon carbide in the scribe line body helps reduce dielectric coupling, reduces signal interference and loss, while maintaining the high voltage and high temperature resistance of silicon carbide material, further improving the integration and performance of the device.

[0044] According to some further exemplary embodiments of this application, such as Figure 3 As shown, the trench penetrates the dicing track body 121, the filling layer 122 is made of the high thermal conductivity dielectric material, and the dicing track body 121 is made of the low-k dielectric material. In this embodiment, the combined use of the high thermal conductivity dielectric material and the low-k dielectric material not only solves the heat dissipation problem but also ensures signal transmission efficiency. This material selection and matching can better adapt to the working requirements of SiC MOS devices under high temperature and high pressure environments, while reducing potential problems caused by traditional material mismatch, such as structural damage caused by thermal expansion coefficient mismatch.

[0045] In other embodiments, the width of the trench in the second direction accounts for 1 / 3 to 2 / 3 of the width of the dicing structure in the second direction, and the second direction is parallel to the thickness direction of the substrate. In this embodiment, the filling material in the trench has high thermal conductivity. This width ratio can further optimize the heat conduction path and further improve thermal management capabilities. During the operation of the semiconductor device, the heat generated can be dissipated more quickly through the high thermal conductivity medium in the trench, avoiding device damage caused by high heat and extending the device's service life.

[0046] It should be noted that the scribe lines of traditional SiC MOS devices are typically filled with conventional dielectric materials such as silicon dioxide. With the shrinking of device size and increasing integration density, stress concentration and signal interference in the scribe line region have become increasingly prominent, especially under high-temperature and high-pressure operating environments. Traditional scribe line structures are prone to crack propagation due to thermal stress, affecting device reliability and yield. Furthermore, traditional SiC device scribe lines use simple trenches filled with SiO2, generating a large amount of heat during long-term high-temperature wafer testing. If this heat cannot be dissipated in time, it can lead to irreversible damage to the device. This application, through a stepped trench structure design, disperses stress concentration in the scribe line region, reducing the risk of crack propagation. Especially during high-temperature and high-pressure testing, the application of low-k dielectric materials reduces signal interference and crosstalk. Compared with traditional scribe line structures, this application reduces the crack initiation rate by more than 40% during high-temperature and high-pressure testing, significantly improving device reliability. This application forms stepped trenches in the scribe line region and then fills them with a high thermal conductivity dielectric material, optimizing the heat conduction path and significantly improving the chip's thermal management capabilities. The chip's temperature is reduced when operating at rated power, and its lifespan is extended.

[0047] Specifically, the low-K dielectric filling process is as follows: 1) After completing all front-side processes, multi-step dry step etching is performed on the scribe line, using F-based gas to form stepped trenches on the SiC substrate. Each stepped trench consists of at least two steps with different widths, and the number of steps is 2-5, extending from the surface of the scribe line into the interior of the scribe line. The depth of each step is 5-30 μm, and the width difference is 2-20 μm; 2) Low-K dielectric material is filled. The relative permittivity of the low-K dielectric material is less than 3.9, preferably fluorinated silicon dioxide or porous silica with a permittivity of 2.5-3.5. The low-K dielectric material completely fills the stepped trenches and is flush with the upper surface of the scribe line structure. The substrate, cell structure, and scribe line structure constitute a wafer; 3) Then, the back side of the substrate is thinned, the back side process is performed, CP testing is performed, and wafer-level reliability testing is performed in sequence. Finally, scribe is completed.

[0048] Specifically, the process flow for filling with a high thermal conductivity dielectric is as follows: 1) After completing all front-side processes, perform multi-step dry step etching on the scribe line, using F-based gas, to form stepped trenches on the SiC substrate. Each stepped trench consists of at least two steps with different widths, with 3-5 steps extending from the surface of the scribe line into its interior. Each step has a depth of 10-50 μm and a width difference of 2-20 μm; 2) Completely fill the stepped trenches with a high thermal conductivity dielectric material, integrating it with the scribe line structure. The upper surface is flush, and the substrate, cell structure and dicing structure constitute the wafer. The high thermal conductivity medium material contains boron nitride or alumina filler. The thermal conductivity of the high thermal conductivity medium material is greater than 10W / mK. It is preferred to fill the epoxy resin composite material with boron nitride. This design can optimize the heat conduction path, significantly improve the thermal management capability of the chip, reduce the temperature of the chip when operating at rated power, and improve the chip lifespan; 3) Then, the back side of the substrate is thinned, the back side process is carried out in sequence, CP test, wafer-level reliability test, and finally the dicing is completed.

[0049] This application also provides a semiconductor device, including any of the above-described semiconductor structures.

[0050] Specifically, the semiconductor device in this application may be a SiC MOS device.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0053] In the semiconductor structure of this application, the semiconductor structure includes a substrate, a cell structure located on the substrate, and a scribe line structure. The scribe line structure is in contact with the sidewalls of the cell structure. The material of the scribe line structure includes a low-k dielectric material and / or a high thermal conductivity dielectric material. Compared with the poor reliability of the scribe line in traditional SiC MOS devices in the prior art, this application uses a low-k dielectric material to fill the area where the scribe line is located, which can significantly reduce signal interference and crosstalk during transmission. The low dielectric constant material helps to reduce the coupling effect of the electric field, thereby reducing mutual interference between signals. This is crucial for high-frequency, high-density integrated circuits, improving the stability and reliability of the device. By using a high thermal conductivity dielectric material in the scribe line structure, the thermal conductivity performance of the semiconductor device can be effectively improved. The introduction of high thermal conductivity material helps to quickly dissipate the heat generated during chip operation, avoiding local overheating, thereby extending the chip's lifespan and improving the stability and reliability of the device.

[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A cellular structure located on a portion of the surface of the substrate; A scribe line structure is located on the remaining surface of the substrate and in contact with the sidewalls of the cell structure. The material of the scribe line structure includes a low-k dielectric material and / or a high thermal conductivity dielectric material. The relative permittivity of the low-k dielectric material is less than 3.9, and the thermal conductivity of the high thermal conductivity dielectric material is greater than 10 W / mK.

2. The semiconductor structure according to claim 1, characterized in that, The slicing channel structure includes: The dicing track body is located on the substrate; The groove is located in the slicing track body; A filler layer is located in the trench, the surface of the filler layer away from the substrate being flush with the surface of the scribe line structure away from the substrate, and the material of the filler layer includes the low-k dielectric material or the high thermal conductivity dielectric material.

3. The semiconductor structure according to claim 2, characterized in that, The sidewall of the trench has a plurality of steps connected in sequence, at least two of the steps having different widths in a first direction, the first direction intersecting the thickness direction of the substrate.

4. The semiconductor structure according to claim 3, characterized in that, The difference in width between any two steps in the first direction is 2μm-20μm.

5. The semiconductor structure according to claim 2, characterized in that, The filling layer is made of the low-K dielectric material, and the sidewalls of the trench have a plurality of steps connected in sequence, the number of which is 2-5. The depth of the steps in a second direction is 5μm-30μm, and the second direction is parallel to the thickness direction of the substrate.

6. The semiconductor structure according to claim 2, characterized in that, The filling layer is made of the high thermal conductivity medium material, and the sidewalls of the trench have a plurality of steps connected in sequence, the number of steps being 3-5, and the depth of the steps in a second direction being 10μm-50μm, the second direction being parallel to the thickness direction of the substrate.

7. The semiconductor structure according to claim 2, characterized in that, The filler layer is made of the low-k dielectric material, and the dicing track body is made of the high thermal conductivity dielectric material or silicon carbide; or, the filler layer is made of the high thermal conductivity dielectric material, and the dicing track body is made of the low-k dielectric material or silicon carbide.

8. The semiconductor structure according to claim 2, characterized in that, The groove penetrates the dicing channel body, the filling layer is made of the high thermal conductivity medium material, and the dicing channel body is made of the low K medium material.

9. The semiconductor structure according to claim 8, characterized in that, The width of the trench in the second direction is 1 / 3 to 2 / 3 of the width of the dicing structure in the second direction, and the second direction is parallel to the thickness direction of the substrate.

10. A semiconductor device, characterized in that, include: The semiconductor structure according to any one of claims 1 to 9.

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