Separated semiconductor chip on interposer through substrate via

Abstract

Devices and systems having interposers that do not include through-substrate vias and methods of forming the same are disclosed herein. In one example, a microelectronic component includes an interposer and one or more integrated circuit (IC) dies coupled to the interposer. The interposer includes one or more conductive traces and one or more vias, but the interposer does not include through-substrate vias. A respective IC die is electrically coupled to the interposer via dielectric-to-dielectric bonds and metal-to-metal bonds at an interface between the interposer and the respective IC die.

Description

BACKGROUND

[0001] In some cases, semiconductor chips can use a passive interposer with through-substrate vias (TSVs) to electrically connect multiple dies to each other and to other integrated circuit components. For example, respective dies can be connected to a front side of the interposer, and a back side of the interposer can be connected to another component such as a package substrate or a circuit board. In addition, the interposer can include a substrate with layers of conductive traces and vias to provide wiring to and from the dies on the front side; and TSVs extending through the substrate to provide wiring between the dies on the front side and other IC components on the back side (e.g., for power delivery and off-chip signaling). However, TSVs have various drawbacks, including higher resistive losses for power delivery and signaling, which degrades performance. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figures 1A-1B An example of separate semiconductor chips on an interposer without through-substrate vias (TSVs) is shown.

[0003] Figures 2A-2J An example process flow for forming separate semiconductor chips on a TSV-less interposer is shown.

[0004] Figure 3 An example of a microelectronic assembly with separate semiconductor chips is shown, in accordance with certain embodiments.

[0005] Figure 4 An example process flow for forming a device or system with separate semiconductor chips is shown, in accordance with certain embodiments.

[0006] Figures 5A-5C An example of a separate semiconductor chip is shown, in accordance with certain embodiments.

[0007] Figure 6 A top view of a wafer and dies that can be included in a microelectronic assembly is shown.

[0008] Figure 7 A cross-sectional side view of an integrated circuit device assembly is shown.

[0009] Figure 8 A block diagram of an example electrical apparatus is shown. DETAILED DESCRIPTION

[0010] Isolated semiconductor chips can use a passive interposer to electrically connect multiple isolated active dies or "chiplets" to each other and to other integrated circuit (IC) components. In particular, passive interposers are commonly used when all active logic is on the chiplets (e.g., central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), and high bandwidth memory (HBM) modules — and only wires are needed to connect the chiplets). In some cases, for example, respective chiplets can be connected to a front side of the interposer using micro ball grid array (μBGA) interconnect or hybrid bond interconnect (HBI), and a back side of the interposer can be connected to another substrate (e.g., a package substrate or a circuit board, which can include other IC components) using ball grid array (BGA) interconnect. Further, the interposer can include a substrate with layers of conductive traces and vias to provide wiring to and from the chiplets on the front side; and through-substrate vias (TSVs) extending through the substrate to provide wiring between the chiplets on the front side and the other IC components on the back side (e.g., for power delivery and off-chip signaling). For example, an interposer formed on a silicon substrate can include through-silicon vias extending through the silicon substrate to provide connections between the front side and the back side of the interposer.

[0011] However, TSVs have various drawbacks, including higher resistive losses for power delivery and signaling, which reduces performance. For example, TSVs increase the electrical resistance of the electrical paths used for power delivery and signaling. This increased electrical resistance reduces the ability to deliver power, which reduces performance. TSVs are also very tall and have a high aspect ratio, which creates capacitive coupling with other TSVs. This capacitive coupling, along with the increased electrical resistance, causes signal integrity loss of input / output (I / O) between the chiplets. This is particularly problematic for high speed applications (e.g., high speed serializer / deserializer (SerDes)) and can require the use of additional metal layers (e.g., package side metal (PSM) layers and / or redistribution layers (RDL)) for isolation between the TSVs and the interconnect bumps or pads.

[0012] Accordingly, the present disclosure presents embodiments of a separate semiconductor die on a passive interposer without through-substrate vias (TSVs). In some embodiments, multiple separate dies (also referred to herein as“chiplets”) are integrated on a substrate-less and TSV-less interposer using hybrid-bonded interconnects (HBIs) and a structural substrate on top. In hybrid-bonded interconnects, also referred to as direct-bonded interconnects, the bond pads on two opposing semiconductor dies and / or substrates are interconnected such that the respective metal bond pads on the dies are bonded directly together through a metal-to-metal bond (e.g., copper-to-copper bond) without an intermediate conductive material such as a solder compound between the bond pads. Similarly, the dielectric material adjacent to the respective metal pads is also bonded directly together through a dielectric-to-dielectric bond without an intermediate dielectric material such as an adhesive, molding compound, underfill material, etc. For example, the interposer is formed by patterning the interconnects (e.g., metal layers of conductive traces and / or pads connected by vias) on a substrate without patterning any TSVs through the substrate. The chiplets are then attached to the front side of the interposer via hybrid-bonded interconnects (HBIs), and a structural substrate is attached on top of the chiplets to increase structural and mechanical stability. The original substrate on which the interposer is formed is then removed (e.g., by etching or grinding) to expose the first conductive layer (e.g., first metal trace, pad, or via layer) on the backside of the interposer, and forming bumps to form a ball grid array (BGA) interconnect on the backside of the interposer is performed. In this way, the completed semiconductor die includes an interposer without a substrate or TSVs.

[0013] The described embodiments can provide various advantages. For example, the described embodiments eliminate the need for TSVs in a passive interposer, which enables the formation of separate semiconductor dies on a substrate-less and TSV-less interposer. In this way, the electrical resistance losses and capacitive coupling caused by TSVs are eliminated, which improves power delivery to the chiplets and increases signal integrity for high-speed signals, which results in improved power efficiency and performance. Furthermore, the processing required for TSV formation is no longer needed, which reduces manufacturing costs.

[0014] Furthermore, while the illustrated embodiments are shown with dies and chiplets implemented with front-side power delivery, the substrate-less and TSV-less interposer can also be used with dies and chiplets implemented with back-side power delivery (e.g., where power is delivered via interconnects on the backside of the die / chiplet substrate).

[0015] Figures 1A-1BCross-sectional views of isolated semiconductor chips 100a, 100b on a passive interposer 102 without through-substrate vias (TSVs) are shown. Specifically, the isolated semiconductor chips 100a, 100b include a plurality of active dies 110 hybridally bonded to the interposer 102, wherein a structural substrate 120 is attached over the dies 110 to increase structural and mechanical stability. Furthermore, the interposer 102 does not include a substrate or any TSVs. As a result, interconnect bumps 104 on the back side of the interposer 102 fall on the interconnect layer 106 of the interposer 102, rather than on the TSVs. For example, in Figure 1A In chip 100a, bump 104 rests directly on the first metal layer 106 of interposer 102. However, in Figure 1B In chip 100b, bump 104 rests on via or pad structure 103 beneath the first metal layer 106 of interposer 102. Via or pad structure 103 can be formed to avoid exposing the first metal layer 106 during processing. The absence of TSVs in interposer 102 eliminates resistive losses and capacitive coupling caused by TSVs, which improves power efficiency and signal integrity and results in higher overall performance.

[0016] Intermediate layer 102 includes patterned conductive traces and vias (together) Figure 1B The chip 100b has a metallized or interconnect layer 106 (bump bonding pads 103) separated by an interlayer dielectric (ILD) layer 105. The interposer 102 also includes conductive bumps 104 and pads 108 on the back and front sides, respectively, which are electrically coupled to each other via the interconnect layer 106. The bumps 104 can be used to electrically couple the back side of the interposer 102 to another component (not shown), such as a package substrate or circuit board, via a ball grid array (BGA) interconnect. The pads 108 are used to electrically couple the die 110 to the front side of the interposer 102 via a hybrid bonding interconnect (HBI), as further described below.

[0017] The corresponding die 110 includes a substrate 112 (e.g., made of silicon) on which active circuitry 114 (e.g., complementary metal-oxide-semiconductor (CMOS) logic, transistors), a metallization or interconnect layer 116 (e.g., patterned as conductive traces and vias), pads 118, and an ILD layer 115 are formed. The active circuitry 114 and pads 118 are electrically coupled through the interconnect layer 116. Furthermore, the pads 118 are used to electrically couple die 110 to the front side of the interposer 102 via HBI interconnects, as further described below.

[0018] In the illustrated embodiment, the corelets 110 are electrically coupled to the interposer 102 via hybrid bond interconnects (HBIs). Specifically, the corelets 110 are hybrid bonded down onto the interposer 102 such that the front side of the corelets 110 are bonded to the front side of the interposer 102. In this way, hybrid dielectric-to-dielectric and metal-to-metal bonds are formed between the corelets 110 and the interposer 102 such that the dielectric layer 115 on the face of the corelets 110 is bonded to the dielectric layer 105 on the face of the interposer 102, and the pads 118 on the corelets 110 are bonded to the pads 108 on the interposer 102.

[0019] The remaining areas between the corelets 110 are filled with ILD 125. In addition, the handle substrate 120 is attached over the corelets 110 via a bonding layer 122 (e.g., an adhesive material such as silicon oxide, silicon nitride).

[0020] In this disclosure, a through-substrate via (TSV) can refer to a via that extends through the entire thickness of a substrate (e.g., between the front side / back side), such as a through-silicon via in a silicon substrate, a through-glass via in a glass substrate, etc.

[0021] An interposer that does not have through-substrate vias (TSVs) can be referred to herein as a “TSV-less” interposer, and an interposer that does not have a substrate (and thus no TSVs) can be referred to herein as a “substrate-less” and / or “TSV-less” interposer.

[0022] The terms “corelet” and “die” can be used interchangeably herein. In some cases, a corelet can refer to an integrated circuit (IC) die or component that implements a subset of the functionality of a more complex component or system (e.g., a functional block), which can be integrated with other corelets to implement a complete component or system. In some embodiments, for example, a corelet and / or die can individually or collectively implement some or all of the functionality of one or more system-on-chips (SoCs), microprocessors (e.g., central processing units (CPUs), graphics processing units (GPUs), vision processing units (VPUs), neural processing units (NPUs), other XPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), network interface controllers (NICs), input / output (I / O) devices and controllers, persistent storage devices and / or memory devices and controllers, etc.

[0023] It will be appreciated that the semiconductor chips 100a, 100b are shown by way of example only, and that many variations and alternative embodiments are within the scope of the present disclosure. In various embodiments, for example, certain elements of the chips 100a, 100b can be modified, replaced, rearranged, omitted, and / or added.

[0024] As an example, in various embodiments, the chips 100a, 100b can include any number of die 110, pads 103, 108, 118, bumps 104, and interconnect layers 106, 116.

[0025] In various embodiments, the die 110 can be attached to the interposer 102 using various arrangements, including bonding to a surface of the interposer 102 (e.g., as shown in Figures 1A-1B FIG. 1) or embedding within the interposer 102 (e.g., in a cavity), etc.

[0026] In various embodiments, any suitable interconnect technology can be used for the respective interconnects on the front side and back side of the interposer 102 (e.g., between the interposer 102 and the die 110 on the front side and between the interposer 102 and another component (not shown) on the back side), including, but not limited to, hybrid-bonded interconnects (HBIs), micro ball grid array (μBGA) interconnects, and / or ball grid array (BGA) interconnects.

[0027] In various embodiments, certain elements / layers of the chips 100a, 100b can have different arrangements than those shown in Figures 1A-1B FIG. 1. Moreover, in some embodiments, the chips 100a, 100b can include various other components not shown in the illustrated embodiments. In some embodiments, for example, the interposer 102 and / or any of the dies 110 can include one or more metal- insulator-metal (MIM) devices (e.g., between the interconnect layers 106, 116), such as MIM capacitors or MIM diodes.

[0028] Examples of various materials that can be used to form the respective elements and / or layers of the semiconductor chips 100a, 100b are provided below. However, in various embodiments, certain elements / layers of the chips 100a, 100b can be made of materials other than those described below.

[0029] The conductive contacts (e.g., bumps 104, pads 108, 118) and interconnect layers / structures (e.g., conductive traces / vias 106, 116, pads 103) can be made of any suitable conductive or metallic material, including, but not limited to, aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), and compounds / alloys thereof (e.g., titanium nitride (TiN)). Thus, in some embodiments, the conductive contacts 104, 108, 118 and interconnect layers / structures 103, 106, 116 can be made of a material that includes elements such as aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), and / or nitrogen (N).

[0030] The core particle substrate 112 can be made of any suitable material, including but not limited to silicon.

[0031] The structure substrate 120 can be made of any suitable material, including but not limited to silicon.

[0032] The bonding layer 122 can be made of any suitable adhesive material, including but not limited to silicon oxide (e.g., Si02) and / or silicon nitride (e.g., SiN, Si3N4). Thus, in some embodiments, the bonding layer 122 can be made of a material that includes elements such as silicon (Si), oxygen (O), and / or nitrogen (N).

[0033] The interlayer dielectric (ILD) 105, 115, 125 can be made of any suitable dielectric material, including but not limited to silicon dioxide (Si02) (and / or other silicon oxides), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or any other isolation oxide. Thus, in some embodiments, the ILD 105, 115, 125 can be made of a material that includes elements such as silicon (Si), oxygen (O), nitrogen (N), and / or carbon (C).

[0034] Additional embodiments of a separate semiconductor chip on a TSV-less interposer, and process flows for forming the same, are described in connection with FIGS. 2-5. The concepts described above with respect to the chips 100a, 100b (including any modifications and variations thereof) also apply to the other embodiments described in this disclosure, and vice versa.

[0035] Figures 2A-2J An example process flow for forming a separate semiconductor chip 200 on a TSV-less interposer 202 is shown. In the example shown, Figures 2A-2J Cross-sectional views (x-z plane) after various steps of the process flow are shown. It will be understood in light of this disclosure that the process flow shown is merely one example method for implementing a separate semiconductor chip 200 on a TSV-less interposer 202.

[0036] The illustrated process flow eliminates the need for through substrate vias (TSVs) in the passive interposer and uses hybrid bonding interconnect (HBI) technology to attach a die (e.g., a chiplet) to the interposer. In particular, no deep trenches are created in the base substrate of the interposer for TSVs. Rather, metal layers (e.g., conductive traces) of the interposer are processed on the base substrate in the same manner as metal layers in other semiconductor manufacturing processes. Once the metal layers and bond pads are processed, the interposer and die are processed using an HBI attachment flow, in which the die is attached to the interposer using a chip-to-wafer (C2W) or wafer-to-wafer (W2W) hybrid bonding process, thereby forming a hybrid bonding interconnect between the die and the interposer. This process requires careful alignment and cleaning (e.g., similar to other silicon process flows). After attachment, the base substrate (e.g., the silicon portion) of the interposer is removed (e.g., by etching or grinding) to expose the first conductive layer (e.g., the first metal / traces, via, or pad layer) of the interposer. A bump process is then performed on the interposer to complete processing.

[0037] The illustrated process flow will now be described in further detail with reference to Figures 2A-2J The illustrated process flow will now be described in further detail with reference to

[0038] In Figure 2A In some embodiments, the base substrate 201 can include silicon (e.g., a silicon wafer or panel).

[0039] In Figure 2B In some embodiments, the base substrate 201 can include silicon (e.g., a silicon wafer or panel).

[0040] In some embodiments, for example, one or more alternating dielectric layers 205 and metal layers 206 can be formed on the base substrate 201 such that the metal layers 206 are separated by the dielectric layers 205. The metal layers 206 can be patterned (e.g., etched) into conductive traces 206, and vias 207 can be formed (e.g., etched and filled) through the alternating dielectric layers 205 to electrically couple the traces 206 in different layers.

[0041] In addition, conductive (e.g., metal) pads 208 can be formed on the front side (and / or back side) of the interposer 202 that are electrically coupled to the vias 207 and traces 206, thereby enabling other components to be electrically coupled to the interposer 202, for example, Figure 2DIC dies 210a, 210b. In some embodiments, for example, the pads 208 can be hybrid bond interconnect (HBI) pads embedded in the dielectric layer 205, a micro ball grid array (μBGA) or ball grid array (BGA) pad, and / or any other type of metal pad.

[0042] Notably, no through-substrate vias are needed in the base substrate 201 because the base substrate 201 will be removed in Figure 2I result, the interposer 202 does not include any through-substrate vias.

[0043] In some embodiments, the interposer 202 can also include other components, such as one or more metal- insulator-metal (MIM) devices (not shown). For example, the interposer 202 can include one or more MIM capacitors and / or MIM diodes among the layers of traces 206 and vias 207.

[0044] In Figure 2C the plurality of integrated circuit (IC) dies 210a, 210b (e.g., chiplets) are picked up and placed down on the front side of the interposer 202 such that the pads 218 on the dies 210a, 210b are aligned with the pads 208 on the interposer 202.

[0045] The respective dies 210a, 210b can include a substrate with active circuitry (not shown) and interconnects including one or more layers of electrically conductive traces 216, vias 217, and / or pads 218 separated by a dielectric layer 215, which can be used to electrically couple the active circuitry in the dies 210a, 210b to the interposer 202.

[0046] In some embodiments, the dies 210a, 210b can also include other components, such as one or more metal- insulator-metal (MIM) devices (not shown). For example, the dies 210a, 210b can include one or more MIM capacitors and / or MIM diodes among the layers of traces 216 and vias 217.

[0047] In Figure 2D the dies 210a, 210b are hybrid bonded to the interposer 202 such that the dielectric layer 215 on the dies 210a, 210b and the interposer 202, respectively, are bonded together and the pads 218 on the dies 210a, 210b and the pads 208 on the interposer 202, respectively, are bonded together, thereby forming hybrid dielectric-to-dielectric and metal-to-metal bonds between the dies 210a, 210b and the interposer 202. In this way, the dies 210a, 210b are attached and electrically coupled to the interposer 202 via hybrid bond interconnects (HBIs).

[0048] In some embodiments, a dielectric liner 213 is formed over the interposer 202 and the dies 210a, 210b, and the area above the liner 213 is filled with a dielectric layer 225 (e.g., oxide). Figure 2E

[0049] In some embodiments, the dielectric liner 213 and the dielectric layer 225 are planarized (e.g., by lapping). Figure 2F

[0050] In some embodiments, a bonding layer 222 is formed over the dielectric layers 213, 225 (e.g., by depositing an adhesive dielectric such as oxide). Figure 2G

[0051] In some embodiments, a structure substrate 220 (e.g., a structure silicon wafer or panel) is attached to the top of the dies 210a, 210b via the bonding layer 222. In this way, the dielectric fill 225 between the structure substrate 220 and the dies 210a, 210b provides sufficient mechanical strength to enable removal of the base substrate 201 (e.g., as shown in FIG. 2B). Figure 2H Figure 2I

[0052] In some embodiments, the base substrate 201 is removed by lapping and polishing (e.g., chemical mechanical polishing (CMP)) to expose the dielectric layer 205 on the backside of the interposer 202. Figure 2I

[0053] In some embodiments, vias 207 are etched through the first metal layer 206 on the backside of the interposer 202, and bumps 204 are formed on the backside of the interposer 202 such that they land on the vias 207. Figure 2J

[0054] At this point, the singulated semiconductor chip 200 can be completed. In some embodiments, the semiconductor chip 200 can then be attached and electrically coupled to another IC component, such as a package substrate and / or a printed circuit board (PCB), via the bumps 204 on the backside of the interposer 202.

[0055] Figure 3 A cross-sectional view of a microelectronic assembly 300 having singulated semiconductor chips 200a, 200b is shown, in accordance with certain embodiments. The microelectronic assembly 300 can also be referred to herein as an integrated circuit (IC) or IC package. In the illustrated embodiment, the microelectronic assembly 300 includes a plurality of singulated semiconductor chips 200a, 200b that are attached to a structure substrate 220 using a bonding layer 222. Figures 2A-2J ​​​​​​​of the design of the separated semiconductor die 200 (for simplicity, only some reference numerals are shown). For example, each separated semiconductor die 200a, 200b includes a TSV-less interposer 202, a plurality of dies 210a, 210b (e.g., chiplets) hybrid bonded to the interposer 202, and a structure substrate 220 bonded on top of the dies 210a, 210b. Further, the respective die 200a, 200b is attached and electrically coupled to a package substrate 302. Specifically, the conductive bumps 204 on the backside of the interposer 202 are bonded to conductive pads (not shown) on the frontside of the package substrate 302 using solder 306, and the gap between the die 200a, 200b and the package substrate 302 is filled with underfill 308 (e.g., epoxy). The package substrate 302 also includes conductive bumps 304 on the backside that serve as interconnects (e.g., BGA interconnects) to electrically couple the package substrate 302 to another component (not shown). In some embodiments, for example, the backside of the package substrate 302 can be electrically coupled to a printed circuit board (PCB) via the conductive bumps 304.

[0056] Figure 4 An exemplary process flow 400 for forming a device or system having separated semiconductor dies is shown, in accordance with certain embodiments. In some embodiments, for example, the device or system can be or can include a microelectronic assembly or an integrated circuit (IC) package having one or more separated semiconductor dies on a TSV-less interposer, as described throughout this disclosure. It will be appreciated in light of this disclosure that the process flow shown is merely one example method for implementing the example separated semiconductor devices and systems shown and described throughout this disclosure.

[0057] The steps of the process flow shown can be performed using any suitable semiconductor fabrication techniques. For example, film deposition— e.g., deposition of layers, filling portions (e.g., removal portions) of layers, and filling via openings— can be performed using any suitable deposition techniques, including, for example, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD). Further, patterning and removal (e.g., interconnect patterning, forming via openings, and shaping) can be performed using any suitable techniques, e.g., lithography-based patterning / masking and / or etching.

[0058] The process flow begins at block 402 by receiving a first substrate (which can also be referred to as a base substrate). In some embodiments, the base substrate can include silicon (e.g., a silicon wafer).

[0059] The process flow then proceeds to block 404 to form an interposer over the base substrate. For example, the interposer can include one or more electrically conductive traces, vias, and / or pads that collectively form interconnects to electrically couple IC components (e.g., dies, package substrates, circuit boards) that are subsequently attached to the front side and back side of the interposer.

[0060] In some embodiments, for example, one or more interleaved dielectric layers and electrically conductive (e.g., metal) layers can be formed over the base substrate such that the electrically conductive layers are separated by the dielectric layers. The electrically conductive layers can be patterned (e.g., etched) into electrically conductive traces, and vias can be formed (e.g., etched and filled) through intervening dielectric layers to electrically couple the traces in different electrically conductive layers. In addition, electrically conductive (e.g., metal) pads can be formed on the front side and / or back side of the interposer that are electrically coupled to the vias and traces, thereby enabling other components to be electrically coupled to the interposer, such as IC dies attached at block 406. In some embodiments, for example, the pads can be hybrid bond interconnect (HBI) pads embedded in a dielectric layer, a micro ball grid array (μBGA) or ball grid array (BGA) pad, and / or any other type of metal pad.

[0061] Notably, no through-substrate vias are needed in the base substrate because the base substrate will be removed later at block 410. As a result, the interposer does not include any through-substrate vias.

[0062] In some embodiments, an etch stop layer can be formed on the base substrate prior to forming the interposer over the base substrate such that, after the interposer is formed, the etch stop layer is between the base substrate and the interposer. In this way, the etch stop layer will prevent etching into the interposer when the base substrate is etched away later at block 410.

[0063] The process flow then proceeds to block 406 to attach one or more integrated circuit (IC) dies (e.g., chiplets) on the front side of the interposer via first level interconnects (FLIs). In some embodiments, for example, the respective IC dies can be hybrid bonded to the front side of the interposer such that hybrid dielectric-to-dielectric and metal-to-metal bonds are formed at the interface between the interposer and the respective dies, thereby electrically coupling the interposer and the respective dies via hybrid bond interconnects (HBIs). Alternatively, in some embodiments, the respective dies can be attached and electrically coupled to the interposer via micro ball grid array (μBGA) interconnects or ball grid array (BGA) interconnects. In addition, in some embodiments, the respective dies can include processing circuitry, memory circuitry, storage circuitry, and / or communication circuitry.

[0064] The process flow then proceeds to block 408 to receive a second substrate and attach the second substrate over the die. The second substrate can be referred to as a structural substrate. In some embodiments, the structural substrate can include silicon (e.g., a structural silicon wafer). In some embodiments, the structural substrate can be bonded on top of the die using a bonding layer between the die and the structural substrate.

[0065] The process flow then proceeds to block 410 to remove the base substrate, thereby exposing the backside of the interposer. In some embodiments, for example, the base substrate can be removed from the backside of the interposer by grinding or etching away the base substrate, thereby exposing the backside of the interposer. For example, if an etch stop layer is formed between the base substrate and the interposer at block 404, the backside of the base substrate can be etched until the etch stop layer is reached, thereby avoiding etching into the interposer. Once the base substrate is removed, the interposer becomes a “substrate-less” interposer, as it no longer includes a substrate.

[0066] The process flow then proceeds to block 412 to expose portions of the first conductive layer on the backside of the interposer. In some embodiments, for example, the first conductive layer can include one or more conductive traces (e.g., a first metal layer), vias, or pads. In addition, portions of the dielectric layer below the first conductive layer can be etched away to expose the traces, vias, or pads in the first conductive layer.

[0067] The process flow then proceeds to block 414 to form one or more interconnect bumps on the backside of the interposer. In particular, one or more conductive (e.g., metal, solder) bumps can be formed on the backside of the interposer such that they land on and are electrically coupled to the exposed traces, vias, or pads in the first conductive layer. In this way, the bumps can serve as second level interconnects (SLIs) to electrically couple the interposer to another IC component, such as an IC package substrate or a printed circuit board (PCB). In some embodiments, for example, the bumps can collectively form a ball grid array (BGA) interconnect.

[0068] The process flow then proceeds to block 416 to perform any remaining processing and assembly. For example, in a wafer-level or panel-level process flow, the resulting panel or wafer can be diced to singulate individual units of semiconductor chips on the wafer or panel. The singulated chips can then be attached or assembled into an IC package, a printed circuit board (PCB), and / or an electronic device or system (e.g., microelectronic assembly 300, IC device 700, electronic device 800), etc. In some embodiments, for example, the backside of the interposer can be attached and electrically coupled to a package substrate via the interconnect bumps on the backside of the interposer, and in turn the package substrate can be electrically coupled to a PCB.

[0069] At this point, the process flow can end. However, in some embodiments, the process flow can restart and / or certain blocks can be repeated. For example, in some embodiments, the process flow can restart at block 402 to continue forming semiconductor devices and systems having the same or similar designs.

[0070] Figures 5A-5C A plan view of example singulated semiconductor chips 500a-c that can be implemented in accordance with embodiments described herein is shown. Specifically, chips 500a-500c include singulated active dies or cores 502a-502b, 504a-504b, 506a-506b, 508, 510a-510b stacked on a passive interposer 501. The active dies / cores collectively include central processing units (CPUs) 502a, 502b, graphics processing units (GPUs) 504a, 504b, field programmable gate arrays (FPGAs) 506a, 506b, XPUs 508 (e.g., any type or combination of processing units, such as CPUs, GPUs, FPGAs, etc.), and high bandwidth memory (HBM) modules 510a, 510b. Further, in some embodiments, interposer 501 can be a substrate-less interposer without through-substrate via (TSV) implementation, active dies / cores 502a-502b, 504a-504b, 506a-506b, 508, 510a-510b can be hybrid bonded to interposer 501, and / or a structural substrate (not shown) can be attached over dies / cores 502a-502b, 504a-504b, 506a-506b, 508, 510a-510b for structural and mechanical stability, as described throughout this disclosure. In Figure 5A In particular, chip 500a includes multiple CPUs 502a, 502b and GPUs 504a, 504b coupled to interposer 501. In Figure 5B In particular, chip 500b includes multiple FPGAs 506a, 506b coupled to interposer 501. In Figure 5C In particular, chip 500c includes XPU 508 and multiple HBM modules 510a, 510b coupled to interposer 501.

[0071] Example integrated circuit embodiments

[0072] Figure 6is a top view of a wafer 600 and dies 602 that can be included in or can include any of the embodiments disclosed herein. In some embodiments, for example, the dies 602 can be included in the microelectronic assemblies and semiconductor packages described throughout the present disclosure (e.g., microelectronic assemblies 100a-100b, 200, 300, 500a-500c, 700). The wafer 600 can be composed of a semiconductor material and can include one or more dies 602 having integrated circuit structures formed on a surface of the wafer 600. Each die 602 can be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After fabrication of the semiconductor product is complete, the wafer 600 can undergo a singulation process in which the dies 602 are separated from one another to provide discrete “chips” of the integrated circuit product. The dies 602 can be any of the dies disclosed herein. The dies 602 can include one or more transistors, support circuitry for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 600 or the dies 602 can include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple ones of these devices can be combined on a single die 602. For example, a memory array formed of multiple memory devices can be formed on the same die 602 as a processor unit (e.g., processor unit 802 of Figure 8 or other logic configured to store information in the memory devices or execute instructions stored in the memory array. Each of the microelectronic assemblies disclosed herein can be fabricated using die-to-wafer assembly techniques in which some dies are attached to a wafer 600 that includes other ones of the dies, and the wafer 600 is then singulated.

[0073] Figure 7 is a cross-sectional side view of an integrated circuit device assembly 700 that can include any of the embodiments disclosed herein. In some embodiments, for example, the interposer 704 can be implemented as a substrate-less interposer without through-substrate vias, and the integrated circuit components 720 can be hybrid bonded to the interposer 704 as described throughout the present disclosure.

[0074] In some embodiments, integrated circuit device assembly 700 may be a microelectronic assembly. Integrated circuit device assembly 700 includes multiple components disposed on a circuit board 702 (which may be a motherboard, system board, motherboard, etc.). Integrated circuit device assembly 700 may include components disposed on a first surface 740 and an opposing second surface 742 of circuit board 702; typically, components may be disposed on one or both of surfaces 740 and 742. Any integrated circuit component discussed below with reference to integrated circuit device assembly 700 may take the form of any suitable embodiment of the microelectronic assembly disclosed herein.

[0075] In some embodiments, circuit board 702 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers spaced apart from each other by dielectric material layers and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 702 (optionally in conjunction with other metal layers). In other embodiments, circuit board 702 may be a non-PCB substrate. Figure 7 The illustrated integrated circuit device assembly 700 includes an on-intermediate package structure 736 coupled to a first side 740 of a circuit board 702 via a coupling member 716. The coupling member 716 electrically and mechanically couples the on-intermediate package structure 736 to the circuit board 702 and may include solder balls (e.g., Figure 7 The coupling element 716 may be used as a coupling element shown herein, including pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a pad grid array (LGA), male and female portions of sockets), adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The coupling element 716 may be used where appropriate as a coupling element shown or described for any substrate assembly or substrate assembly component described herein.

[0076] The on-intermediate package structure 736 may include an integrated circuit component 720 coupled to the intermediate layer 704 via a coupling member 718. The coupling member 718 may take any suitable form for the application, such as the form discussed above with reference to coupling member 716. Although Figure 7 A single integrated circuit component 720 is shown, but multiple integrated circuit components can be coupled to the interposer 704; in fact, additional interposers can be coupled to the interposer 704. The interposer 704 can provide an interposer substrate for bridging the circuit board 702 and the integrated circuit component 720.

[0077] Integrated circuit component 720 may be a packaged or unpackaged integrated circuit product, comprising one or more integrated circuit dies (e.g., Figure 6and / or one or more other suitable components. A packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, where the integrated circuit dies and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 720, a single monolithic integrated circuit die includes solder bumps that attach to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 704. The integrated circuit component 720 can include one or more computing system components, such as one or more processor units (e.g., system on a chip (SoC), processor core, graphics processor unit (GPU), accelerator, corelet processor), I / O controllers, memory, or network interface controllers. In some embodiments, the integrated circuit component 720 can include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0078] In embodiments where the integrated circuit component 720 includes multiple integrated circuit dies, the dies can be of the same type (homogeneous multi-die integrated circuit component) or two or more different types of dies (heterogeneous multi-die integrated circuit component). Multi-die integrated circuit components can be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0079] In addition to including one or more processor units, the integrated circuit component 720 can include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as the processor units, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor units. These separate integrated circuit dies can be referred to as “corelets.” In embodiments where the integrated circuit component includes multiple integrated circuit dies, interconnect between the dies can be provided by a package substrate, one or more silicon interposers, one or more silicon bridge interconnects (e.g., embedded multi-die interconnect bridge (EMIB)) embedded in the package substrate, or a combination thereof.

[0080] In general, the interposer 704 can extend connections to a wider pitch or re-route connections to different connections. For example, the interposer 704 can couple the integrated circuit component 720 to a set of ball grid array (BGA) conductive contacts of the coupling component 716 to be coupled to the circuit board 702. In some embodiments, the interposer 704 can include one or more through-silica vias (TSVs) that extend through the interposer 704 to provide an electrical connection between a conductive contact of the integrated circuit component 720 and a conductive contact of the coupling component 716. Figure 7 ​In the illustrated embodiment, integrated circuit component 720 and circuit board 702 are attached to opposite sides of interposer 704; in other embodiments, integrated circuit component 720 and circuit board 702 can be attached to the same side of interposer 704. In some embodiments, three or more components can be interconnected through interposer 704.

[0081] In some examples, interposer 704 can be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 704 can be formed of epoxy, fiberglass-reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, interposer 704 can be formed of alternative rigid or flexible materials, which can include the same materials described above for use in semiconductor substrates, e.g., silicon, germanium, and other III-V and IV materials. Interposer 704 can include metal interconnects 708 and vias 710, including but not limited to through-hole vias 710-1 (which extend from a first face 750 of interposer 704 to a second face 754 of interposer 704), blind vias 710-2 (which extend from either first face 750 or second face 754 of interposer 704 to an internal metal layer), and buried vias 710-3 (which connect internal metal layers).

[0082] In some embodiments, interposer 704 can include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect a connection on a first face of the silicon interposer to an opposite second face of the silicon interposer. In some embodiments, an interposer 704 including a silicon interposer can further include one or more wiring layers to route a connection on a first face of interposer 704 to an opposite second face of interposer 704.

[0083] Interposer 704 can further include embedded devices 714, including passive and active devices. Such devices can include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices can also be formed on interposer 704, e.g., radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices. Interposer-up package structure 736 can take the form of any interposer-up package structure known in the art. In embodiments where the interposer is not a printed circuit board.

[0084] The integrated circuit device assembly 700 can include an integrated circuit component 724 coupled to the first face 740 of the circuit board 702 by a coupling component 722. The coupling component 722 can take the form of any of the embodiments discussed above with reference to the coupling component 716, and the integrated circuit component 724 can take the form of any of the embodiments discussed above with reference to the integrated circuit component 720.

[0085] Figure 7 The integrated circuit device assembly 700 shown in FIG. 8B includes a layer stack package structure 734 coupled to the second face 742 of the circuit board 702 by a coupling component 728. The layer stack package structure 734 can include an integrated circuit component 726 and an integrated circuit component 732 coupled together by coupling components 730, such that the integrated circuit component 726 is disposed between the circuit board 702 and the integrated circuit component 732. The coupling components 728 and 730 can take the form of any of the embodiments of the coupling component 716 discussed above, and the integrated circuit components 726 and 732 can take the form of any of the embodiments of the integrated circuit component 720 discussed above. The layer stack package structure 734 can be configured according to any layer stack package structure known in the art.

[0086] Figure 8 is a block diagram of an example electrical device 800 that can include one or more embodiments disclosed herein. For example, any suitable one of the components of the electrical device 800 can include one or more of the integrated circuit device assemblies 100a- 100b, 200, 300, 500a-500c, 700, the integrated circuit component 720, or the integrated circuit die 602 disclosed herein. Multiple components are shown in Figure 8 in FIG. 8A, but any one or more of these components can be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 800 can be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system on a chip (SoC) die.

[0087] Additionally, in various embodiments, the electrical device 800 can not include Figure 8The electrical device 800 can include one or more components illustrated in FIG. 8, but the electrical device 800 can include interface circuitry to couple to one or more components. For example, the electrical device 800 can not include the display device 806, but can include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 806 can be coupled. In another example set, the electrical device 800 can not include the audio input device 824 or the audio output device 808, but can include audio input or output device interface circuitry (e.g., a connector and support circuitry) to which an audio input device 824 or an audio output device 808 can be coupled.

[0088] The electrical device 800 can include one or more processor units 802 (e.g., one or more processing units). As used herein, the term “processor unit,” “processing unit,” or “processor” can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 802 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors within hardware that perform cryptographic algorithms), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit can be referred to as an XPU (or xPU).

[0089] The electrical device 800 can include a memory 804, which can itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 804 can include memory that is on the same integrated circuit die as the processor unit 802. The memory can be used as cache memory (e.g., level 1 (LI), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and can include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0090] In some embodiments, the electrical device 800 can include one or more processor units 802 that are heterogeneous or asymmetric from another processor unit 802 in the electrical device 800. There can be a variety of differences between the processor units 802 in the system, including architectural, microarchitectural, thermal, power consumption characteristics, and the like. The differences can effectively manifest themselves as asymmetry and heterogeneity between the processor units 802 within the electrical device 800.

[0091] In some embodiments, the electrical device 800 can include a communication component 812 (e.g., one or more communication components). For example, the communication component 812 can manage wireless communications for the transfer of data to and from the electrical device 800. The term“wireless” and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, and the like, that can communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0092] The communication components 812 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long-Term Evolution (LTE) projects and any amendments, updates and / or revisions thereof (e.g., LTE-Advanced and / or LTE Beyond), Ultra Mobile Broadband (UMB) project also referred to as "3GPP2" and / or the like. IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and interoperability tests for the IEEE 802.16 standards. The communication components 812 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile

[0093] In some embodiments, the communication components 812 can manage wired communications, e.g., electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standards). As described above, the communication components 812 can include multiple communication components. For instance, a first communication component 812 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth and a second communication component 812 can be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, a first communication component 812 can be dedicated to wireless communication and a second communication component 812 can be dedicated to wired communication.

[0094] The electrical device 800 can include battery / power circuitry 814. The battery / power circuitry 814 can include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 800 to an energy source (e.g., an AC line power source) separate from the electrical device 800.

[0095] The electrical device 800 can include a display device 806 (or corresponding interface circuitry, as discussed above). The display device 806 can include one or more embedded or externally connected visual indicators, e.g., a heads-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0096] The electrical device 800 can include an audio output device 808 (or corresponding interface circuitry, as discussed above). The audio output device 808 can include any embedded or externally connected device generating an audible indicator, e.g., a speaker, headphones, or earbuds.

[0097] The electrical device 800 can include an audio input device 824 (or corresponding interface circuitry, as discussed above). The audio input device 824 can include any embedded or externally connected device generating a signal representative of sound, e.g., a microphone, microphone array, or digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 800 can include a global navigation satellite system (GNSS) device 818 (or corresponding interface circuitry, as discussed above), e.g., a global positioning system (GPS) device. The GNSS device 818 can communicate with satellite-based systems and can determine a geographic location of the electrical device 800 based on information received from one or more GNSS satellites, as is known in the art.

[0098] The electrical device 800 can include other output devices 810 (or corresponding interface circuitry, as discussed above). Examples of the other output devices 810 can include an audio codec, a video codec, a printer, a wired or wireless transmitter to provide information to other devices, or additional storage devices.

[0099] The electrical device 800 can include other input devices 820 (or corresponding interface circuitry, as discussed above). Examples of the other input devices 820 can include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a touchpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a bar code reader, a quick response (QR) code reader, an electrocardiography (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0100] The electrical device 800 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular telephone, a smartphone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-l convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a display device (e.g., a monitor, a television), a set-top box, an entertainment control unit, a video game console, a video playback device, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart appliance, a consumer electronic product, or manufacturing equipment). In some embodiments, the electrical device 800 can be any other electronic device that processes data. In some embodiments, the electrical device 800 can include multiple discrete physical components. A given electrical device 800 can exhibit the range of devices of various embodiments, and in some embodiments, the electrical device 800 can be referred to as a computing device or a computing system.

[0101] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure and the appended claims.

[0102] In the drawings, some of the structural or methodological features can be shown in particular arrangements and / or order. It should be understood that such specific arrangements and / or order can not be required. Instead, in some embodiments, such features can be arranged in a different manner and / or order than shown in the illustrative figures. Additionally, inclusion of a structural or methodological feature in a particular figure is not meant to imply that such feature is required in all embodiments, and in some embodiments, such feature can not be included or can be combined with other features. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0103] Further, the illustrations and / or descriptions of various embodiments can be simplified or approximated for purposes of clarity and / or ease of understanding, and thus, they can not necessarily be drawn to scale. For example, while some of the drawings generally indicate straight lines, right angles and smooth surfaces, actual implementations of the disclosed embodiments can have imperfect straight lines and right angles, and some features can have surface roughness or otherwise be non-smooth given the real-world limitations of manufacturing processes, etc. Similarly, illustrations and / or descriptions of how components are arranged can be simplified or approximated for purposes of clarity and / or ease of understanding, and some error magnitudes can vary in actual implementations (e.g., due to manufacturing processes, etc.).

[0104] The use of ordinal adjectives such as "first," "second," and "third" and the like in the description and / or claims to describe different instances of the same object are used to distinguish between the different instances of the object and do not imply that the objects must occur in a given sequence or order.

[0105] The terms "substantially," "approximately," "near," "about," and "almost" generally mean within + / - 10% of a target value (unless otherwise specified). Similarly, terms describing spatial relationships (e.g., "perpendicular," "orthogonal," or "coplanar") can mean substantially within the described spatial relationship (e.g., within + / - 10 degrees of orthogonal).

[0106] Certain terminology can also be used in the foregoing description for the purposes of reference only, and, thus, is not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology can include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0107] As used herein, the terms "over," "under," "between," "adjacent to," "up to," and "on" can refer to a relative positioning of one layer or component with respect to other layers or components. For example, a layer that is "over," "under," or "on" another layer, "adjacent to" another layer, or "bonded to" another layer can be directly in contact with the other layer or can have one or more intervening layers. Further, a layer that is "between" layers can be directly in contact with the layers or can have one or more intervening layers.

[0108] The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "into" and "onto."

[0109] For the purposes of the present disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0110] Views labeled "cross-sectional," "profile," and "plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, the figures are labeled with axes to indicate the orientation of the figure.

[0111] The term "package" generally refers to a self-contained carrier of one or more dies, where the dies are attached to a package substrate or embedded in a package substrate and can be encapsulated for protection, with integrated or wire bond interconnections between the dies and leads, pins, or bumps located on an external portion of the package substrate. A package can contain a single die or multiple dies that provide the respective functionality. A package can be mounted on a printed circuit board to interconnect with other packaged integrated circuits and discrete components, forming a larger circuit.

[0112] The term "tape-out" generally refers to the process of sending a design layout to a foundry for fabrication. The term "tape-out" can also refer to the design layout itself.

[0113] The term "coreless" generally refers to a substrate of an integrated circuit package that lacks a core. The lack of a core can allow for high-density packaging architectures, as through-vias can have a relatively large size and pitch compared to high-density interconnects.

[0114] The term "pad side" generally refers to the side of an integrated circuit package substrate that is closest to the attachment plane of a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which generally refers to the side of an integrated circuit package substrate to which one or more dies are attached.

[0115] The terms "dielectric" and "dielectric material" generally refer to any type or quantity of non-conductive material. In some cases, a dielectric material can be used to construct a structure of a package substrate. For example, a dielectric material can be incorporated into an integrated circuit package as a laminate film layer or as a resin molded over an integrated circuit die mounted on a substrate.

[0116] The term "metallization" generally refers to a metal layer formed on, over, and / or through a dielectric material of a package substrate. The metal layer is typically patterned to form metal structures such as traces and bond pads. The metallization of a package substrate can be confined to a single layer or multiple layers separated by dielectric layers.

[0117] The term "bond pad" generally refers to a metallized structure that terminates an integrated trace and via in an integrated circuit package and die. The term "solder pad" can sometimes substitute for "bond pad" and can have the same or similar meaning.

[0118] The term "bump" generally refers to a conductive layer or structure formed on a bond pad, which is typically made of solder or metal and has a rounded or curved shape, hence the term "bump."

[0119] The term "substrate" generally refers to a planar platform that can include dielectric and / or metallized structures. A substrate can mechanically support and electrically couple one or more IC dies on a single platform, where the one or more IC dies are encapsulated by a moldable dielectric material. A substrate can include bumps or pads on one or both sides as bond interconnects. For example, one side of a substrate (often referred to as the "die side") can include bumps or pads for die or chip bonding. The opposite side of a substrate (often referred to as the "pad side") can include bumps or pads for bonding the package to a printed circuit board.

[0120] The term "assembly" generally refers to grouping of parts into a single functional unit. For example, certain parts can be permanently bonded together, integrated together, and / or mechanically assembled (e.g., where parts can be removable) into a functional unit.

[0121] The terms "coupled" or "connected" refer to a direct or indirect connection, such as by way of one or more passive or active intermediary devices, between the things that are connected, electrically, mechanically, magnetically, or fluidly.

[0122] The term “circuit” or “module” can refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0123] Embodiments

[0124] The following provides illustrative examples of the techniques described throughout this disclosure. Embodiments of the techniques can include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures can be configured to perform one or more operations, techniques, processes, and / or methods as set forth in the examples below.

[0125] Example 1 includes a microelectronic assembly comprising: an interposer, wherein the interposer includes one or more conductive traces and one or more vias, wherein the interposer does not include a through-substrate via; and one or more integrated circuit (IC) dies coupled to the interposer, wherein a respective IC die is electrically coupled to the interposer via a dielectric-to-dielectric and metal-to-metal bond at an interface between the interposer and the respective IC die.

[0126] Example 2 includes the microelectronic assembly of Example 1, further comprising a substrate, wherein the substrate is over the IC dies, and wherein the IC dies are over the interposer.

[0127] Example 3 includes the microelectronic assembly of Example 2, wherein a first side of the respective IC die is coupled to the interposer via the dielectric-to-dielectric and metal-to-metal bond, and wherein a second side of the respective IC die is coupled to the substrate.

[0128] Example 4 includes the microelectronic assembly of any of Examples 2-3, wherein the substrate is a structural substrate.

[0129] Example 5 includes the microelectronic assembly of any of Examples 1-4, wherein the interposer further includes a plurality of conductive bumps, wherein the conductive bumps are on a first side of the interposer; and the respective IC die is coupled to a second side of the interposer via the dielectric-to-dielectric and metal-to-metal bond.

[0130] Example 6 includes the microelectronic assembly of Example 5, wherein the conductive bumps are coupled to a first conductive layer of the interposer, wherein the first conductive layer includes: one or more of the conductive traces, one or more of the vias, or one or more conductive pads.

[0131] Example 7 includes the microelectronic assembly of any of Examples 1-6, wherein the interposer does not include a substrate.

[0132] Example 8 includes the microelectronic assembly of any of Examples 1-7, wherein at least one of the IC dies includes one or more metal-insulator-metal (MIM) devices; or the interposer further includes one or more MIM devices.

[0133] Example 9 includes the microelectronic assembly of Example 8, wherein the one or more MIM devices include at least one of a MIM capacitor or a MIM diode.

[0134] Example 10 includes the microelectronic assembly of any of Examples 1-9, wherein the interposer is electrically coupled to a package substrate; and the package substrate is electrically coupled to a circuit board.

[0135] Example 11 includes the microelectronic assembly of any of Examples 1-10, wherein at least one of the IC dies includes processing circuitry, memory circuitry, storage circuitry, or communication circuitry.

[0136] Example 12 includes a system comprising: a circuit board; and an integrated circuit (IC) electrically coupled to the circuit board, wherein the IC includes: an interposer, wherein the interposer includes one or more electrically conductive traces and one or more vias, wherein the interposer does not include a substrate; one or more IC dies over the interposer, wherein a first side of a respective IC die is electrically coupled to the interposer via hybrid dielectric-to-dielectric and metal-to-metal bonding; and a structural substrate over the IC dies, wherein the structural substrate is coupled to a second side of the respective IC die.

[0137] Example 13 includes the system of Example 12, wherein the interposer further includes a plurality of electrically conductive bumps, wherein the electrically conductive bumps are on a first side of the interposer and the respective IC die is coupled to a second side of the interposer.

[0138] Example 14 includes the system of Example 13, wherein the electrically conductive bumps are coupled to a first electrically conductive layer of the interposer, wherein the first electrically conductive layer includes: one or more of the electrically conductive traces, one or more of the vias, or one or more electrically conductive pads.

[0139] Example 15 includes the system of any of Examples 12-14, wherein the interposer does not include a through-substrate via.

[0140] Example 16 includes the system of any of Examples 12-15, wherein the one or more IC dies include one or more dielets.

[0141] Example 17 includes the system of any of Examples 12-16, wherein at least one of the IC dies includes a central processing unit, a graphics processing unit, a field programmable gate array, or a memory device.

[0142] Example 18 includes a method comprising: receiving a first substrate; forming an interposer over the first substrate, wherein the interposer includes one or more conductive traces and one or more vias; attaching one or more integrated circuit (IC) dies to the interposer; attaching a second substrate over the one or more IC dies; and removing the first substrate from the interposer.

[0143] Example 19 includes the method of Example 18, wherein the one or more IC dies are attached to a first side of the interposer, the first substrate is removed from a second side of the interposer, and the method further comprises: forming one or more conductive bumps on the second side of the interposer after removing the first substrate from the interposer.

[0144] Example 20 includes the method of Example 19, wherein the method further comprises: attaching the second side of the interposer to a package substrate after forming the one or more conductive bumps on the second side of the interposer, wherein the interposer and the package substrate are electrically coupled via the one or more conductive bumps; and the method is a method of forming an IC package, wherein the IC package includes the package substrate, the interposer, the one or more IC dies, and the second substrate.

[0145] Example 21 includes the method of any of Examples 18-20, wherein attaching the one or more IC dies to the interposer includes hybrid bonding the one or more IC dies to the interposer, wherein dielectric-to-dielectric and metal-to-metal bonds are formed between respective IC dies and the interposer.

[0146] Example 22 includes the method of any of Examples 18-20, wherein attaching the one or more IC dies to the interposer includes attaching the one or more IC dies to the interposer via a ball grid array interconnect.

[0147] Example 23 includes the method of any of Examples 18-22, wherein removing the first substrate from the interposer includes grinding or etching away the first substrate.

Claims

1. A microelectronic assembly, comprising: an interposer, wherein the interposer includes one or more electrically conductive traces and one or more vias, wherein the interposer does not include a through-substrate via; and one or more integrated circuit (IC) dies coupled to the interposer, wherein a respective IC die is electrically coupled to the interposer via a dielectric-to-dielectric bonding and a metal-to-metal bonding at an interface between the interposer and the respective IC die.

2. The microelectronic assembly of claim 1, further comprising a substrate, wherein, the substrate is located above the IC dies, and wherein the IC dies are located above the interposer.

3. The microelectronic assembly of claim 2, wherein, a first side of the respective IC die is coupled to the interposer via the dielectric-to-dielectric bonding and the metal-to-metal bonding, and wherein a second side of the respective IC die is coupled to the substrate.

4. The microelectronic assembly of claim 2, wherein, the substrate is a structural substrate.

5. The microelectronic assembly of any one of claims 1-4: wherein: the interposer further includes a plurality of electrically conductive bumps, wherein the electrically conductive bumps are on a first side of the interposer; and the respective IC die is coupled to a second side of the interposer via the dielectric-to-dielectric bonding and the metal-to-metal bonding.

6. The microelectronic assembly of claim 5, wherein, the electrically conductive bumps are coupled to a first electrically conductive layer of the interposer, wherein the first electrically conductive layer includes one or more of the electrically conductive traces, one or more of the vias, or one or more electrically conductive pads.

7. The microelectronic assembly of any of claims 1-4, wherein, the interposer does not include a substrate.

8. The microelectronic assembly of any one of claims 1-4, wherein: at least one of the IC dies includes one or more metal-insulator-metal (MIM) devices; or the interposer further includes one or more MIM devices.

9. The microelectronic assembly of claim 8, wherein, the one or more MIM devices include at least one of a MIM capacitor or a MIM diode.

10. The microelectronic assembly of any one of claims 1-4, wherein: the interposer is electrically coupled to a package substrate; and the package substrate is electrically coupled to a circuit board.

11. The microelectronic assembly of any of claims 1-4, wherein, at least one of the IC dies includes processing circuitry, memory circuitry, storage circuitry, or communication circuitry.

12. A system, comprising: a circuit board; and an integrated circuit (IC) electrically coupled to the circuit board, wherein the IC includes: an interposer, wherein the interposer includes one or more electrically conductive traces and one or more vias, wherein the interposer does not include a substrate; one or more IC dies above the interposer, wherein a first side of a respective IC die is electrically coupled to the interposer via a hybrid dielectric-to-dielectric bonding and a metal-to-metal bonding; and a structural substrate above the IC dies, wherein the structural substrate is coupled to a second side of the respective IC die.

13. The system of claim 12, wherein: the interposer further includes a plurality of electrically conductive bumps, wherein the electrically conductive bumps are on a first side of the interposer; and the respective IC die is coupled to a second side of the interposer.

14. The system of claim 13, wherein, The conductive bumps are coupled to a first conductive layer of the interposer, wherein the first conductive layer includes one or more of the conductive traces, one or more of the vias, or one or more conductive pads.

15. The system of any one of claims 12-14, wherein, The interposer does not include a through-substrate via.

16. The system of any of claims 12-14, wherein: at least one of the IC dies includes one or more metal-insulator-metal (MIM) devices; or the interposer further includes one or more MIM devices.

17. The system of claim 16, wherein, The one or more MIM devices include at least one of a MIM capacitor or a MIM diode.

18. The system of any one of claims 12-14, wherein, The one or more IC dies include one or more corelets.

19. The system of any one of claims 12-14, wherein, At least one of the IC dies includes a central processing unit, a graphics processing unit, a field programmable gate array, or a memory device.

20. A method comprising: receiving a first substrate; forming an interposer over the first substrate, wherein the interposer includes one or more conductive traces and one or more vias; attaching one or more integrated circuit (IC) dies to the interposer; attaching a second substrate over the one or more IC dies; and removing the first substrate from the interposer.

21. The method of claim 20, wherein: the one or more IC dies are attached to a first side of the interposer; the first substrate is removed from a second side of the interposer; and the method further includes forming one or more conductive bumps on the second side of the interposer after removing the first substrate from the interposer.

22. The method of claim 21, wherein: the method further includes, after forming the one or more conductive bumps on the second side of the interposer, attaching the second side of the interposer to a package substrate, wherein the interposer and the package substrate are electrically coupled via the one or more conductive bumps; and the method is a method of forming an IC package, wherein the IC package includes the package substrate, the interposer, the one or more IC dies, and the second substrate.

23. The method of any one of claims 20-22, wherein, attaching the one or more IC dies to the interposer includes hybrid bonding the one or more IC dies to the interposer, wherein a dielectric-to-dielectric bond and a metal-to-metal bond are formed between a respective IC die and the interposer.

24. The method of any one of claims 20-22, wherein, attaching the one or more IC dies to the interposer includes attaching the one or more IC dies to the interposer via a ball grid array interconnect.

25. The method of any one of claims 20-22, wherein, removing the first substrate from the interposer includes grinding or etching away the first substrate.

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