Package substrate and preparation method thereof, semiconductor stacking structure and electronic equipment

Abstract

The embodiment of the invention belongs to the technical field of semiconductors, particularly relates to a packaging substrate and a preparation method thereof, a semiconductor stacking structure and electronic equipment, and is used for improving the warping phenomenon of the packaging substrate in related technologies. The packaging substrate comprises a substrate, a connecting part and a rewiring layer. The substrate comprises a substrate body and a plurality of conductive columns, the conductive columns penetrate through at least part of the substrate body in the first direction, and the distance between any two adjacent conductive columns is smaller than 15 mm; the connecting part is positioned on one side of the substrate along the first direction and is in contact with the conductive column; the redistribution layer is located on the other side of the substrate in the first direction, and the redistribution layer is in contact with the conductive columns. Through the arrangement of the substrate body and the plurality of conductive columns, the rigidity of the substrate is improved, and the warping of the packaging substrate is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a packaging substrate and its preparation method, a semiconductor stacking structure, and an electronic device. Background Technology

[0002] To further meet the miniaturization requirements of electronic devices, higher demands are placed on semiconductor integration technology. Electronic devices include semiconductor stacked structures, which comprise a packaging substrate and chips stacked on the packaging substrate. The packaging substrate includes a redistribution layer, and the chips are connected to the redistribution layer. However, in related technologies, the packaging substrate may warp or deform, making it difficult to increase the number of chips in the semiconductor stacked structure or resulting in poor performance of the semiconductor stacked structure, hindering the continuous improvement of chip integration. Summary of the Invention

[0003] The purpose of this application is to provide a packaging substrate and its preparation method, a semiconductor stacking structure, and an electronic device, thereby improving the difficulty in controlling the warpage of packaging substrates in related technologies.

[0004] To achieve the above objectives, the embodiments of this application provide the following solutions:

[0005] In a first aspect, embodiments of this application provide a packaging substrate, which includes a substrate, a connection portion, and a redistribution layer. The substrate includes a substrate body and a plurality of conductive pillars, each conductive pillar penetrating at least a portion of the substrate body along a first direction, with the distance between any two adjacent conductive pillars being less than 15 mm. The connection portion is located on one side of the substrate along the first direction and contacts the conductive pillars. The redistribution layer is located on the other side of the substrate along the first direction and contacts the conductive pillars.

[0006] With the above configuration, the conductive pillars connect the redistribution layer and the connector, enabling interconnection between them. In practical applications, the connector connects to the circuit board, and through the connector, the redistribution layer connects to the chip, thus allowing the packaging substrate to function as an adapter board, enabling the chip to connect to the circuit board. Simultaneously, by providing the substrate body and multiple conductive pillars, the rigidity of the substrate is improved, reducing warpage of the packaging substrate. Furthermore, the distance between any two adjacent conductive pillars is less than 15mm, which is smaller than the chip size, making it impossible to place a chip between two adjacent conductive pillars. Moreover, this configuration further improves the rigidity of the substrate and reduces warpage of the packaging substrate.

[0007] In some embodiments, including those described above, the redistribution layer includes conductive lines and a dielectric layer. The conductive lines are in contact with conductive posts, and the coefficient of thermal expansion of the dielectric layer is the same as or similar to that of the substrate body. With this configuration, when the ambient temperature changes (e.g., a sudden drop in ambient temperature or a sudden rise in temperature, or when the temperature of the packaging substrate is high during operation), the equivalent thermal stress of the dielectric layer and the substrate body is similar, reducing the interaction force between the dielectric layer and the substrate body, thereby reducing stress deformation between them and mitigating the warpage of the packaging substrate. Furthermore, when both materials are the same, the adhesion between the substrate body and the redistribution layer is better, which is beneficial for improving the connection reliability between the substrate body and the redistribution layer.

[0008] In some embodiments, including those described above, the substrate body of the packaging substrate includes a first layer and a second layer stacked together, with the second layer located between the first layer and the redistribution layer. The coefficients of thermal expansion of the first layer and the second layer are similar. This arrangement achieves a multi-layer structure for the substrate body, which helps to further improve the rigidity of the packaging substrate and mitigate substrate deformation caused by changes in the external environment, such as pressure (e.g., pressure during grinding processes), thus further controlling substrate warpage. Furthermore, this arrangement ensures that under varying ambient temperatures (e.g., sudden cooling or heating, or high operating temperatures of the packaging substrate), the equivalent thermal stresses of the first and second layers are similar, reducing the interaction force between them and thus decreasing stress deformation, thereby mitigating substrate warpage. Simultaneously, when the materials of the two layers are similar, the adhesion between the first and second layers is better than when using materials with significant differences, improving the reliability of the connection between the substrate body and the redistribution layer.

[0009] In some embodiments, including those described above, the conductive post penetrates the second layer, and the connecting portion penetrates the first layer to contact the conductive post. Alternatively, the conductive post penetrates both the second and first layers. This arrangement ensures that the conductive post contacts the connecting portion, thereby enabling the redistribution layer and the connecting portion to be interconnected via the conductive post.

[0010] In some embodiments, including those described above, the material of the first layer includes an organic material; and / or, the material of the second layer includes a molding material. With this configuration, the coefficient of thermal expansion of the first layer is similar to that of the dielectric layer in the redistribution layer, and also similar to that of the second layer. This results in similar equivalent thermal stresses between the first layer, the second layer, and the dielectric layer, reducing the interaction forces between the first layer, the second layer, and the dielectric layer, thereby reducing stress deformation between the first layer, the second layer, and the dielectric layer, and achieving the goal of mitigating the warpage of the packaging substrate.

[0011] In some embodiments, including those described above, the packaging substrate further includes electronic components located between two adjacent conductive pillars. A connector is provided on the side of the electronic component facing away from the connection portion, and the electronic component is connected to the conductive line via the connector. This arrangement, placing the electronic component between two adjacent conductive pillars, helps improve the performance of the packaging substrate while avoiding the electronic component occupying a large space on the packaging substrate, thus improving the integration of the packaging substrate.

[0012] Secondly, embodiments of this application provide a semiconductor stacking structure, which includes a chip and a packaging substrate as described in any of the above embodiments. The chip and the packaging substrate are stacked together, and the chip and the packaging substrate are connected by a redistribution layer. The semiconductor stacking structure provided by the embodiments of this application includes the packaging substrate as described above, and therefore has all the aforementioned beneficial effects, which will not be repeated here.

[0013] In some embodiments, including those described above, the number of chips is multiple, with at least one chip flip-chip bonded to the packaging substrate and at least one chip wire-bonded to the packaging substrate. This configuration enables hybrid bonding in the semiconductor stacked structure, and by appropriately increasing the number of chips, the performance of the semiconductor stacked structure can be effectively improved.

[0014] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and a semiconductor stacked structure as described in any of the above embodiments. The semiconductor stacked structure and the circuit board are stacked together, and the circuit board and the semiconductor stacked structure are connected at a connection point. The electronic device provided by the embodiments of this application includes the semiconductor stacked structure as described above, and therefore has all the aforementioned beneficial effects, which will not be repeated here.

[0015] Fourthly, embodiments of this application provide a method for preparing a packaging substrate. The method includes: providing a carrier plate; forming a substrate on the carrier plate, the substrate including a substrate body and a plurality of conductive pillars, the conductive pillars penetrating the substrate body along a first direction, and the distance between any two adjacent conductive pillars being less than 15 mm; forming a redistribution layer on one side of the substrate, the redistribution layer contacting the conductive pillars; removing the carrier plate; and forming a connecting portion on the other side of the substrate, the connecting portion contacting the conductive pillars. The method for preparing a packaging substrate provided by embodiments of this application is used to prepare a packaging substrate including the above-described material, and therefore has all the aforementioned beneficial effects, which will not be repeated here.

[0016] In some embodiments, including those described above, forming a substrate on a carrier plate includes: forming a plurality of conductive pillars on the carrier plate; filling the spaces between the conductive pillars with a molding material to form the substrate body. Through this arrangement, the conductive pillars are stabilized by the molding material, which also possesses a certain degree of temperature resistance, such as being less prone to chemical or physical changes at the highest operating temperature of the encapsulated substrate.

[0017] In some embodiments including those described above, before forming multiple conductive pillars on the carrier plate, the method for preparing the packaging substrate further includes: forming a first layer on the carrier plate, the first layer being made of an organic material; removing a portion of the first layer to form through-holes penetrating the first layer; and forming multiple conductive pillars on the carrier plate, including forming conductive pillars within the through-holes. Through the above configuration, the substrate body can have a multi-layer structure, mitigating substrate deformation caused by changes in the external environment, such as pressure (e.g., pressure during grinding processes), which helps to further improve the rigidity of the packaging substrate and further control substrate warpage.

[0018] In some embodiments including those described above, before forming multiple conductive pillars on the carrier plate, the method for preparing the packaging substrate further includes: forming a first layer on the carrier plate, the first layer being made of an organic material. After removing the carrier plate, before forming a connection portion on the other side of the substrate, the method for preparing the packaging substrate further includes: removing a portion of the first layer to form a through-hole exposing the conductive pillars. Forming the connection portion on the other side of the substrate includes: forming the connection portion within the through-hole. Through the above configuration, the substrate body can have a multi-layer structure, mitigating substrate body deformation caused by changes in the external environment, such as pressure (e.g., pressure during grinding processes), which is beneficial for further improving the rigidity of the packaging substrate and further controlling packaging substrate warpage.

[0019] In some embodiments including those described above, the method for fabricating the packaging substrate further includes: after forming a plurality of conductive pillars on a carrier plate, and before filling the spaces between the conductive pillars with molding material, the method further includes: placing an electronic device between two adjacent conductive pillars, with a connector disposed on the side of the electronic device facing away from the connecting portion. After filling the spaces between the conductive pillars with molding material, the method further includes: grinding a first end face of the substrate body to expose the connector of the electronic device on the first end face, the first end face being located on the side of the substrate body facing away from the carrier plate. Through this arrangement, while placing the electronic device between two adjacent conductive pillars, the method avoids the electronic device occupying a large space on the packaging substrate, which is beneficial for improving the integration of the packaging substrate. Simultaneously, this arrangement can also improve the performance of the packaging substrate and expand its application scenarios. Attached Figure Description

[0020] Figure 1 A structural diagram of an electronic device provided in an embodiment of this application;

[0021] Figure 2 This is a structural diagram of a semiconductor stacked structure provided in an embodiment of this application;

[0022] Figure 3A structural diagram of a packaging substrate provided in an embodiment of this application;

[0023] Figure 4 This is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0024] Figure 5 This is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0025] Figure 6 This is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0026] Figure 7 This is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0027] Figure 8 This is a structural diagram of another packaging substrate provided in an embodiment of this application;

[0028] Figure 9 A flowchart illustrating the steps of a method for fabricating a packaging substrate according to an embodiment of this application;

[0029] Figure 10 A structural diagram of the carrier plate provided in a method for preparing a packaging substrate according to an embodiment of this application;

[0030] Figure 11 This is a structural diagram of the substrate after it has been formed, provided in an embodiment of this application for the preparation of a packaging substrate.

[0031] Figure 12 This is a structural diagram of a packaging substrate after the redistribution layer is formed, provided in an embodiment of this application.

[0032] Figure 13 This is a structural diagram of a packaging substrate after the connection portion is formed in a method for preparing a packaging substrate according to an embodiment of this application;

[0033] Figure 14 This is a structural diagram of the substrate after it has been formed, provided in another method for preparing a packaging substrate according to an embodiment of this application.

[0034] Figure 15 This is a structural diagram of the substrate after it has been formed, provided in another method for preparing a packaging substrate according to an embodiment of this application.

[0035] Figure 16 This is a structural diagram of the substrate after the connection portion is formed in another method for preparing a packaging substrate according to an embodiment of this application.

[0036] Figure 17 This is a structural diagram of the substrate after it has been formed, provided in another method for preparing a packaging substrate according to an embodiment of this application.

[0037] Figure 18 This is a structural diagram of the substrate after the connection portion is formed in another method for preparing a packaging substrate according to an embodiment of this application.

[0038] Figure 19 This is a schematic diagram of cutting the packaging substrate according to an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0041] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0042] In describing some embodiments, the terms "connection," "electrical connection," and their derivative expressions may be used. For example, the term "connection" may be used to indicate that two or more components are in direct physical contact with each other, and the term "electrical connection" may be used to indicate that two or more components are in electrical contact with each other.

[0043] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0044] This document describes exemplary embodiments with reference to structural diagrams as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0045] Please refer to Figure 1 , Figure 1 This is a structural diagram of an electronic device 10 provided in an embodiment of this application. The electronic device 10 may include an image sensor, NAND flash memory, high-bandwidth memory, a mobile phone, a tablet computer, a television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products. This application does not impose any special limitations on the specific form of the aforementioned electronic device 10.

[0046] The aforementioned electronic device 10 may include a circuit board 120 and a semiconductor stack structure 110, which are stacked on top of each other. The semiconductor stack structure 110 includes a packaging substrate, and the packaging substrate includes a connection portion 230. The circuit board 120 is connected to the connection portion 230.

[0047] For example, the connection portion 230 may include pads, bumps, etc. The shape of the bumps may include spherical, columnar, etc. The material of the connection portion 230 may include a combination of one or more conductive materials such as copper, nickel, gold, titanium, cobalt, and tungsten, or other conductive alloy materials. By providing the connection portion 230, electrical interconnection between the circuit board 120 and the semiconductor stack structure 110 can be achieved. Simultaneously, the connection portion 230 can also serve as a stress buffer.

[0048] Please refer to Figure 2 , Figure 2 The present application provides an exemplary embodiment of a semiconductor stacking structure 110, which includes a packaging substrate 200 and a chip 300. The chip 300 is stacked on top of the packaging substrate 200 and connected to the packaging substrate 200.

[0049] Please continue to refer to Figure 2In some embodiments, there are multiple chips 300. At least one chip 300 is flip-chip bonded to the packaging substrate 200, and at least one chip 300 is wire-bonded to the packaging substrate 200.

[0050] In this embodiment, the number of chips 300 is not limited. At least one chip 300 is a first chip 310, which is flip-chip bonded to the packaging substrate 200. At least one chip 300 is a second chip 320, which is wire-bonded to the packaging substrate 200. This configuration enables hybrid bonding in the semiconductor stack structure 110. By appropriately increasing the number of first chips 310 and second chips 320, the performance of the semiconductor stack structure 110 can be effectively improved.

[0051] For example, there may be two first chips 310, and the two first chips 310 are spaced apart along a direction parallel to the packaging substrate 200. The first chips 310 are flip-chip bonded (FCB) to the packaging substrate 200. Here, "flip-chip bonding" can be understood as mounting the first chips 310 on the packaging substrate 200 by flipping (reversing 180 degrees) via bumps. For example, the bumps may include a flip chip ball grid array (FCBGA).

[0052] For example, the number of second chips 320 can be eight, and the multiple second chips 320 are stacked in a direction perpendicular to the packaging substrate 200. The multiple second chips 320 are also located on the side of the first chip 310 facing away from the packaging substrate 200. The second chips 320 are wire bonded to the packaging substrate 200. Here, "wire bonding" can be understood as the front side of the second chip 320 being bonded to the packaging substrate 200 through leads 400 (e.g., metal wires).

[0053] In some embodiments, the first chip 310 and the second chip 320 can also be interconnected. For example, the first chip 310 and the second chip 320 can also be connected via a through silicon via (TSV).

[0054] In some embodiments, the semiconductor stack structure 110 may include at least a portion of a memory. The first chip 310 may include a logic chip. The logic chip may include any or more chips containing logic circuits, such as a Central Processing Unit (CPU) or a System on Chip (SOC). The second chip 320 may include a memory chip, which may include a DRAM chip.

[0055] Please refer to Figure 3 , Figure 3 This is a structural diagram of a packaging substrate 200 provided in an embodiment of this application. In some embodiments, the packaging substrate 200 may include a redistribution layer 220 (RDL). The redistribution layer 220 includes conductive lines 221 and a dielectric layer 222. The conductive lines 221 can rearrange the I / O (input / output) ports, placing them in a more spacious area and forming a planar array arrangement. Thus, the redistribution layer 220 serves to rearrange and distribute electrical signals. The first chip 310 can be connected to the conductive lines 221 of the redistribution layer 220 via bumps, and the second chip 320 can be connected to the conductive lines 221 of the redistribution layer 220 via leads 400.

[0056] To increase the interconnect density between chips 300 in the semiconductor stack structure 110, it is necessary to reduce the linewidth and increase the line density of the redistribution layer 220 in the packaging substrate 200. In some embodiments, the redistribution layer 220 can be fabricated on an advanced packaging line. However, the wire bonding between the chips 300 and the packaging substrate 200 still needs to be performed on a conventional packaging line.

[0057] In some embodiments, after the redistribution layer 220 is fabricated on an advanced process line, it needs to be diced to a suitable size before being transported to a conventional packaging line for wire bonding. However, because the redistribution layer 220 is relatively thin, it is prone to warping and deformation during dicing, which can make it difficult to increase the number of chips 300 in the semiconductor stack structure 110, or result in poor performance of the semiconductor stack structure 110.

[0058] In view of this, continue to refer to Figure 3The packaging substrate 200 includes a substrate 210, which includes a substrate body 211 and a plurality of conductive pillars 212. The conductive pillars 212 penetrate at least a portion of the substrate body 211 along a first direction Y. The packaging substrate 200 also includes a connecting portion 230, which is located on one side of the substrate 210 along the first direction Y and contacts the conductive pillars 212. A redistribution layer 220 is located on the other side of the substrate 210 along the first direction Y and contacts the conductive pillars 212.

[0059] For ease of explanation, the direction perpendicular to the substrate body 211 will be referred to as the first direction Y. The conductive post 212 penetrates at least a portion of the substrate body 211 along the first direction Y, which can be understood as: the conductive post 212 penetrates the entire substrate body 211 along the first direction Y (e.g., ...). Figure 3 (as shown), or, the conductive post 212 penetrates a portion of the substrate body 211 along the first direction Y (as shown). Figure 4 (As shown).

[0060] Please refer to Figure 3 The substrate body 211 can be generally plate-shaped, and this plate-shaped structure can be perpendicular to the first direction Y. By setting the substrate body 211, it can provide a certain degree of support and load-bearing for the redistribution layer 220. In this embodiment, the material of the substrate body 211 may include molding materials, such as epoxy molding compound (EMC), to give the substrate body 211 good stability and a certain degree of compressive strength. For example, at the highest operating temperature of the packaging substrate 200 or under processes such as grinding, epoxy molding compound is not prone to chemical or physical changes.

[0061] Please continue to refer to Figure 3 In some embodiments, the redistribution layer 220 includes conductive lines 221, the linewidth of which can be less than 8 μm. This application does not impose any limitations on this. With the above configuration, the smaller the linewidth of the conductive lines 221, the greater the line density of the conductive lines 221 in the redistribution layer 220. Furthermore, because multiple chips 300 in the semiconductor stack structure 110 are co-bonded with the redistribution layer 220 of the packaging substrate 200, increasing the line density of the conductive lines 221 in the redistribution layer 220 is necessary to meet the high-density interconnection requirements between the chips 300 and the packaging substrate 200 in the application of the semiconductor stack structure 110.

[0062] Please continue to refer to Figure 3 and combined Figure 2The conductive post 212 can be approximately cylindrical in shape, and its extension direction can be parallel to the first direction Y. One end of the conductive post 212 along the first direction Y can be connected to the conductive line 221 of the redistribution layer 220, and the other end of the conductive post 212 along the first direction Y can be connected to the connection portion 230. By providing the conductive post 212, interconnection between the redistribution layer 220 and the connection portion 230 can be achieved. In this embodiment, the material of the conductive post 212 may include one or more conductive materials selected from copper, nickel, gold, titanium, cobalt, tungsten, etc., or other conductive alloy materials; this application does not impose any limitations on this.

[0063] Please continue to refer to Figure 3 The distance between any two adjacent conductive posts 212 is less than 15 mm. For example, the distance between any two adjacent conductive posts 212 can be 13 mm, 10 mm, or 8 mm. Since this distance is smaller than the size of the chip 300, limiting the distance between two adjacent conductive posts 212 prevents the chip 300 from being placed between two adjacent conductive posts 212. Furthermore, this setting also helps to increase the distribution density of conductive posts 212 in the substrate 210, further improving the rigidity of the substrate 210, and thus reducing the warpage of the packaging substrate 200.

[0064] In summary, through the above arrangement, the conductive post 212 connects the redistribution layer 220 and the connection portion 230, thereby interconnecting the redistribution layer 220 and the connection portion 230. In practical applications, the redistribution layer 220 can be connected to the chip 300 (in conjunction with...). Figure 2 As shown), the connecting part 230 is connected to the circuit board 120 (in combination). Figure 1 As shown, the packaging substrate 200 functions as an adapter board, enabling the chip 300 to connect to the circuit board 120. Simultaneously, the inclusion of the substrate body 211 and multiple conductive posts 212 improves the rigidity of the substrate 210 and reduces warpage of the packaging substrate 200. Furthermore, the distance between any two adjacent conductive posts 212 is less than 15mm, which is smaller than the size of the chip 300, making it impossible to place the chip 300 between adjacent conductive posts 212. This arrangement further enhances the rigidity of the substrate 210 and reduces warpage of the packaging substrate 200. Since the packaging substrate 200 possesses a certain rigidity, the linewidth of the conductive lines 221 in the redistribution layer 220 can be reduced, thereby increasing the circuit density and meeting the requirement for high-density interconnection between the chip 300 and the packaging substrate 200.

[0065] Please continue to refer to Figure 3 In some embodiments, the coefficient of thermal expansion of the dielectric layer 222 is the same as or similar to that of the substrate body 211.

[0066] For example, the material of dielectric layer 222 may include organic materials such as polyimide (PI), benzocyclobutene (BCB), ajinomoto build-up film (ABF), etc.

[0067] In some examples, the material of dielectric layer 222 can be the same as or similar to the material of substrate body 211 to ensure that their coefficients of thermal expansion are the same or similar. When the ambient temperature changes (e.g., a sudden drop in ambient temperature, or a high operating temperature of the package substrate 200), the equivalent thermal stress of dielectric layer 222 and substrate body 211 is the same or similar, reducing the interaction force between them and thus decreasing stress deformation, thereby mitigating the warpage of package substrate 200. Simultaneously, when the materials are the same or similar, the adhesion between substrate body 211 and redistribution layer 220 is better, which helps improve the connection reliability between substrate body 211 and redistribution layer 220.

[0068] Here, "similar" can be understood as the difference between the thermal expansion coefficient of dielectric layer 222 and the thermal expansion coefficient of substrate body 211 being within 10%.

[0069] Please refer to Figure 4 In some embodiments, the substrate body 211 may include a first layer 2111 and a second layer 2112 stacked together, and the second layer 2112 may be disposed between the first layer 2111 and the redistribution layer 220.

[0070] Please continue to refer to Figure 4 As described in the above embodiments, the conductive post 212 penetrates at least a portion of the substrate body 211. For example, the conductive post 212 may penetrate the second layer 2112 of the substrate body 211, so that the conductive post 212 penetrates a portion of the substrate body 211. Correspondingly, the connecting portion 230 may penetrate the first layer 2111 to contact the conductive post 212, so that the connecting portion 230 can be connected to the conductive post 212. For example, the first layer 2111 may have a through hole 700, and the connecting portion 230 extends into the through hole 700 and contacts the conductive post 212.

[0071] Please refer to Figure 5 The conductive post 212 can penetrate through both the first layer 2111 and the second layer 2112, so that the conductive post 212 penetrates the entire substrate body 211. Correspondingly, the connecting portion 230 can be located on the side of the first layer 2111 opposite to the second layer 2112, and the connecting portion 230 can contact the conductive post 212. For example, the first layer 2111 can have a through hole 700, through which the conductive post 212 penetrates and contacts the connecting portion 230.

[0072] With the above configuration, the multi-layer structure of the substrate body 211 is conducive to further improving the rigidity of the packaging substrate 200, mitigating the deformation of the substrate body 211 caused by changes in the external environment, such as under pressure (e.g., under pressure during grinding processes), and further controlling the warping of the packaging substrate 200.

[0073] In the above embodiments, the coefficients of thermal expansion of the first layer 2111 and the second layer 2112 can be similar. Here, "similar" can be understood as the difference between the coefficients of thermal expansion of the first layer 2111 and the second layer 2112 being within 10%. As described in the above embodiments, when the coefficients of thermal expansion of the first layer 2111 and the second layer 2112 are similar, under changes in ambient temperature (e.g., sudden cooling or heating of the ambient temperature, or a high operating temperature of the packaging substrate 200), the equivalent thermal stresses of the first layer 2111 and the second layer 2112 are similar, which reduces the interaction force between the first layer 2111 and the second layer 2112, thereby reducing the stress deformation between the first layer 2111 and the second layer 2112, and achieving the purpose of reducing the warpage of the packaging substrate 200. Meanwhile, when the materials of the two are similar, the bonding effect between the first layer 2111 and the second layer 2112 is better than that of using materials with greater differences. This also helps to improve the connection reliability between the substrate body 211 and the redistribution layer 220.

[0074] In some embodiments, the material of the first layer 2111 may include an organic material, such as polyimide (PI), ajinomoto build-up film (ABF), etc. In some embodiments, the material of the second layer 2112 may include a molding material.

[0075] With the above configuration, the thermal expansion coefficient of the first layer 2111 is similar to that of the dielectric layer 222 in the redistribution layer 220, and the thermal expansion coefficient of the first layer 2111 is also similar to that of the second layer 2112. This makes the equivalent thermal stress between the first layer 2111, the second layer 2112, and the dielectric layer 222 similar, thereby reducing the interaction force between the first layer 2111, the second layer 2112, and the dielectric layer 222, and further reducing the stress deformation between the first layer 2111, the second layer 2112, and the dielectric layer 222, thus achieving the purpose of reducing the warpage of the packaging substrate 200.

[0076] Please refer to Figure 6In some embodiments, the packaging substrate 200 may further include an electronic device 240 located between two adjacent conductive pillars 212. A connector 241 is provided on the side of the electronic device 240 away from the connection portion 230, and the electronic device 240 can be connected to the conductive line 221 of the redistribution layer 220 in the packaging substrate 200 through the connector 241. The connector 241 of the electronic device 240 may, for example, include the pins of the electronic device 240.

[0077] Please continue to refer to Figure 6 In an embodiment where the substrate body 211 includes a single-layer film, the electronic device 240 can penetrate the entire substrate body 211, wherein the electronic device 240 can be located between two adjacent conductive pillars 212.

[0078] Please refer to Figure 7 and Figure 8 In embodiments where the substrate body 211 includes a first layer 2111 and a second layer 2112, the electronic device 240 may penetrate a portion of the substrate body 211. For example, the electronic device 240 may be located between the first layer 2111 and the redistribution layer 220, and the electronic device 240 may penetrate the second layer 2112. The electronic device 240 may also be located between two adjacent conductive pillars 212.

[0079] In some other embodiments where the substrate body 211 includes a first layer 2111 and a second layer 2112, the electronic device 240 may also penetrate the entire substrate body 211. For example, the electronic device 240 may penetrate the first layer 2111 and the second layer 2112, and the electronic device 240 may be located between two adjacent conductive pillars 212.

[0080] Of course, the embodiment of this application does not specifically limit the arrangement of the electronic device 240. The electronic device 240 is located in the packaging substrate 200 and can be connected to the redistribution layer 220.

[0081] In some embodiments, corresponding electronic devices 240 may be provided according to different application requirements. In this embodiment, the electronic devices 240 may include active devices and passive devices. Active devices may include transistors, diodes, etc., and passive devices may include capacitors, inductors, resistors, etc.

[0082] In this embodiment, the electronic device 240 may further include an integrated passive device (IPD). This application does not limit the number or type of the electronic device 240.

[0083] By setting up the above configuration, placing the electronic device 240 between two adjacent conductive pillars 212 can improve the performance of the packaging substrate 200 while avoiding the electronic device 240 occupying a large space in the packaging substrate 200, thus improving the integration of the packaging substrate 200.

[0084] Please refer to Figure 9 , Figure 9 This is a flowchart illustrating the steps of a method for fabricating a packaging substrate 200 according to an embodiment of this application. The method includes steps S101 to S105.

[0085] S101, Provide carrier board.

[0086] Please refer to Figure 10 Provides a 600 carrier board.

[0087] The carrier 600 may be made of ceramic, glass, silicon, or any other suitable material that can serve as a load-bearing material. It is understood that some subsequent processes will need to be performed on the carrier 600, hence the provision of a temporary carrier 600.

[0088] In this embodiment, after providing the carrier board 600, step S102 is also included.

[0089] S102. A substrate is formed on a carrier plate. The substrate includes a substrate body and a plurality of conductive pillars. The conductive pillars penetrate the substrate body along a first direction, and the distance between any two adjacent conductive pillars is less than 15 mm.

[0090] Please refer to Figure 11 After providing the carrier plate 600, multiple conductive pillars 212 can be formed on the carrier plate 600.

[0091] Conductive pillars 212 can be formed on the carrier substrate 600 using through-mold via (TMV) technology. Alternatively, the conductive pillars 212 can be formed using a layer-addition method. Forming the conductive pillars 212 provides rigidity to the packaging substrate 200. The spacing of the conductive pillars 212 does not exceed 15 mm, which helps to increase the distribution density of the conductive pillars 212 in the packaging substrate 210, further improving the rigidity of the packaging substrate 200 and controlling warpage.

[0092] Please continue to refer to Figure 11 After the conductive pillars 212 are formed, molding material can be filled between the multiple conductive pillars 212 to form the substrate body 211.

[0093] For example, molding, lamination, chemical vapor deposition (CVD), physical vapor deposition (PVD), coating, spin coating, etc., can be employed. The substrate body 211 is formed around the conductive pillars 212, and the substrate body 211 is positioned between adjacent conductive pillars 212. Through this arrangement, the substrate body 211 can fix the conductive pillars 212. Simultaneously, due to the good stability and certain compressive strength of the substrate body 211, the performance of the packaging substrate 200 can be stabilized.

[0094] For ease of explanation, the surface of the substrate body 211 facing away from the carrier plate 600 will be referred to as the first end surface 800, and the surface of the substrate body 211 facing closer to the carrier plate 600 will be referred to as the second end surface 900.

[0095] In some embodiments, after filling the space between the plurality of conductive pillars 212 with molding material, the method for preparing the encapsulation substrate 200 further includes: grinding a first end face 800 of the substrate body 211, the first end face 800 being located on the side of the substrate body 211 facing away from the carrier plate 600. This arrangement exposes the conductive pillars 212 to the first end face 800, and simultaneously adjusts the flatness of the first end face 800.

[0096] For example, the first end face 800 of the grinding substrate body 211 can be ground on the side of the substrate body 211 facing away from the carrier plate 600. Grinding can include backside grinding (BG) and chemical mechanical polishing (CMP).

[0097] In this embodiment, after the substrate 210 is formed, step S103 is also included.

[0098] S103. A redistribution layer is formed on one side of the substrate, and the redistribution layer is in contact with the conductive pillar.

[0099] Please refer to Figure 12 A redistribution layer 220 is formed on one side of the substrate 210. The redistribution layer 220 may include conductive lines 221 and a dielectric layer 222, such that the conductive lines 221 are in contact with the conductive pillars 212. For example, forming the redistribution layer 220 includes: forming the dielectric layer 222; after forming the dielectric layer 222, a circuit pattern may be formed by a process such as photolithography, and then the conductive lines 221 may be formed by electroplating. The above steps may be repeated multiple times to form the redistribution layer 220.

[0100] This allows the conductive line 221 in the redistribution layer 220 to come into contact with the conductive post 212, thereby connecting the conductive post 212 to the redistribution layer 220.

[0101] In some embodiments, the line width of the conductive line 221 is made less than 8 μm to increase the line density of the conductive line 221 in the redistribution layer 220.

[0102] In this embodiment, after the redistribution layer 220 is formed, step S104 is also included.

[0103] S104. Remove the carrier plate.

[0104] Please refer to Figure 12 and Figure 13 After removing the carrier plate 600, the substrate 210 has a certain rigidity and can bear and withstand pressure during processes such as grinding.

[0105] In this embodiment, after removing the carrier plate 600, step S105 is also included.

[0106] S105. A connection portion is formed on the other side of the substrate, and the connection portion contacts the conductive post.

[0107] Please continue to refer to Figure 13 In some embodiments, the process includes grinding the second end face 900 to smooth the surface flatness of the substrate body 211 while exposing the conductive pillars 212 to the second end face 900 of the substrate body 211.

[0108] Please continue to refer to Figure 13 A connection portion 230 is formed on the other side of the substrate 210. For example, using surface mount technology (SMT), at the location where the conductive post 212 is exposed on the second end face 900 of the substrate body 211, the conductive post 212 is connected using soldering material. Heating melts the soldering material, thereby forming the connection portion 230, wherein the connection portion 230 contacts the conductive post 212. With the above arrangement, the conductive post 212 connects the redistribution layer 220 and the connection portion 230. The soldering material may include solder paste.

[0109] In some embodiments, the connection portion 230 may further include solder balls, which may be formed by a ball-planting process to enable electrical interconnection between the solder balls and the conductive post 212.

[0110] Please refer to Figure 14In some embodiments, after forming a plurality of conductive pillars 212 on the carrier plate 600 and before filling the space between the plurality of conductive pillars 212 with molding material, the method for preparing the encapsulation substrate 200 further includes: placing an electronic device 240 between two adjacent conductive pillars 212, the electronic device 240 being located on the carrier plate 600, and a connector 241 being provided on the side of the electronic device 240 facing away from the connector 230.

[0111] As described in the above embodiments, the first end face 800 of the substrate body 211 is polished so that the conductive post 212 is exposed on the first end face 800. Further, while polishing the first end face 800 of the substrate body 211, the connector 241 of the electronic device 240 is also exposed on the first end face 800.

[0112] In this way, the electronic device 240 can be disposed in the packaging substrate 200, and the connector 241 of the electronic device 240 is exposed on the first end face 800, so that the electronic device 240 is connected to the conductive line 221, thereby realizing the connection between the electronic device 240 and the redistribution layer 220 (e.g., Figure 6 (As shown).

[0113] Please refer to Figure 15 In some embodiments, before forming a plurality of conductive pillars 212 on the carrier 600, the method for preparing the packaging substrate 200 further includes forming a first layer 2111 on the carrier 600. For example, the first layer 2111 can be formed by processes such as lamination, chemical vapor deposition (CVD), physical vapor deposition (PVD), coating, or spin coating. The material of the first layer 2111 includes organic materials. The organic material of the first layer 2111 can be as described in the above embodiments, and will not be repeated here.

[0114] After the first layer 2111 is formed, a portion of the first layer 2111 can be removed to form a through-hole 700 penetrating the first layer 2111. For example, a portion of the first layer 2111 can be removed by processes such as laser drilling or photolithography.

[0115] After forming the through hole 700, a conductive post 212 can be formed within the through hole 700. The conductive post 212 can be formed using the steps described in the above embodiments, and will not be repeated here. Furthermore, the conductive post 212 not only fills the through hole 700, but can also extend from the through hole 700 to the side opposite to the carrier plate 600, so that the dimension of the conductive post 212 along the first direction Y is larger than the dimension of the first layer 2111 along the first direction Y.

[0116] In some embodiments, after the conductive pillar 212 is formed in the through hole 700, an electronic device 240 may be disposed between two adjacent conductive pillars 212. With the above arrangement, the electronic device 240 is located on the side of the first layer 2111 facing away from the carrier plate 600.

[0117] As described in the above embodiments, after the electronic device 240 is disposed, a substrate body 211 can be formed to form a substrate 210. The substrate body 211 can be fabricated and formed as described in the above embodiments, and will not be repeated here.

[0118] Please refer to Figure 16 After forming the substrate 210, the redistribution layer 220 can be formed through the steps described in step S103 above. After forming the redistribution layer 220, the carrier board 600 is removed as described in step S104 above. After removing the carrier board 600, the connection portion 230 is formed as described in step S105 above to form the encapsulation substrate 200, which will not be described again here.

[0119] Please refer to Figure 17 In some other embodiments, before forming a plurality of conductive pillars 212 on the carrier plate 600, the method for preparing the encapsulation substrate 200 further includes: forming a first layer 2111 on the carrier plate 600, wherein the material of the first layer 2111 includes an organic material.

[0120] After the first layer 2111 is formed, a plurality of conductive pillars 212 are formed. The fabrication process for forming the plurality of conductive pillars 212 can be as described in the above embodiments, and will not be repeated here.

[0121] In some embodiments, after forming a plurality of conductive pillars 212, an electronic device 240 may be disposed between two adjacent conductive pillars 212. With the above arrangement, the electronic device 240 is located on the side of the first layer 2111 facing away from the carrier plate 600.

[0122] After forming the plurality of conductive pillars 212 and the electronic device 240, a substrate body 211 can be formed. The formation of the substrate body 211 can be as described in the above embodiments, and will not be repeated here.

[0123] Please refer to Figure 18 As shown, the redistribution layer 220 can be formed through step S103. After the redistribution layer 220 is formed, the carrier board 600 can be removed through the above step S104, which will not be described in detail here.

[0124] After removing the carrier plate 600 and before forming the connection portion 230 on the other side of the substrate 210, the method for preparing the encapsulation substrate 200 further includes: removing a portion of the first layer 2111 to form a through-hole 700 exposing the conductive pillars 212. Exemplary removal methods may include grinding, chemical etching, physical etching, etc.

[0125] After removing part of the first layer 2111 to form a through hole 700, a connecting portion 230 can be formed on the other side of the substrate 210. For example... Figure 18 As shown, a connection portion 230 is formed on the second end face 900 of the substrate 210. The step of forming the connection portion 230 may include forming the connection portion 230 within a through-hole 700, such that a conductive post 212 is connected to the connection portion 230. In this case, the conductive post 212 can penetrate the second layer 2112 of the substrate body 211, and the conductive post 212 connects the redistribution layer 220 to the connection portion 230.

[0126] Please refer to Figure 19 As shown, in some embodiments, after step S103, the entire packaging substrate 200 is further cut. The cutting method may include laser cutting, hybrid cutting, etc., and the embodiments of this application do not limit the cutting method.

[0127] For example, after the connecting portion 230 can be formed in step S105, the entire encapsulation substrate 200 can be laser-cut first, and then cut with a blade. For example, the encapsulation substrate 200 can be cut to a size with a width W of approximately 77.5 mm and a height L of approximately 240 mm (e.g., ...). Figure 19 (As shown). In this embodiment, the dimensions of the packaged substrate 200 after cutting are not limited; the specific dimensions are subject to application requirements.

[0128] With the above settings, the packaging substrate 200 can be cut to a suitable size so that the packaging substrate 200 can be sent to the strip packaging processing line for packaging processing.

[0129] For example, the packaging substrate 200 is transferred to a strip packaging processing line for packaging processing. At least one chip 300 is flip-chip bonded to the packaging substrate 200, and at least one chip 300 is wire-bonded to the packaging substrate 200, so that the semiconductor stack structure 110 can achieve hybrid bonding. Through the above-described method for preparing the packaging substrate 200, the warpage of the packaging substrate 200 can be reduced, and the line width of the redistribution layer 220 can be further reduced, thereby further increasing the line density of the redistribution layer 220. This allows the redistribution layer 220 of the packaging substrate 200 to achieve high-density interconnection after hybrid bonding with the chip 300, without being constrained by the warpage problem of the packaging substrate 200.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A packaging substrate, characterized in that, include: A substrate, the substrate comprising a substrate body and a plurality of conductive pillars, wherein the conductive pillars penetrate at least a portion of the substrate body along a first direction, and the distance between any two adjacent conductive pillars is less than 15 mm. The connecting portion is at least partially located on one side of the substrate along the first direction, and the connecting portion is in contact with the conductive post; A redistribution layer is located on the other side of the substrate along the first direction, and the redistribution layer is in contact with the conductive pillar.

2. The packaging substrate according to claim 1, characterized in that, The redistribution layer includes conductive lines and a dielectric layer. The conductive lines are in contact with the conductive pillars. The coefficient of thermal expansion of the dielectric layer is the same as or similar to that of the substrate body.

3. The packaging substrate according to claim 2, characterized in that, The substrate body includes a first layer and a second layer stacked together, with the second layer located between the first layer and the redistribution layer; the thermal expansion coefficients of the first layer and the second layer are similar.

4. The packaging substrate according to claim 3, characterized in that, The conductive post penetrates the second layer, and the connecting portion penetrates the first layer to contact the conductive post; or, the conductive post penetrates both the second layer and the first layer.

5. The packaging substrate according to claim 3 or 4, characterized in that, The material of the first layer includes organic materials; and / or, the material of the second layer includes molding materials.

6. The packaging substrate according to any one of claims 1-5, characterized in that, The packaging substrate also includes electronic devices, which are located between two adjacent conductive pillars. A connector is provided on the side of the electronic device away from the connecting portion, and the electronic device is connected to the conductive line through the connector.

7. A semiconductor stacked structure, characterized in that, The device includes a chip and a packaging substrate as described in any one of claims 1-6, wherein the chip and the packaging substrate are stacked together, and the chip is connected to the redistribution layer of the packaging substrate.

8. The semiconductor stacked structure according to claim 7, characterized in that, The number of chips is multiple.

9. An electronic device, characterized in that, It includes a circuit board and the semiconductor stack structure as described in claim 7 or 8, wherein the semiconductor stack structure is stacked on top of the circuit board, and the connection portion of the circuit board and the semiconductor stack structure is connected.

10. A method for preparing a packaging substrate, characterized in that, Provide carrier board; A substrate is formed on the carrier plate. The substrate includes a substrate body and a plurality of conductive pillars. The conductive pillars penetrate the substrate body along a first direction, and the distance between any two adjacent conductive pillars is less than 15 mm. A redistribution layer is formed on one side of the substrate, and the redistribution layer is in contact with the conductive pillar; Remove the carrier plate; A connection portion is formed on the other side of the substrate, and the connection portion contacts the conductive post.

11. The method for preparing the packaging substrate according to claim 10, characterized in that, The process of forming a substrate on the carrier plate includes: A plurality of the conductive pillars are formed on the carrier plate; Molding material is filled between the plurality of conductive pillars to form a substrate body.

12. The method for preparing the packaging substrate according to claim 11, characterized in that, Before forming the plurality of conductive pillars on the carrier plate, the method for preparing the packaging substrate further includes: A first layer is formed on the carrier plate, the material of the first layer comprising organic materials; Remove a portion of the first layer to form a through-hole penetrating the first layer; The formation of a plurality of conductive pillars on the carrier plate includes: forming the conductive pillars within the through holes.

13. The method for preparing the packaging substrate according to claim 11, characterized in that, Before forming the plurality of conductive pillars on the carrier plate, the method for preparing the packaging substrate further includes: A first layer is formed on the carrier plate, the material of the first layer comprising organic materials; After removing the carrier plate and before forming the connection portion on the other side of the substrate, the method for preparing the encapsulation substrate further includes: removing a portion of the first layer to form a through hole exposing the conductive pillars; The method of forming a connection portion on the other side of the substrate includes: forming the connection portion within the through hole.

14. The method for preparing a packaging substrate according to claim 12 or 13, characterized in that, The method for preparing the encapsulation substrate further includes, after forming the plurality of conductive pillars on the carrier plate and before filling the spaces between the plurality of conductive pillars with molding material: An electronic device is disposed between two adjacent conductive posts, and a connector is disposed on the side of the electronic device away from the connecting part; After filling the space between the plurality of conductive pillars with molding material, the method for preparing the encapsulation substrate further includes: The first end face of the substrate body is ground to expose the connector of the electronic device on the first end face, which is located on the side of the substrate body away from the carrier plate.

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