Quantum error detection map decoding with reduced delay

Abstract

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims priority to U.S. Application No. 18 / 449,314, filed August 14, 2023, entitled “LATENCY-REDUCED QUANTUM ERROR DETECTION GRAPH DECODING,” the contents of which are incorporated in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to quantum computing systems, and more particularly, to error correction for quantum computing systems. BACKGROUND

[0004] Quantum computing is a method of computing that leverages quantum effects, such as superposition of states and entanglement, to perform certain computations more efficiently than classical digital computers. Unlike digital computers, which store and process information in the form of bits (e.g., “1” or “0”), quantum computing systems can use qubits to process information. A qubit can refer to a quantum device that can superpose multiple states, e.g., data in “0” and “1” states, and / or to the superposition of the data itself in multiple states. According to conventional terminology, the superposition of “0” and “1” states in a quantum system can be represented as, for example, + b The “0” and “1” states of a digital computer are analogous to the and ground states of a qubit, respectively. SUMMARY

[0005] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or can be apparent from the description, or can be learned through practice of the embodiments.

[0006] One example aspect of the present disclosure relates to a computer-implemented method. The method includes obtaining, by one or more computing devices, a multi-dimensional quantum error detection graph. The multi-dimensional quantum error detection graph represents one or more quantum error detection measurements over a period of time. The method includes determining, by the one or more computing devices, a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection graph based at least in part on a decoding latency and a fusion latency. The method includes partitioning, by the one or more computing devices, the multi-dimensional quantum error detection graph into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding, by the one or more computing devices, each block of the plurality of blocks. The method includes fusing, by the one or more computing devices, the plurality of blocks into a decoded detection graph based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection graph.

[0007] These and other features, aspects, and advantages of various embodiments of the present disclosure will be better understood when the following description is read with reference to the accompanying drawings and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, explain related principles. BRIEF DESCRIPTION OF DRAWINGS

[0008] With reference to the accompanying drawings, a detailed discussion of embodiments in view of the ordinary level of skill in the art is set forth in the detailed description section of the specification, in which:

[0009] Figure 1 An example embodiment of a quantum computing system is depicted in accordance with example embodiments of the present disclosure.

[0010] Figure 2 An overview of an example decoding process for quantum error correction is depicted in accordance with example embodiments of the present disclosure.

[0011] Figure 3 An example partitioning scheme for partitioning a multi-dimensional quantum error detection graph is depicted in accordance with example embodiments of the present disclosure.

[0012] Figure 4 A representation of an example fusion tree data structure is depicted in accordance with example embodiments of the present disclosure.

[0013] Figure 5 A representation of an example fusion tree data structure is depicted in accordance with example embodiments of the present disclosure.

[0014] Figure 6 An example partitioning scheme resulting from a latency-optimized fusion tree (LOFT) process is depicted in accordance with example embodiments of the present disclosure.

[0015] Figure 7 A flowchart of an example method is depicted in accordance with example embodiments of the present disclosure.

[0016] Figure 8 A flowchart of an example method is depicted in accordance with example embodiments of the present disclosure.

[0017] Figure 9 A flowchart of an example method is depicted in accordance with example embodiments of the present disclosure.

[0018] Figure 10 A block diagram of an example computing system is depicted in accordance with example embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Example aspects of the present disclosure relate to systems, apparatuses, and computer-implemented methods for error detection in quantum computing systems. More specifically, example aspects relate to decoding multi-dimensional quantum error detection graphs for use in quantum error correction processes. For example, quantum error correction processes can include reducing error rates of logical qubits in a quantum computing system by detecting and tracking physical errors within the system. Uncorrected physical errors can generate errors in logical qubits, but a quantum computing system can be configured to allow physical errors to be identified and tracked. In this way, operations can be implemented (e.g., on a classical processing level) to mitigate the effects of such physical errors, thereby improving the performance of the quantum computing system.

[0020] For example, in some embodiments, each logical qubit can be encoded in a plurality of physical qubits. For example, a code (e.g., a topological code, such as a surface code) can encode a logical qubit using a plurality of data qubits and a plurality of measurement qubits. The measurement qubits can be configured such that their respective states can be measured, thereby detecting physical errors (e.g., errors in the physical qubits and / or errors in measurements of these physical qubits). These error detection measurements can be measured over a period of time, and then combined to construct an error detection graph, where the weights of the links in the graph correspond to the associated error probabilities.

[0021] Over time, the detection graphs can become large and difficult to process, and the process of decoding these graphs can also become costly (e.g., in terms of time or latency). The decoding latency can be defined as the time interval between when all measurements needed to determine a logical observable are first available and when the observable is predicted to be available. The decoding latency can limit the logical clock speed of a fault-tolerant quantum computer. Thus, there is a need in the field for a process that can efficiently and effectively decode detection graphs so that operations can be performed on the quantum computing system in a timely manner to correct potential errors.

[0022] The computational overhead of techniques that exploit error correlations can be large. For example, some techniques require processing all error detection measurements to determine a first set of results, adjusting the probabilities of certain error detection measurements according to known correlations between the first set of results, and then reprocessing all error detection measurements using the adjusted probabilities. For real-time tracking of quantum errors, the intervals between successive error detection measurements are typically on the order of microseconds, and iterative global processing of the entire set of error detection measurements can result in a large computational overhead.

[0023] Advantageously, systems and methods according to example aspects of the present disclosure allow for the creation and operation of a decoding system that can parallelize the work of the decoding system in space and time by dividing a quantum error detection graph into individual decoding blocks that can be decoded independently, and fusing the results of each block into an overall decoding prediction that can then be used to operate a quantum computing system.

[0024] For example, in some embodiments, a computer-implemented method can include one or more computing devices receiving a process of a multi-dimensional quantum error detection graph. The quantum error detection graph can represent quantum error detection measurements over a period of time. The computer-implemented method can divide the quantum error detection graph into a plurality of blocks, decode the individual blocks, and fuse the individual blocks together to obtain a decoded graph that can then be used to operate a quantum computing system.

[0025] More specifically, in some examples, a plurality of fusion tree data structures can be generated for the detection graph. Each fusion tree data structure can include a partitioning scheme for dividing the detection graph into a plurality of blocks (e.g., straight tetrapods) and a fusion plan. A delay of each fusion tree can be estimated using two functions: (1) a function for estimating a decoding time of each block; and (2) a function for estimating a fusion time of two or more blocks. A delay optimal fusion tree (LOFT) process can be implemented to determine a fusion tree that reduces the decoder delay.

[0026] The inputs to the LOFT process can include a quantum error detection graph and at least one arbitrary function that estimates the cost of: (a) decoding within a quantum error detection block; and (b) fusing two adjacent quantum error detection blocks. The LOFT process can determine which partitioning scheme and fusion scheme from a series of partitioning schemes and fusion schemes of the weighted quantum error detection graph will have the best delay, and select that partitioning scheme and fusion scheme to decode the quantum error detection blocks.

[0027] Systems and methods according to example aspects of the present disclosure can provide a number of technical effects and benefits, including but not limited to improvements in computing technology (e.g., quantum computing technology). For example, example aspects of the present disclosure can reduce the evaluation time of error information, and / or evaluate error information in a scalable manner. Example aspects of the present disclosure are also particularly focused on low latency, which is an important aspect of efficient quantum computers. This is particularly advantageous in real-world (e.g., noisy) quantum computing applications that require fast, real-time error tracking on an ever-increasing number of qubits.

[0028] Example embodiments of the present disclosure will now be discussed in further detail with reference to the accompanying drawings.

[0029] Figure 1An example quantum computing system 100 is depicted. System 100 is an example of a system of one or more classical computers and / or quantum computing devices located in one or more locations in which the systems, components, and techniques described below can be implemented. Using the disclosure provided herein, those of ordinary skill in the art will appreciate that other quantum computing devices or systems can be used without departing from the scope of the present disclosure.

[0030] System 100 includes quantum hardware 102 in data communication with one or more classical processors 104. Classical processor 104 can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. Quantum hardware 102 includes components for performing quantum computations. For example, quantum hardware 102 includes a quantum system 110, a control device 112, and a readout device 114 (e.g., a readout resonator). Quantum system 110 can include one or more multi-level quantum subsystems, such as a register of qubits (e.g., qubit 120). In some implementations, the multi-level quantum subsystems can include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, spin-based qubits, and the like.

[0031] The type of multi-level quantum subsystems used by system 100 can vary. For example, in some cases, it can be convenient to include one or more readout devices 114 attached to one or more superconducting qubits (e.g., transmon qubits, flux qubits, gmon qubits, xmon qubits, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities (e.g., with which a qubit can not be needed to prepare a state) can be used. Additional examples of implementations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots, or phosphorus quantum bits.

[0032] A quantum circuit can be constructed and applied to a register of qubits included in quantum system 110 via a plurality of control lines coupled to one or more control devices 112. An example control device 112 operating on a register of qubits can be used to implement a quantum gate or a quantum circuit having a plurality of quantum gates, such as a Pauli gate, an Hadamard gate, a controlled not (CNOT) gate, a controlled phase gate, a T gate, a multi-qubit quantum gate, a coupler quantum gate, and the like. One or more control devices 112 can be configured to operate on quantum system 110 by one or more respective control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystems can be superconducting qubits, and control device 112 can be configured to provide control pulses to the control lines to produce a magnetic field to adjust the frequency of the qubits.

[0033] Quantum hardware 102 may further include a readout device 114 (e.g., a readout resonator). Measurement results 108 acquired via the measurement device can be provided to classical processor 104 for processing and analysis. In some implementations, quantum hardware 102 may include quantum circuits, and control device 112 and readout device 114 may implement one or more quantum logic gates that operate quantum hardware 102 via physical control parameters (e.g., microwave pulses) transmitted via wires included in quantum hardware 102. Further examples of the control device include an arbitrary waveform generator, wherein a DAC (digital-to-analog converter) creates the signal.

[0034] The readout device 114 can be configured to perform a quantum measurement on the quantum system 110 and send the measurement result 108 to the classical processor 104. Additionally, the quantum hardware 102 can be configured to receive data from the classical processor 104 specifying physical control qubit parameter values ​​106. The quantum hardware 102 can use the received physical control qubit parameter values ​​106 to update the actions of the control device 112 and the readout device 114 on the quantum system 110. For example, the quantum hardware 102 can receive data specifying a new value representing the voltage intensity of one or more DACs included in the control device 112, and the quantum hardware can update the actions of the DACs on the quantum system 110 accordingly. The classical processor 104 can be configured, for example, to initialize the quantum system 110 in an initial quantum state by sending data specifying an initial parameter set 106 to the quantum hardware 102.

[0035] In some implementations, the readout device 114 may utilize elements of a quantum system (such as qubits). and The impedance difference between states is used to measure the state of an element (e.g., a qubit). For example, due to the nonlinearity of the qubit, when the qubit is in a state... or state The resonant frequency of the readout resonator can be different. Therefore, the microwave pulse reflected from the readout device 114 carries an amplitude and phase shift that depends on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device 114 to block microwave propagation at the qubit frequency.

[0036] In some embodiments, the quantum system 110 may include, for example, a plurality of qubits 120 arranged in a two-dimensional grid 122. For clarity, Figure 1The two-dimensional grid 122 depicted includes 4x4 qubits; however, in some implementations, system 110 may include fewer or more qubits. In some embodiments, multiple qubits 120 may interact with each other via multiple qubit couplers (e.g., qubit coupler 124). A qubit coupler can define the nearest-neighbor interaction between the multiple qubits 120. In some implementations, the strength of the multiple qubit couplers is an adjustable parameter. In some cases, the multiple qubit couplers included in the quantum computing system 100 may be couplers with a fixed coupling strength.

[0037] In some implementations, each of the multiple qubits 120 can operate using a corresponding operating frequency, such as an idle frequency and / or an interaction frequency and / or a readout frequency and / or a reset frequency. The operating frequencies of different qubits can be different. For example, each qubit may be idle at a different operating frequency. The operating frequencies of the qubits 120 can be selected before computation is performed.

[0038] In some implementations, the plurality of qubits 120 may include data qubits (such as qubit 126) and measurement qubits (such as qubit 128). Data qubits are qubits that participate in computations performed by system 100. Measurement qubits are qubits that can be used to determine the result of a computation performed by the data qubits. That is, during computation, the unknown state of a data qubit is transferred to a measurement qubit using appropriate physical operations and measured via appropriate measurement operations performed on the measurement qubit.

[0039] In some examples, the qubit grid 122 can serve as a quantum surface code. For example... Figure 2 As shown, the qubit grid 122 can be an interleaved qubit grid containing one or more data qubits 126 and / or one or more measurement qubits 128. For example, time series of quantum gate operations can be implemented using some or all of the data qubits 126, thereby defining a quantum algorithm on some or all of the data qubits 126. The data qubits 126 can be surrounded by the measurement qubits 128. Additionally and / or alternatively, the measurement qubits 128 can be positioned within a square or other surface defined by two or more (e.g., four) data qubits 126. The measurement qubits 128 can be configured to provide readouts from the output of the data qubits 126 and / or measure errors (e.g., parity) in these outputs. Errors can be detected based on parity or differences between the measurement qubits 128 surrounding or near the data qubits 126.

[0040] Figure 1An example quantum computing system that can be used to implement the methods and operations according to the example aspects of this disclosure is described. Other quantum computing systems may be used without departing from the scope of this disclosure.

[0041] Figure 2 A quantum computing system (e.g., according to an example embodiment of this disclosure) is described. Figure 1 At least part of the error detection process of a quantum computing system. Figure 2 An example of generating an error detection map 130 from an example qubit grid 122 (e.g., a surface code) is depicted. The error detection map 130 may have x-axis and y-axis corresponding to the xy-space dimensions of the surface code. The error detection map 130 may have a z-axis corresponding to time. The error detection map 130 may have nodes corresponding to detected events (e.g., endpoints of parity mismatches). For example, in some implementations, the computational system may receive error information including coordinates describing the endpoints of parity mismatches (e.g., between data qubits and / or measurement qubits). This can be used to construct the error detection map 130. The error detection map 130 may be provided to a decoder 140, which may decode portions of the error detection map 130 in parallel. In some examples, decoding the error detection map 130 may include solving for the minimum-cost alternating path between endpoint pairs to provide a decoded map 150. The minimum-cost alternating path may indicate the most likely source of error leading to a parity mismatch at the endpoint. Therefore, the minimum-cost alternating path may indicate the location of the qubit where the error occurred. In some cases, these errors can propagate in quantum computing, so timely detection and / or correction can be beneficial.

[0042] According to an example aspect of this disclosure, the quantum error detection graph 130 can be divided into blocks for parallel processing by the decoder 140. These blocks can be decoded in parallel and then rejoined to reduce latency. According to an example aspect of this disclosure, the LOFT process 145 can be implemented, for example, by a classical computing system, to determine the optimal method for dividing the error detection graph into blocks (e.g., rectangular prisms), decoding each individual block, and rejoining these blocks to reduce latency in the decoding process.

[0043] Figure 3 An example partition of error detection graph 130 is depicted. More specifically, Figure 3Two different partitioning schemes for dividing the error detection map 130 are depicted. In partitioning scheme 202, the error detection map 130 is divided into blocks 202.1, 202.2, 202.3, ..., 202.n by partitioning along the time dimension (z-axis). Each block in blocks 202.1, 202.2, 202.3, ..., 202.n can be decoded (e.g., in parallel) and then re-fused together to provide a decoded error detection map. In partitioning scheme 202, each block 202.1, 202.2, 202.3, ..., 202.n has the same size.

[0044] In partitioning scheme 204, the error detection map 130 is divided into blocks 204.1, 204.2, ..., 204.27, ..., 204.n by partitioning along the time dimension (z-axis) and along the spatial dimensions (x- and y-dimensions) associated with the qubit grid 122 (e.g., surface code). Each block in blocks 204.1, 204.2, ..., 204.27, ..., 204.n can be decoded (e.g., in parallel) and then rejoined to provide a decoded error detection map. In partitioning scheme 204, each block 204.1, 204.2, ..., 204.27, ..., 204.n is of equal size.

[0045] Figure 3 Two example partitioning schemes are depicted for illustrative and discussion purposes. Those skilled in the art will understand using the disclosure provided herein that the error detection graph 130 can be partitioned and re-merged in various ways. According to an example aspect of this disclosure, a LOFT process can be implemented to determine the optimal way to partition and merge the blocks to reduce latency when processing the error detection graph 130.

[0046] Each block 202.1, 202.2, 202.3, ..., 202.n or block 204.1, 204.2, ..., 204.27, ..., 204.n can have a volume. Furthermore, adjacent blocks can have merged regions. For example, block 202.1 can have a volume V and a boundary area A for merging with data block 202.2. The cost of decoding a block of volume V is c1. V. The cost of merging blocks with boundary areas of A is c2. A.

[0047] As used herein, each decoding module is shown as a right square prism. Those skilled in the art will understand using the disclosure provided herein that the blocks may have other suitable shapes without departing from the scope of this disclosure.

[0048] The LOFT process determines which fusion tree (e.g., partitioning scheme and fusion scheme) provides the optimal latency (e.g., minimum latency) for decoding the error detection graph. The input to the LOFT process can be the error detection graph and two functions that estimate the cost / latency of decoding a block and the cost / latency of merging two blocks together. An example function for estimating the cost / latency associated with the fused block can provide a constant latency / cost for merging two blocks. Another example function for estimating the cost / latency associated with the fused block can provide a cost / latency proportional to the boundary area A between the two blocks. For example, a disjoint-set data structure-based algorithm and / or the minimum weighted perfect matching (MWPM) algorithm can be used to determine the decoding cost / latency associated with the decoded block.

[0049] According to an example aspect of this disclosure, the LOFT process can determine multiple fused tree data structures for an error detection graph. Figure 4 A representation of an example fusion tree 250 according to an example aspect of this disclosure is depicted. Each fusion tree 250 comprises two components. The first component is a partitioning scheme 252 for partitioning the error detection graph 130 (e.g., partitioning scheme 202) into multiple blocks. The second component is a tree data structure 254 that specifies the partial order relation for fusion of the blocks (e.g., blocks 202.1, 202.2, and 202.3).

[0050] As shown in the figure, blocks 202.1 (block A), 202.2 (block B), and 202.3 (block C) are represented by leaf nodes in tree data structure 254. Figure 4 In the example, blocks 202.1 and 202.2 are merged together to generate a merged block represented by node 256. The merged block represented by node 256 is then merged with block 202.3 to generate a merged block represented by node 258. For purposes of illustration and discussion, aspects of this disclosure will be discussed using a binary tree as an example. Those skilled in the art will understand using the disclosure provided herein that aspects of this disclosure can be implemented using a tree structure of any degree (e.g., a ternary tree, etc.).

[0051] For each partitioning scheme, there may be multiple fusion trees. For example, Figure 5 Another example fusion tree 260 associated with partitioning scheme 252 is depicted. Figure 5In the example, the fusion tree 260 includes two components. The first component is a partitioning scheme 252, which divides the error detection graph 130 (e.g., partitioning scheme 202) into multiple blocks. The second component is a tree data structure 264, which specifies the partial order relation that merges the blocks (e.g., blocks 202.1, 202.2, and 202.3) together.

[0052] As shown in the figure, blocks 202.1 (block A), 202.2 (block B), and 202.3 (block C) are represented by leaf nodes in the tree data structure 264. Figure 5 In the example, blocks 202.2 and 202.3 are merged together to generate a merged block represented by node 266. Then, the merged block represented by node 266 is merged with block 202.1 to generate a merged block represented by node 268.

[0053] Various aspects of this disclosure relate to determining a fusion tree that provides optimal latency for decoding an error detection map. For example, given a detection map G = (V, E), the fusion tree W of G is a tuple W = (L, T), where:

[0054] (1) L is a list of disjoint subsets of V, L = [S1,…,S2] n The union of these subsets is V (the set of detector vertices in the matching graph). This is an example partitioning scheme.

[0055] (2) There is a rooted tree T, with the root node labeled r and the n leaf nodes labeled 1, ..., n. This is a tree data structure.

[0056] The fusion tree W specifies the procedure for decoding on graph G. S i It is a block. The n leaf nodes correspond to S1, ..., S2 respectively. n Each block can be decoded individually, and decoding begins once the final measurement for each block is available. These blocks are then merged according to T, where each internal node corresponds to the merging of its child nodes.

[0057] To estimate the decoding latency of the fused tree W = (L, T), we estimate the time for decoding within a block and the time for merging two blocks together. For example, suppose each vertex v ∈ V has a time coordinate t(v) at which the vertex becomes available. For convenience, given a subset S V, definition

[0058] t(S) := maxv ∈ S t(v)

[0059] The delay in decoding a subset S of V is defined as the difference between t(S) and the time it takes to decode S. Assume we can use two functions:

[0060] (1) Tdecode(S) returns the time of the decoded set S.

[0061] (2) Tfuse(S1, S2) returns the result of fusing the outputs decoded on S1 and S2 respectively into a single output on S1. The time of the output decoded on S2.

[0062] Tfuse and Tdecode can be arbitrary functions. As discussed above, Tfuse can provide a constant latency / cost for merging two blocks. Another example function for estimating the cost / latency associated with a merged block can provide a cost / latency proportional to the boundary area A between the two blocks. For example, Tdecode can include disjoint-set data structure-based algorithms and / or minimum weighted perfect matching (MWPM) algorithms. In some examples, the empirical observation detection frequency per vertex in G can be used to better estimate Tfuse and Tdecode. In some examples, Tfuse and Tdecode can include latency / cost lookup tables based on, for example, block size or other parameters.

[0063] The delay W of the fusion tree can be determined as follows. Each vertex v ∈ T corresponds to an intermediate decoded output of a subset S(v). This output will become available at some time as follows. The leaf node marked i in T corresponds to the decoding within block Si. This process can begin exactly at t(Si) (i.e., the sooner the better). Then, the output will become available at time t(i) := t(Si) + Tdecode(Si).

[0064] An internal node v ∈ T with child nodes c1 and c2 corresponds to the fusion of the outputs of these child nodes. This process begins at max(t(c1), t(c2)) and completes within time Tfuse(S(c1), S(c2)). Therefore, t(v) := max(t(c1), t(c2)) + Tfuse(S(c1), S(c2)).

[0065] The delay in decoding graph G using the fusion tree W = (L, T) is denoted as Latency(W). As shown above, Latency(W) = t(r) - t(V), where r is the root node of T. Given W and G, Latency(W) is easily computed. We can either start recursively from the root node or simply construct t(v) for each node v ∈ T starting from the leaf nodes.

[0066] In some examples, the LOFT procedure can select W that minimizes the latency(W) of a given G. Below is an example LOFT procedure algorithm:

[0067] Consider an example where T is a binary tree, and all internal nodes correspond to merging right square prisms to generate a single right square prism. As defined above, two functions, Tfuse and Tdecode, have been defined for estimating the merging latency for t : V → [0, ∞). min_latency(S) can be recursively defined in pseudocode as follows:

[0068]

[0069] In some examples, dynamic programming can be used to take advantage of the fact that the number of right prisms in subset S (i.e., V) is only polynomial in order. The resulting algorithm is as follows:

[0070]

[0071]

[0072] Figure 6 An example partitioning scheme that can be determined by the LOFT process according to an example embodiment of this disclosure is described. For example... Figure 6 As shown, multiple possible solutions can be determined. For example, partitioning scheme 182 does not involve any partitioning. Partitioning scheme 184 involves partitioning into blocks of unequal size along the time dimension. Partitioning scheme 186 involves partitioning into blocks of unequal size along the time dimension. Partitioning scheme 188 involves partitioning into blocks of unequal size along the time dimension. Partitioning scheme 190 involves partitioning into blocks of unequal size along both the spatial (x and / or y) and time dimensions.

[0073] Figure 7 A flowchart illustrating an example method 200 according to an exemplary embodiment of this disclosure is provided. These operations can be implemented using a quantum computing system and / or a classical computing system. For example, these operations can be performed by... Figure 10 The method 200 is implemented by the computing system 300 depicted herein (e.g., one or more processors 312 of the computing system). For illustrative and discussion purposes, method 200 illustrates operations performed in a specific order. Those skilled in the art will understand using the disclosure provided herein that the various operations of any method described herein can be adjusted, modified, rearranged, omitted, added, and / or extended in various ways without departing from the scope of this disclosure.

[0074] In (202), the method includes acquiring a multidimensional quantum error detection map. This multidimensional quantum error detection map can represent one or more quantum error detection measurements over a period of time. For example, the method may include acquiring a quantum error detection map 130. The quantum error detection measurements can be derived from a surface code. For example, the quantum error detection measurements can be obtained from the parity between qubits in the surface code (e.g., data qubit 126 and measurement qubit 128).

[0075] In (204), the method includes determining a partitioning scheme and a fusion scheme for the multidimensional quantum error detection graph, at least in part based on the decoding delay and the fusion delay. For example, the method can achieve, as follows: Figure 2 to Figure 6 The LOFT process 145 is used to determine the partitioning and fusion schemes, thereby reducing latency.

[0076] Figure 8 A flowchart illustrating the determination of partitioning and fusion schemes according to exemplary embodiments of the present disclosure is provided. These operations can be implemented using quantum computing systems and / or classical computing systems. For example, these operations can be performed by... Figure 10 The computing system 300 depicted herein (e.g., one or more processors 312 of the computing system) is used to implement this. Figure 8 For illustrative and discussion purposes, operations performed in a specific order are shown. Those skilled in the art will understand using the disclosure provided herein that the various operations of any method described herein can be adjusted, modified, rearranged, omitted, added, and / or extended in various ways without departing from the scope of this disclosure.

[0077] In (252), determining the partitioning scheme and the fusion scheme may include generating multiple fusion tree data structures. Each fusion tree data structure may include data indicating candidate partitioning schemes and data indicating candidate fusion schemes associated with said candidate partitioning schemes. (See reference...) Figure 4 and Figure 5 An example fusion tree data structure is discussed.

[0078] In (254), determining the partitioning and fusion schemes may include selecting one of a plurality of fusion tree data structures as the selected fusion tree data structure based on the decoding latency associated with candidate partitioning schemes and the fusion latency associated with candidate fusion schemes. For example, one or more functions may be used to estimate the latency associated with each candidate partitioning scheme and the latency associated with each candidate fusion scheme. An example function for estimating the cost / latency associated with a fusion block can provide a constant latency / cost for fusion of two blocks. Another example function for estimating the cost / latency associated with a fusion block can provide a cost / latency proportional to the boundary area A between the two blocks. For example, a disjoint-set data structure-based algorithm and / or a minimum weighted perfect matching (MWPM) algorithm may be used to determine the decoding cost / latency associated with a decoding block. In some examples, the candidate fusion tree data structure with the minimum latency may be selected as the selected fusion tree data structure.

[0079] In (256), determining the partitioning and fusion schemes may include determining the partitioning and fusion schemes for the multidimensional quantum error detection graph based at least in part on the selected fusion tree data structure. For example, candidate partitioning and candidate fusion schemes associated with the selected fusion tree data structure may be determined as the partitioning and fusion schemes, respectively.

[0080] Reference Figure 7 In (206), method 200 may include dividing the multidimensional quantum error detection graph into multiple blocks, at least in part, based on a partitioning scheme. In some examples, these blocks may be right square prisms. However, without departing from the scope of this disclosure, these blocks may have other suitable shapes. In some examples, the blocks may be of equal size, such as... Figure 3 As shown. In some examples, the block sizes may not be equal, such as... Figure 6 As shown. The partitioning scheme can partition the quantum error detection graph in the time dimension. In some examples, the partitioning scheme can partition the quantum error detection graph in both the spatial dimension (e.g., the x and / or y dimensions) and the time dimension.

[0081] In (208), the method may include decoding each of the multiple blocks. For example, decoding each block may include solving for a minimum-cost alternating path between endpoint pairs to provide a decoded graph. The minimum-cost alternating path may indicate the most likely source of error leading to a parity mismatch at the endpoint. Therefore, the minimum-cost alternating path may indicate the location of the qubit where the error occurred.

[0082] In (210), the method may include fusing multiple blocks into a decoded detection map, at least in part, based on a fusion scheme. The fusion scheme may be, for example, the fusion scheme determined in (204) using the LOFT procedure.

[0083] In (212), the method may include operating the quantum computing system at least in part based on the decoded detection map. For example, the method may include implementing one or more error correction processes based on the decoded detection map.

[0084] Figure 9 A flowchart depicts an example error correction process according to an exemplary embodiment of this disclosure. These operations can be implemented using quantum computing systems and / or classical computing systems. For example, these operations can be performed by... Figure 10 The computing system 300 depicted herein (e.g., one or more processors 312 of the computing system) is used to implement this. Figure 9 For illustrative and discussion purposes, operations performed in a specific order are shown. Those skilled in the art will understand using the disclosure provided herein that the various operations of any method described herein can be adjusted, modified, rearranged, omitted, added, and / or extended in various ways without departing from the scope of this disclosure.

[0085] In (262), operating a quantum computing system may include identifying one or more qubits that have erred from a decoded detection map. As discussed above, the decoded detection map may include data indicating the location of the erroneous qubit.

[0086] In (264), operating a quantum computing system may include performing a corrective action at the qubit. In some examples, the corrective action may include resetting the qubit, calibrating the qubit, implementing a quantum gate at the qubit to compensate for an error, or other suitable quantum computing operations. In some examples, the corrective action may include performing a classical computation process to compensate for an error at the qubit (e.g., modifying the output to compensate for an error).

[0087] Figure 10 A block diagram of an example computing system 300 is depicted, which can be used to implement systems and methods according to example embodiments of this disclosure, such as those referenced. Figure 7 to Figure 9 The methods discussed herein. System 300 includes a classical computing system 310 and a quantum computing system 330 communicatively coupled via a network 350. One or more aspects of any of the methods described herein can be implemented on the classical computing system 310 and / or the quantum computing system 330.

[0088] The classical computing system 310 may include any type of computing device (e.g., a classical computing device). The classical computing system 310 includes one or more processors 312 and memory 314. The one or more processors 312 may include any suitable processing device (e.g., processor core, microprocessor, ASIC, FPGA, controller, microcontroller, etc.) and may be a single processor or multiple processors operatively connected. The memory 314 may include one or more non-transitory computer-readable storage media, such as RAM, ROM, EEPROM, EPROM, flash memory devices, disks, etc., and combinations thereof. The memory 314 may store data 316 (e.g., qubit parameters, measurements, etc.) and instructions 318 that are executed by the processor 312 to cause the classical computing system 310 to perform operations, such as one or more aspects of any of the methods disclosed herein. According to an example embodiment of this disclosure, the classical computing system 310 may be configured to process error information (e.g., error detection graph 320) obtained by measuring the output of a quantum system (e.g., quantum system 340) to identify errors in quantum computing.

[0089] Quantum computing system 330 includes one or more processors 332 and memory 334. The one or more processors 332 may include suitable processing devices (e.g., processor cores, microprocessors, ASICs, FPGAs, controllers, microcontrollers, etc.) and may be a single processor or multiple processors operatively connected. Memory 334 may include one or more non-transitory computer-readable storage media, such as RAM, ROM, EEPROM, EPROM, flash memory devices, disks, etc., and combinations thereof. Memory 334 may store data 336 and instructions 338, which are executed by processor 332 to cause quantum computing system 330 to perform operations, such as implementing a quantum circuit with one or more quantum gates on a quantum system 340 having multiple qubits and acquiring associated measurements (e.g., error detection graph 320). Quantum computing system 330 may be similar to reference [reference]. Figure 1 The quantum computing system discussed and described. Other suitable quantum computing systems may be used without departing from the scope of this disclosure.

[0090] Network 350 can be any type of communication network, such as a local area network (e.g., intranet), a wide area network (e.g., the Internet), or some combination thereof, and can include any number of wired or wireless links. Generally, communication over network 350 can be conducted using various communication protocols (e.g., TCP / IP, HTTP, SMTP, FTP), encodings or formats (e.g., HTML, XML), and / or protection schemes (e.g., VPN, Secure HTTP, SSL) via any type of wired and / or wireless connection. In some implementations, network 350 can be omitted, allowing classical computing system 310 to communicate directly with quantum computing system 330.

[0091] The implementations of the digital, classical, and / or quantum themes, as well as digital function operations and quantum operations described in this specification, may be implemented in digital electronic circuit systems, suitable quantum circuit systems, or more generally, quantum computing systems, in tangibly implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of these. The term "quantum computing system" may include, but is not limited to, quantum computers / computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0092] The implementation of the digital and / or quantum themes described in this specification can be implemented as one or more digital and / or quantum computer programs (e.g., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device). The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit / qubit structures, or a combination thereof. Alternatively or additionally, program instructions can be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, which is then transmitted to a suitable receiver device for execution by the data processing device.

[0093] The terms quantum information and quantum data refer to information or data carried, stored, or housed in quantum systems, the smallest nontrivial system being a qubit (i.e., a system that defines a unit of quantum information). It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems can include multi-level systems, for example, systems with two or more energy levels. Examples of such systems include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational ground state is considered as the ground state and the first excited state; however, it should be understood that other settings where the computational state is considered as a higher-level excited state (e.g., a qubit) are also possible.

[0094] The term "data processing device" refers to digital and / or quantum data processing hardware and encompasses all kinds of devices, apparatuses, and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, or multiple digital and quantum processors or computers, and combinations thereof. The device may also be or include dedicated logic circuit systems, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), or quantum simulators, i.e., quantum data processing devices designed to simulate or generate information about a particular quantum system. Specifically, a quantum simulator is a dedicated quantum computer without the ability to perform general-purpose quantum computing. In addition to hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0095] Digital or classical computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a digital computing environment. Quantum computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages) and translated into a suitable quantum programming language, or can be written in quantum programming languages ​​such as QCL, Quipper, Cirq, etc.

[0096] Digital and / or quantum computer programs may, but do not necessarily, correspond to files in a file system. Programs may be stored as a portion of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code sections). Digital and / or quantum computer programs may be deployed to execute on a single digital or quantum computer, or on multiple digital and / or quantum computers located at a single site or distributed across multiple sites and interconnected via digital and / or quantum data communication networks. A quantum data communication network is understood as a network that can transmit quantum data using quantum systems (e.g., qubits). Generally, digital data communication networks cannot transmit quantum data; however, quantum data communication networks can transmit both quantum data and digital data.

[0097] The processes and logic flows described in this specification can be executed by one or more programmable digital and / or quantum computers (which may operate using one or more digital and / or quantum processors, as appropriate) executing one or more digital and / or quantum computer programs to perform functions by manipulating input digital and quantum data and generating outputs. The processes and logic flows can also be executed by a dedicated logic circuit system (e.g., an FPGA or ASIC or a quantum simulator) or by a combination of a dedicated logic circuit system or a quantum simulator and one or more programmable digital and / or quantum computers, and the device can also be implemented as said dedicated logic circuit system or said combination.

[0098] For a system of one or more digital and / or quantum computers or processors that is “configured” or “operable to” perform a specific operation or action, it means that the system has software, firmware, hardware, or a combination thereof installed thereon that causes the system to perform the operation or action in operation. For one or more digital and / or quantum computer programs configured to perform a specific operation or action, it means that the one or more programs include instructions that cause the device to perform the operation or action when executed by a digital and / or quantum data processing device. A quantum computer can receive instructions from a digital computer that cause the device to perform the operation or action when executed by a quantum computing device.

[0099] Digital and / or quantum computers suitable for executing digital and / or quantum computer programs may be based on general-purpose or special-purpose digital and / or quantum microprocessors or both, or any other kind of central digital and / or quantum processing unit. Generally, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from read-only memory, or random access memory, or a quantum system suitable for transmitting quantum data (e.g., photons), or a combination thereof.

[0100] Some example elements of a digital and / or quantum computer are a central processing unit (CPU) that makes or executes instructions and one or more memory devices for storing instructions and digital and / or quantum data. The CPU and memory may be supplemented by or incorporated into a dedicated logic circuit system or quantum simulator. Generally, a digital and / or quantum computer will also include one or more mass storage devices for storing digital and / or quantum data, such as magnetic disks, magneto-optical disks, or optical disks, or quantum systems suitable for storing quantum information, or operatively coupled to receive digital and / or quantum data from or to said one or more mass storage devices, or both. However, a digital and / or quantum computer need not have such devices.

[0101] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memories, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable hard disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device capable of storing quantum data for a long period with high fidelity and high efficiency, for example, using light for transmission and using matter for storage and preservation of quantum characteristics (such as superposition or quantum coherence) of the quantum data at an optical-material interface.

[0102] Control of the various systems or portions thereof described in this specification may be implemented using digital and / or quantum computer program products, which include instructions stored on one or more tangible, non-transitory, machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or portions thereof described in this specification may each be implemented as an apparatus, method, or electronic system, which may include one or more digital and / or quantum processing devices and memory for storing executable instructions to perform the operations described in this specification.

[0103] While this specification contains numerous details of specific implementations, these details should not be construed as limiting the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features described in this specification within the context of individual implementations may also be implemented in combination within a single implementation. Conversely, individual features described within the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features are described above as functioning in certain combinations, and even initially claimed to be so, one or more features from a claimed combination may, in some cases, be removed from said combination, and the claimed combination may be for a sub-combination or a variation thereof.

[0104] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. Furthermore, the separation of the various system modules and components in the implementation described above should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0105] Specific implementations of this subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions described in the claims can be performed in different orders and still achieve the desired result. As an example, the processes depicted in the figures do not necessarily require a specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous.

[0106] Various aspects of this disclosure have been described with respect to their illustrative implementations. Numerous other implementations, modifications, and alterations within the scope and spirit of the appended claims will arise in those skilled in the art upon careful reading of this disclosure. Any and all features of the following claims can be combined or rearranged in any possible manner. Therefore, the scope of this disclosure is illustrative rather than limiting, and this disclosure does not exclude such modifications, alterations, and / or additions to the subject matter that will be readily understood by those skilled in the art. Furthermore, terms are described herein using a list of example elements connected by conjunctions such as “and,” “or,” and “however.” It should be understood that such conjunctions are provided for illustrative purposes only. For example, a list connected by a specific conjunction such as “or” may refer to “at least one” or “any combination” of the example elements listed therein, where “or” should be understood as “and / or” unless otherwise indicated. Furthermore, terms such as “based on” should be understood as “at least partially based on.”

[0107] Those skilled in the art will understand using the disclosure provided herein that elements of any claim, operation, or process discussed herein can be adjusted, rearranged, expanded, omitted, combined, or modified in various ways without departing from the scope of this disclosure. Some claims are described with letter references to claim elements for illustrative purposes and are not intended to be limiting. Letter references do not imply a particular order of operations. For example, letter identifiers such as (a), (b), (c)..., (i), (ii), (iii)... may be used to describe operations. Such identifiers are provided for the convenience of the reader and do not indicate a particular order of steps or operations. Operations indicated by list identifiers (a), (i), etc., may be performed before, after, or in parallel with another operation indicated by list identifiers (b), (ii), etc.

Claims

1. A computer-implemented method, the method comprising: A multidimensional quantum error detection map is obtained by one or more computing devices, wherein the multidimensional quantum error detection map represents one or more quantum error detection measurements over a period of time; The partitioning and fusion schemes for the multidimensional quantum error detection graph are determined by the one or more computing devices, based at least in part on decoding delay and fusion delay; The multidimensional quantum error detection graph is divided into multiple blocks by the one or more computing devices, at least in part, based on the partitioning scheme; Each of the plurality of blocks is decoded by the one or more computing devices; The plurality of blocks are fused into a decoded detection map by the one or more computing devices, at least in part, based on the fusion scheme; and The quantum computing system operates at least in part based on the decoded detection map.

2. The computer-implemented method of claim 1, wherein the quantum error detection measurement is obtained from a surface code comprising a plurality of measurement qubits and a plurality of data qubits.

3. The computer-implemented method as described in claim 1, wherein the partitioning scheme partitions the multidimensional quantum error detection map in the time dimension.

4. The computer-implemented method of claim 1, wherein the partitioning scheme partitions the multidimensional quantum error detection map in one or more spatial dimensions.

5. The computer-implemented method of claim 1, wherein determining the partitioning scheme and fusion scheme by the one or more computing devices includes: Multiple fusion tree data structures are generated by the one or more computing devices, each fusion tree data structure including data indicating candidate partitioning schemes and data indicating candidate fusion schemes associated with the candidate partitioning schemes; The one or more computing devices select one of the plurality of fusion tree data structures as the selected fusion tree data structure based on the latency associated with the candidate partitioning scheme and the latency associated with the candidate fusion scheme; as well as The partitioning scheme and the fusion scheme for the multidimensional quantum error detection graph are determined by the one or more computing devices, at least in part, based on the selected fusion tree data structure.

6. The computer-implemented method of claim 5, wherein the data indicating the candidate fusion scheme is represented in a tree data structure.

7. The computer-implemented method of claim 6, wherein the tree data structure includes a plurality of leaf nodes, each of the plurality of leaf nodes representing one of a plurality of blocks associated with the candidate partitioning scheme, and the tree data structure includes one or more nodes, the one or more nodes representing the fusion of two or more of the plurality of blocks associated with the candidate partitioning scheme.

8. The computer-implemented method of claim 1, wherein decoding the plurality of blocks includes decoding at least a portion of the plurality of blocks in parallel.

9. The computer-implemented method of claim 1, wherein fusing the plurality of blocks includes merging at least a portion of the plurality of blocks in parallel.

10. The computer-implemented method of claim 1, wherein operating the quantum computing system based at least in part on the decoded detection map comprises: Identify the erroneous qubit using one or more computing devices; as well as The correction action is performed at the qubit by one or more computing devices.

11. The method of claim 1, wherein the plurality of blocks are of equal size.

12. The method of claim 1, wherein the plurality of blocks are of unequal size.

13. A quantum computing system, comprising: Surface code including multiple qubits; One or more processors; One or more memory devices storing computer-readable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, the operations including: Obtain a multidimensional quantum error detection map, wherein the multidimensional quantum error detection map represents one or more quantum error detection measurements over a period of time; The partitioning and fusion schemes for the multidimensional quantum error detection graph are determined at least in part based on the decoding delay and fusion delay. The multidimensional quantum error detection graph is divided into multiple blocks, at least in part, based on the partitioning scheme described above; Decode each of the plurality of blocks; and The multiple blocks are fused into a decoded detection map, at least in part, based on the fusion scheme.

14. The quantum computing system of claim 13, wherein the surface code comprises a plurality of measurement qubits and a plurality of data qubits.

15. The quantum computing system of claim 13, wherein the operation of determining the partitioning scheme and the fusion scheme comprises: Multiple fusion tree data structures are generated, each fusion tree data structure including data indicating candidate partitioning schemes and data indicating candidate fusion schemes associated with the candidate partitioning schemes; One of the plurality of fusion tree data structures is selected as the selected fusion tree data structure based on the delay associated with the candidate partitioning scheme and the delay associated with the candidate fusion scheme; as well as The partitioning scheme and the fusion scheme for the multidimensional quantum error detection graph are determined at least in part based on the selected fusion tree data structure.

16. The quantum computing system of claim 13, wherein the partitioning scheme partitions the multidimensional quantum error detection map in the time dimension.

17. The quantum computing system of claim 13, wherein the partitioning scheme partitions the multidimensional quantum error detection map in one or more spatial dimensions.

18. One or more non-transitory computer-readable media storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations, the operations including: Multiple fusion tree data structures are generated, each fusion tree data structure including data indicating candidate partitioning schemes of the multidimensional quantum error detection graph of the quantum computing system and data indicating candidate fusion schemes associated with the candidate partitioning schemes; One of the plurality of fusion tree data structures is selected as the selected fusion tree data structure based on the delay associated with the candidate partitioning scheme and the delay associated with the candidate fusion scheme; as well as The partitioning and fusion schemes for the multidimensional quantum error detection graph are determined at least in part based on the selected fusion tree data structure.

19. The one or more non-transitory computer-readable media of claim 18, wherein the selection of one of the plurality of fused tree data structures as the selected fused tree data structure is implemented at least in part using dynamic programming.

20. The one or more non-transitory computer-readable media of claim 18, wherein the data indicating the candidate fusion scheme is represented in a tree data structure, wherein the tree data structure includes a plurality of leaf nodes, each of the plurality of leaf nodes representing one of a plurality of blocks associated with the candidate partitioning scheme, and the tree data structure includes one or more nodes, the one or more nodes representing the fusion of two or more of the plurality of blocks associated with the candidate partitioning scheme.

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