Phase lock validity detection method and device for SOGI-PLL, electronic equipment and medium

Abstract

The invention discloses a phase lock effectiveness detection method and device for SOGI-PLL, electronic equipment and a medium, and the method comprises the following steps: carrying out the fundamental wave adaptive extraction of a power grid voltage sampling signal through a first-stage SOGI and an adaptive wave trap structure, and outputting a fundamental wave component; a hysteresis comparison and linear interpolation algorithm is adopted to carry out accurate detection of zero-crossing time on the phase-locked phase output by the SOGI-PLL; dynamically adjusting the size of a sliding window according to the frequency of the power grid and the power + voltage amplitude V of the power grid, and calculating a self-adaptive sliding mean value of the fundamental component; according to the fundamental wave voltage peak value and the total harmonic distortion rate, a dynamic judgment threshold value is generated in real time; and fusing the sliding mean value judgment dimension and the frequency ripple judgment dimension, and outputting a phase locking effectiveness judgment result. Through cascade filtering and dynamic threshold value fusion, the misjudgment rate is lower than 0.1% under the working condition that the THD reaches up to 10%. Zero-cross detection is compensated through linear interpolation, the phase locking failure judgment time delay is shortened to be within 10 ms, and the method can automatically adapt to the working conditions of large-range frequency hopping and voltage drop.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a method, apparatus, electronic device, and medium for detecting the phase-locked loop effectiveness of SOGI-PLL. Background Technology

[0002] With the large-scale grid-connected application of new energy power generation technologies, grid-connected inverters, as the core unit of energy conversion, directly affect the stable operation of the power grid. In grid-connected control algorithms, phase-locked loops (PLLs) are used to track the phase and frequency of the grid voltage in real time, and are a key link in achieving synchronous operation between the grid-connected inverter and the grid. Among them, PLLs based on second-order generalized integrators (SOGIs) have been widely used in single-phase and three-phase unbalanced systems due to their excellent filtering characteristics and frequency adaptive capabilities.

[0003] However, in complex real-world power grid environments, voltage dips, frequency fluctuations, and severe harmonic distortion are common. These abnormal conditions can cause the SOGI-PLL output phase to shift or oscillate. If the system cannot detect the effectiveness of the phase-locked loop (PLL), i.e., its accuracy and stability, in a timely manner, the inverter may inject low-quality current into the grid, potentially causing equipment shutdown due to overcurrent or loss of synchronism. Existing PLL detection methods mostly employ fixed-window averaging or fixed-threshold judgment methods, which are less effective when facing large frequency jumps or high total harmonic distortion (THD) rates. THD Under normal operating conditions, there are problems such as high false alarm rate, insufficient detection accuracy and slow dynamic response. Summary of the Invention

[0004] The purpose of this invention is to provide an adaptive detection method, device, electronic device and storage medium for the effectiveness of SOGI-PLL in power grids, so as to solve the technical problems of low detection reliability and poor threshold adaptability of related technologies under complex power grid operating conditions.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides a method for detecting the phase-locked loop validity of SOGI-PLL, the method comprising the following steps: The grid voltage signal is sampled using a single-stage SOGI and an adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; The phase-locked phase of the SOGI-PLL output is obtained by employing a hysteresis comparison and linear interpolation algorithm. Passing through the zero hour Accurate detection; According to the power grid frequency and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component adaptive moving average ; Based on the peak value of the fundamental voltage With total harmonic distortion Real-time generation of dynamic judgment thresholds ; By integrating the moving average and frequency ripple determination dimensions, the output of the phase-locked loop validity determination result is obtained. .

[0006] In one or more embodiments of the present invention, the method further includes: Frequency tracking is performed using a single-stage SOGI, and its resonant frequency is tracked. PLL Output frequency ; An adaptive notch filter is incorporated into the cascaded structure to suppress the dominant harmonics of the power grid based on a preset order. The notch filter center frequency is set to... ,in For harmonic order; The signal after notch filtering is purified using a two-stage SOGI method, and the fundamental component is output. .

[0007] In one or more embodiments of the present invention, the transfer function of the first-level SOGI during frequency tracking is: , ; in, The damping coefficient is... Angular frequency; The transfer function of the adaptive notch filter when suppressing the dominant harmonics of the power grid according to a preset order is: ; in, This is the quality factor.

[0008] In one or more embodiments of the present invention, the zero-crossing time The detection process includes: Set upper threshold Lower threshold ,when from leap to When the rising edge crosses zero, it is determined to be zero. If the first The control period phase is , No. +1 Periodic phase is ,and <0< Then the zero-crossing time is: ,in, To control the cycle.

[0009] In one or more embodiments of the present invention, the adaptive moving average The calculation process includes: Calculate the power grid coefficient , ,in, For coefficients, To control the cycle; Based on power grid coefficient Determine the adaptive window size. ; Calculate the first using a recursive method k Periodic moving average: ,in For the first Periodic fundamental voltage sliding sum, for N The fundamental voltage value one cycle ago.

[0010] In one or more embodiments of the present invention, the fundamental peak value The total harmonic distortion rate can be obtained by detecting the amplitude of the fundamental component output by SOGI. It is possible FFT Analysis revealed that the total harmonic distortion rate ,in, The fundamental amplitude, for Second harmonic amplitude; The dynamic threshold .

[0011] In one or more embodiments of the present invention, the moving average determination includes

[0012] The frequency ripple determination includes calculating the intermediate variable angular velocity of the phase-locked loop. ω Peak-to-peak value within a power grid cycle ,like <0.1rad / s, then ,otherwise ; The fusion moving average determination dimension and the frequency ripple determination dimension include: ,in, This is a weighted value, and its specific value can be adjusted according to the working conditions.

[0013] In another aspect of the invention, a phase-locked loop validity detection device for SOGI-PLL is provided, the device comprising: The fundamental frequency extraction module is used to sample the grid voltage signal through a single-stage SOGI and an adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; The fundamental frequency extraction module is used to extract the phase-locked phase of the SOGI-PLL output using a hysteresis comparison and linear interpolation algorithm. Passing through the zero hour Accurate detection; A moving average calculation module, which is used to calculate the moving average based on the power grid frequency. and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component adaptive moving average ; A threshold generation module is used to generate a threshold based on the fundamental voltage peak value. With total harmonic distortion Real-time generation of dynamic judgment thresholds ; The fusion determination module is used to fuse the moving average determination dimension and the frequency ripple determination dimension, and output the phase-locked loop validity determination result. .

[0014] In another aspect of the invention, an electronic device is provided, comprising: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform a phase-locked loop validity detection method for SOGI-PLL.

[0015] In another aspect of the invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of a phase-locked loop validity detection method for SOGI-PLL.

[0016] Compared with the prior art, the phase-locked loop effectiveness detection method for SOGI-PLL according to the embodiments of the present invention has the following significant improvements: This invention ensures the purity of the fundamental frequency extraction at the source by using a cascaded SOGI and notch filter structure; it eliminates the impact of frequency jumps on the mean calculation by introducing an adaptive sliding window; and the dynamic threshold generation mechanism makes the detection system more robust in high THD environments. This application can identify the out-of-step or deviation state of the phase-locked loop in real time and accurately under complex power grid conditions, significantly reducing the false alarm rate and providing a reliable decision basis for the safe tripping or protection action of the grid-connected inverter. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a phase-locked loop effectiveness detection method for SOGI-PLL according to one embodiment of the present invention; Figure 2 This is a flowchart illustrating a phase-locked loop effectiveness detection method for SOGI-PLL according to one embodiment of the present invention. Figure 3 This is a basic schematic diagram of a first-stage SOGI-PLL in one embodiment of the present invention. Figure 4 This is a waveform diagram (I) of a power grid signal containing harmonics after SOGI fundamental wave extraction and after moving average. Figure 5 The following is a waveform diagram (II) of the power grid containing harmonics, the signal after SOGI fundamental wave extraction, and the signal after moving average in one embodiment of the present invention. Figure 6 This is a waveform diagram before and after sliding window averaging processing in one embodiment of the present invention. Figure 7 This is a waveform diagram after the amplitude drops in one embodiment of the present invention; Figure 8 This is a waveform diagram showing the phase-locked loop result in one embodiment of the present invention; Figure 9 This is a block diagram of a phase-locked loop validity detection device for SOGI-PLL according to one embodiment of the present invention; Figure 10 This is a hardware structure diagram of a computing device according to an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0020] As described in the background section, existing technologies suffer from low detection reliability and poor threshold adaptability under complex power grid conditions.

[0021] In response to the above technical problems, such as Figures 1-2 As shown, this invention provides a method for detecting the phase-locked loop validity of SOGI-PLL, comprising the following steps: Step 1: Sample the grid voltage signal using a single-stage SOGI and adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; Step 2: Employ hysteresis comparison and linear interpolation algorithms to adjust the phase-locked loop output of the SOGI-PLL. Passing through the zero hour Accurate detection; Step 3: Based on the power grid frequency and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component adaptive moving average ; Step 4: Based on the fundamental voltage peak value With total harmonic distortion Real-time generation of dynamic judgment thresholds ; Step 5: Combine the moving average determination dimension and the frequency ripple determination dimension to output the phase-locked loop validity determination result. .

[0022] In a further embodiment, the SOGI fundamental frequency adaptive extraction in step 1 includes the following steps: like Figure 3 As shown, a single-stage SOGI is used for computation, and tracking is performed at the single-stage SOGI resonant frequency. PLL Output frequency The transfer function for the first-level SOGI is: , ; in, The damping coefficient is used to reflect the equilibrium dynamic response and stability. In this embodiment, the damping coefficient is... The preferred value is 0.707; In a further embodiment, an adaptive notch filter is configured, with a notch center frequency of [value missing] for the dominant harmonics of the power grid (e.g., the 3rd and 5th harmonics). ( (where the harmonic order is 0), the transfer function is: ; Among them, quality factor =10, the quality factor Used to enhance harmonic suppression capability; In a further embodiment, a secondary SOGI is also provided to further purify the notch-filtered signal and output the fundamental component. .

[0023] In this embodiment, a two-stage cascaded SOGI structure is adopted, and the center frequency of the first-stage SOGI follows the output frequency of the phase-locked loop in real time. It is used for preliminary extraction of orthogonal signals; an adaptive notch filter is connected in series between the two stages to specifically suppress the 3rd and 5th harmonics, which are prevalent in the power grid. After secondary filtering by the two-stage SOGI, the fundamental component of the output is... It can highly reproduce the true fundamental waveform of the power grid.

[0024] In a further embodiment, step 2 involves zero-crossing reconstruction in a discrete system. Due to the limited sampling frequency of the controller, the sampling point often cannot accurately fall at the 0-degree phase moment. This application sets an upper threshold. Lower threshold ,when from leap to When the rising edge crosses zero, it is determined; when two adjacent sampling periods are detected... k and k+1 Phase-locked phase When a transition from negative to positive occurs, linear interpolation is performed using the following formula: ,in, To control the cycle, this compensation algorithm eliminates the phase detection delay caused by discrete sampling, providing an accurate integration starting point for subsequent moving average calculation.

[0025] In a further embodiment, the adaptive sliding window mechanism in step 3 is a key step in dealing with frequency fluctuations. When the grid frequency fluctuates between 45Hz and 55Hz, the system calculates the window width in real time. ,in For the power grid coefficient, , For coefficients, In this embodiment, appropriate coefficients are obtained through multiple experiments. The preferred value is 0.00072727. To control the cycle. Therefore, the first... k The formula for calculating the moving average over a period is: ,in For the first Periodic fundamental voltage sliding sum, for N The fundamental voltage value one cycle ago.

[0026] This embodiment ensures the moving average by dynamically increasing or decreasing the number of samples within the sliding window. The calculation is always performed within a complete fundamental frequency cycle. This method effectively eliminates the non-periodic integral residue caused by frequency jumps and avoids false alarms during frequency abrupt changes.

[0027] In a further embodiment, step 4 introduces environmentally adaptive threshold logic, based on the fundamental voltage peak value. With total harmonic distortion Adjust the judgment threshold in real time fundamental peak value The total harmonic distortion (THD) is obtained by detecting the amplitude of the fundamental component output by SOGI. It is possible FFT Analysis revealed that the total harmonic distortion rate ,in, The fundamental amplitude, for Subharmonic amplitude; the dynamic threshold In this embodiment, when When = 20%), It is compatible with harmonic interference.

[0028] In a further embodiment, step 5 performs a multi-dimensional fusion determination of phase-locked loop validity, fusing the moving average determination and frequency ripple determination through a weighted fusion method, wherein the moving average determination includes: Frequency ripple determination includes calculating the intermediate variable angular velocity of the phase-locked loop. ω Peak-to-peak value within a power grid cycle ,like <0.1rad / s, then ,otherwise The fusion of the moving average determination dimension and the frequency ripple determination dimension includes: ,in, This is a weighted value, the specific value of which can be adjusted according to the working conditions. In this embodiment... The values ​​can be 0.6 and 0.4 respectively, and the weights can be adjusted according to the working conditions of the implementation example.

[0029] To verify the effectiveness of this method, a simulation model under complex working conditions was established using Matlab simulation software. The working conditions included: setting the grid voltage to 220V. Vrms At 50Hz and an initial phase of 30°, a 30° phase jump occurred in the simulated power grid at t=0.2s. Traditional detection methods, due to fixed thresholds, only detected the anomaly after 3 cycles. However, the method described in this application, through precise zero-crossing detection and dynamic threshold adjustment, identifies the phase-locked loop failure state within 0.5 cycles. According to the appendix... Figures 4-8 Simulation results show that when the adaptive window is adjusted from 4 to 3 after the amplitude drops, the mean distortion rate decreases from 5% to 1.2%; when the dynamic threshold is adjusted from 3V to 6V, the number of false positives decreases from 2 to 0. The effective recognition accuracy of phase-locked loop based on multi-dimensional judgment has been significantly improved.

[0030] The phase-locked loop validity adaptive detection method in this embodiment can achieve at least the following technical effects: through cascaded filtering and dynamic threshold fusion, in THD Under conditions with up to 10% of operating rates, the false positive rate is less than 0.1%. By utilizing linear interpolation to compensate for zero-crossing detection, the delay in determining phase-locked loop failure is reduced to less than 10ms (under 50Hz conditions). It automatically adapts to operating conditions with a wide range of frequency jumps (±5Hz) and voltage drops (0.1pu-1.2pu), eliminating the need for manually setting hard thresholds based on different grid connection point environments.

[0031] like Figure 9 As shown, an apparatus for implementing a phase-locked loop validity detection method for SOGI-PLL according to a specific embodiment of the present invention is described, the apparatus comprising: The fundamental frequency extraction module is used to sample the grid voltage signal through a single-stage SOGI and an adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; The zero-crossing detection module, and the fundamental wave extraction module, are used to perform phase-locked phase extraction on the SOGI-PLL output using a hysteresis comparison and linear interpolation algorithm. Passing through the zero hour Accurate detection; A moving average calculation module, which is used to calculate the moving average based on the power grid frequency. and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component adaptive moving average ; A threshold generation module is used to generate a threshold based on the fundamental voltage peak value. With total harmonic distortion Real-time generation of dynamic judgment thresholds ; The fusion determination module is used to fuse the moving average determination dimension and the frequency ripple determination dimension, and output the phase-locked loop validity determination result. .

[0032] Figure 10 A hardware structure diagram of a computing device 30 for a phase-locked loop validity detection method for SOGI-PLL is shown according to an embodiment of this specification. Figure 10 As shown, the computing device 30 may include at least one processor 301, a memory 302 (e.g., non-volatile memory), a main memory 303, and a communication interface 304, and the at least one processor 301, memory 302, main memory 303, and communication interface 304 are connected together via a bus 305. At least one processor 301 executes at least one computer-readable instruction stored or encoded in the memory 302.

[0033] It should be understood that the computer-executable instructions stored in memory 302, when executed, cause at least one processor 301 to perform the above-described combinations in the various embodiments of this specification. Figures 1-8 The description includes various operations and functions.

[0034] In the embodiments of this specification, the computing device 30 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile computing device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld system, messaging device, wearable computing device, consumer electronic device, etc.

[0035] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0036] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A system that specifies functions in one or more boxes.

[0037] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including an instruction set implemented in a process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0038] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0040] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for detecting the phase-locked loop validity of SOGI-PLL, characterized in that, The method includes the following steps: The grid voltage signal is sampled using a single-stage SOGI and an adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; The phase-locked phase of the SOGI-PLL output is obtained by employing a hysteresis comparison and linear interpolation algorithm. Passing through the zero hour Accurate detection; According to the power grid frequency and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component Adaptive moving average ; Based on the peak value of the fundamental voltage With total harmonic distortion Real-time generation of dynamic judgment thresholds ; By integrating the moving average and frequency ripple determination dimensions, the output of the phase-locked loop validity determination result is obtained. .

2. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 1, characterized in that, The method further includes: Frequency tracking is performed using a single-stage SOGI, and its resonant frequency is tracked. PLL Output frequency ; An adaptive notch filter is incorporated into the cascaded structure to suppress the dominant harmonics of the power grid based on a preset order. The notch filter center frequency is set to... ,in For harmonic order; The signal after notch filtering is purified using a two-stage SOGI method, and the fundamental component is output. .

3. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 2, characterized in that, The transfer function for frequency tracking in the first-level SOGI is: ， ； in, The damping coefficient is... Angular frequency; The transfer function of the adaptive notch filter when suppressing the dominant harmonics of the power grid according to a preset order is: ； in, This is the quality factor.

4. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 1, characterized in that, The zero-crossing time The detection process includes: Set upper threshold Lower threshold ,when from leap to When the rising edge crosses zero, it is determined to be zero. If the first The control period phase is , No. +1 period phase is ,and <0< Then the zero-crossing time is: ,in, To control the cycle.

5. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 1, characterized in that, The adaptive moving average The calculation process includes: Calculate the power grid coefficient , ,in, For coefficients, To control the cycle; Based on power grid coefficient Determine the adaptive window size. ; Calculate the first using a recursive method k Periodic moving average: ,in For the first Periodic fundamental voltage sliding sum, This represents the fundamental voltage value N cycles ago.

6. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 1, characterized in that, The fundamental frequency peak The total harmonic distortion rate can be obtained by detecting the amplitude of the fundamental component output by SOGI. The total harmonic distortion rate can be obtained through FFT analysis. ,in, The fundamental amplitude, for Second harmonic amplitude; The dynamic threshold .

7. The method for detecting the phase-locked loop validity of SOGI-PLL according to claim 1, characterized in that, The moving average determination includes... The frequency ripple determination includes calculating the intermediate variable angular velocity of the phase-locked loop. ω Peak-to-peak value within a power grid cycle ,like <0.1 rad / s, then ,otherwise ; The fusion moving average determination dimension and the frequency ripple determination dimension include: ,in, This is a weighted value, and its specific value can be adjusted according to the working conditions.

8. A phase-locked loop validity detection device for SOGI-PLL, characterized in that, include: The fundamental frequency extraction module is used to sample the grid voltage signal through a single-stage SOGI and an adaptive notch filter structure. Perform fundamental frequency adaptive extraction and output fundamental frequency component. ; The zero-crossing detection module is used to perform phase-locked phase detection on the SOGI-PLL output using a hysteresis comparison and linear interpolation algorithm. Passing through the zero hour Accurate detection; A moving average calculation module, which is used to calculate the moving average based on the power grid frequency. and grid voltage amplitude V Dynamically adjust the size of the sliding window N Calculate the fundamental component Adaptive moving average ; A threshold generation module is used to generate a threshold based on the fundamental voltage peak value. With total harmonic distortion Real-time generation of dynamic judgment thresholds ; The fusion determination module is used to fuse the moving average determination dimension and the frequency ripple determination dimension, and output the phase-locked loop validity determination result. .

9. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the phase-locked loop validity detection method for SOGI-PLL as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the phase-locked loop validity detection method for SOGI-PLL as described in any one of claims 1 to 7.

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