A test execution method for negative bias temperature instability test

Abstract

This application discloses a test execution method for negative bias temperature instability testing, belonging to the field of semiconductor technology. Addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the test time and heating time for semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and the rapid test time is equivalent to the degradation degree that occurs when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation.

Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to a test execution method for negative bias temperature instability testing. Background Technology

[0002] Negative bias temperature instability (NBTI) testing is an accelerated aging test used to evaluate the long-term reliability of semiconductor devices, especially pMOSFETs. It involves applying a negative voltage (opposite to the source) to the transistor's gate at high temperatures and observing device parameters such as the threshold voltage V. th Leakage current I ds ) Degradation over time.

[0003] In actual testing, it is often necessary to collect device test results multiple times over a relatively long testing period to extrapolate the device's expected or target lifespan and potential failure scenarios. This further increases the time requirements for testing. Therefore, how to reduce the testing time due to unstable negative bias temperature is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a test execution method for negative bias temperature instability testing. The test execution method includes: determining the batch activation energy of a target batch of semiconductor devices under test (SDD), wherein the SDD refers to multiple semiconductor devices in the same batch under advanced processes. Based on the batch activation energy and a power-law lifetime model, the target lifetime of the negative bias temperature instability test under standard test conditions is mapped to a rapid test time under rapid test conditions, wherein the degree of degradation of the SDD under rapid test conditions after rapid test time is equivalent to the degree of degradation under standard test conditions when operating to the target lifetime. The gate voltage under rapid test conditions is greater than the gate voltage under standard test conditions, and the test temperature under rapid test conditions indicates room temperature. Based on the rapid test conditions and rapid test time, a negative bias temperature instability test is performed on the SDD to determine the test result. The power-law lifetime model is as follows: Where TTF is the failure time, Ea is the batch activation energy, α is the acceleration factor of the gate voltage, K is the Boltzmann constant, and V gs The value of the gate voltage is T, and the absolute temperature value of the test temperature is T.

[0005] Based on the test execution method for negative bias temperature instability testing provided in this application, addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application can map the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude, based on the power-law lifetime model of semiconductor devices. This reduces the test time and heating time of semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process of semiconductor devices. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and rapid test time is equivalent to the degradation degree that occurs when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation. Attached Figure Description

[0006] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 This is an exemplary flowchart of a test execution method for negative bias temperature instability testing provided in some embodiments of this application.

[0008] Figure 2 This is a schematic diagram showing the deterioration curves of drain current over test time at different temperatures provided in some embodiments of this application.

[0009] Figure 3 This is an exemplary flowchart of a screening threshold determination method provided in some embodiments of this application.

[0010] Figure 4 This is a schematic diagram illustrating the correlation between lifetime estimates and drain current degradation indices provided in some embodiments of this application.

[0011] Figure 5 This is an exemplary flowchart of a testing method based on preparation parameters provided in some embodiments of this application.

[0012] Figure 6 This is a schematic diagram of test results under various changes in preparation parameters provided in some embodiments of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0015] In this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0016] Application Overview:

[0017] In semiconductor device design and wafer acceptability testing (WAT), to assess the impact of new process parameters on the long-term reliability of devices, it is typically necessary to perform NBTI testing on semiconductor devices fabricated using different process parameters. During the testing process, the semiconductor fabrication process outputs multiple experimental lots with different process parameters. In actual testing, different batches of devices are often tested one by one, sequentially.

[0018] A typical testing implementation involves placing the semiconductor device under test (DUT) in a parametric analyzer equipped with a high-temperature probe station. During testing, the entire thermal chuck supporting the wafer is heated to a preset high-temperature stress condition (e.g., 125°C). The probe station moves its probes to sequentially contact the pads at each test location on the wafer, applying a constant negative bias stress to the gate of each individual device (source / drain / substrate grounded), while devices at other locations on the wafer are only subjected to thermal stress without any electrical stress.

[0019] However, the core purpose of NBTI testing is not to directly obtain device parameters under a fixed stress time, but to evaluate whether the performance degradation of the device is acceptable over a target operating life of several years (e.g., 10 years AC or 5 years DC) and to determine the device's failure lifetime (i.e., the estimated lifetime). Since actual testing over such a long period is not feasible, existing technologies generally employ a method of "accelerated testing + data extrapolation".

[0020] This involves applying stress to a single device at a high temperature (e.g., 125°C) and a fixed gate voltage for several thousand to tens of thousands of seconds. During this prolonged stress process, it is necessary to periodically interrupt the stress, switch to measurement mode, and collect key parameters (such as drain current I). ds or threshold voltage V th The instantaneous value of ) is then obtained. Multiple "time-parameter degradation" data points are then fitted to construct a curve showing the performance degradation of the device over time under a specific stress condition (i.e., a degradation kinetic curve). Finally, based on the fitted curve model, mathematical extrapolation is performed to a longer time scale to predict when the device degradation reaches a preset failure criterion (e.g., I). ds The stress time required to reduce the stress by 10% is equivalent to the estimated lifespan of the device under the test conditions (it can also be derived to analyze whether its parameters fail after a certain period of time).

[0021] The above process results in extremely long testing times: First, the stress and measurement cycle required for each test point alone can take thousands of seconds; second, to obtain a sufficiently accurate fitting curve, multiple interruptions in the measurement are required within a single cycle, further increasing the total time consumption; third, to evaluate process variables, this complete process needs to be repeated for multiple batches of devices under different process conditions.

[0022] For example, for a batch of 25 wafers, NBTI testing is performed on 5 test sites on each wafer. Each test can be performed at 125°C, and the corresponding single test time is approximately 1000s to 10000s (taking 1000s as an example). Each wafer needs to be tested at multiple points (e.g., 5, including edge points, center points, specific structures, etc.), and each test needs to be performed three times with high voltage, medium voltage, and low voltage. At the same time, the heating time for each wafer is about 3 hours. After completing NBTI testing on 25 wafers with the aforementioned different fabrication parameters, it will take approximately 47 days to complete the process.

[0023] Furthermore, the aforementioned parameter analyzers are expensive, and setting up multiple sets for parallel execution is costly. Even with multiple sets of equipment for testing, each wafer requires approximately two days for testing.

[0024] To address the aforementioned time-consuming issue, those skilled in the art typically consider accelerating the NBTI degradation process by increasing the gate voltage amplitude. According to reliability physics, increasing the gate voltage enhances the electric field in the gate oxide layer, thereby accelerating the formation rate of interface traps and causing the device performance to reach observable degradation levels in a shorter stress time. However, this simple voltage acceleration does not fundamentally change the testing paradigm, and its limitations remain significant.

[0025] First, increasing the voltage still does not eliminate the dependence on the degradation kinetics curve. To establish a reliable lifetime prediction model, even under high gate voltage conditions, it is still necessary to interrupt and measure key device parameters (such as IT) multiple times at different stress points. ds or V th） To obtain sufficient "time-degradation" data points for curve fitting. Although increasing the voltage may reduce the stress time required for each test from thousands of seconds to hundreds of seconds, the number of measurement points required to ensure fitting accuracy and the interval time required for the measurement itself are not reduced, and the entire "stress-measurement-stress" cycle is still necessary.

[0026] Secondly, a high-temperature testing environment remains indispensable. NBTI is essentially a degradation mechanism resulting from the combined effects of thermal activation and an electric field, with its activation energy (Ea) being a key parameter in the model. If testing is conducted by simply increasing the voltage at room temperature, the obtained degradation data will lack a temperature acceleration factor and cannot be directly used to calculate long-term lifetime at actual operating temperatures (typically lower than the high-temperature stress temperature). Therefore, existing voltage-accelerated solutions still require high temperatures (e.g., 125°C), and the time overhead of device heating and cooling, as well as the equipment and energy costs of high-temperature testing, remain.

[0027] In summary, even with conventional acceleration methods such as increasing gate voltage, NBTI testing remains constrained by high-temperature environments, long-term data acquisition sequences, and the lengthy and complex process of subsequent data fitting and extrapolation. For process development requiring rapid iteration, the time savings are very limited and cannot meet the need for real-time, rapid assessment of the reliability impact of process changes at wafer test (WAT) sites. Therefore, there is an urgent need for an innovative method that can eliminate the aforementioned multi-step measurement and extrapolation process and directly utilize room-temperature, short-time test results to make an equivalent judgment on device lifetime.

[0028] To address the technical problem of long testing times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the testing time and heating time for semiconductor devices under negative bias temperature instability testing, thereby accelerating the testing process. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions over a rapid testing time is equivalent to the degradation degree that would occur when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index for the device at the target lifetime after the test is completed, without the need for further derivation.

[0029] Specifically, the logic of the traditional testing paradigm can be summarized as "test time → data extrapolation → target lifetime". That is, under certain set test conditions (such as high temperature, normal voltage), a relatively long test time is actually performed, and by monitoring the degradation data during this period, the total time required for the device to reach the failure standard (i.e., the predicted target lifetime) is extrapolated and estimated. Fundamentally different, the new paradigm proposed in this application lies in the logic of "target lifetime → equivalent mapping → rapid test conditions". This application does not extrapolate from a test time, but directly uses the product's required target lifetime (e.g., a 5-year lifetime requirement under DC operation) as a known input and equivalent benchmark.

[0030] By using a power-law model, a set of enhanced test conditions (i.e., higher gate voltage combined with room temperature) is derived in reverse. Under these new conditions, the actual performance degradation induced by a very short test time (e.g., a few seconds to tens of seconds) is exactly equivalent to the degradation endpoint state that the device should reach after running for the full target lifetime under the original standard conditions.

[0031] Therefore, since the endpoint of the rapid test is directly designed to be equivalent to the target lifetime endpoint, the performance degradation measured after the rapid test is itself a direct reflection of the device's state at the target lifetime endpoint. The evaluation process is simplified to directly comparing the result of this single measurement with the expected endpoint criterion, thus completely bypassing the necessary and time-consuming "long sequence data acquisition - curve fitting - mathematical extrapolation" steps in traditional methods, achieving a qualitative leap from "estimating lifetime" to "verifying the endpoint state".

[0032] To achieve the aforementioned equivalence, this application utilizes an equivalent model for testing semiconductor devices under negative bias temperature instability (NBTI). As semiconductor manufacturing technology advances to advanced process nodes (e.g., for p-type metal-oxide-semiconductor devices operating at 1.8V and below), the feature size of devices continues to shrink, making the NBTI effect increasingly significant and a key factor limiting the long-term reliability of devices. Against this backdrop, this application employs a power law lifetime model as the equivalent test model for the aforementioned test conditions, addressing the degradation characteristics of such advanced process devices.

[0033] Specifically, the power-law lifetime model can be characterized as: .

[0034] Wherein, TTF (Time to Failure) is the failure time, defined as the time to failure under given constant electrothermal stress conditions (a specific gate voltage V). gs At an absolute temperature T, key performance parameters of semiconductor devices (such as drain current I) ds or threshold voltage V th V is the total stress time experienced when the electrode degrades to a specific failure criterion (such as a preset failure criterion, such as a 10% drain current loss). A is the pre-exponential factor (i.e., the constant influence factor preceding the exponential part, usually abbreviated as pre-exponential factor), a material- and process-related constant; V gs α represents the magnitude of the applied gate voltage (already positive); α is the voltage acceleration factor of the gate voltage, characterizing the amplification effect of the gate electric field on the degradation rate. Ea is the activation energy, which is the energy barrier reflecting the thermal activation characteristics of the NBTI degradation process (such as interface state formation), and is measured in electron volts (eV). K is the Boltzmann constant; T is the absolute temperature at which stress is applied.

[0035] The aforementioned power-law lifetime model clearly reveals that the NBTI failure time is simultaneously affected by the electric field (V). gs The model is dominated by both the α-power effect and the thermal activation effect (exp(Ea / (K×T))). Therefore, based on this model, the target lifetime required by the product specifications can be substituted into the model as the known TTF, and a desired, extremely short rapid test time and room temperature can be selected as the target test temperature. By solving the power-law model equation in reverse, the precise gate voltage value required to produce a degradation amount completely equivalent to the target lifetime at this short time and room temperature can be calculated. In other words, its core is to utilize the model under the constraint of TTF equivalence to determine the V... gs The three variables, V, T, and t (test time), were reallocated and optimized, resulting in a significant improvement in V. gsThis is to compensate for the decrease in T and the sharp shortening of t, thereby achieving a direct physical equivalence to the degradation endpoint, rather than tracking and extrapolating the degradation process.

[0036] Example testing method:

[0037] Based on the aforementioned equivalent logic, this application provides an exemplary flowchart of a test execution method for negative bias temperature instability testing ( Figure 1 ).

[0038] like Figure 1 As shown, the semiconductor device testing method P100 may include the following steps:

[0039] S110. Determine the batch activation energy of the target batch of the semiconductor device under test.

[0040] S120, based on batch activation energy and power-law lifetime model, maps the target lifetime of negative bias temperature instability test under standard test conditions to rapid test time under rapid test conditions.

[0041] S130. Based on rapid test conditions and rapid test time, perform negative bias temperature instability test on the semiconductor device under test to determine the test results of the semiconductor device under test.

[0042] In the aforementioned S110, the semiconductor device under test can refer to the specific object to be tested by the test execution scheme provided in this application, which can be a semiconductor device manufactured using advanced manufacturing processes (such as 28nm and below advanced technology nodes). For example, the experimental chip used in the execution of this method can be a p-type metal-oxide-semiconductor (PMOS) device manufactured using a 28nm manufacturing process, with an operating voltage of, for example, 1.8V.

[0043] The target batch can refer to the same production batch (Lot) of the semiconductor device under test, which has the same manufacturing process and tape-out history. Since slight fluctuations in the manufacturing process may affect device reliability, this method calibrates the activation energy and maps it to the test conditions on a batch-by-batch basis to ensure the specificity and accuracy of the evaluation.

[0044] The batch activation energy (Ea) is the first physical parameter that needs to be clarified in this method. It mainly describes the average energy barrier that a semiconductor device needs to overcome, usually measured in electron volts (eV). This parameter is used to establish an equivalent mapping between standard test conditions and rapid test conditions. The batch activation energy should be able to be accurately calculated from experimental data, and for the same batch of semiconductor devices, this calculated value should be usable as input to the power-law lifetime model, ensuring the accuracy of the mapping.

[0045] In some embodiments, S110 (i.e., determining the activation energy of the batch) can be achieved in two main ways: First, by direct retrieval, i.e., querying or retrieving previously measured and stored batch activation energy values ​​from an existing database of device reliability characteristics for that batch. Second, by measurement, i.e., extracting representative sample devices from the target batch, and using NBTI test data at two different temperatures (e.g., 125°C and 85°C), calculating the activation energy of the batch (e.g., Ea = 0.81 eV) on-site based on the physical relationship between degradation time and temperature (i.e., the Arrhenius relation).

[0046] In the aforementioned S120, the power-law lifetime model is the equivalent model adopted in this application, as detailed in the foregoing description. In practical applications, other models can also be used to equivalently execute the method provided in this application for non-advanced processes, which will not be elaborated here.

[0047] Standard test conditions refer to the traditional baseline conditions for evaluating the reliability of a device's NBTI (Not Including Test Time). These typically include a high temperature (e.g., 125°C) and a standard stress gate voltage determined based on the device's operating voltage (e.g., -1.98V, 1.1Vcc). The target lifetime is the minimum reliable operational life, expressed in time units (e.g., 5 years, DC), that the device is required to achieve under the aforementioned standard test conditions, as required by product specifications. In this method, this target lifetime is directly used as the known failure time (TTF) input in the power-law lifetime model.

[0048] The rapid test conditions are new combinations of conditions that this method aims to obtain to replace the standard test. Their gate voltage amplitude is greater than that of the standard test conditions, and their test temperature indicates room temperature conditions (e.g., 25°C).

[0049] Rapid testing time is the length of time stress needs to be applied under rapid testing conditions to produce a degradation level equivalent to the target lifetime under standard testing conditions. This time should be sufficiently short (e.g., on the order of seconds to minutes), and its value should be calculated based on the equivalent degradation principle using a power-law lifetime model so that applying rapid testing conditions within this time can achieve an evaluation effect equivalent to that of long-term standard testing.

[0050] In some embodiments, the aforementioned S120 can be implemented based on the aforementioned equivalent logic. That is, based on the power-law relationship between failure time and gate voltage and the exponential relationship with temperature expressed by the aforementioned power-law lifetime model, so that the mapping relationship established based on the model between different test conditions (voltage, temperature) can ensure the equivalence of the degree of device degradation.

[0051] For example, the determined batch activation energy (Ea), standard test conditions and their corresponding target lifetime, and the desired rapid test temperature (i.e., room temperature) can be substituted into the model. By setting or selecting a desired, extremely short rapid test time, the model equations are constructed. Thus, only the rapid test gate voltage remains an unknown in the model equations. Solving this equation fully defines the rapid test conditions, ensuring that the degradation of the semiconductor device under test under these rapid test conditions over a rapid test time is equivalent to the degradation that occurs when operating under standard test conditions to the target lifetime.

[0052] In some embodiments, the aforementioned equivalent mapping process can be further refined into step-by-step execution to improve the robustness and verifiability of the mapping process. First, a fast test time can be determined, i.e., a test time value (e.g., 10 seconds) that is much shorter than the target lifetime and is expected to be used in the fast test is preset or selected. Then, based on the batch activation energy and the fast test time, the standard test conditions are mapped to intermediate test conditions using a power-law lifetime model. The intermediate test conditions are a set of transitional condition parameters introduced in the step-by-step mapping process. Their test temperature is the same as the standard test conditions, but their gate voltage is higher than the standard test conditions, and the degree of degradation caused by applying the fast test time under these conditions is equivalent to the degree of degradation caused by reaching the target lifetime under the standard test conditions. That is, the intermediate test conditions are a virtual state of "same temperature but higher voltage" to separate the two physical effects of "voltage acceleration" and "temperature transition," so that the first step of the mapping only focuses on compensating for the sharp reduction in time by increasing the voltage at a fixed temperature.

[0053] Then, based on the batch activation energy, the intermediate test conditions are mapped to the rapid test conditions through the power-law lifetime model. This allows the temperature to be converted from the high temperature of the standard test to room temperature while maintaining the equivalence of the degradation level and test time. Finally, the gate voltage required to perform the rapid test at room temperature is calculated.

[0054] Based on the aforementioned model, in actual calculations, the aforementioned equivalence can be performed directly without fully calculating the model. The intermediate test conditions and the standard test conditions satisfy the following relationship: Where TTF0 is the target lifetime, V gs0 The gate voltage is the standard test condition, TTF1 is the fast test time, and V is the voltage at which the gate voltage is measured. gs1 This represents the gate voltage under intermediate test conditions. This mapping relationship is directly derived from the inverse power-law relationship between failure time and gate voltage at a fixed temperature in the power-law model.

[0055] Intermediate test conditions and rapid test conditions satisfy the following relationship: Where T0 is the test temperature under standard test conditions, T1 is the test temperature under rapid test conditions, and V gs2This is the gate voltage for rapid testing conditions. This mapping ensures that the equivalence of degradation levels is maintained by adjusting the gate voltage when the temperature changes.

[0056] To further illustrate the above process, this application also provides the following specific calculation example. Specifically, for a batch of 1.8V PMOS devices, its batch activation energy Ea is known to be 0.81eV. The standard test conditions are: temperature T0 = 125℃ (398K), gate voltage V... gs0 =1.98V, target lifetime TTF0=5 years (approximately 1.58×10⁻⁶) 8 The desired rapid test temperature T1 is 25℃ (298K), and the rapid test time TTF1 is set to 10 seconds. First, the initial mapping is performed (temperature fixed at 125℃): According to the power-law lifetime model, under conditions of equivalent degradation and the same temperature, the standard condition (V...) is applied. gs0 The gate voltage V under intermediate test conditions was calculated using TTF0. gs1 ≈3.2V. Then, a second mapping step is performed (time fixed at 10 seconds, temperature changed from 125℃ to 25℃): According to the power-law lifetime model, under the conditions of equivalent degradation degree and the same time, the intermediate condition (V) is used. gs1 The final fast test gate voltage V is calculated by (T0). gs2 ≈4.0V. Therefore, the aforementioned calculation process, through step-by-step calculations, clarifies the complete equivalent mapping path from "125℃ / -1.98V / 5 years" to "25℃ / -4.0V / 10 seconds". Furthermore, the devices involved in the aforementioned calculation process are common devices used in practical applications of this application. That is, when executing this application, the semiconductor device under test can be a 1.8V p-type metal-oxide-semiconductor device. The standard test conditions for this semiconductor device are a test temperature of 125℃, a gate voltage amplitude of 1.98V, and a target lifetime of 5 years. When testing this type of device, its batch activation energy is generally 0.81eV (generally fluctuating by 10%). Based on the aforementioned calculation process and the test method of this application, the rapid test conditions are a test temperature of 25℃ (i.e., room temperature), a test time of 10 seconds, and a gate voltage amplitude of 4.0V. In some embodiments, to ensure the safety and model validity of the finally determined rapid test conditions during actual execution, a safety verification step can be added after the mapping calculation. Specifically, based on the batch activation energy, the gate voltage V under rapid test conditions is calculated using a power-law lifetime model. gs2 Next, it is determined whether applying the voltage to the semiconductor device under test during the rapid testing time might trigger nonlinear effects (such as significant gate oxide tunneling current, which may deviate from the prediction law of the power-law model). This determination can be based on the device's physical parameters (such as the known gate oxide breakdown voltage V). bdThe test is conducted according to the established safety margin. If it is determined that no nonlinear effect is triggered (i.e., safe), the rapid test time and rapid test conditions are directly adopted. If it is determined that a nonlinear effect may be triggered (i.e., unsafe), the rapid test conditions need to be redefined. This is usually achieved by extending the rapid test time and re-performing the aforementioned mapping calculation with the updated time value to obtain a new set of rapid test conditions with a lower voltage. The safety assessment is then performed again until a safe and equivalent combination of test conditions is obtained.

[0057] In step S130, performing the negative bias temperature instability test refers to applying corresponding electrothermal stress to the semiconductor device under test according to the rapid test conditions determined in step S120. Specifically, at room temperature, a calculated negative voltage of a relatively high amplitude is applied to the gate of the device, and the test is continued for a precise rapid test time. Thus, after completing the aforementioned short-term stress, the degree of degradation is quantified by measuring the changes in the device's electrical parameters, forming a conclusion that can be used for reliability assessment. This result directly reflects the endpoint degradation state reached under rapid test conditions, and this state has been ensured to be equivalent to the endpoint state under the target lifetime through model mapping. Therefore, this test result can be directly used to determine whether the device meets the target lifetime requirements without any additional time extrapolation or lifetime conversion.

[0058] Therefore, based on the aforementioned test execution method P100 for negative bias temperature instability testing, addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions of negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the test time and heating time of semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process of semiconductor devices. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and rapid test time is equivalent to the degradation degree produced when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation.

[0059] In some embodiments, the determination of test results can be concretized into a standardized measurement and calculation process. For the target semiconductor device in the semiconductor device under test, its first drain current (denoted as I) before testing is first determined. dsT0 That is, before applying rapid test stress, under specified measurement conditions (such as a specific source-drain voltage V), dsThe initial drain current of the device was measured under the following conditions. This value serves as a benchmark for evaluating performance degradation. Immediately after applying stress under rapid test conditions (high voltage, short duration), the second drain current (denoted as I) was determined under identical measurement conditions. dsT1 T1 is the fast test time.

[0060] Based on the first drain current and the second drain current, the drain current degradation index of the target semiconductor device can be determined. This index is typically the rate of change of the second drain current relative to the first drain current, and can be expressed by the formula degradation index I. ds %=(I dsT0 -I dsT1 ) / I dsT0 The result is calculated (or converted to a percentage). This metric quantifies the performance loss caused by rapid stress and is closely related to the reliability of the device. Ultimately, the test results are determined based on the drain current degradation metric of the target semiconductor device, which includes at least the quantified metric itself and may further include a preliminary evaluation based on that metric.

[0061] It should be understood that, apart from drain current, other key electrical parameters such as threshold voltage V th The amount of drift (ΔV) th It can also serve as a basis for quantifying performance degradation by measuring V before and after stress. th The changes are analyzed and their relative or absolute changes are calculated to form a similar deterioration indicator.

[0062] Based on the aforementioned testing process, to facilitate rapid and consistent acceptance / failure determination of test results, a preset screening threshold can be introduced. The screening threshold is a critical percentage value used to determine whether a drain current degradation index (or other quantitative indicator) is acceptable. Determining the test result of the target semiconductor device involves comparing the calculated drain current degradation index with the screening threshold. The specific judgment rule can be: if the drain current degradation index of the target semiconductor device is less than the screening threshold, the test result is considered passed, meaning the device is expected to meet the target lifetime requirement; if the drain current degradation index is greater than the screening threshold, the test result is considered failed. The screening threshold itself is not arbitrarily set; its value can be based on historical test results of devices of the same specification as the target semiconductor device, by establishing a correlation model between lifetime estimation and the drain current degradation index, and then substituting the target lifetime into this model to deduce the result. Preferably, the screening threshold for the drain current degradation index of the semiconductor device under test is 2.8%.

[0063] To further illustrate the process of determining the batch activation energy, this application also provides a schematic diagram of the deterioration curves of drain current with test time at different temperatures. Figure 2 ).

[0064] To ensure accurate test results during actual testing, the activation energy of the aforementioned batch can be determined through testing. Specifically, representative sample devices can be selected from the target batch and subjected to NBTI testing at at least two different constant temperatures (e.g., 125°C and 85°C), while maintaining consistent other stress conditions (such as gate voltage). By monitoring and recording the degradation data of drain current (or threshold voltage) over stress time through real-time or periodic stress interruptions, a graph can be plotted as follows. Figure 2 The performance degradation curves (i.e., the "time-degradation" curves) shown are presented at different temperatures. The horizontal axis represents exponentially increased time, and the vertical axis represents the drain current degradation rate (Ids) (in %), i.e., the aforementioned I... ds %).

[0065] The key to determining the activation energy lies in utilizing the time difference corresponding to the same degree of degradation. On two curves, select the curve that reaches the same degree of performance degradation (e.g., I0). ds The stress times corresponding to 10% are denoted as t3 (at high temperature) and t4 (at low temperature), respectively. Since the degradation mechanism is the same, the time required to reach the same degradation amount follows an Arrhenius relation, meaning the reaction rate (inversely proportional to time) is exponentially related to temperature. Therefore, the batch activation energy Ea can be calculated using a power-law equivalent model under the same TTF. Thus, the activation energy Ea value specific to this batch of devices (e.g., 0.81 eV) can be directly calculated. This method provides customized key input parameters for the reliability model using measured data.

[0066] In addition, determining the gate voltage acceleration factor α usually requires an independent experiment that controls the temperature to remain constant while changing the gate voltage. The principle is similar to the method of calculating Ea based on temperature change mentioned above, but the specific formula and variables are different, which will not be elaborated here.

[0067] To further illustrate the aforementioned screening threshold, this application also provides an exemplary flowchart of a method for determining the screening threshold ( Figure 3 ).

[0068] like Figure 3 As shown, the screening threshold determination method P300 may include the following steps:

[0069] S310. Determine the correlation between lifetime estimation and drain current degradation index based on historical test results of devices of the same specification as the target semiconductor device.

[0070] S320. Load the target lifetime into the correlation, determine the drain current degradation index corresponding to the target lifetime, and configure it as the screening threshold.

[0071] In step S310, the historical test results of devices of the same specification refer to the complete test dataset accumulated from devices manufactured in the past that have the same design specifications and process nodes as the current target semiconductor device. This dataset contains at least two types of key information: first, the "lifetime estimate" (usually in years) of the corresponding device evaluated through traditional, reliable long-term NBTI testing or a validated lifetime model; and second, the corresponding drain current degradation index (in %, e.g., I) measured using the rapid testing method of this application (or an equivalent method of the same principle). ds %).

[0072] In some embodiments, the execution of S310 can employ data analysis methods (e.g., linear regression, nonlinear regression, curve fitting, etc.) to extract a mathematical model from the aforementioned historical data that can describe the quantitative correlation between the two. Typically, lifetime estimation is used as the independent variable (denoted as X), and drain current degradation index is used as the dependent variable (denoted as Y), establishing a functional relationship Y=f(X). This model can be an explicit mathematical formula, and its fitted form may be Y=a×ln(X)+b or Y=c×exp(-d×X), etc., where a, b, c, and d are fitting parameters. The process of determining this correlation requires that the established model pass statistical tests (e.g., has a high coefficient of determination R²), indicating a significant and predictable correlation trend between device lifetime and rapid testing degradation index, thus ensuring the reliability of this relationship as a basis for threshold derivation.

[0073] In step S320, the target lifetime is the minimum lifetime standard (e.g., 5 years, DC) that must be achieved under standard test conditions, as set by the product specifications or reliability requirements for the current batch of devices under test. Substituting the target lifetime into the correlation means taking the specific value of the target lifetime as the X value and substituting it into the mathematical model Y=f(X) determined in step S310. The calculated function value Y is the drain current degradation index corresponding to the target lifetime.

[0074] To further illustrate this point, this application also provides a schematic diagram illustrating the correlation between lifetime estimation and drain current degradation index. Figure 4 ).

[0075] like Figure 4 As shown, the horizontal axis of the correlation between lifetime estimate and drain current degradation index can be lifetime, and the vertical axis can be the drain current degradation rate Ids (in %, denoted as I). ds Based on the discrete points determined in the preceding steps, data fitting can be performed. Considering that the lifetime distribution may have a large range, the logarithm can be taken, and ln(x) can be processed as a whole.

[0076] like Figure 4As shown, the fitted result is y = -0.002ln(x) + 0.0338. Substituting the aforementioned target lifetime into this fitted result yields the aforementioned degradation rate threshold. Based on the aforementioned logic, the degradation rate threshold determined by the aforementioned process actually reflects that the drain current degradation rate, after conversion, exactly corresponds to the target lifetime. Therefore, if the drain current degradation rate determined by the test is less than this degradation rate threshold, it can be said that the target lifetime is met.

[0077] Therefore, by substituting the aforementioned target lifetime (e.g., 5 years, DC) as the X value into the fitted formula, the calculated Y value (e.g., approximately 2.8%) is the desired screening threshold. The threshold determined based on this logic reflects that if a device's rapid test degradation index is less than this threshold, it means its estimated lifetime is greater than the target lifetime, and it can be determined to meet the requirements; otherwise, it cannot meet the requirements.

[0078] Therefore, this calculated specific Y value (e.g., 2.8%) can be formally set as a fixed or dynamically callable key parameter (i.e., screening threshold) for rapid testing and judgment of this product batch. In the production testing system or quality control software, this threshold will be entered and compared in real time with the measured degradation index of each device under test, thereby achieving automated and standardized "pass / fail" judgment. Determining the screening threshold through the above data-driven method ensures the scientific and objective nature of the threshold setting, directly tracing it to product life requirements rather than relying on empirical estimations, thus significantly improving the accuracy and reliability of rapid testing and judgment results.

[0079] In some embodiments, in addition to determining whether lifetime requirements are met, the aforementioned semiconductor device testing method can also be used to guide process optimization. To further illustrate this process, this application also provides an exemplary flowchart of a testing method based on fabrication parameters (…). Figure 5 ).

[0080] like Figure 5 As shown, process P500 may include the following steps:

[0081] S510. Identify semiconductor devices under test that have differences in fabrication parameters.

[0082] S520. Determine the drain current degradation index of each semiconductor device in the semiconductor device under test.

[0083] S530. Identify the target device from the semiconductor devices under test whose drain current degradation index meets the test requirements.

[0084] S540. Determine the direction of parameter optimization based on the fabrication parameters of the target device.

[0085] In S510, a semiconductor device under test with differences in fabrication parameters refers to a group of experimental devices belonging to the same product specification, but whose key manufacturing process parameters (i.e., fabrication parameters) are intentionally set to different levels. These fabrication parameters are variables that need to be optimized during process development, such as gate oxide thickness, annealing temperature, and ion implantation concentration. Each parameter combination corresponds to an experimental group, and by comparing the reliability performance of different groups of devices, the optimal process window can be identified.

[0086] When performing S520, all devices from the different experimental groups mentioned above can be tested using the method described in this application (i.e., rapid testing based on equivalent mapping), and following standardized procedures (such as measuring stress before and after I). ds The rate of change is calculated to obtain the drain current degradation index for each device. This index serves as a unified and objective measure for quantitatively evaluating the NBTI performance of devices under various process conditions.

[0087] When executing S530, the device (or device group) with the best performance is selected from the test data of all experimental group devices by comparing the values ​​of the drain current degradation index. The test requirements can refer to the selection criteria for the target device, which generally include basic requirements (such as meeting the aforementioned fast screening criteria or other design requirements for the drain current degradation index) and / or optimal principles (such as one or more devices with the lowest drain current degradation index). For example, the lower the drain current degradation index, the stronger the device's resistance to NBTI degradation and the longer its expected lifetime. Therefore, the target device can be all or part of the devices corresponding to the experimental group with the lowest average degradation index. For example, in a gate oxide thickness experiment, the average degradation index of the experimental group devices with thickness B is 1.5%, significantly lower than that of thickness group A (3.0%) and thickness group C (2.5%). Therefore, the devices in thickness group B are determined as the target devices for this experiment.

[0088] When executing S540, after identifying the target device, its manufacturing file is consulted to determine the specific fabrication parameter values ​​used for that group of devices (e.g., the gate oxide thickness for the target device is B, the annealing temperature is 950°C, and the ion implantation concentration is C_medium). Based on this, a clear direction for parameter optimization can be derived. This direction is typically stated as follows: in subsequent process development or production adjustments, the corresponding fabrication parameters should be controlled to be close to or approach the parameter values ​​(or ranges) used by the target device. For example, if the target device corresponds to a high annealing temperature, the optimization direction can be determined as using an annealing process at a temperature no lower than this preferred temperature; if the target device corresponds to a specific ion implantation concentration, the direction can be determined as using this concentration as the center value for process settings.

[0089] In some embodiments, when making the selection in S530, in addition to the direct indication of the drain current degradation index, the estimated lifetime can also be determined based on the drain current degradation index by combining the correlation between the determined lifetime estimate and the drain current degradation index, and displayed in a more intuitive form.

[0090] For example, this application also provides schematic diagrams of test results for gate oxide layer thickness experiment (a), annealing temperature experiment (b), and IMP concentration experiment (c). Figure 6 (a, b, c). Each test result is presented in relation to... Figure 4 In a similar coordinate system, users can select target devices based on estimated lifetime. That is, as... Figure 6 As shown, all three implementations are based on the aforementioned Ids, which can be understood as lifetime assessment based on Ids (i.e., lifetime gap vs Ids degradation).

[0091] Through the above process, the rapid testing method provided in this application not only realizes the reliability assessment of a single device, but also extends into an efficient process development and optimization tool. It can objectively identify the optimal solution from multiple process experimental schemes in a very short time (such as within a few hours) and provide a clear optimization path, thereby greatly accelerating the R&D iteration cycle of high-performance and high-reliability semiconductor manufacturing processes.

[0092] In summary, the semiconductor device testing method provided in this application has achieved the following unexpected results:

[0093] ① Fundamental Revolution in Testing Paradigm and Leapfrog Improvement in Efficiency: Addressing the core pain point of excessively long evaluation times for negative bias temperature instability (NBTI) in semiconductor process development, which severely hinders R&D iteration, this application breaks through the traditional technical paradigm of "long-term stress - multi-point data acquisition - curve extrapolation." By creatively introducing the inverse logic of "target lifetime → equivalent mapping → rapid testing conditions" based on a power-law lifetime model, the standard reliability test, which must rely on high temperatures and lasts for tens of days, is transformed into a room-temperature, second-level rapid screening that can be performed at wafer test (WAT) sites. Without sacrificing the physical basis of evaluation accuracy, this method reduces the typical evaluation time for a batch of 25 wafers from approximately 47 days to approximately 0.35 hours, improving efficiency by more than three orders of magnitude, and providing crucial real-time feedback capabilities for rapid optimization and closed-loop management of process parameters.

[0094] ② Precise Equivalence and Safety Assurance Driven by a Physical Model: This application is not a simple empirical acceleration, but rather delves into and systematically utilizes the intrinsic physical laws of NBTI degradation—the Power Law Lifetime Model. By precisely measuring the key parameter "batch activation energy (Ea)" for a specific batch and performing rigorous mathematical mapping calculations based on this model, the physical basis for achieving strict equivalence to high-temperature long-term standard tests (e.g., 125℃, -1.98V, 5 years, DC) at the degradation endpoint can be established by applying a specific high-pressure stress for an extremely short time (e.g., -4.0V, 10 seconds) at room temperature. Simultaneously, the method incorporates a safety verification mechanism for the calculated high gate voltage, determining whether it may trigger nonlinear effects such as gate oxide breakdown, and adaptively adjusting the test time as needed to ensure that the test conditions are always within a safe and model-valid range, thus guaranteeing the reliability and universality of the method.

[0095] ③ Validation of the strong correlation and universality of process optimization-oriented methods: This scheme confirms that the established rapid testing methods and indicators exhibit strong correlation and universality in experiments with different process variables. In improvement experiments of various key processes such as gate oxide thickness, annealing temperature, and ion implantation concentration, a clear and consistent correlation is shown between the drain current degradation index obtained by rapid testing and the final NBTI lifetime result evaluated by traditional long-term testing. Therefore, this method can effectively and sensitively identify the subtle impact of different process conditions on device reliability, thereby quickly and objectively locking in the optimal process window from numerous experimental schemes, greatly accelerating the learning and optimization closed loop of "test-analysis-decision" in process development.

[0096] ④ Extreme simplification of the evaluation process and seamless integration with mass production: Addressing the threshold voltage (V) issue in traditional NBTI evaluation... th This application innovatively addresses the complex, time-consuming, and difficult-to-process-in-real-time challenges of lifespan assessment by shifting the criterion from V... th Drift transfer to drain current (I ds The degradation rate is an electrical parameter that is easier to measure quickly and accurately. This is achieved by establishing I... ds The quantitative correlation between degradation rate and lifespan, and the determination of the corresponding screening threshold (e.g., 2.8%), simplifies the entire evaluation process from complex parameter extraction and model calculation to a one-time "stress-measurement-comparison" action. This significantly reduces the technical implementation threshold and equipment dependence, enabling this rapid screening method to be seamlessly integrated into existing mass-produced WAT testing environments. It achieves online, real-time, and automated reliability monitoring and sorting, ensuring the high feasibility and stability of the technology in large-scale manufacturing.

[0097] The embodiments disclosed above are merely illustrative of this application. The embodiments do not exhaustively describe all details, nor do they limit the application to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A test execution method for negative bias temperature instability testing, characterized in that, include: Determine the batch activation energy of the target batch of the semiconductor device under test, wherein the semiconductor device under test refers to multiple semiconductor devices in the same batch under advanced process technology; Based on the batch activation energy and power-law lifetime model, the target lifetime of the negative bias temperature instability test under standard test conditions is mapped to the rapid test time under rapid test conditions. The degree of degradation of the semiconductor device under test under the rapid test conditions and the rapid test time is equivalent to the degree of degradation that occurs when the device reaches the target lifetime under the standard test conditions. The gate voltage under the rapid test conditions is greater than the gate voltage under the standard test conditions, and the test temperature under the rapid test conditions indicates room temperature. Based on the rapid testing conditions and the rapid testing time, the negative bias temperature instability test is performed on the semiconductor device under test to determine the test result of the semiconductor device under test; The power-law lifetime model is as follows: Where TTF is the failure time, Ea is the batch activation energy, α is the acceleration factor of the gate voltage, and K is the Boltzmann constant. The amplitude of the gate voltage is T, the absolute temperature value of the test temperature is T, and the pre-exponential factor is A.

2. The test execution method according to claim 1, characterized in that, The process of mapping the target lifetime under standard test conditions to a rapid test time under rapid test conditions, based on the batch activation energy and power-law lifetime model, includes: Determine the rapid test time; Based on the batch activation energy and the rapid test time, the standard test conditions are mapped to intermediate test conditions using the power-law lifetime model. The degree of degradation of the semiconductor device under test under the intermediate test conditions and the rapid test time is equivalent to the degree of degradation when the device reaches the target lifetime under the standard test conditions. The gate voltage of the intermediate test conditions is greater than the gate voltage of the standard test conditions, and the test temperature is the same. Based on the batch activation energy, the intermediate test conditions are mapped to the fast test conditions using the power-law lifetime model, wherein the degradation degree of the semiconductor device under test based on the intermediate test conditions is equivalent to the degradation degree based on the fast test conditions, and the test time of the intermediate test conditions and the fast test conditions are equal.

3. The test execution method according to claim 2, characterized in that, The intermediate test conditions and the standard test conditions satisfy the following relationship: Where TTF0 is the target lifetime, V gs0 The gate voltage under the standard test conditions is V, TTF1 is the fast test time, and V is the voltage at which the test conditions are met. gs1 The gate voltage under the intermediate test conditions; The intermediate test conditions and the rapid test conditions satisfy the following relationship: Where T0 is the test temperature under the standard test conditions, T1 is the test temperature under the rapid test conditions, and V gs2 The gate voltage under the rapid test conditions.

4. The test execution method according to claim 2, characterized in that, The process of mapping the intermediate test conditions to the rapid test conditions based on the batch activation energy using the power-law lifetime model includes: Based on the batch activation energy, the intermediate test conditions are mapped to the gate voltage of the fast test conditions using the power-law lifetime model; Determine whether the gate voltage applied to the semiconductor device under test under the rapid test conditions during the rapid test time triggers a nonlinear effect; If not, then the rapid test time and the rapid test conditions shall be used; If so, the rapid test conditions are redefined and the rapid test time is adjusted based on the updated rapid test conditions.

5. The test execution method according to claim 1, characterized in that, The determination of the batch activation energy of the target batch of the semiconductor device under test includes: Obtain test results for the target batch of semiconductor devices under test at different test temperatures, wherein the test results include at least the test time at the same degree of degradation; The activation energy of the target batch is determined based on the difference in test time to reach the same degree of degradation at different test temperatures.

6. The test execution method according to claim 1, characterized in that, Determining the test results of the semiconductor device under test includes: For the target semiconductor device in the semiconductor device under test, determine the first drain current of the target semiconductor device before the test and the second drain current after the test; The drain current degradation index of the target semiconductor device is determined based on the first drain current and the second drain current, wherein the drain current degradation index is the rate of change of the second drain current relative to the first drain current. The test results of the target semiconductor device are determined based on the drain current degradation index of the target semiconductor device, thereby determining the test results of the semiconductor device under test, wherein the test results include the drain current degradation index and the device evaluation determined based on the drain current degradation index.

7. The test execution method according to claim 6, characterized in that, The semiconductor device under test has different fabrication parameters. Determining the test results of the semiconductor device under test includes: From the semiconductor device under test, determine the target device whose drain current degradation index meets the test requirements; The direction of parameter optimization is determined based on the fabrication parameters of the target device.

8. The test execution method according to claim 6, characterized in that, The determination of the test results of the target semiconductor device based on the drain current degradation index of the target semiconductor device includes: The test results of the target semiconductor device are determined based on the screening threshold of the drain current degradation index. Wherein, if the drain current degradation index of the target semiconductor device is less than the screening threshold, the test result of the target semiconductor device is a pass; if the drain current degradation index of the target semiconductor device is greater than the screening threshold, the test result of the target semiconductor device is a fail.

9. The test execution method according to claim 8, characterized in that, The screening threshold is determined based on the following method: The correlation between lifetime estimation and drain current degradation index is determined based on historical test results of devices of the same specification as the target semiconductor device. The target lifetime is loaded into the correlation to determine the drain current degradation index corresponding to the target lifetime, and configured as the screening threshold.

10. The test execution method according to claim 7, characterized in that, The semiconductor device under test is a 1.8V p-type metal-oxide-semiconductor device; The standard test conditions are a test temperature of 125°C and a gate voltage amplitude of 1.98V; the target lifetime is 5 years; the rapid test conditions are a test temperature of 25°C, a test time of 10 seconds, and a gate voltage amplitude of 4.0V. The screening threshold for the drain current degradation index of the semiconductor device under test is 2.8%; The batch activation energy is 0.81 eV; The differences in the fabrication parameters of the semiconductor device under test include at least one of the following: gate oxide thickness, annealing temperature, or ion implantation concentration.

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