Photoelectric co-packaging structure and light emitting module

Abstract

The invention provides a photoelectric co-packaging structure and a light emitting module, electric conduction and thermal conduction between an electric chip and a circuit board are realized through a conduction structure arranged in a substrate in a penetrating manner, the circuit board is arranged on the first side of the substrate, a light emitting chip is embedded and connected to the circuit board, and the light emitting chip is arranged on the first side of the substrate. The electric chip and the dimming chip are inversely arranged on the second side of the substrate through the micro convex points, the electric chip and the dimming chip are electrically connected through the rewiring layer arranged on the surface of the substrate, the dimming chip and the light-emitting chip are conducted through the optical waveguide, and the refrigeration piece is arranged on the circuit board, so that heat dissipation is conducted on the light-emitting chip and the electric chip, and the light-emitting chip is cooled. Therefore, the stability and the reliability of the photoelectric packaging structure are effectively improved, the transmission loss and the signal crosstalk of high-frequency signals in the transmission process are reduced, and the photoelectric co-packaging structure is ensured to work more effectively.

Description

Technical Field

[0001] This application relates to the fields of optical communication and integrated circuit packaging technology, and in particular to an optoelectronic co-packaging structure and an optical emitting module. Background Technology

[0002] With the explosive growth of cloud computing and artificial intelligence, the demand for bandwidth in data centers has increased dramatically. Co-Packaged Optics (CPO) technology has emerged to meet this need. Its core concept is to directly integrate optical chips such as lasers and modulators with electrical chips in the same package substrate, shortening the optical-electrical interconnect path from the traditional board level to the millimeter level, thereby significantly reducing transmission loss, power consumption, and latency.

[0003] Existing optoelectronic co-packaging structures, especially in high-power-density packaging, struggle to dissipate heat generated by optical chips such as lasers in a timely manner. This leads to temperature rise causing wavelength drift, and the mismatch in the coefficients of thermal expansion (CTE) between different materials results in mechanical stress, impacting reliability. Furthermore, the high dielectric loss of traditional substrate materials leads to severe high-frequency signal transmission losses, and the CTE mismatch in organic substrates causes thermal stress, further exacerbating signal crosstalk. In addition, traditional free-space interconnects require sub-micron level alignment, relying on high-precision equipment, resulting in low yield and high cost.

[0004] Therefore, how to provide a novel optoelectronic co-packaging structure that can systematically solve the above-mentioned problems of thermal management, high-frequency signal integrity and optical interconnection is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] This application provides an optoelectronic co-package structure and an optical emitting module, which systematically solves key technical problems such as high-frequency signal integrity, thermal management, optical coupling accuracy and packaging integration.

[0006] The first aspect of this application provides an optoelectronic co-packaging structure, comprising:

[0007] A substrate has a first side and a second side opposite to each other along the thickness direction, and a conductive structure is provided in the substrate that penetrates the first side and the second side. A redistribution layer is provided on the second side of the substrate.

[0008] A circuit board is disposed on the first side of the substrate;

[0009] A light-emitting chip is embedded and connected to the circuit board;

[0010] An electrical chip and a dimming chip are disposed on the second side of the substrate and electrically connected through the redistribution layer. The electrical chip is electrically and thermally connected to the circuit board through the conductive structure. The dimming chip and the light-emitting chip are optically connected through an optical waveguide.

[0011] A cooling component, disposed on the circuit board, is used to dissipate heat from the light-emitting chip and the electrical chip.

[0012] In one embodiment of the first aspect of this application, the conductive structure is a through hole penetrating the first side and the second side of the substrate, the through hole is filled with a conductive and thermally conductive element, and the conductive and thermally conductive element is used for electrical and thermal conduction between the electrical chip and the circuit board.

[0013] In one embodiment of the first aspect of this application, an insulating layer is provided between the inner sidewall of the through hole and the outer peripheral wall of the conductive and heat-conducting element.

[0014] In one embodiment of the first aspect of this application, it further includes: an optical fiber array, wherein the optical fiber array is optically coupled to the dimming chip;

[0015] The fiber array includes multiple spaced fibers, the number of which is equal to the number of output waveguides of the dimming chip, and the spacing between adjacent fibers is equal to the spacing between the output waveguides of the dimming chip.

[0016] In one embodiment of the first aspect of this application, the dimming chip includes:

[0017] An optical modulation chip, wherein the light inlet of the optical modulation chip is optically connected to the light-emitting chip through the optical waveguide;

[0018] A wavelength division multiplexing (WDM) chip, wherein the input optical port of the WDM chip is connected to the output optical port of the optical modulation chip, and the output optical port of the WDM chip is optically coupled to the fiber array.

[0019] In one embodiment of the first aspect of this application, the electrical chip and the optical chip are spaced apart along the extending direction of the substrate;

[0020] And / or, there are multiple electrical chips, and the multiple electrical chips are spaced apart along the extension direction of the substrate in the circumferential direction of the dimming chip, and the electrical chips are misaligned with the output optical port of the dimming chip.

[0021] In one embodiment of the first aspect of this application, the difference between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the dimming chip is less than or equal to 1 ppm / ℃;

[0022] And / or, the substrate includes a glass substrate.

[0023] In one embodiment of the first aspect of this application, the circuit board has a mounting through hole, and the light-emitting chip is embedded in the mounting through hole.

[0024] In one embodiment of the first aspect of this application, the cooling element is disposed on the side of the circuit board opposite to the substrate;

[0025] Along the thickness direction of the substrate, a heat sink is disposed between the light-emitting chip and the cooling component, and they are connected through the heat sink.

[0026] In one embodiment of the first aspect of this application, the electrical chip and the dimming chip are flip-chip connected to the second side of the substrate via microbumps and are correspondingly connected to the conductive structure;

[0027] And / or, the circuit board is connected to the first side of the substrate via microbumps and is correspondingly connected to the conductive structure.

[0028] In one embodiment of the first aspect of this application, the redistribution layer includes multiple wiring layers, the multiple wiring layers are stacked along the thickness direction of the substrate, a ground layer is disposed between two adjacent wiring layers, and interconnect vias are disposed in the ground layer, the interconnect vias connecting two adjacent wiring layers.

[0029] The routing direction of the top wiring layer is perpendicular to the routing direction of the bottom wiring layer;

[0030] The routing direction of at least one of the middle routing layers forms an angle of 45° with the routing direction of the top routing layer and / or the routing direction of the bottom routing layer.

[0031] In one embodiment of the first aspect of this application, the optical waveguide has a tapered structure with a gradually changing cross-sectional size, wherein the taper of the tapered structure is greater than or equal to 5° and less than or equal to 15°;

[0032] Wherein, the cross section is the cross section of the optical waveguide perpendicular to the direction of light transmission.

[0033] A second aspect of this application provides a light emitting module, including an optoelectronic co-packaging structure as described in any of the first aspects of this application.

[0034] In summary, the optoelectronic co-packaging structure and light-emitting module provided in this application can achieve electrical and thermal conductivity between the electronic chip and the circuit board through a through-through conductive structure in the substrate. The circuit board is positioned on the first side of the substrate, and the light-emitting chip is embedded and connected to the circuit board. The electronic chip and the dimming chip are flip-chip mounted on the second side of the substrate via micro-bumps. Furthermore, a redistribution layer on the substrate surface enables electrical connection between the electronic chip and the dimming chip, facilitating lateral transmission of electrical signals between them. The dimming chip and the light-emitting chip are optically conductive via an optical waveguide. Additionally, a cooling component is placed on the circuit board to dissipate heat from both the light-emitting chip and the electronic chip. The optoelectronic co-packaging structure provided in this application, through its three-dimensional heterogeneous integration of the optical and electronic chips, allows for timely heat dissipation from the light-emitting chip, effectively improving the stability and reliability of the optoelectronic packaging structure. Furthermore, by selecting and configuring the substrate, the coupling loss of the optical interface is significantly reduced, the transmission distance of the optical-electric interface is shortened, and the transmission loss of high-frequency signals during transmission is reduced. Signal crosstalk is also reduced. Thus, while solving the problem of high-frequency signal integrity, the stability and reliability of the optoelectronic co-packaging structure are significantly improved through the synergistic optimization of materials and structure. This enables the optoelectronic co-packaging structure to systematically overcome the problems of thermal management, high-frequency signal integrity, and optical interconnection, ensuring that the optoelectronic co-packaging structure can work more effectively. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A three-dimensional structural diagram of the optoelectronic co-packaging structure provided in this application;

[0037] Figure 2 A front view of the optoelectronic co-packaging structure provided in this application;

[0038] Figure 3 A top view of the optoelectronic co-packaging structure provided in this application;

[0039] Figure 4 A schematic diagram of one step of the packaging process for the optoelectronic co-packaging structure provided in this application;

[0040] Figure 5 A schematic diagram of one step of the packaging process for the optoelectronic co-packaging structure provided in this application;

[0041] Figure 6A schematic diagram of one step of the packaging process for the optoelectronic co-packaging structure provided in this application;

[0042] Figure 7 A schematic diagram of one step of the packaging process for the optoelectronic co-packaging structure provided in this application;

[0043] Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the optical emitting module provided in this application;

[0044] Figure 9 This is a schematic diagram of the structure of an embodiment of the optical module provided in this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] With the rapid development of cloud computing, artificial intelligence, and big data technologies, the global data center traffic demand is growing exponentially. This recurring growth trend in data center traffic has driven the generational evolution of optical interconnect technology, from traditional pluggable optical modules to higher bandwidth density co-packaged optoelectronics (CPO) technology.

[0048] Specifically, the core objective of CPO technology is to directly integrate optical chips such as optical engine lasers and modulators with electrical chips such as switches within the same package substrate. This shortens the optical-electrical interconnect path to the millimeter level, significantly reducing transmission loss, power consumption, and latency. This technology is primarily applied to high-speed optical communication scenarios with bandwidths of 1.6T / 3.2T and above, such as Data Center Interconnect (DCI), High-Performance Computing (HPC), and 5G / 6G communication infrastructure. These scenarios place extremely high demands on energy efficiency, integration density, signal integrity, and thermal management capabilities, necessitating breakthroughs in traditional packaging technologies.

[0049] In existing technologies, the optical ports of traditional pluggable optical modules are connected to the switch ASIC via an electrical backplane. However, due to the high-frequency loss and insertion loss of copper cables, it is difficult to support stable transmission of PAM4 signals >56 Gb / s. On-Board Optics (OBO) technology can place the optical engine close to the ASIC on the PCB surface, using copper traces as a high-speed channel, but it still suffers from high power consumption, severe electromagnetic interference, and difficulties in thermal management. CPO technology integrates the optical engine and electrical chip on the same substrate, shortening the interconnection path and reducing power consumption and loss.

[0050] However, existing optoelectronic co-packaging structures, especially in high-power-density packaging, struggle to dissipate heat generated by optical chips such as lasers in a timely manner. This leads to temperature increases causing wavelength drift, and the mismatch in the coefficients of thermal expansion (CTE) between different materials results in mechanical stress, impacting reliability. Furthermore, the high dielectric loss of traditional substrate materials leads to severe high-frequency signal transmission losses, and the CTE mismatch in organic substrates causes thermal stress, further exacerbating signal crosstalk. In addition, traditional free-space interconnects require sub-micron level alignment, relying on high-precision equipment, resulting in low yield and high cost.

[0051] Therefore, how to provide a novel optoelectronic co-packaging structure that can systematically solve the above-mentioned problems of thermal management, high-frequency signal integrity and optical interconnection is a technical problem that needs to be solved in this field.

[0052] Based on this, this application provides a three-dimensional heterogeneous integration solution for an optoelectronic co-packaging structure and a light emitting module incorporating this structure. It systematically solves key technical problems in existing technologies such as high-frequency signal integrity, thermal management, optical coupling accuracy, and packaging integration, providing an efficient, reliable, and mass-producible solution for next-generation CPO technology.

[0053] The technical solution of this application will now be described in detail with reference to the accompanying drawings and specific embodiments. Figure 1This is a three-dimensional structural diagram of the optoelectronic co-packaging structure provided in this application. Figure 2 This is a front view of the optoelectronic co-packaging structure provided in this application. Figure 3 This is a top view of the optoelectronic co-packaging structure provided in this application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0054] Specifically, the optoelectronic co-packaging structure provided in this application includes:

[0055] The substrate 7 has a first side and a second side opposite to each other along the thickness direction. At the same time, a conductive structure is provided in the substrate 7 through the first side and the second side, and a redistribution layer (RDL) 12 is provided on the second side of the substrate 7. The redistribution layer 12 can be used for the connection between the electrical chip 9 and the light-emitting chip 1.

[0056] In one specific implementation, the coefficient of thermal expansion of the substrate 7 provided in Embodiment 1 of this application matches the coefficient of thermal expansion of the dimming chip 1.

[0057] Specifically, the difference between the coefficient of thermal expansion of substrate 7 and the coefficient of thermal expansion of dimming chip 1 is less than or equal to 1 ppm / ℃. For example, substrate 7 can be a glass substrate, which can be made of borosilicate glass (such as Schott Borofloat) with a thermal conductivity of 1.1 W / m•K. The difference between its coefficient of thermal expansion (CTE≈3.3 ppm / ℃) and that of the dimming chip 1 (CTE≈2.6 ppm / ℃) made of silicon material is less than 1 ppm / ℃, thus resulting in a higher degree of matching and effectively reducing thermal stress.

[0058] In contrast to the high high-frequency loss and severe crosstalk issues of organic substrates used in existing optoelectronic co-packaging structures, the substrate 7 provided in this application has a lower dielectric constant (typically 3.8) and a smaller loss tangent (typically tanδ=0.0002), which can significantly reduce dielectric loss and significantly improve electrical performance. In particular, it performs excellently in signal coupling and crosstalk control, resulting in a significant improvement in the transmission efficiency of radio frequency signals.

[0059] In one embodiment, the conductive structure provided in the substrate 7 can be a through hole 11 penetrating the first and second sides of the substrate 7. The substrate 7 can be made of glass, and the through hole 11 can specifically be a through glass via (TGV) 11, which can be used to realize electrical and thermal conduction between the electrical chip 9 and the PCB 4.

[0060] In one embodiment, the through-hole 11 is further filled with a conductive and thermally conductive element to form a conductive channel and a thermally conductive channel. Specifically, the conductive and thermally conductive element may be a copper-nickel composite layer.

[0061] In one embodiment, after the through hole 11 is filled with a conductive and thermally conductive element, electrochemical polishing can be performed to suppress the skin effect.

[0062] In one embodiment, an insulating layer is deposited between the inner wall of the through-hole 1 and the outer peripheral wall of the conductive and heat-conducting element to control the characteristic impedance. Specifically, the insulating layer may be a benzocyclobutene (BCB) insulating layer, which can control the characteristic impedance within 50Ω ± 5%.

[0063] Circuit board 4 is disposed on the first side of substrate 7. In one embodiment, the circuit layout on circuit board 4 is matched to the required number of interfaces of dimming chip 1, light-emitting chip 10, and electrical chip 9. Furthermore, some metal layers on circuit board 4 can also serve a heat dissipation function, helping to disperse heat from the components in the circuit and preventing overheating damage.

[0064] In one embodiment, circuit board 4 may specifically be a printed circuit board (PCB).

[0065] The light-emitting chip 10 is embedded and connected to the circuit board 4.

[0066] In one embodiment, the light-emitting chip 10 is embedded in the substrate 7 from a first side of the substrate 7, thereby being disposed on a different side of the substrate 7 from the electrical chip 9 and the dimming chip 1.

[0067] In one embodiment, the light-emitting chip 10 may be a laser, specifically a side-emitting laser, in which the laser is drilled with a thickness of 0.2 mm and embedded in the first side of the substrate 7.

[0068] In one embodiment, the light-emitting chip 10 is a high-power laser with a height of about 0.2 mm designed using a group III-V quaternary compound semiconductor material, and is decomposed into a single chip with a length of about 1.5 mm. When vertically packaged, the output waveguide of the laser and the input port of the dimming chip 1 are on the same side.

[0069] Electrical chip 9 and dimming chip 1 are disposed on the second side of substrate 7 and are electrically connected through redistribution layer 12. Specifically, electrical chip 9 is electrically and thermally connected to circuit board 4 through the conduction structure provided by substrate 7, and dimming chip 1 and light-emitting chip 10 are optically connected through optical waveguide 2.

[0070] In one embodiment, the electrical chip 9 is fixed to the second side of the substrate 7 using a microbump (μbump, micro bump) flip-chip process, achieving both mechanical fixation and electrical connection. Specifically, microbump technology is a technique used to achieve high-density, high-reliability electrical interconnections between chips and substrates, and is widely used in various advanced chip packaging technologies, such as 2.5D packaging and 3D packaging. In 2.5D packaging, μbumps are commonly used to connect the chip to the interposer; while in 3D packaging, they may be used to achieve stacked interconnections between chips. Microbumps include solder ball bumps or solder ball bumps, and the solder balls can be SnAg solder, etc.

[0071] In one embodiment, the electrical chip 9 is attached to a high thermal conductivity heat sink made of diamond or aluminum nitride (AlN) with a thermal conductivity greater than 170 W / m·K.

[0072] In one embodiment, the electrical chip 9 is specifically a driver chip for the dimming chip 1 and the light-emitting chip 10. In a specific implementation, the number of electrical chips 9 can be one or more. For example, the number of electrical chips used to drive the dimming chip 1 can be two (to control the DC signal and the radio frequency signal respectively), and the number of electrical chips used to drive the light-emitting chip 10 can be one, which is used to control the DC signal.

[0073] In one embodiment, the electrical chip 9 and the dimming chip 1 are flip-chip connected to the second side of the substrate 7 via a microbump flip-chip process, and are connected to the conductive structure in the substrate 7 accordingly.

[0074] The microbumps (μbump) can include solder balls (BGA) or solder balls.

[0075] In another embodiment, the circuit board 4 is connected to the first side of the substrate 7 via microbumps and is correspondingly connected to the conductive structure in the substrate 7.

[0076] In one embodiment, the dimming chip 1 may specifically include a modulation chip and a wavelength division multiplexing (WDM) chip. The input port of the modulation chip is optically connected to the light-emitting chip 10 via an optical waveguide, the input port of the WDM chip is connected to the output port of the modulation chip, and the output port of the WDM chip is optically coupled to the fiber optic array.

[0077] In one embodiment, combined with Figure 3 The top view of the optoelectronic co-packaging structure shown shows that the electrical chip 9 and the optical chip are spaced apart along the extension direction of the substrate 7.

[0078] In another embodiment, there may be multiple electrical chips 9, which are spaced apart along the extension direction of the substrate 7 and arranged around the dimming chip 1. The electrical chips 9 and the output light port of the dimming chip 1 are misaligned.

[0079] In one embodiment, the dimming chip 1 may be a push-pull modulator made of thin-film lithium niobate with a bandwidth of 67 GHz and an overall height of approximately 0.6 m.

[0080] In one embodiment, the optical waveguide 2 between the dimming chip 1 and the light-emitting chip 10 can specifically be a photonic wire bonding (PWB) waveguide. PWB technology utilizes high-precision manufacturing techniques such as two-photon lithography to directly print three-dimensional free-form waveguides between photonic chips or between a photonic chip and an optical fiber. These waveguides achieve adiabatic mode field transformation through gradual changes in their cross-sections, thereby enabling efficient transmission of optical signals.

[0081] In one specific embodiment, the PWB waveguide can adopt a tapered structure with a gradually changing cross-sectional size. The cross-section is perpendicular to the light transmission direction, and the taper of the tapered structure is greater than or equal to 5° and less than or equal to 15°. This effectively improves the coupling efficiency between the dimming chip 1 and the light-emitting chip 10 through PWB technology, effectively increasing the allowable lateral misalignment tolerance and longitudinal height difference, thereby improving the packaging yield.

[0082] In this embodiment, the optical connection between the dimming chip 1 and the light-emitting chip 10 does not use traditional lens coupling. Instead, it employs a PWB waveguide using two-photon 3D lithography. For example, an S-shaped polymer waveguide can be directly printed between the waveguide ports of the two dimming chips 1 and the light-emitting chip 10. The two ends of this waveguide are designed with tapered structures to match the Gaussian beam of the laser and the waveguide mode field of the modulator, achieving low-loss (<1dB / interface) and high-tolerance connection. Furthermore, it can be combined with laser direct writing (LDW) maskless process and an online monitoring system, which improves the packaging yield compared to traditional free-space optical interconnects.

[0083] The optoelectronic co-packaging structure provided in this application embodiment also includes a cooling component 5, wherein the cooling component 5 is disposed on the circuit board 4 and is used to dissipate heat for the light-emitting chip 10 and the electrical chip 9.

[0084] In one embodiment, the cooling element 5 can specifically be a thermoelectric cooler (TEC). A thermoelectric cooler is a device that utilizes the Peltier effect of semiconductor materials to achieve cooling or heating functions. By precisely controlling the current, a thermoelectric cooler can achieve very precise temperature control, typically reaching ±0.1℃ or even higher accuracy. In specific implementations, the structure and size of the thermoelectric cooler can be customized for easy integration.

[0085] In one embodiment, the cooling element 5 is disposed on the side of the circuit board 4 away from the substrate 7. Meanwhile, along the thickness direction of the substrate 7, a heat sink is disposed between the light-emitting chip 10 and the cooling element 5, so that the light-emitting chip 10 and the cooling element 5 are connected through the heat sink.

[0086] In one embodiment, the circuit board 4 also has mounting through holes, so that the light-emitting chip 10 is embedded in the mounting through holes.

[0087] In one embodiment, the light-emitting chip 10 includes a top electrode, a light-emitting layer, and a bottom electrode stacked along the thickness direction of the substrate, wherein the top electrode and the bottom electrode are electrically connected to a circuit board. In one embodiment, the bottom electrode of the light-emitting chip 10 abuts against a heat sink.

[0088] As can be seen, by opening through holes 11 at the corresponding positions on the circuit board 4, the electrical chip 9 can directly contact the cooling component 5 at the bottom through the through holes 11. When the cooling component 5 is a semiconductor cooler, the semiconductor cooler can adjust the current in real time through the temperature control circuit to ensure that the operating temperature of the electrical chip 9 is constant. In addition, the contact surface between the electrical chip 9 and the substrate 7 can also be coated with high thermal conductivity silver paste for auxiliary heat dissipation.

[0089] It should be noted that in this embodiment, the cooling element 5 is used as an example of a semiconductor cooler. The cooling element 5 can also be in other forms, such as a liquid cooling plate structure. Furthermore, this application does not limit the placement and shape of the cooling element 5. For example, the liquid cooling element 5 can be ring-shaped and surround the circuit board 4, or the liquid cooling element 5 can be plate-shaped and adaptively fit the side of the circuit board 4 opposite to the substrate 7.

[0090] In summary, the optoelectronic co-packaging structure provided in this embodiment can achieve electrical and thermal conductivity between the electrical chip 9 and the circuit board 4 through the through-through conductive structure in the substrate 7. The circuit board 4 is disposed on the first side of the substrate 7, and the light-emitting chip 10 is embedded and connected to the circuit board 4. The electrical chip 9 and the dimming chip 1 are flip-chip mounted on the second side of the substrate 7 through micro-bumps. The dimming chip 1 and the light-emitting chip 10 are connected through the light waveguide 2. The electrical connection between the electrical chip 9 and the dimming chip 1 is achieved through the redistribution layer 12 disposed on the surface of the substrate 7, realizing the lateral transmission of electrical signals between the electrical chip 9 and the dimming chip 1. Furthermore, the cooling component 5 is disposed on the circuit board to dissipate heat for the light-emitting chip 10 and the electrical chip 9.

[0091] As can be seen, the optoelectronic co-packaging structure provided in this embodiment, through the three-dimensional heterogeneous integration of the optical chip and the electrical chip, enables the heat generated by the light-emitting chip 10 to be dissipated in a timely manner, effectively improving the stability and reliability of the optoelectronic packaging structure. Furthermore, through the selection and arrangement of the substrate 7, the coupling loss of the optical interface is significantly reduced, the transmission distance of the optical-electrical interface is shortened, and the transmission loss of high-frequency signals during transmission is reduced. Signal crosstalk is also reduced. Thus, while solving the high-frequency signal integrity problem, the synergistic optimization of materials and structure significantly improves the stability and reliability of the optoelectronic co-packaging structure. This allows the optoelectronic co-packaging structure provided in this embodiment to systematically overcome the thermal management, high-frequency signal integrity, and optical interconnection problems existing in the prior art, ensuring that the optoelectronic co-packaging structure can work more effectively.

[0092] In one embodiment, the optoelectronic co-packaging structure provided in this application further includes an optical fiber array 3, wherein the optical fiber array 3 is optically coupled to the dimming chip 1.

[0093] In one embodiment, the fiber array 3 includes a plurality of spaced-apart optical fibers, and the number of optical fibers in the fiber array 3 is equal to the number of output waveguides of the dimming chip 1, and the spacing between adjacent optical fibers is equal to the spacing between the output waveguides of the dimming chip.

[0094] In one embodiment, the redistribution layer 12 includes multiple wiring layers stacked along the thickness direction of the substrate 7. A ground layer is disposed between adjacent wiring layers, and interconnect vias are disposed in the ground layer, connecting adjacent wiring layers. The routing direction of the top wiring layer is perpendicular to the routing direction of the bottom wiring layer. The routing direction of at least one intermediate wiring layer forms an angle of 45° with the routing directions of the top and / or bottom wiring layers.

[0095] In one embodiment, the thickness of each wiring layer in the redistribution layer 12 can be adjusted according to requirements and processes. For example, when the dimming chip 1 is a high-speed modulator, the layer thickness of the redistribution layer 12 can be set in the range of 3-5 μm.

[0096] In the specific implementation, the thickness of the redistribution layer 12 can be changed according to the actual situation (such as the bandwidth and size required by the packaged module). It should be noted that, as... Figure 1 The routing of redistribution layer 12 shown is only an example. In actual applications, the routing angle of the RDL can be optimized by modeling with high-frequency electromagnetic simulation software. For example, a 45° angled routing layout can be used to avoid crosstalk and interference between adjacent signals, and tightly coupled differential pairs can be used for critical signals to suppress common-mode noise.

[0097] In one embodiment, the cooling element 5 and the substrate 7 are further connected by a thin-film circuit formed from high thermal conductivity silver paste or diamond / aluminum nitride heat sink materials. Specifically, the thin-film circuit can be a substrate made of diamond or aluminum nitride materials, with a thickness reduced to 0.2 mm, and its surface plated with gold for fabrication. The thermal conductivity of diamond and aluminum nitride substrates can reach 2000~2600 W / m•K and 170~320 W / m•K, respectively. In specific applications, appropriate materials can be selected to fabricate the substrate according to the application scenario.

[0098] This application also provides an optical emitting module, including at least one optoelectronic co-packaging structure, wherein the optoelectronic co-packaging structure may be provided by any of the foregoing embodiments of this application.

[0099] Figures 4-7 This is a schematic diagram of the packaging process for the optoelectronic co-packaging structure provided in this application, as shown below. Figures 4-7 The packaging process of the optoelectronic co-packaging structure provided in this application includes:

[0100] like Figure 4 , Figure 5 and Figure 6 As shown, the electrical chip 9 and the dimming chip 1 are mounted on the second side of the substrate 7 via microbumps 8 formed by a microbump flip-chip process. On the first side of the substrate 7, they are directly bonded to the pads of the circuit board 4 via solder balls 6 (such as SnAg solder) or copper pillar bumps.

[0101] like Figure 7As shown, a substrate 7 with an appropriate coefficient of thermal expansion is selected, and a conductive structure penetrating the first and second sides is fabricated in the substrate 7. Conductive and thermally conductive elements are filled into the through-holes, and an insulating layer is provided between the inner wall of the through-hole and the outer peripheral wall of the conductive and thermally conductive elements. A circuit board 4 is mounted on the first side of the substrate 7. The circuit board 4 is connected to the conductive structure in the substrate via micro-bumps, and mounting through-holes are formed on the circuit board 4. A light-emitting chip 10 is embedded in the mounting through-holes of the circuit board, and an optical waveguide is fabricated between the dimming chip 1 and the light-emitting chip 10 using photonic wire bonding. An optical fiber array optically coupled to the dimming chip 1 is installed. A cooling element 5 is installed on the side of the circuit board 4 facing away from the substrate, and a heat sink is placed between the light-emitting chip 10 and the cooling element 5. Finally, through the above process, the optoelectronic co-packaging structure is completed.

[0102] Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the optical emitting module provided in this application, as shown below. Figure 8 The light emitting module shown may include the optoelectronic co-packaging structure provided in any of the foregoing embodiments of this application.

[0103] Specifically, such as Figure 8 The optical emission module shown includes a multi-channel laser, a modulator, and an amplifier, all of which are connected to a wavelength division multiplexer.

[0104] In one embodiment, this application also provides an optical module. Figure 9 This is a schematic diagram of the structure of an embodiment of the optical module provided in this application, as shown below. Figure 9 The optical module shown includes, for example: Figure 8 The light emitting module shown.

[0105] In one embodiment, such as Figure 9 The optical module shown also includes an optical receiving module.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A photoelectric co-packaging structure, characterized in that, include: A substrate has a first side and a second side opposite to each other along the thickness direction, and a conductive structure is provided in the substrate that penetrates the first side and the second side. A redistribution layer is provided on the second side of the substrate. A circuit board is disposed on the first side of the substrate; A light-emitting chip is embedded and connected to the circuit board; An electrical chip and a dimming chip are disposed on the second side of the substrate and electrically connected through the redistribution layer. The electrical chip is electrically and thermally connected to the circuit board through the conductive structure. The dimming chip and the light-emitting chip are optically connected through an optical waveguide. A cooling component, disposed on the circuit board, is used to dissipate heat from the light-emitting chip and the electrical chip.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that, The conductive structure is a through hole penetrating the first side and the second side of the substrate. The through hole is filled with a conductive and thermally conductive component, which is used for electrical and thermal conduction between the electrical chip and the circuit board.

3. The optoelectronic co-packaging structure according to claim 2, characterized in that, An insulating layer is provided between the inner wall of the through hole and the outer peripheral wall of the conductive and heat-conducting component.

4. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, It also includes an optical fiber array, which is optically coupled to the dimming chip; The fiber array includes multiple spaced fibers, the number of which is equal to the number of output waveguides of the dimming chip, and the spacing between adjacent fibers is equal to the spacing between the output waveguides of the dimming chip.

5. The optoelectronic co-packaging structure according to claim 4, characterized in that, The dimming chip includes: An optical modulation chip, wherein the light inlet of the optical modulation chip is optically connected to the light-emitting chip through the optical waveguide; A wavelength division multiplexing (WDM) chip, wherein the input optical port of the WDM chip is connected to the output optical port of the optical modulation chip, and the output optical port of the WDM chip is optically coupled to the fiber array.

6. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The electrical chip and the optical chip are spaced apart along the extending direction of the substrate; And / or, there are multiple electrical chips, and the multiple electrical chips are spaced apart along the extension direction of the substrate in the circumferential direction of the dimming chip, and the electrical chips are misaligned with the output optical port of the dimming chip.

7. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The difference between the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the dimming chip is less than or equal to 1 ppm / ℃; and / or, the substrate comprises a glass substrate.

8. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The circuit board has mounting through holes, and the light-emitting chip is embedded in the mounting through holes.

9. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The cooling component is disposed on the side of the circuit board opposite to the substrate; Along the thickness direction of the substrate, a heat sink is disposed between the light-emitting chip and the cooling component, and they are connected through the heat sink.

10. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The electrical chip and the dimming chip are flip-chip connected to the second side of the substrate via microbumps and are correspondingly connected to the conductive structure. And / or, the circuit board is connected to the first side of the substrate via microbumps and is correspondingly connected to the conductive structure.

11. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The redistribution layer includes multiple wiring layers, which are stacked along the thickness direction of the substrate. A ground layer is provided between two adjacent wiring layers, and interconnect vias are provided in the ground layer to connect two adjacent wiring layers. The routing direction of the top wiring layer is perpendicular to the routing direction of the bottom wiring layer; The routing direction of at least one of the middle routing layers forms an angle of 45° with the routing direction of the top routing layer and / or the routing direction of the bottom routing layer.

12. The optoelectronic co-packaging structure according to any one of claims 1-3, characterized in that, The optical waveguide has a tapered structure with a gradually changing cross-sectional size, and the taper of the tapered structure is greater than or equal to 5° and less than or equal to 15°. Wherein, the cross section is the cross section of the optical waveguide perpendicular to the direction of light transmission.

13. A light emitting module, characterized in that, The optoelectronic co-packaging structure includes any one of claims 1-12.

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