Pre-reading method and device applied to random reading, equipment and storage medium
By using a state transition model in the storage system to predict the next access address of a random read request, the problem of high random read latency in existing technologies is solved, achieving more efficient data prefetching and cache hit rate, and improving the real-time performance and overall system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-03-31
AI Technical Summary
Existing storage systems lack the assumption of address contiguity during random read requests, causing the read-ahead mechanism to fail, increasing response latency, and failing to effectively improve the real-time performance of random reads.
A state transition model is used to predict the next access address of a random read request. By constructing and updating the transition matrix of historical access sequences, the target address difference with the highest transition probability is selected for pre-reading, and the data is cached for subsequent matching.
It significantly improves cache hit rate in random read scenarios, reduces media response latency, and enhances the real-time performance of data reading and system performance.
Smart Images
Figure CN121764409A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of data reading, and in particular to a pre-reading method, apparatus, device and storage medium for random reading. Background Technology
[0002] In storage systems, host data access patterns are mainly divided into two categories: sequential read and random read. Sequential read refers to the host initiating read requests continuously or nearly continuously according to logical block addresses (LBAs), exhibiting a high degree of spatial locality. Random read, on the other hand, is characterized by irregular LBA jumps, discrete access locations, and large intervals, lacking obvious continuous characteristics. With the popularization of applications such as smart terminals, edge computing, and real-time data processing, the real-time requirements for storage I / O response are becoming increasingly stringent. Especially in embedded devices, low-latency and high-efficiency data reading capabilities directly determine the overall user experience and the upper limit of system performance.
[0003] To improve read real-time performance, existing storage firmware commonly employs a prefetching mechanism. In sequential read scenarios, this mechanism monitors the trend of the current LBA sequence, predicts the range of addresses that may be accessed subsequently, and loads the corresponding data into the cache in advance. Because sequential access is highly predictable, this prefetching strategy can significantly improve cache hit rate, effectively hide media access latency, and thus ensure real-time response of read operations.
[0004] However, when faced with random reads, existing read-ahead methods fail due to their reliance on the assumption of address continuity. This is because the system cannot determine the next access location, so the read-ahead function is usually turned off. As a result, each random read request must go through the entire process of command parsing, medium addressing, and data transmission, which significantly increases the response latency. Summary of the Invention
[0005] To overcome the shortcomings of the prior art, this application provides a pre-reading method, apparatus, device and storage medium for random reads, which can realize data pre-reading for random read access modes, thereby improving the real-time performance of random reads.
[0006] The technical solution adopted by this application to solve its technical problem is: In a first aspect, this application provides a pre-read method for random reading, the method comprising: In response to the completion of the current random read request, obtain the current logical block address corresponding to the current random read request, and check whether there are any pending host commands; If the host command to be processed does not exist, the system enters the pre-read mode. In the pre-read mode, the current logical block address is input to the state transition model pre-deployed in the target firmware. The state transition model selects the target address difference that has the highest transition probability with the current logical block address. The pre-read logical block address is determined based on the target address difference and the current logical block address, and the pre-read data corresponding to the pre-read logical block address is cached. In response to the next random read request, the pre-read logical block address is matched with the target logical block address corresponding to the next random read request. If the match is successful, the pre-read data is output; otherwise, the data corresponding to the target logical block address is read and output.
[0007] Optionally, before the step of inputting the current logical block address into the pre-deployed state transition model in the target firmware, the method further includes: Obtain historical access sequences; the historical access sequences include multiple logical block transfer entries constructed based on logical block access timing, and each logical block transfer entry includes a source logical block address and a corresponding logical block address difference; The transfer terms of each logic block are preprocessed to obtain a transfer sample sequence; Based on the transfer sample sequence, the number of transfers for each source logical block address under the difference between the logical block addresses is counted, and the transfer probability corresponding to each source logical block address is calculated based on the number of transfers. An initial transition matrix is constructed using the address of each source logical block as the row index and the difference between the addresses of each logical block as the column index; each element of the initial transition matrix represents the transition probability from the source logical block address corresponding to the row index via the logical block address difference indicated by the column index; Based on the initial transition matrix, the target firmware is modeled and deployed to form the state transition model.
[0008] Optionally, the step of preprocessing the historical access sequence to obtain the transfer sample sequence includes: Determine whether the occurrence frequency of each logical block transfer item is lower than a preset frequency threshold, and determine whether the logical block address difference corresponding to each logical block transfer item exceeds a preset difference range; Remove all logical block transfer entries in the historical access sequence that occur at frequencies lower than the preset frequency threshold and / or exceed the preset difference range to obtain the transfer sample sequence.
[0009] Optionally, the step of deploying the target firmware model based on the initial transition matrix to form the state transition model includes: The initial transition matrix is subjected to sparse compression and dimensionality reduction to obtain a lightweight transition matrix; The lightweight transition matrix is loaded into the target firmware, and the state transition model is deployed through the lightweight transition matrix.
[0010] Optionally, after the step of matching the pre-read logical block address with the target logical block address corresponding to the next random read request, the method further includes: Based on the current logical block address and the logical address difference between the current logical block address and the target logical block address, a transfer item to be updated is constructed; The transition item to be updated is applied to the lightweight transition matrix in the target firmware to update the transition probability of the entry in the lightweight transition matrix corresponding to the current logical block address and the logical address difference, so as to update the state transition model.
[0011] Optionally, after the step of entering the pre-read mode, the method further includes: In response to a preset trigger condition, the transfer probability corresponding to each source logic block address in the lightweight transfer matrix of the target firmware is traversed. Remove matrix elements corresponding to transition probabilities less than a preset probability threshold to update the state transition model.
[0012] Optionally, the step of selecting the target address difference with the current logical block address that has the highest transition probability through the state transition model includes: Locate the target row index corresponding to the current logical block address in the state transition model; Iterate through the logical block address differences corresponding to each column index in the target row index, and filter to obtain the target column index with the highest transfer probability; The difference in logical block addresses corresponding to the target column index is used as the target address difference.
[0013] The working principle of this application is as follows: During the idle window period when the current random read request is completed and there are no other host commands to be processed, the system takes the current logical block address as input and sends it to the state transition model pre-deployed in the firmware. This model uses statistical learning to associate multiple possible next access offsets (i.e., target address differences) for each logical block address and assigns corresponding transition probabilities. The system selects the target address difference with the highest probability, combines it with the current address to calculate the pre-read logical block address most likely to be accessed subsequently, and loads the corresponding data into the cache in advance. When the next random read request arrives, if its target address happens to match the pre-read address, the data can be directly output from the cache, avoiding further access to the physical medium.
[0014] The beneficial effect of this application is that it no longer treats random reads as completely unpredictable noise, but instead captures the LBA transition patterns implicit in historical accesses through a state transition model. Even if the access sequence appears discrete and disordered on the surface, as long as certain recurring transition patterns exist in long-term operation, the model can quantify them into a probability distribution and trigger targeted pre-reads at appropriate times.
[0015] Based on this, by continuously reflecting potential patterns based on actual access behavior, effective prediction can be achieved under a wider range of random read loads, significantly improving the cache hit rate in random read scenarios, reducing latency caused by waiting for media response, and thus enhancing the real-time performance of the overall read operation. Attached Figure Description
[0016] Figure 1 This is a flowchart illustrating a pre-read method for random reading provided in an embodiment of this application; Figure 2 This is a schematic diagram of a virtual structure of a read-ahead device for random reading provided in this application; Figure 3 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0017] The present application will be further described below with reference to the accompanying drawings and embodiments.
[0018] The following will clearly and completely describe the concept, specific structure, and resulting technical effects of this application in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this application can be combined interactively without contradicting each other.
[0019] In storage systems, host access to storage devices typically falls into two basic modes: sequential read and random read. Sequential read refers to the access of logical block addresses (LBAs) in a continuous or near-continuous manner, exhibiting high predictability. Random read, on the other hand, is characterized by unpredictable LBA access patterns and strong jumps, making it difficult to predict using simple linear extrapolation. With the increasing demands for response speed in embedded systems, mobile terminals, and edge computing devices, real-time data reading has become a key indicator for measuring storage performance. This is especially true in typical application scenarios such as database queries, small file loading, and log reading, where random read operations dominate, and their latency directly impacts the overall system experience.
[0020] To improve read real-time performance, existing storage firmware commonly employs a prefetching mechanism. This mechanism, upon detecting a sequential read pattern, proactively loads the data corresponding to several subsequent LBAs into the cache in advance, thus achieving "hit-and-go" response when subsequent requests arrive, significantly reducing effective access latency. This type of prefetching strategy relies on the assumptions of locality and continuity of address access, and is highly effective in sequential read scenarios, having been widely integrated into various Solid State Drive (SSD) controllers. However, when facing random reads, due to the lack of stable address change patterns, traditional prefetching algorithms cannot effectively identify potential access trends, typically opting to disable prefetching or operate with only a highly conservative strategy, resulting in underutilization of cache resources.
[0021] This limitation directly leads to incomplete test paths: the existing pre-read mechanism only covers sequential or quasi-sequential LBA transfer paths, completely ignoring the numerous random LBA jump paths that exist in actual loads, which, although not continuous, have statistical correlations. Because there is no ability to model historical random access behavior, the system cannot identify recurring but non-adjacent LBA transfer patterns, resulting in a large number of predictable and pre-loadable data paths not being included in the testing and optimization scope. Consequently, in high-frequency random read scenarios, the storage device remains in a passive response state, unable to proactively improve data readiness, severely restricting further improvements in the real-time performance of random reads.
[0022] To address the aforementioned technical shortcomings of random read operations, refer to Figure 1 , Figure 1 This is a flowchart illustrating the pre-read method for random reads provided in an embodiment of this application. Figure 1 The diagram illustrates several key steps involved in the random read pre-read method based on historical patterns provided in this application, which are explained in detail below: In step S1, in response to the completion of the current random read request, the current logical block address corresponding to the current random read request is obtained, and it is detected whether there is a host command to be processed.
[0023] The Logical Block Address (LBA) is a linear address abstraction used in storage devices to identify the physical location of data. The host initiates read and write requests to the storage device through the LBA. Pending host commands refer to I / O instructions sent by the host but not yet executed by the storage device firmware, including read, write, or other control commands.
[0024] Specifically, after a random read operation is completed, the system first captures the LBA accessed by the request, i.e., the current logical block address, as the starting point for subsequent pre-read decisions. Immediately afterwards, the system checks the command queue for other pending host commands. If pending commands exist, it indicates that the host is about to initiate a new I / O operation; in this case, pre-read should not be initiated to avoid consuming bandwidth and cache resources and interfering with high-priority real-time requests. Conversely, if the command queue is empty, it indicates that the host has no new requests in the short term, the system is in an idle window, and it has the opportunity and resource conditions to perform pre-read operations.
[0025] More specifically, by identifying idle gaps available for pre-reading and triggering pre-reading, the resource contention and performance interference caused by blind pre-reading during active host interaction are reduced, so that pre-reading only occurs when the host is truly idle. This creates conditions for improving the random read hit rate without sacrificing real-time responsiveness.
[0026] In one specific embodiment, when a user quickly swipes to browse photos on a mobile device, each swipe triggers a random read request, and the accessed LBAs may be scattered and without a clear order. When a photo data read is completed (e.g., LBA1024), the firmware immediately checks the command queue and finds that the host has not yet issued a read command for the next photo (i.e., there are no pending host commands), thus determining that it enters pre-read mode. At this time, the system uses LBA 1024 as the current logical block address and prepares to call the state transition model to predict the next LBA that may be accessed. Since pre-reading is only triggered in such idle intervals, it neither blocks user operations nor fails to utilize previously idle bus and cache bandwidth, thereby loading data in advance for possible next random reads without affecting the smoothness of interaction, significantly improving the continuity of the user experience.
[0027] In step S2, if the host command to be processed does not exist, the system enters the pre-read mode. In the pre-read mode, the current logical block address is input to the state transition model pre-deployed in the target firmware, and the target address difference with the highest transition probability with the current logical block address is selected through the state transition model.
[0028] The state transition model is a probabilistic prediction model built based on historical access behavior, used to characterize the probability distribution of transitions from one logical block address to another. In the state transition model, address transitions are represented as "address differences," that is, the address difference between the target LBA address and the source LBA address. The target address difference refers to the LBA address difference with the highest transition probability calculated by the model under the current LBA conditions.
[0029] Specifically, once the system confirms that there are no pending host commands, it determines that it is currently in an idle state where pre-reading is possible and then enters pre-reading mode. In this mode, the system takes the current logical block address that has just been accessed as input and sends it to the state transition model pre-deployed in the target firmware. The state transition model finds the address difference with the highest transition probability based on the current logical block address, which is the target address difference.
[0030] It is worth noting that, in order to prevent the model from becoming bloated or distorted due to the accumulation of low-value data, this application proposes a method for managing the scale and complexity of the state transition model during long-term operation. Specifically, after the step of entering the pre-read mode, the method further includes: In response to a preset trigger condition, the transfer probabilities corresponding to the addresses of each source logic block in the lightweight transfer matrix of the target firmware are traversed.
[0031] Among them, the preset trigger conditions refer to the criteria for determining the timing of the start model cleanup operation that are pre-set during the firmware operation, such as the system idle time reaching a certain threshold, the device running for 24 hours, or a certain number of I / O requests being completed.
[0032] Furthermore, matrix elements corresponding to transition probabilities less than a preset probability threshold are removed to update the state transition model.
[0033] The preset probability threshold is a small positive number used to define which transition probabilities are considered low-frequency or invalid jumps. Matrix elements refer to the specific transition probability values stored in the lightweight transition matrix, and their positions are determined by the difference between the source logic block address and the corresponding logic block address.
[0034] Specifically, after entering read-ahead mode, the read-ahead mode is activated. When a preset trigger condition is met, periodic maintenance of the state transition model is initiated. The preset trigger condition is that there are currently no host I / O requests being processed, the host command queue is empty, and the host is in a waiting state where it can perform background operations but does not need to respond to external requests. At this time, the firmware traverses all recorded source logical block addresses in the lightweight transition matrix and checks whether the corresponding transition probability of each source address and the corresponding logical block address difference is less than a preset probability threshold. For all matrix elements below this threshold, the system removes them from the model, i.e., clears them or deletes their records from the sparse storage structure.
[0035] More specifically, this process essentially eliminates long-term unverified or infrequently occurring jump paths, preventing the matrix elements from growing indefinitely due to continuous online updates and exceeding firmware memory limits. Simultaneously, removing low-probability terms increases the relative significance of high-probability paths, allowing subsequent pre-read decisions to focus more on truly high-frequency access patterns, indirectly improving prediction accuracy. Furthermore, regular cleanup prevents historical noise or temporary abnormal behavior from causing long-term interference with the model, ensuring its stability and representativeness.
[0036] Furthermore, before inputting the current logical block address into the state transition model, the model needs to be constructed and deployed first. This application embodiment proposes that, before the step of inputting the current logical block address into the pre-deployed state transition model in the target firmware, the method further includes: Get the historical access sequence.
[0037] Among them, the historical access sequence refers to a series of logical block address access events that occur in chronological order during the operation of the storage device. The logical block transfer item is the basic statistical unit extracted from the sequence, which consists of a source logical block address and the logical block address difference corresponding to its subsequent access.
[0038] Specifically, the system collects historical access sequences from the actual operating environment, extracts adjacent LBAs one by one according to the access time sequence, and forms multiple logical block transfer entries. Each transfer entry contains a source logical block address and the logical block address difference from the source logical block address to the next address.
[0039] Furthermore, the transfer terms of each logic block are preprocessed to obtain a transfer sample sequence.
[0040] Specifically, all transfer items are preprocessed to remove noisy data with excessively low frequency or abnormal address differences, resulting in a high-quality transfer sample sequence. Furthermore, this embodiment of the application proposes that the step of preprocessing the historical access sequence to obtain the transfer sample sequence includes: Determine whether the occurrence frequency of each logical block transfer item is lower than a preset frequency threshold, and determine whether the logical block address difference corresponding to each logical block transfer item exceeds a preset difference range; The preset frequency threshold refers to the minimum number of occurrences set before model training, used to filter out accidental or noisy address jump behaviors. The preset difference range refers to the valid range of allowed logical block address differences, which is usually predetermined based on the typical access span of the storage device or the characteristics of the application scenario.
[0041] Further, all logical block transition items in the historical access sequence that appear less than the preset frequency threshold and / or exceed the preset difference range are removed to obtain the transition sample sequence.
[0042] Specifically, after extracting the original logical block transfer entries from the historical access sequence, the system performs two independent but jointly judged filtering conditions on each entry: First, it counts the frequency of each logical block transfer entry in the entire historical sequence. If the frequency is lower than a preset frequency threshold, it is regarded as an accidental event or measurement noise and is removed. Second, it checks whether the logical block address difference contained in the transfer entry falls within a preset difference range. If it exceeds the range (for example, the difference is too large, far exceeding the normal jump range of the application), it is judged as an abnormal jump or system interference behavior and is also removed.
[0043] More specifically, the two conditions mentioned above are combined using an "AND / OR" logic, meaning that if either removal condition is met, the transfer item is removed. After this cleaning process, the remaining transfer items constitute a high-quality transfer sample sequence, possessing sufficient repeatability to reflect real access patterns while eliminating interference from extreme or invalid jumps. Frequency filtering avoids misjudging one-off, atypical random jumps as regular behavior; difference range limitation prevents unreasonable large-span jumps introduced by system anomalies, firmware errors, or test interference from polluting the probability statistics. The combination of these two methods ensures that the model only learns real, stable address transfer paths that conform to the characteristics of the application scenario.
[0044] In one specific embodiment, the main control system periodically reads several fixed configuration blocks (such as LBA 200, 300, 400) and occasionally triggered log areas (such as LBA 10000). The historical access sequence may contain a large number of high-frequency transition items such as (200, +100) and (300, +100), but also some individual transitions such as (200, +9800), which only occur due to a single abnormal log read. Without filtering, this low-frequency, large-difference item would be included in the model, causing an incorrect allocation of probability to +9800 when starting from LBA 200, diluting the probability weight of the truly high-frequency path +100. By setting a preset frequency threshold of 3 times and a preset difference range of [-500, +500], the system removes (200, +9800) because its frequency is below the threshold and its difference exceeds the range, retaining only valid items such as (200, +100). The final constructed transition sample sequence accurately reflects the actual access habits of the device, enabling the state transition model to predict the next configuration block address with a high probability during runtime, thereby achieving efficient pre-reading.
[0045] Furthermore, based on the transfer sample sequence, the number of transfers for each source logical block address under the difference between the logical block addresses is counted, and the transfer probability corresponding to each source logical block address is calculated based on the number of transfers.
[0046] An initial transition matrix is constructed using the address of each source logical block as the row index and the difference between the addresses of each logical block as the column index. Each element of the initial transition matrix represents the transition probability of moving from the source logical block address corresponding to the row index via the logical block address difference indicated by the column index.
[0047] The initial transition matrix is a two-dimensional probability table constructed with the source logical block address as the row index and the logical block address difference as the column index. It is used to quantify the probability of different address jump behaviors occurring.
[0048] Specifically, based on the transfer sample sequence, the number of transfers for each source logical block address under various logical block address differences is counted, and the number of transfers is normalized to a transfer probability. On this basis, an initial transfer matrix is constructed with all observed source logical block addresses as rows and all occurrences of logical block address differences as columns, where each element represents the probability of a transfer occurring from a source address via a specific address difference.
[0049] Furthermore, the target firmware is modeled and deployed based on the initial transition matrix to form the state transition model.
[0050] Specifically, the initial transition matrix is compressed and optimized before being loaded into the target firmware to form a state transition model that can be invoked at runtime. In this embodiment, the step of deploying the model to the target firmware based on the initial transition matrix to form the state transition model further discloses the following steps: The initial transition matrix is subjected to sparse compression and dimensionality reduction to obtain a lightweight transition matrix.
[0051] Sparse compression refers to utilizing the scarcity of non-zero elements in a matrix, employing storage methods such as Coordinate Format (COO) and Compressed Sparse Rows (CSR) to preserve only the valid data and its location information, thereby reducing storage usage. Dimensionality reduction refers to further reducing the matrix size by merging nearby addresses, clustering similar rows, or truncating low-contribution dimensions.
[0052] Furthermore, the lightweight transition matrix is loaded into the target firmware, and the state transition model is deployed through the lightweight transition matrix.
[0053] Specifically, after the initial transition matrix is constructed, its original form often contains a large number of LBA rows and a wide range of address difference columns. Directly deploying it to the firmware of a resource-constrained storage device will face problems such as excessive memory consumption and low table lookup efficiency.
[0054] Therefore, the matrix needs to be optimized first: First, sparse compression is performed to remove all elements with zero probability or below a very small threshold, retaining only non-zero transition probability terms with actual predictive value, and recording their row and column positions and values using an efficient encoding method; then, dimensionality reduction is performed, for example, mapping adjacent or semantically similar source logic block addresses to the same representative address, or bucketing and aggregating address differences, thereby significantly reducing the matrix dimension within an acceptable range of accuracy loss. The resulting lightweight transition matrix is small in size and compact in structure, and can be fully loaded into the limited memory space of the target firmware, and directly called as a runtime state transition model.
[0055] After completing the deployment of the state transition model, this application embodiment, based on the above model matrix architecture, further proposes the following step: selecting the target address difference with the current logical block address that has the highest transition probability through the state transition model, including: Locate the target row index corresponding to the current logical block address in the state transition model; Iterate through the logical block address differences corresponding to each column index in the target row index, and filter to obtain the target column index with the highest transfer probability; The difference in logical block addresses corresponding to the target column index is used as the target address difference.
[0056] Specifically, when it is necessary to select the most likely next-hop address from the state transition model, the system first finds the corresponding target row index in the model based on the current logical block address. This row index records the historical probability distribution of transitions from the current logical block address to the differences between various possible logical block addresses.
[0057] Subsequently, the system iterates through all valid column indices in the row index (i.e., all address differences that have occurred during transfers), compares the transfer probability values stored in each column, and selects the column position with the highest probability, which is the target column index. Finally, the logical block address difference mapped to this target column index is extracted and used as the target address difference for this pre-read decision.
[0058] In one specific embodiment, the user frequently switches between the health data page (LBA 4000) and the settings menu (LBA 6200), forming a stable transition pattern. In the state transition model, under the row index corresponding to LBA 4000, the transition probability for the address difference +2200 is 0.75, which is much higher than other differences (such as +100 probability 0.1, -500 probability 0.05). When a read of LBA4000 is completed and there are no pending commands, the system locates that row, traverses all columns, and determines that the column containing +2200 is the highest probability item, using it as the target address difference.
[0059] In step S3, the pre-read logical block address is determined based on the target address difference and the current logical block address, and the pre-read data corresponding to the pre-read logical block address is cached.
[0060] Caching refers to temporarily storing pre-read data in a high-speed buffer (such as SRAM or DRAM) that the firmware can quickly access, so that it can be returned directly when a subsequent request is hit, avoiding access to the slower NAND flash memory.
[0061] Specifically, after obtaining the target address difference and the current logical block address, the system adds the two together to obtain the pre-read logical block address, i.e.: pre-read logical block address = current logical block address + target address difference. Subsequently, the system initiates a data read operation on the storage medium for the pre-read logical block address and stores the read data in the firmware-managed cache area.
[0062] In one specific embodiment, in a smart in-vehicle navigation device, users frequently switch between the main interface and the detailed route page, causing LBA access to jump between two fixed areas, for example, from LBA 5000 (main interface data) to LBA 8200 (route details), with an address difference of +3200. When a read of LBA 5000 is completed and the command queue is empty, the system calculates the pre-read logic block address as 5000 + 3200 = 8200 based on the target address difference of +3200 output by the state transition model, and immediately reads the data block corresponding to LBA 8200 from the NAND flash memory and stores it in the cache.
[0063] In step S4, in response to the initiation of the next random read request, the pre-read logical block address is matched with the target logical block address corresponding to the next random read request. If the match is successful, the pre-read data is output; otherwise, the data corresponding to the target logical block address is read and output.
[0064] Specifically, when the host initiates the next random read request, the system first parses the target logical block address contained in the request and immediately compares it with the pre-read logical block address determined and cached in the previous pre-read phase. If the two are exactly the same, it is determined that the "match is successful", and the system directly retrieves the corresponding pre-read data from the cache and returns it as a response to the host. The entire process does not require access to the underlying storage medium. If the two are inconsistent, it means that the pre-read has missed, and the system switches to the regular read process, that is, reads the required data from physical storage units such as NAND flash memory according to the target logical block address and outputs the data to the host. At the same time, the previously cached pre-read data is usually discarded or overwritten.
[0065] More specifically, in the case of a successful match, full physical I / O latency is avoided, significantly shortening the response time of random read requests; in the case of a failed match, the system can still fall back to the standard read path, ensuring that functional correctness is not affected. This design, which accelerates performance when a match occurs and leaves no loss when a match occurs, effectively improves the average performance in random read scenarios without increasing the complexity of the host protocol, while maintaining the robustness and compatibility of the system.
[0066] In one specific embodiment, in a mobile payment terminal device, after a user completes a transaction, the system often needs to randomly read the transaction log (LBA 7000) and the user credential (LBA 9500). There is no sequential relationship between the two, but the access pattern is repetitive. Assuming the previous operation just finished reading LBA 7000 and the command queue is empty, the system predicts the next address difference to be +2500 based on a state transition model, thus pre-reading data from LBA 9500 and caching it. When the user immediately initiates a new transaction, and the host issues a random read request for LBA 9500, the firmware detects that the target logical block address (9500) is completely consistent with the pre-read logical block address (9500), and immediately outputs the pre-read data from the cache, significantly reducing the response time.
[0067] Furthermore, to enable the dynamic evolution of the state transition model during runtime and endow it with online learning capabilities, this application also proposes an online learning method. That is, after the step of matching the pre-read logical block address with the target logical block address corresponding to the next random read request, the method further includes: Based on the current logical block address and the logical address difference between the current logical block address and the target logical block address, a transfer item to be updated is constructed.
[0068] The logical address difference refers to the numerical difference between the target logical block address and the current logical block address of the next random read request during actual I / O, i.e.: Logical address difference = Target logical block address - Current logical block address. The transfer item to be updated is a tuple consisting of the current logical block address and the logical address difference, used to reflect an actual address jump.
[0069] Furthermore, the transition item to be updated is applied to the lightweight transition matrix in the target firmware to update the transition probability of the entry in the lightweight transition matrix corresponding to the current logical block address and the logical address difference, so as to update the state transition model.
[0070] Specifically, after determining whether a pre-read hit has occurred, the system updates the model based on the actual access behavior, regardless of whether the match is successful. Specifically, it first calculates the logical address difference between the current logical block address and the target logical block address actually requested by the host, and then constructs a transfer item to be updated based on this difference.
[0071] Subsequently, this transition term is used to locate the corresponding entry in the lightweight transition matrix, specifically the position with the current logical block address as the row and the logical address difference as the column. The system incrementally updates the transition probability stored at this location, for example, through weighted averaging, counting accumulation, and then normalization, to make the probability value of this jump path closer to the latest observation results. This process enables the model to dynamically evolve during runtime, allowing it to continuously adapt to changes in host access patterns.
[0072] In one specific embodiment, users initially primarily access LBA 3000 (device status page) and LBA 5000 (control panel), and the model has learned that an address difference of +2000 has a high probability. However, as users add automation scenarios, they begin to frequently jump from LBA 3000 to LBA 7000 (automation configuration page), and the logical address difference becomes +4000. After a read of LBA 3000 is completed, the system pre-reads LBA 5000 (based on the old model), but the next request actually accesses LBA 7000, resulting in a matching failure. At this point, the system calculates the logical address difference to be +4000, constructs a transition term to be updated (3000, +4000), finds the corresponding entry in the lightweight transition matrix, and increases its transition probability from near 0 to an observable value. After multiple similar accesses, the transition probability of +4000 gradually exceeds that of +2000, and the model automatically adapts to the new behavior.
[0073] Reference Figure 2 , Figure 2 This is a virtual structural diagram of a read-ahead device for random reading provided in this application. A second aspect of this application provides a read-ahead device for random reading, comprising: The pre-read trigger judgment module 100 is used to obtain the current logical block address corresponding to the current random read request and detect whether there is a host command to be processed in response to the completion of the current random read request. The pre-read address acquisition module 200 is used to enter the pre-read mode if the host command to be processed does not exist. In the pre-read mode, the current logical block address is input to the state transition model pre-deployed in the target firmware, and the target address difference with the current logical block address with the highest transition probability is selected through the state transition model. The pre-read data reading module 300 is used to determine the pre-read logical block address based on the target address difference and the current logical block address, and to cache the pre-read data corresponding to the pre-read logical block address; The instruction matching output module 400 is used to respond to the next random read request by matching the pre-read logical block address with the target logical block address corresponding to the next random read request. If the match is successful, the pre-read data is output; otherwise, the data corresponding to the target logical block address is read and output.
[0074] The pre-read device for random reading described in this application embodiment can execute the pre-read method for random reading provided in the above embodiments. The pre-read device for random reading has the corresponding functional steps and beneficial effects of the pre-read method for random reading described in the above embodiments. For details, please refer to the embodiments of the pre-read method for random reading described above. The embodiments of this application will not be repeated here.
[0075] This application also provides an electronic device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include a processor and a memory, which can be connected via a bus or other means. The processor may be a Central Processing Unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips. The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the pre-read method applied to random reads in the embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the pre-read method applied to random reads in the above method embodiments.
[0076] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. One or more modules are stored in the memory and, when executed by the processor, perform the pre-read method for random reads as described in the above method embodiments. Specific details of the above electronic device can be understood by referring to the corresponding descriptions and effects in the above method embodiments, and will not be repeated here. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it may include the processes of the embodiments of the above methods. The storage medium may be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium may also include a combination of the above types of memory.
[0077] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0078] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed application requires more features than expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0079] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.
Claims
1. A pre-reading method applied to random reads, characterized in that, The method includes: In response to the completion of the current random read request, obtain the current logical block address corresponding to the current random read request, and check whether there are any pending host commands; If the host command to be processed does not exist, the system enters the pre-read mode. In the pre-read mode, the current logical block address is input to the state transition model pre-deployed in the target firmware. The state transition model selects the target address difference that has the highest transition probability with the current logical block address. The pre-read logical block address is determined based on the target address difference and the current logical block address, and the pre-read data corresponding to the pre-read logical block address is cached. In response to the next random read request, the pre-read logical block address is matched with the target logical block address corresponding to the next random read request. If the match is successful, the pre-read data is output; otherwise, the data corresponding to the target logical block address is read and output.
2. The pre-read method for random reading according to claim 1, characterized in that, Before the step of inputting the current logical block address into the pre-deployed state transition model in the target firmware, the method further includes: Obtain historical access sequences; the historical access sequences include multiple logical block transfer entries constructed based on logical block access timing, and each logical block transfer entry includes a source logical block address and a corresponding logical block address difference; The transfer terms of each logic block are preprocessed to obtain a transfer sample sequence; Based on the transfer sample sequence, the number of transfers for each source logical block address under the difference between the logical block addresses is counted, and the transfer probability corresponding to each source logical block address is calculated based on the number of transfers. An initial transition matrix is constructed using the address of each source logical block as the row index and the difference between the addresses of each logical block as the column index; each element of the initial transition matrix represents the transition probability from the source logical block address corresponding to the row index via the logical block address difference indicated by the column index; Based on the initial transition matrix, the target firmware is modeled and deployed to form the state transition model.
3. The pre-read method for random reading according to claim 2, characterized in that, The step of preprocessing the historical access sequence to obtain the transfer sample sequence includes: Determine whether the occurrence frequency of each logical block transfer item is lower than a preset frequency threshold, and determine whether the logical block address difference corresponding to each logical block transfer item exceeds a preset difference range; Remove all logical block transfer entries in the historical access sequence that occur at frequencies lower than the preset frequency threshold and / or exceed the preset difference range to obtain the transfer sample sequence.
4. The pre-read method for random reading according to claim 2, characterized in that, The step of deploying the target firmware model based on the initial transition matrix to form the state transition model includes: The initial transition matrix is subjected to sparse compression and dimensionality reduction to obtain a lightweight transition matrix; The lightweight transition matrix is loaded into the target firmware, and the state transition model is deployed through the lightweight transition matrix.
5. The pre-read method for random reading according to claim 4, characterized in that, After the step of matching the pre-read logical block address with the target logical block address corresponding to the next random read request, the method further includes: Based on the current logical block address and the logical address difference between the current logical block address and the target logical block address, a transfer item to be updated is constructed; The transition item to be updated is applied to the lightweight transition matrix in the target firmware to update the transition probability of the entry in the lightweight transition matrix corresponding to the current logical block address and the logical address difference, so as to update the state transition model.
6. The pre-read method for random reads according to claim 4, characterized in that, After the step of entering the pre-read mode, the method further includes: In response to a preset trigger condition, the transfer probability corresponding to each source logic block address in the lightweight transfer matrix of the target firmware is traversed. Remove matrix elements corresponding to transition probabilities less than a preset probability threshold to update the state transition model.
7. The pre-read method for random reading according to claim 2, characterized in that, The step of selecting the target address difference with the current logical block address that has the highest transition probability through the state transition model includes: Locate the target row index corresponding to the current logical block address in the state transition model; Iterate through the logical block address differences corresponding to each column index in the target row index, and filter to obtain the target column index with the highest transfer probability; The difference in logical block addresses corresponding to the target column index is used as the target address difference.
8. A pre-read device for random reading, characterized in that, include: The pre-read trigger judgment module is used to obtain the current logical block address corresponding to the current random read request and detect whether there is a host command to be processed in response to the completion of the current random read request. The pre-read address acquisition module is used to enter the pre-read mode if the host command to be processed does not exist. In the pre-read mode, the current logical block address is input to the state transition model pre-deployed in the target firmware, and the target address difference with the current logical block address with the highest transition probability is selected through the state transition model. The pre-read data reading module is used to determine the pre-read logical block address based on the target address difference and the current logical block address, and to cache the pre-read data corresponding to the pre-read logical block address; The instruction matching output module is used to respond to the next random read request by matching the pre-read logical block address with the target logical block address corresponding to the next random read request. If the match is successful, the pre-read data is output; otherwise, the data corresponding to the target logical block address is read and output.
9. An electronic device, characterized in that, include: One or more processors; One or more memory units; And one or more computer programs, wherein the one or more computer programs are stored in the one or more memories, the one or more computer programs including instructions that, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The storage medium stores a program or instructions that, when executed, implement the method as described in any one of claims 1 to 7.