Instruction processing method and device, equipment and storage medium

Abstract

The invention provides an instruction processing method and device, equipment and a storage medium, and the method comprises the steps: obtaining an assembly instruction, and forming an instruction sequence; decoding assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence; determining a micro-packaging identifier of each micro-operation in the micro-operation sequence; carrying out micro-operation dispatching according to the micro-packaging identifier; executing the dispatched micro-operation; and graduation processing is carried out on the executed micro-operation. The method provided by the invention comprises the following steps: determining a micro-packaging identifier of each micro-operation in a micro-operation sequence; carrying out micro-operation dispatching according to the micro-packaging identifier; executing the dispatched micro-operation; according to the method, graduation processing is carried out, so that the micro-operations of the same micro-packaging identifier can be processed through the same assembly line, each micro-operation is not processed through the assembly line, and the execution efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction processing method, apparatus, device, and storage medium. Background Technology

[0002] Modern processors or processor cores process instructions in a pipelined manner. A typical pipeline usually includes various stages such as instruction fetch, instruction decode, instruction dispatch, instruction execution, and instruction graduation.

[0003] Currently, when processing instructions, the instructions are decoded into micro-operations, and each micro-operation is processed at a time. Each processing session executes all stages of the pipeline, which reduces execution efficiency. Summary of the Invention

[0004] To address one of the aforementioned technical deficiencies, this application provides an instruction processing method, apparatus, device, and storage medium.

[0005] A first aspect of this application provides an instruction processing method, the method comprising: Obtain assembly instructions and form an instruction sequence; The assembly instructions in the instruction sequence are decoded into micro-operations to form a micro-operation sequence; Determine the micro-packet identifier for each micro-operation in the micro-operation sequence; Dispatch of micro-operations based on micro-packaging identifiers; Perform micro-operations to dispatch; Perform graduation processing on the completed micro-operations.

[0006] A second aspect of this application provides an instruction processing apparatus, the apparatus comprising: The instruction fetching module is used to fetch assembly instructions and form an instruction sequence. The instruction decoding module is used to decode the assembly instructions in the instruction sequence into micro-operations, forming a micro-operation sequence; and to determine the micro-packet identifier of each micro-operation in the micro-operation sequence. The instruction dispatch module is used to dispatch micro-operations based on micro-packet identifiers; The instruction execution module is used to perform the micro-operations of the dispatch. The instruction graduation module is used to perform graduation processing on micro-operations that have been executed.

[0007] A third aspect of this application provides an electronic device, comprising: Memory; Processor; and Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method described in the first aspect above.

[0008] In a fourth aspect, this application provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the method described in the first aspect above.

[0009] This application provides an instruction processing method, apparatus, device, and storage medium. The method includes: acquiring assembly instructions to form an instruction sequence; decoding the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence; determining a micro-packet identifier for each micro-operation in the micro-operation sequence; dispatching micro-operations according to the micro-packet identifiers; executing the dispatched micro-operations; and performing graduation processing on the executed micro-operations. The method provided by this application determines the micro-packet identifier for each micro-operation in the micro-operation sequence; dispatches micro-operations according to the micro-packet identifiers; executes the dispatched micro-operations; and performs graduation processing, enabling micro-operations with the same micro-packet identifier to be processed through the same pipeline, instead of being processed separately through a pipeline for each micro-operation, thus improving execution efficiency. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the structure of a first instruction processing device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a second instruction processing device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a third instruction processing device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the fourth instruction processing device provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the fifth instruction processing device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the sixth instruction processing device provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the seventh instruction processing device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of the eighth instruction processing device provided in the embodiments of this application; Figure 9 A flowchart illustrating an instruction processing method provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of the first packaging instruction provided in an embodiment of this application; Figure 11 This is a schematic diagram of the structure of the first release instruction provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the second release instruction provided in an embodiment of this application; Figure 13 A schematic diagram of the first type of instruction provided in an embodiment of this application; Figure 14 This is a schematic diagram of a first micro-operation sequence provided in an embodiment of this application; Figure 15 A schematic diagram illustrating the implementation principle of the first instruction decoding module provided in this application embodiment; Figure 16 A schematic diagram illustrating the implementation principle of the second instruction decoding module provided in this application embodiment; Figure 17 This is a schematic diagram of a second micro-operation sequence provided in an embodiment of this application; Figure 18 A schematic diagram illustrating the implementation principle of the third instruction decoding module provided in this application embodiment; Figure 19 A schematic diagram illustrating the implementation principle of the fourth instruction decoding module provided in this application embodiment; Figure 20 This is a schematic diagram of a third micro-operation sequence provided in an embodiment of this application; Figure 21 A schematic diagram of a DAG provided for an embodiment of this application; Figure 22 This is a schematic diagram of the fourth micro-operation sequence provided in the embodiments of this application; Figure 23 This is a schematic diagram of the dispatching process provided in an embodiment of this application; Figure 24 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0011] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0012] In the process of realizing this application, the inventors discovered that currently, when processing instructions, the instructions are decoded into micro-operations, and each micro-operation is processed at a time. Each processing time executes each stage of the pipeline, which reduces the execution efficiency.

[0013] To address the aforementioned problems, this application provides an instruction processing method, apparatus, device, and storage medium. The method includes: acquiring assembly instructions to form an instruction sequence; decoding the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence; determining a micro-packet identifier for each micro-operation in the micro-operation sequence; dispatching micro-operations according to the micro-packet identifiers; executing the dispatched micro-operations; and performing graduation processing on the executed micro-operations. The method provided in this embodiment determines the micro-packet identifier for each micro-operation in the micro-operation sequence; dispatches micro-operations according to the micro-packet identifiers; executes the dispatched micro-operations; and performs graduation processing. This allows micro-operations with the same micro-packet identifier to be processed through the same pipeline, instead of being processed separately through a pipeline for each micro-operation, thus improving execution efficiency.

[0014] This embodiment provides an instruction processing method, which can be implemented by an instruction processing device. The instruction processing device can be as follows: Figure 1 As shown, it includes: instruction acquisition module 101, instruction decoding module 102, instruction dispatch module 103, instruction execution module 104, and instruction graduation module 105.

[0015] 1. Instruction Acquisition Module 101 The instruction acquisition module 101 is used to acquire instructions and form an instruction sequence.

[0016] The instructions may include only assembly instructions, or they may include both assembly instructions and other instructions.

[0017] Other instructions are pack instructions and / or release instructions.

[0018] Packing instructions are used to indicate the assembly instructions in the package and the instruction dependency identifiers.

[0019] The release instruction is used to indicate whether the corresponding register should be released after the execution of multiple subsequent assembly instructions.

[0020] In a specific implementation, the instruction fetch module 101 can be composed of an instruction cache (ICache), a branch prediction unit (BPU), and an instruction fetch unit (IFetch), such as... Figure 2 As shown.

[0021] 1) Instruction Cache (ICache) The instruction cache (ICache) is used to store copies of recently used instructions, which speeds up assembly instruction retrieval and reduces memory access latency.

[0022] 2) Branch Prediction Unit (BPU) The branch prediction unit (BPU) is used to predict the direction of program branches (such as if / else statements and loops), obtain assembly instructions in advance, and avoid pipeline stalls.

[0023] Each cycle of the processor must determine where to fetch the next assembly instruction.

[0024] If there are no branches in the current instruction stream, the program counter (PC) simply adds the assembly instruction length. If a branch is encountered, the branch prediction unit (BPU) predicts whether to jump using the branch history table (BHT); if a jump is expected, the target address is predicted using the branch target buffer (BTB). The prediction result is sent to the instruction fetch logic to ensure uninterrupted instruction flow.

[0025] In addition, in specific implementations, the branch prediction unit (BPU) can adopt a hybrid prediction architecture, such as including both BTB and TAGE (Tagged Geometric History Branch Predictor).

[0026] 3) Instruction fetch unit (IFetch) The instruction fetch unit (IFetch) is used to fetch assembly instructions from the program counter (PC) to form an instruction sequence.

[0027] For example, the instruction fetch unit (IFetch) fetches assembly instructions based on the predicted program counter (PC). If a hit occurs, the instruction byte is returned directly. If a miss occurs, a request is sent to L2 / L3 or memory.

[0028] A CPU (Central Processing Unit) can fetch multiple assembly instructions simultaneously per cycle; for example, an x86 CPU can fetch 16 bytes or more. The fetched assembly instructions are then sent to an instruction sequence (such as an Instr Queue).

[0029] 2. Instruction decoding module 102 The instruction decoding module 102 is used to decode the assembly instructions in the instruction sequence formed by the instruction acquisition module 101 into micro-operations, form a micro-operation sequence, and determine the micro-packet identifier of each micro-operation in the micro-operation sequence.

[0030] In addition, each micro-operation may also include a micro-dependency identifier.

[0031] In addition, each micro-operation may also include a delay flag and / or a source register release flag.

[0032] For example, the instruction decoding module 102 can translate assembly instructions (raw binary code, i.e., assembly instructions in the instruction sequence formed by the instruction fetching module 101) into micro-operations (micro-ops or μops, i.e. basic operations that the processor can recognize and execute), forming a micro-operation sequence (such as a μops queue).

[0033] When the instruction decoding module 102 converts machine code into CPU-unified micro-operations (μops), for a RISC (Reduced Instruction Set Computer) architecture, typically one assembly instruction is decoded into one μop, while for a CISC (Complex Instruction Set Computer) (x86) architecture, it may be decoded into multiple μops. Simultaneously, it determines the source register release flag for each μop. Subsequently, the μops and their source register release flags are stored in a micro-operation sequence (such as a μops queue).

[0034] The instruction decoding module 102 includes one or more decoding units, each with the same architecture and implementation principle. Each decoding unit can independently determine the micro-operations of the instruction sequence formed by the instruction fetching module 101, forming a micro-operation sequence. Therefore, the instruction decoding module 102 can perform parallel decoding of multiple assembly instructions. Figure 3 As shown, the instruction decoding module 102 includes four decoding units, namely decoding unit 1, decoding unit 2, decoding unit 3 and decoding unit 4.

[0035] Instruction decoding module 102 includes instruction packing module, such as Figure 4 As shown. The instruction packing module is used to determine the micro-packing identifier of each micro-operation in the micro-operation sequence.

[0036] In a specific implementation, the instruction decoding module 102 may also include a release extractor, such as... Figure 5 As shown. The release extractor is used to extract information from the release command.

[0037] Additionally, the instruction decoding module 102 may also include an information extractor, such as... Figure 6 As shown.

[0038] In addition, the instruction decoding module 102 may also include a release analysis module, such as... Figure 7 As shown.

[0039] In other words, the instruction decoding module 102 may or may not include a release extractor, information extractor, or release analysis module in addition to the instruction packing module, or it may include one or more of the release extractor, information extractor, and release analysis module. This embodiment does not limit the specific configuration of the instruction decoding module 102.

[0040] 3. Command dispatch module 103 The instruction dispatch module 103 is used to dispatch micro-operations based on micro-packet identifiers.

[0041] For example, instruction dispatch module 103 is a Dispatch Unit. Instruction dispatch module 103 sends the decoded micro-operations μops into the core area of ​​out-of-order execution (such as a Reservation Station (RS)) and waits for execution.

[0042] In addition, frequently used code snippets may be cached in the μops Cache (micro-operation cache) so that they can be directly hit during subsequent instruction fetching without re-decoding.

[0043] Instruction dispatch module 103 places micro-operations (μops) into a dispatch queue (such as a dispatch queue) to wait: Arithmetic Logic Unit (ALU) queue Floating Point Unit (FPU) Queue Load / Store Queue (LSU Queue) Branch Queue Micro-operations monitor dependencies in the waiting queue: once all source operands are ready (from registers or forwarded results), they can be launched.

[0044] Multiple assembly instructions can be issued simultaneously in each cycle.

[0045] Furthermore, in a specific implementation, the instruction processing apparatus provided in this embodiment may also include a register renaming module, such as a Rename Unit (Register Renaming). Figure 8 As shown, the micro-operation is dispatched by the instruction dispatch module 103 and then input to the register renaming module.

[0046] The Rename Unit eliminates pseudo-data dependencies (such as WAR and WAW dependencies) and improves the parallelism of out-of-order execution by allocating more physical registers. The CPU has a set of logical registers (architecture-defined, e.g., x86 has 16 general-purpose registers), but internally it has many more physical registers. The Rename Unit maps logical registers to the Physical Register Table (PRT), allowing assembly instructions to execute in parallel without being blocked by name conflicts.

[0047] Modern CPUs allow out-of-order execution, but register name conflicts must be resolved.

[0048] For example: add r1, r2, r3 sub r1, r4, r5 If the execution is sequential, there is no problem, but if the second step is to be executed earlier, a conflict will occur because both steps will use r1.

[0049] The register renaming unit allocates an independent physical register for each logical register at the hardware level. For example, a mapping table (logical register → physical register) is established. When a new assembly instruction writes to the target register, a new physical register is allocated, and the old value is retained until the assembly instruction is committed. In this way, each assembly instruction can independently use its own copy of the physical register, thus achieving out-of-order parallelism.

[0050] 4. Instruction Execution Module 104 The instruction execution module 104 is used to execute the micro-operations dispatched by the instruction dispatch module 103.

[0051] For example, the instruction execution module 104 is an Exe (Execution Unit). The instruction execution module 104 is the core component that actually executes assembly instructions, including an arithmetic logic unit (ALU), a floating-point unit (FPU), and a branch unit.

[0052] The instruction execution module 104 requires only one cycle to process simple arithmetic logic (addition, subtraction, and logical operations). It requires multiple cycles to process complex operations (multiplication, division, and floating-point operations).

[0053] In addition, the branch instruction is only judged to be correct during the execution of the instruction execution module 104.

[0054] The branching results determined in the Branch Unit of the instruction execution module 104 are used to correct and update the prediction data of the Branch Prediction Unit (BPU). Therefore, in Figure 1 or Figure 2 or Figure 3 The instruction execution module 104 has a line that folds back to the instruction acquisition module 101.

[0055] The results of the executed assembly instructions are temporarily stored in: • In the ROB (Reorder Buffer): the status, result, and destination register of each assembly instruction are recorded.

[0056] • In Store Buffer / Load Queue: Store memory operations that have not yet been committed.

[0057] ROB maintains the assembly instructions in PC order and serves as the "timeline" for the entire out-of-order engine.

[0058] 5. Instruction Graduation Module 105 The instruction graduation module 105 is used to perform graduation processing on the micro-operations completed by the instruction execution module 104.

[0059] In addition, the instruction graduation module 105 is also used to release the corresponding registers based on the micro-dependency identifier.

[0060] If the micro-operation includes a source register release flag, the instruction graduation module 105 is also used to release the corresponding register according to the source register release flag.

[0061] For example, the instruction graduation module 105 is a GRU (Graduation Unit). The instruction graduation module 105 ensures that the results of assembly instruction execution are written to logic registers and main memory strictly in the order indicated by the program counter (PC). The instruction graduation module 105 is responsible for ensuring that although the instructions are executed out of order internally, from an architectural perspective, the program's execution results and state updates still occur in the original program order.

[0062] For example, the GRU (Graduation Unit) checks the ROB header instruction. If the assembly instruction has been executed and there are no exceptions or branch mispredictions, the GRU will "commit" it, that is, update the values ​​of the physical registers to the architecture-visible state; release the old register mappings and ROB entries; if it is a Store instruction, allow writing to the cache.

[0063] If an anomaly is detected (such as a page fault or mispredicted branch), GRU will discard all uncommitted assembly instructions; restore the register map to the correct state; and jump to the address of the branch that caused the anomaly or the correct branch to re-execute.

[0064] In this way, although the CPU instructions are executed out of order, the effect observed from the outside is completely equivalent to sequential execution.

[0065] However, when releasing a register, the instruction graduation module 105 can release the corresponding register according to the source register release flag.

[0066] Furthermore, in a specific implementation, the instruction processing apparatus provided in this embodiment may also include a load / store unit, such as an LSU (Load / Store Unit). Figure 8 As shown, the load / store unit is responsible for handling all memory access instructions (Load and Store) and managing the interaction of the data cache (DCache).

[0067] The Load / Store Unit (LSU) can process Load / Store instructions, for example: Load: Access L1 DCache (a few cycles if it hits, tens of cycles if it misses).

[0068] Store: First write to the Store Buffer, then wait until it is safe to write back.

[0069] This embodiment of the present application provides an instruction processing device that dispatches micro-operations based on micro-packet identifiers; executes the dispatched micro-operations; and performs graduation processing, so that micro-operations with the same micro-packet identifiers can be processed through the same pipeline, instead of each micro-operation being processed through a separate pipeline, thereby improving execution efficiency.

[0070] Based on the above Figures 1 to 8 In any of the instruction processing devices shown in the figures, this embodiment provides an instruction processing method, see below. Figure 9 The implementation process of the instruction processing method provided in this embodiment is as follows: 901, fetch instructions and form an instruction sequence.

[0071] The instructions may include only assembly instructions, or they may include both assembly instructions and other instructions.

[0072] Other instructions are pack instructions and / or release instructions.

[0073] Packing instructions are used to indicate the assembly instructions in the package and the instruction dependency identifiers.

[0074] The release instruction is used to indicate whether the corresponding register should be released after the execution of multiple subsequent assembly instructions.

[0075] Regardless of the type of instruction, step 901 is implemented by the instruction acquisition module 101, that is, the instruction acquisition module 101 acquires the instruction and forms an instruction sequence.

[0076] A. Packaging Instructions The packaging instructions are obtained by the compiler.

[0077] High-level language code instructs the compiler whether to generate packing instructions. For example, special directives or parameters can be added to the high-level language code to instruct the compiler on whether to generate packing instructions. If the high-level language code instructs the compiler to generate packing instructions, the instructions obtained in step 901 will include assembly instructions, deallocation instructions, and packing instructions. If the high-level language code instructs the compiler not to generate packing instructions, the instructions obtained in step 901 will only include assembly instructions and deallocation instructions.

[0078] Packing instructions are used to indicate that multiple consecutive assembly instructions are located in the same package. Packing instructions include the number of instructions that make up the package and the instruction dependency identifiers of each instruction that makes up the package.

[0079] Packing instructions are generated by the compiler during the process of translating high-level language code into assembly instructions.

[0080] During the process of translating high-level language code into assembly instructions, the compiler can determine whether each assembly instruction constitutes a package based on the high-level language code. If a package is formed, a corresponding package instruction will be generated and inserted into the assembly instructions.

[0081] The packing instruction occupies instN bits, where instN is an even number. In practice, the width of the packing instruction is the same as the width of the assembly instruction. If the assembly instruction is 32 bits, then the packing instruction is also 32 bits; if the assembly instruction is 16 bits, then the packing instruction is also 16 bits.

[0082] Taking a 16-bit packing instruction as an example, the packing instruction includes: length information (such as...) Figure 10 Len in the package), instruction dependency identifiers of each assembly instruction in the package (such as Len), and instruction dependency identifiers of each assembly instruction in the package (such as Len). Figure 10 OutputLabel in the command identifier (such as OutputLabel) Figure 10 PackagedMark in the middle.

[0083] Among them, length information (such as Figure 10 The Len instruction (e.g., 4 bits) occupies the instruction identifier (e.g., ... Figure 10 The PackagedMark occupies 3 bits, and the rest are instruction dependency identifiers for each assembly instruction in the package (such as...). Figure 10 (OutPutLabel in the middle).

[0084] The length information indicates the number of assembly instructions in a packet. Len ranges from 1 to 10, and Len indicates that there are multiple consecutive assembly instructions in the same packet, starting from the next instruction and including the next instruction. For example... Figure 10In the Len instruction, the binary number 1001 is equivalent to the decimal number 9, indicating that nine consecutive assembly instructions following the pack instruction are located in the same pack.

[0085] Instruction dependency identifiers for each assembly instruction in the package (e.g.) Figure 10 Each bit in the OutputLabel represents an instruction dependency identifier for an assembly instruction. (e.g., ...) Figure 10 As shown in the OutputLabel, the instruction dependency flag of the first assembly instruction after the packing instruction is 0, the instruction dependency flag of the second assembly instruction after the packing instruction is 0, the instruction dependency flag of the third assembly instruction after the packing instruction is 0, the instruction dependency flag of the fourth assembly instruction after the packing instruction is 0, the instruction dependency flag of the fifth assembly instruction after the packing instruction is 0, the instruction dependency flag of the sixth assembly instruction after the packing instruction is 1, the instruction dependency flag of the seventh assembly instruction after the packing instruction is 0, the instruction dependency flag of the eighth assembly instruction after the packing instruction is 1, and the instruction dependency flag of the ninth assembly instruction after the packing instruction is 1.

[0086] Instruction identifiers are used to indicate that this instruction is a package instruction. A specific value (e.g., special value XXX) can be set according to the specific assembly instruction set space. Figure 10 The PackagedMark in the instruction. In the specific implementation, the last three digits of the instruction can be identified. If the following three digits are special values ​​(such as XXX), the instruction decoding module 102 determines that the instruction is a package instruction.

[0087] The instruction dependency flag indicates whether the corresponding assembly instruction is dependent on assembly instructions outside the instruction package it belongs to. If it is not dependent on assembly instructions outside the instruction package, its instruction dependency flag is the third flag (e.g., 0). If it is dependent on assembly instructions outside the instruction package, its instruction dependency flag is the fourth flag (e.g., 1).

[0088] The process for determining instruction dependency identifiers and packaging instructions is as follows: 1001, the compiler will determine the first assembly instruction generated as the current instruction.

[0089] 1002, the initialization instruction package is empty.

[0090] If there is no instruction package currently, the process of initializing the instruction package to be empty is as follows: create a new empty instruction package, which contains 0 assembly instructions.

[0091] If an instruction package already exists, the process of initializing the instruction package to be empty is as follows: clear all assembly instructions in the instruction package.

[0092] 1003, Determine if the current instruction has side effects.

[0093] One of the side effects is causing CPU jumps or synchronization issues.

[0094] Assembly instructions with side effects are assembly instructions that can be decoded into micro-operations with side effects.

[0095] Micro-operations with side effects include ordinary jumps, jumps that can cause exceptions, and atomic operations, such as Load, Store, Branch, and atomic operations. Common micro-operations with side effects in the RISC-V (Reduced Instruction Set Computer Five) architecture include: LB, LH, SB, SH, JAL, BEQ, BLT, FENCE, ECALL, EBREAK, CSRRW, CSRRS, CSRRC, AMOSWAP.W, AMOADD.W, etc.

[0096] Micro-operations without side effects include, for example, data movement between registers, arithmetic operations, and logical shifts. Examples include MOV, ADD, and SHL.

[0097] 1004. If the current instruction has side effects, then the next assembly instruction of the current instruction will be determined as the current instruction, and the steps of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps will be repeated.

[0098] Since the instruction package must not meet the packaging conditions before executing step 1004, the current instruction has side effects and the instruction package does not meet the packaging conditions at step 1004. At this time, the next assembly instruction of the current instruction is determined as the current instruction, and all assembly instructions in the instruction package are cleared to realize the initialization of the instruction package in step 1002 and subsequent steps.

[0099] 1005. If the current instruction has no side effects, determine whether the current instruction meets the inclusion condition. If the current instruction does not meet the inclusion condition, determine the next assembly instruction of the current instruction as the current instruction, and repeat the step of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps.

[0100] If the current instruction has no side effects, then: 1101, Determine whether the current instruction needs to be added to the instruction packet. That is, determine whether the addition conditions are met.

[0101] The conditions for joining are as follows: The current instruction is depended upon by assembly instructions within the instruction package, but is not depended upon by assembly instructions outside the instruction package.

[0102] or, The current instruction is depended upon by assembly instructions within the instruction package, and the current instruction is depended upon by assembly instructions outside the instruction package, and... .

[0103] in, This represents the total number of assembly instructions within the instruction package and the current instruction. This represents the number of assembly instructions within the instruction package and the number of assembly instructions in the current instruction that depend on external instructions. This represents the number of assembly instructions within the instruction package and the number of assembly instructions in the current instruction that are externally dependent. This is the preset fourth ratio. For example, .

[0104] or, The current instruction is not dependent on any instruction within the instruction package, nor is it dependent on any assembly instruction outside the instruction package, and the number of assembly instructions within the instruction package is less than a preset fourth value. For example, the fourth value is 4.

[0105] Taking the current instruction as assembly instruction 4, the instruction package contains 3 assembly instructions: assembly instruction 1, assembly instruction 2, and assembly instruction 3. For example, the fourth value is 4: If assembly instruction 4 is only dependent on assembly instruction 1, then assembly instruction 4 is dependent on assembly instructions within the instruction package, and assembly instruction 4 is not dependent on assembly instructions outside the instruction package, thus satisfying the inclusion condition.

[0106] If assembly instruction 4 is dependent on assembly instruction 1 and also on assembly instruction 5, and assembly instruction 2 depends on assembly instruction 0 (i.e., the first instruction preceding this instruction package), assembly instruction 3 is dependent on assembly instruction 6, and assembly instruction 4 depends only on assembly instruction 1, then the assembly instructions within the instruction package and the current instruction are assembly instruction 1, assembly instruction 2, assembly instruction 3, and assembly instruction 4. Within the instruction package, the assembly instruction that depends on the external instruction is assembly instruction 2, and the assembly instruction that the external instruction depends on is assembly instruction 3. Therefore, the assembly instruction within the instruction package and the assembly instruction in the current instruction that depends on the external instruction are assembly instruction 2 (i.e., ), assembly instructions within the instruction package and assembly instructions in the current instruction that are externally dependent are assembly instruction 3 and assembly instruction 4 (i.e. At this point, assembly instruction 4 is depended upon by assembly instructions within the instruction package, and also by assembly instructions outside the instruction package. Therefore, it is determined that the conditions for joining are not met.

[0107] If assembly instruction 4 is not dependent on assembly instruction 1 or assembly instruction 5, and the number of assembly instructions in the instruction package is 3 < 4, then the inclusion condition is met.

[0108] The dependency relationship between assembly instructions is as follows: if assembly instruction 15 reads the result of assembly instruction 13, then assembly instruction 15 depends on assembly instruction 13.

[0109] The dependencies between assembly instructions are obtained based on existing methods. For example, the compiler determines the dependencies by analyzing the data flow and control flow between assembly instructions, mainly using techniques such as data dependency analysis, control dependency analysis, and program dependency graphs.

[0110] 1102. If the current instruction does not meet the inclusion condition, the next assembly instruction of the current instruction is determined as the current instruction, and the step of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps are repeated.

[0111] Since the instruction package must not meet the packing conditions before step 1102, the current instruction does not meet the addition conditions and the instruction package does not meet the packing conditions in step 1102. At this time, the next assembly instruction of the current instruction is determined as the current instruction, and all assembly instructions in the instruction package are cleared to implement the instruction package initialization in step 1002 and subsequent steps.

[0112] 1103. If the current instruction meets the inclusion condition, add the current instruction to the instruction package. If the instruction package meets the packing condition, determine the instruction dependency identifiers of each assembly instruction within the instruction package, generate a packing instruction, insert the generated packing instruction before all assembly instructions in the instruction package, determine the next assembly instruction of the current instruction as the current instruction, and repeat the step of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps. If the instruction package does not meet the packing condition, determine the next assembly instruction of the current instruction as the current instruction, and repeat the step of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps.

[0113] Since the instruction packet does not meet the packaging conditions before step 1103, in step 1103, the current instruction meets the addition conditions but the instruction packet does not meet the packaging conditions. At this time: 1. Add the current instruction to the instruction package.

[0114] Taking the current instruction as assembly instruction 4, and the instruction package containing 3 assembly instructions, namely assembly instruction 1, assembly instruction 2, and assembly instruction 3, as an example, after adding assembly instruction 4 to the instruction package, the instruction package will contain 4 assembly instructions, namely assembly instruction 1, assembly instruction 2, assembly instruction 3, and assembly instruction 4.

[0115] 2. Determine whether the instruction package meets the packaging conditions.

[0116] Among them, the packaging conditions are: ,and, .

[0117] in, This represents the number of assembly instructions within the instruction package. This represents the number of assembly instructions within the instruction package that depend on external instructions. This represents the number of assembly instructions within the instruction package that are externally dependent. For the preset third value, such as , For the preset third ratio, such as .

[0118] The instruction package contains four assembly instructions: assembly instruction 1, assembly instruction 2, assembly instruction 3, and assembly instruction 4. Assembly instruction 4 is dependent on assembly instruction 5, assembly instruction 2 depends on assembly instruction 0 (the first instruction preceding this instruction in the package), assembly instruction 3 is dependent on assembly instruction 6, and assembly instruction 4 depends only on assembly instruction 1. , For example, the number of assembly instructions in the instruction package The assembly instructions that the instruction package depends on external ones are assembly instructions 2 (i.e., ... The assembly instructions within the instruction package that are externally dependent are assembly instruction 3 and assembly instruction 4 (i.e., ...). ). (Right now ),but If so, it is determined that the instruction package does not meet the packaging conditions.

[0119] 3. If the instruction package meets the packaging conditions, then: (1) The instruction dependency identifier of the assembly instructions within the instruction package that are depended by external (here, "external" refers to the assembly instructions outside the package) is determined as the fourth identifier (e.g., 1). The instruction dependency identifier of the assembly instructions within the instruction package that are not depended by external (here, "external" refers to the assembly instructions outside the package) is determined as the third identifier (e.g., 0).

[0120] Although the instruction package does not meet the packaging conditions before executing step 1103, new assembly instructions will be added to the instruction package after executing step 1 of step 1103. In step 2 of step 1103, it is determined that the instruction package with the added new assembly instructions meets the packaging conditions. Therefore, in step 3 of step 1103, the instruction package meets the packaging conditions. At this time, the instruction dependency identifiers of each assembly instruction in the instruction package will be determined.

[0121] (2) Generate a packing instruction and insert the generated packing instruction before all assembly instructions in the instruction pack.

[0122] The binary value of the number of instructions in the instruction package is used as Len, the instruction dependency identifier of each assembly instruction in the instruction package is used to form OutPutLabel, and special values ​​(such as XXX) are determined as PackagedMark to form packaged instructions.

[0123] If the packing instruction is packing instruction 1, the assembly instruction preceding packing instruction 1 is instruction 10, and the nine assembly instructions following packing instruction 1 are 11-19, then the final instruction is assembly instruction 10, packing instruction 1, assembly instruction 11, assembly instruction 12, assembly instruction 13, assembly instruction 14, assembly instruction 15, assembly instruction 16, assembly instruction 17, assembly instruction 18, and assembly instruction 19.

[0124] (3) Determine the next assembly instruction of the current instruction as the current instruction, and repeat the step of initializing the instruction package to be empty (i.e. step 1002) and subsequent steps.

[0125] 4. If the instruction package does not meet the packaging conditions, the next assembly instruction of the current instruction is determined as the current instruction, and the steps of initializing the instruction package to be empty (i.e., step 1002) and subsequent steps are repeated.

[0126] Although the instruction package does not meet the packing conditions before executing step 1103, after executing step 1 of step 1103, a new assembly instruction will be added to the instruction package. In step 2 of step 1103, it is determined that the instruction package with the added new assembly instruction does not meet the packing conditions. Therefore, in step 4 of step 1103, the instruction package does not meet the packing conditions. The next assembly instruction of the current instruction is determined as the current instruction, and all assembly instructions in the instruction package are cleared to complete the instruction package initialization in step 1002 and subsequent steps.

[0127] Packaging instructions can group consecutive assembly instructions that have few dependencies on external assembly instructions into packages, which can then be processed by package, i.e., dispatching a package of multiple assembly instructions at a time, thus avoiding the inefficiency of dispatching each assembly instruction individually.

[0128] In addition, when determining the next assembly instruction of the current instruction as the current instruction, if the compiler does not obtain the next assembly instruction of the current instruction, it will pause execution until it obtains the new assembly instruction, and then use the new assembly instruction as the next assembly instruction of the current instruction, and thus determine the new assembly instruction as the current instruction.

[0129] B. Release command The release instruction is obtained by the compiler.

[0130] High-level language code instructs the compiler whether to generate release instructions. For example, special directives or parameters can be added to the high-level language code to instruct the compiler on whether to generate release instructions. If the high-level language code instructs the compiler to generate release instructions, the instructions obtained in step 901 will include both assembly instructions and release instructions. If the high-level language code instructs the compiler not to generate packing instructions, the instructions obtained in step 901 will only include assembly instructions.

[0131] The release instruction is used to indicate whether the corresponding register should be released after the execution of multiple subsequent assembly instructions.

[0132] Release instructions are generated by the compiler during the process of translating high-level language code into assembly instructions.

[0133] During the process of translating high-level language code into assembly instructions, the compiler can determine the dependencies of the source operands involved in each assembly instruction based on the high-level language code. Based on the dependencies, it forms a release instruction and places it before all the assembly instructions it represents, thus placing the release instruction into the assembly instruction.

[0134] If any assembly instruction involves at least two source operands.

[0135] The release instruction occupies instN bits, where instN is an even number. In practice, the width of the release instruction is the same as the width of the assembly instruction. If the assembly instruction is 32 bits, then the release instruction is also 32 bits; if the assembly instruction is 16 bits, then the release instruction is also 16 bits.

[0136] Taking a 16-bit release instruction (i.e., instN=16) as an example, such as Figure 11 As shown, the 16 bits will be grouped into 8 groups of 2 bits each. For example, 0 and 1 are in group 1, 2 and 3 are in group 1, 4 and 5 are in group 1, 6 and 7 are in group 1, 8 and 9 are in group 1, 10 and 11 are in group 1, 12 and 13 are in group 1, and 14 and 15 are in group 1.

[0137] Each group of bits indicates whether the assembly instruction following the release instruction releases the registers corresponding to the first two source operands after execution. For example, the g-th group of 2 bits of any release instruction indicates whether the g-th assembly instruction following the release instruction releases the registers corresponding to the first two source operands after execution.

[0138] Where g is the sequence index, g=1,2,…,instN / 2.

[0139] In this context, the first bit of the g-th group indicates whether the g-th assembly instruction following any release instruction releases the register corresponding to the first source operand after execution, and the second bit indicates whether the g-th assembly instruction following any release instruction releases the register corresponding to the second source operand after execution.

[0140] For example, the fifth flag (e.g., the fifth flag is 1) indicates that the assembly instruction can release the physical register of the corresponding source operand after execution, while the sixth flag (e.g., the sixth flag is 0) indicates that the assembly instruction cannot release the physical register of the corresponding source operand after execution. Therefore, if... Figure 12As shown, if each assembly instruction involves only the first and second source operands, then the first group of 01 indicates that after the execution of the first assembly instruction following the release instruction (such as `instr1`), the physical register of the first source operand of `instr1` cannot be released, but the physical register of the second source operand of `instr1` can be released. The second group of 10 indicates that after the execution of the second assembly instruction following the release instruction (such as `instr2`), the physical register of the first source operand of `instr2` can be released, but the physical register of the second source operand of `instr2` cannot be released. The third group of 00 indicates that after the execution of the third assembly instruction following the release instruction (such as `instr3`), the physical register of the first source operand of `instr3` cannot be released, nor can the physical register of the second source operand of `instr3` be released. The fourth group of 11 indicates that after the execution of the fourth assembly instruction following the release instruction (such as `instr4`), the physical register of the first source operand of `instr4` can be released, and the physical register of the second source operand of `instr4` can also be released. Group 5 (00) indicates that after the execution of the fifth assembly instruction following this release instruction (e.g., `instr5`), the physical register of the first source operand of `instr5` cannot be released, nor can the physical register of the second source operand of `instr5` be released. Group 6 (10) indicates that after the execution of the sixth assembly instruction following this release instruction (e.g., `instr6`), the physical register of the first source operand of `instr6` can be released, but the physical register of the second source operand of `instr6` cannot be released. Group 7 (11) indicates that after the execution of the seventh assembly instruction following this release instruction (e.g., `instr7`), the physical register of the first source operand of `instr7` can be released, and the physical register of the second source operand of `instr7` can also be released. Group 8 (01) indicates that after the execution of the eighth assembly instruction following this release instruction (e.g., `instr8`), the physical register of the first source operand of `instr8` cannot be released, but the physical register of the second source operand of `instr8` can be released.

[0141] Thus, one release instruction can represent the release of the physical registers of the source operands of instN / 2 assembly instructions. Therefore, in practical applications, the first instruction obtained in step 901 is a release instruction, and thereafter, a release instruction is placed every instN / 2 assembly instructions, such as... Figure 13 As shown.

[0142] Whether the value corresponding to each assembly instruction in the release instruction is the fifth identifier (e.g., 1) or the sixth identifier (e.g., 1) is determined by the compiler based on whether the corresponding source operand is depended upon by other assembly instructions.

[0143] For example, if the first operand of an assembly instruction (such as `instr1`) is dependent on other assembly instructions, then after `instr1` is executed, its first operand cannot be released because it is still dependent on other assembly instructions. Therefore, the value of the first operand of an assembly instruction (such as `instr1`) in the release instruction is 0. If the second operand of an assembly instruction (such as `instr1`) is not dependent on other assembly instructions, then after `instr1` is executed, its second operand can be released early because it is not dependent on other assembly instructions. Therefore, the value of the second operand of an assembly instruction (such as `instr1`) in the release instruction is 1.

[0144] It should be noted that regardless of whether the instruction includes assembly instructions and pack instructions, or assembly instructions, release instructions, and pack instructions, the implementation process in step 901 is the same: fetch the instruction and place the fetched instruction into the instruction sequence (such as the Instr Queue). In other words, step 901 is only the process of fetching the instruction and placing it into the instruction sequence; it does not involve determining what type of instruction it is.

[0145] 902. According to the packing instruction, the assembly instructions in the instruction sequence are decoded into micro-operations to form a micro-operation sequence.

[0146] Step 902 can be implemented by instruction decoding module 102, which decodes the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence.

[0147] The decoding process adopts an existing process. This embodiment does not limit the implementation process of the instruction decoding module 102 decoding the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence.

[0148] 903, determine the micro-packet identifier of each micro-operation in the micro-operation sequence.

[0149] In practical implementation, while determining the micro-packaging identifier, the micro-dependency identifier of each micro-operation can also be determined.

[0150] Additionally, micro-operations, their micro-packaging identifiers, and micro-dependency identifiers can be placed into a micro-operation sequence (such as μopQueue).

[0151] Micro-packaging identifiers indicate whether micro-operations are in the same package; micro-operations with the same micro-packaging identifier are in the same package. Micro-dependency identifiers indicate whether the target operand of a micro-operation is dependent on by micro-operations outside the current micro-operation package.

[0152] For example, add two columns to a micro-operation sequence (such as a μops queue): one column stores the micro-packet identifier, and the other stores the micro-dependency identifier. The micro-packet identifier is stored in... Figure 14 The PL column in the database contains micro-dependency identifiers stored in... Figure 14 The OL column is defined in the table. The micro-packaging identifier is 2 bits, and the micro-dependency identifier is 1 bit. Therefore, the possible values ​​for the micro-packaging identifier are 00, 01, 10, and 11, while the possible values ​​for the micro-dependency identifier are 0 and 1.

[0153] 00 is set as the default value for the micro-packaging identifier (for ease of explanation, the default value for the micro-packaging identifier is named the first identifier). 0 is set as the default value for the micro-dependency identifier (for ease of explanation, the default value for the micro-dependency identifier is named the third identifier).

[0154] When determining the micro-packet identifier, it can be determined by the instruction packing module of the instruction decoding module 102 (such as...). Figure 15 The μopPackager implementation is used in this context.

[0155] Since the micro-package identifier is determined in addition to the micro-dependency identifier, the process of determining the micro-package identifier and the micro-dependency identifier will be explained below.

[0156] 1201, designates the first micro-operation in the current micro-operation sequence as the current micro-operation.

[0157] The micro-operation sequence is obtained from step 902.

[0158] The last micro-operation is the first to enter the micro-operation sequence and is also the oldest micro-operation, such as... Figure 15 μop21 in (the part).

[0159] 1202, The initial micro-operation package is empty.

[0160] If there is no micro-operation package currently, the process of initializing the micro-operation package to be empty is as follows: create a new empty micro-operation package, which contains 0 micro-operations.

[0161] If a micro-operation package already exists, the process of initializing the micro-operation package to be empty is as follows: clear all micro-operations in the micro-operation package.

[0162] 1203, determine whether the current micro-operation has side effects.

[0163] One of the side effects is causing CPU jumps or synchronization issues.

[0164] Micro-operations with side effects include ordinary jumps, jumps that can cause exceptions, and atomic operations, such as Load, Store, Branch, and others. Common micro-operations with side effects in the RISC-V (Reduced Instruction Set Computer Five) architecture include: LB, LH, SB, SH, JAL, BEQ, BLT, FENCE, ECALL, EBREAK, CSRRW, CSRRS, CSRRC, AMOSWAP.W, AMOADD.W, etc.

[0165] Micro-operations without side effects include, for example, data movement between registers, arithmetic operations, and logical shifts. Examples include MOV, ADD, and SHL.

[0166] 1204. If the current micro-operation has side effects, then the next micro-operation in the micro-operation sequence is determined as the current micro-operation, and the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps are repeated.

[0167] by Figure 15 Taking the micro-operation sequence shown (such as μops Queue) as an example, if the current micro-operation is μop21, and μop21 has side effects, then... Figure 15 In the micro-operation sequence shown (such as the μops Queue), the next micro-operation after μop21 (i.e., μop22) is determined as the current micro-operation. Step 1202 is re-executed to initialize the micro-operation package (e.g., clear all micro-operations in the micro-operation package) and subsequent steps.

[0168] Since the micro-operation package must not meet the packaging conditions before executing step 1204, the current micro-operation has side effects and the micro-operation package does not meet the packaging conditions at step 1204. At this time, the next micro-operation in the micro-operation sequence is determined as the current micro-operation, and all micro-operations in the micro-operation package are cleared to realize the initialization of the micro-operation package in step 1202 and subsequent steps.

[0169] 1205. If the current micro-operation has no side effects, determine whether the current micro-operation meets the inclusion condition. If the current micro-operation does not meet the inclusion condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps.

[0170] If the current micro-operation has no side effects, then: 1301, Determine whether the current micro-operation needs to be added to the micro-operation package. That is, determine whether the addition conditions are met.

[0171] The conditions for joining are as follows: The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is not depended upon by micro-operations outside the micro-operation package.

[0172] or, The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is depended upon by micro-operations outside the micro-operation package, and... .

[0173] in, This represents the number of micro-operations within the micro-operation package and the total number of current micro-operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations in the current micro-operation that depend on external operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations that the current micro-operation depends on externally. This is a preset second ratio. For example, .

[0174] or, The current micro-operation is not dependent on any micro-operations within the micro-operation package, nor is it dependent on any micro-operations outside the micro-operation package, and the number of micro-operations within the micro-operation package is less than a preset second value. For example, the second value is 4.

[0175] With the current micro-operation being μop8, the micro-operation package contains three micro-operations: μop9, μop10, and μop11. For example, the second value is 4: If μop8 is only dependent on μop11, then μop11 is dependent on micro-operations within the micro-operation package, and μop11 is not dependent on micro-operations outside the micro-operation package, thus satisfying the inclusion condition.

[0176] If μop8 is depended on by μop11 and also by μop7, and μop10 depends on μop7, μop9 is depended on by μop6, and μop11 depends only on μop8, then the micro-operations within the micro-operation package and the current micro-operation are μop8, μop9, μop10, and μop11. Within a micro-operation package, micro-operations that depend on external operations are denoted by μop10, and those that are depended upon by external operations are denoted by μop9. Therefore, micro-operations within the micro-operation package and micro-operations in the current micro-operation that depend on external operations are both denoted by μop10 (i.e., μop10). ), micro-operations within the micro-operation package and micro-operations that are externally dependent in the current micro-operation are μop9 and μop8 (i.e. At this point, μop8 is depended on by micro-operations within the micro-operation package, and also by micro-operations outside the micro-operation package, but... Therefore, it is determined that the conditions for joining are not met.

[0177] If μop8 is not dependent on μop11 or μop7, and the number of microoperations in the microoperation package is 3 < 4, then the inclusion condition is satisfied.

[0178] The dependencies between micro-operations are as follows: if the result of micro-operation μop13 is used by micro-operation μop15, then μop15 depends on μop13.

[0179] The dependencies of microinstructions are obtained based on existing methods; for example, dependencies are determined by microprogram sequence control fields. These sequence control fields (such as discrimination test fields) dynamically generate the address of the next microinstruction based on the program state and operation results, thereby determining the execution order of micro-operations.

[0180] 1302. If the current micro-operation does not meet the addition condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps.

[0181] Since the micro-operation package must not meet the packaging conditions before step 1302, the current micro-operation does not meet the addition conditions and the micro-operation package does not meet the packaging conditions in step 1302. At this time, the next micro-operation in the micro-operation sequence is determined as the current micro-operation, and all micro-operations in the micro-operation package are cleared to realize the initialization of the micro-operation package in step 1202 and subsequent steps.

[0182] 1303. If the current micro-operation meets the addition condition, add the current micro-operation to the micro-operation package. If the micro-operation package meets the packaging condition, determine the micro-packaging identifier and micro-dependency identifier of the micro-operations within the micro-operation package, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps. If the micro-operation package does not meet the packaging condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps.

[0183] Since the micro-operation package does not meet the packaging conditions before step 1303, in step 1303, the current micro-operation meets the addition conditions but the micro-operation package does not meet the packaging conditions. At this time: 1. Add the current micro-operation to the micro-operation package.

[0184] Taking the current micro-operation as μop8, and the micro-operation package containing 3 micro-operations, μop9, μop10, and μop11, as an example, after adding μop8 to the micro-operation package, the micro-operation package will contain 4 micro-operations, μop8, μop9, μop10, and μop11.

[0185] 2. Determine whether the micro-operation package meets the packaging requirements.

[0186] Among them, the packaging conditions are: ,and, .

[0187] in, This represents the number of microoperations within the microoperation package. This represents the number of micro-operations within the micro-operation package that depend on external operations. This represents the number of micro-operations within the micro-operation package that are externally dependent. The preset first value, such as , For the preset first ratio, such as .

[0188] The micro-operation package contains four micro-operations: μop8, μop9, μop10, and μop11. μop8 depends on μop7, μop10 depends on μop7, μop9 depends on μop6, and μop11 depends only on μop8. , For example, the number of micro-operations within a micro-operation package The micro-operation package that depends on external micro-operations is μop10, i.e. The microoperations within the microoperation package that are externally dependent are μop8 and μop9, i.e. . (Right now ),but If so, it is determined that the micro-operation package does not meet the packaging conditions.

[0189] 3. If the micro-operation package meets the packaging conditions, determine the micro-packaging identifier and micro-dependency identifier of the micro-operation within the micro-operation package, determine the next micro-operation of the current micro-operation in the micro-operation sequence as the current micro-operation, and repeat the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps.

[0190] The process of determining the micro-packaging identifier of micro-operations within a micro-operation package is as follows: all micro-packaging identifiers of micro-operations within the micro-operation package are set to the second identifier. The process of determining the micro-dependency identifier of micro-operations within a micro-operation package is as follows: the micro-dependency identifier of micro-operations within the micro-operation package that are depended upon by external entities (here, "external entities" refers to entities outside the package, not entities outside the micro-operation sequence) is set to the fourth identifier.

[0191] The second identifier is different from the first identifier, and the second identifier is also different from the alignment identifier. The first identifier is the initial value of the micro-packet identifier for any micro-operation. The alignment identifier is the micro-packet identifier in the micro-operation sequence that is closest to the micro-operation within the micro-operation package and is not the first identifier.

[0192] The fourth identifier is different from the third identifier. The third identifier is the initial value of the micro-dependency identifier for any micro-operation.

[0193] Although the micro-operation package does not meet the packaging conditions before executing step 1303, a new micro-operation will be added to the micro-operation package after executing step 1 of step 1303. When step 2 of step 1303 is executed, it is determined that the micro-operation package with the added new micro-operation meets the packaging conditions. Therefore, when step 3 of step 1303 is executed, the micro-operation package meets the packaging conditions. At this time, the micro-packaging identifier and micro-dependency identifier of the micro-operation in the micro-operation package will be determined, and then the next micro-operation will be processed.

[0194] Micro-packaging identifiers indicate whether micro-operations are in the same package. Micro-operations with the same micro-packaging identifier are in the same package, for example... Figure 15 The micropackaging identifiers for μop22, μop23, and μop24 are all 01, indicating that they are in one package.

[0195] Micro-operations in a micro-operation sequence (such as a μops queue) can occur in different packets. Since the micro-packet identifier can only take three values: 01, 10, and 11, for more than three packets, there may be cases where two packets use the same micro-packet identifier. To distinguish between different packets with the same micro-packet identifier, this embodiment determines that the micro-packet identifier cannot be the same as the default value of the micro-packet identifier (such as 00), nor can it be the same as its adjacent micro-packet identifier.

[0196] The micro-dependency flag indicates whether the target operand of a micro-operation is dependent on by micro-operations outside the current micro-operation package, for example... Figure 15 The micro-dependency flag for μop23 and μop24 is 1, indicating that the target operands generated by μop23 and μop24 are dependent on micro-operations outside the package whose micro-packing flag is 01, and therefore the physical registers of the target operands of these micro-operations cannot be released. For example... Figure 15 If the micro-dependency flag of μop22 is 0, it means that the target operands generated by these micro-operations are local variables of the package with the micro-packet flag of 01. The physical registers of the target operands of these micro-operations can be released after the package with the micro-packet flag of 01 is graduated.

[0197] If we name the micro-dependency identifier of a micro-operation within a micro-operation package that is externally dependent (here, "external" means outside the package, not outside the micro-operation sequence) as the fourth identifier, and the initial value of the micro-dependency identifier (i.e., the default value, such as 0) as the third identifier, then in order to distinguish whether it is dependent on a micro-operation that is externally dependent, the fourth identifier must be 1. Therefore, the fourth identifier is different from the third identifier.

[0198] Taking a micro-operation package that meets the packaging conditions and contains three micro-operations, μop22, μop23, and μop24, where μop22 is dependent on μop23, μop23 is dependent on μop27, and μop24 is dependent on μop26 as an example, in this step, the micro-packaging identifiers of μop22, μop23, and μop24 are all determined to be 01, the micro-dependency identifiers of μop23 and μop24 are all determined to be 1, and the micro-dependency identifier of μop23 is determined to be 0. Figure 15 As shown.

[0199] Then, the next micro-operation (i.e., μop25) of the current micro-operation (i.e., μop24) in the micro-operation sequence is determined as the current micro-operation. All micro-operations in the micro-operation package are cleared (i.e., μop22, μop23, and μop24 in the micro-operation package are cleared, and the micro-operation package is empty at this time) to realize the initialization of the micro-operation package in step 1202 and subsequent steps.

[0200] 4. If the micro-operation package does not meet the packaging conditions, the next micro-operation in the current micro-operation sequence is determined as the current micro-operation, and the step of initializing the micro-operation package to be empty (i.e., step 1202) and subsequent steps are repeated.

[0201] Although the micro-operation package does not meet the packaging conditions before executing step 1303, a new micro-operation will be added to the micro-operation package after executing step 1 of step 1303. In step 2 of step 1303, it is determined that the micro-operation package with the added new micro-operation does not meet the packaging conditions. Therefore, in step 4 of step 1303, the micro-operation package does not meet the packaging conditions. At this time, the next micro-operation in the current micro-operation sequence is determined as the current micro-operation, and all micro-operations in the micro-operation package are cleared to realize the initialization of the micro-operation package in step 1202 and subsequent steps.

[0202] Furthermore, when determining the next micro-operation in the micro-operation sequence as the current micro-operation, if the current micro-operation is the first micro-operation in the micro-operation sequence (e.g., μops Queue)... Figure 15 If μop31 is added to the micro-operation sequence (such as μops Queue), execution will be paused until a new micro-operation is added to the micro-operation sequence. Then, the newly added micro-operation will be used as the next micro-operation of the current micro-operation, and thus the newly added micro-operation will be determined as the current micro-operation.

[0203] In addition, in the specific implementation, the instruction execution counter can be initialized to 0 (the instruction execution counter is used to determine the sequence number of the first package instruction in the instruction sequence). The instruction execution counter is used to count the number of consecutive assembly instructions. That is, when the instruction decoding module 102 obtains the first instruction from the instruction sequence, the instruction execution counter is incremented by 1 every time an assembly instruction is obtained, until the package instruction is obtained for the first time, after which the instruction execution counter is no longer updated.

[0204] If no packing instruction is obtained and the instruction execution counter value has not reached the preset number of instructions (e.g., 1000), the micro-packing identifier of each assembly instruction is determined to be the first identifier (i.e., the default value, e.g., 00), and the micro-dependency identifier of each assembly instruction is determined to be the third identifier (i.e., the default value, e.g., 0). If the instruction execution counter value reaches the preset number of instructions (e.g., 1000) and no packing instruction is obtained, the instruction decoding module 102 uses the above method to determine the micro-packing identifier and the micro-dependency identifier (i.e., steps 1201-1205).

[0205] If a packaging instruction is obtained, and the value of the instruction execution counter does not reach the preset number of entries (e.g., 1000), then the micro-packaging identifier and micro-dependency identifier will no longer be determined by the above method (i.e., steps 1201-1205), but will be determined based on the packaging instruction.

[0206] The process for determining whether an instruction is a packaging instruction is as follows: After the instruction decoding module 102 acquires an instruction in step 902 (for ease of description, the acquired instruction is defined as the currently processed instruction), the information extractor of the instruction decoding module 102 (such as...) Figure 16 The PackageInfoExtracter extracts the last 3 bits of the current processing instruction.

[0207] The packaging instructions include length information (such as...) Figure 10 Len in the package), instruction dependency identifiers of each assembly instruction in the package (such as Len), and instruction dependency identifiers of each assembly instruction in the package (such as Len). Figure 10 OutputLabel in the command identifier (such as OutputLabel) Figure 10 PackagedMark in the middle.

[0208] Among them, the instruction identifier (such as Figure 10 The PackagedMark in the instruction occupies 3 bits and is used to indicate whether the instruction is a package instruction.

[0209] If the last 3 bits of the instruction are not special values ​​(such as XXX), then the current instruction being processed is determined to be an assembly instruction; if the last 3 bits of the instruction are special values ​​(such as XXX), then the current instruction being processed is determined to be a packing instruction.

[0210] The implementation process is as follows: 1. When the instruction execution counter value has not reached the preset threshold (e.g., 1000): ① In step 902, each instruction obtained by the instruction decoding module 102 is treated as the current instruction to be processed, and the instruction execution counter is incremented by 1. It then determines whether the last 3 bits of the current instruction to be processed are a special value (such as XXX).

[0211] ② If the last 3 bits of the current processing instruction are not special values ​​(such as XXX), then the current processing instruction is determined to be an assembly instruction. In this case, the micro-packet identifier of the micro-operation obtained by decoding the current processing instruction is determined to be the first identifier (such as 00), and the micro-dependency identifier is determined to be the third identifier (such as 0).

[0212] ③ If the last 3 bits of the current processing instruction are special values ​​(such as XXX), then the current processing instruction is determined to be a packing instruction. At this time, the instruction execution counter will not be updated, nor will the relationship between the instruction execution counter and the number of instructions threshold (such as 1000) be judged. Instead, the micro-packing identifier and micro-dependency identifier will be determined directly based on the packing instruction.

[0213] 2. When the value of the instruction execution counter reaches the preset number of records threshold (e.g., 1000), the instruction execution counter will no longer be updated, nor will the relationship between the instruction execution counter and the number of records threshold (e.g., 1000) be determined. Instead, the micro-packaging identifier and micro-dependency identifier will be determined directly through the above method (i.e., steps 1201-1205).

[0214] The process of determining the micro-packing identifier and micro-dependency identifier based on the packaging instructions is as follows: 1. Information extractor of instruction decoding module 102 (e.g.) Figure 16 The PackageInfo Extractor extracts length information (such as...) from the packaging instructions. Figure 10 Len (in the middle).

[0215] 2. Determine that the micro-packing identifiers of the micro-operations of the consecutive Len assembly instructions following the packing instruction are all the same value (for ease of description, this value is named the second identifier, which is different from the first identifier), and determine that the micro-dependency identifiers of the micro-operations of the consecutive Len assembly instructions following the packing instruction are the instruction dependency identifiers of the currently processed instruction.

[0216] 3. After obtaining the (Len+1)th instruction after the current processing instruction in step 902, the instruction decoding module 102 determines the (Len+1)th instruction after the current processing instruction as the new current processing instruction. The information extractor of the instruction decoding module 102 (such as...) Figure 16The PackageInfo Extractor in the instruction decoder extracts the last 3 bits of the new current instruction. It then repeats the process, using the last 3 bits to determine if the new current instruction is a packaged instruction. If it is not a packaged instruction, the micro-package identifier of the micro-operation obtained from the decoded current instruction is set as the first identifier (e.g., 00), and the micro-dependency identifier is set as the third identifier (e.g., 0). If it is a packaged instruction, the information extractor in the instruction decoder module 102 (e.g., ...) extracts the last 3 bits of the new current instruction. Figure 16 The PackageInfo Extractor extracts length information (such as...) from the packaging instructions. Figure 10 The steps and subsequent steps of Len in the text.

[0217] Micro-operations in a micro-operation sequence (such as a μops queue) can occur in different packets. Since the micro-packet identifier can only take three values: 01, 10, and 11, for more than three packets, there may be cases where two packets use the same micro-packet identifier. To distinguish between different packets with the same micro-packet identifier, this embodiment determines that the micro-packet identifier cannot be the same as the default value of the micro-packet identifier (such as 00), nor can it be the same as its adjacent micro-packet identifier.

[0218] If we name the micro-packet identifier of the micro-operation to be determined as the second identifier (e.g., the micro-packet identifiers of μop5 and μop6 are both the second identifier), the initial value of the micro-packet identifier (i.e., the default value, such as 00) is named the first identifier, and the micro-packet identifier that is closest to the micro-operation in the micro-operation packet and is not the first identifier (i.e., its adjacent micro-packet identifier, such as...) is named the first identifier. Figure 16 If the 01 of μop1-μop4 is named the alignment identifier, then the second identifier is different from the first identifier, and the second identifier is different from the alignment identifier.

[0219] In other words, the micro-packet identifiers for micro-operations corresponding to the same package are all the second identifier. The second identifier is different from the first identifier, and also different from the alignment identifier. The first identifier is the initial value of the micro-packet identifier for any micro-operation. The alignment identifier is the micro-packet identifier in the micro-operation sequence that is closest to the micro-operation corresponding to the same package and is not the first identifier.

[0220] by Figure 16 For example, let's further explain the process of determining the micro-packaging identifier and micro-dependency identifier based on the packaging instructions: 1. After the instruction decoding module 102 obtains the first instruction (i.e., Package Instr1) from the instruction sequence, it determines that the currently processed instruction is Package Instr1, such as... Figure 16 As shown, the first 4 bits are Len, the last 3 bits are PackagedMark, and the middle 9 bits are OutputLabel.

[0221] 2. The information extractor of the instruction decoding module 102 extracts the PackageMark of Package Instr1, thereby determining that Package Instr1 is a package instruction. The instruction decoding module 102 determines that the subsequent three instructions (i.e., decimal 3 represented by binary 0011) are assembly instructions in the same package based on the Len extracted from Package Instr1 by the information extractor. It is determined that the micro-packaging identifiers of the micro-operations of the first assembly instruction (i.e., instr1), the second assembly instruction (i.e., instr2), and the third assembly instruction (i.e., instr3) following Package Instr1 are all the same. Based on the first bit of the OutputLabel of Package Instr1 extracted by the information extractor, the micro-dependency flag of the micro-operation of the first assembly instruction (i.e., instr1) after Package Instr1 is determined to be 0. Based on the second bit of the OutputLabel of Package Instr1 extracted by the information extractor, the micro-dependency flag of the micro-operation of the second assembly instruction (i.e., instr2) after Package Instr1 is determined to be 0. Based on the third bit of the OutputLabel of Package Instr1 extracted by the information extractor, the micro-dependency flag of the micro-operation of the third assembly instruction (i.e., instr3) after Package Instr1 is determined to be 1.

[0222] If instruction decoding module 102 decodes instr1 to µop1, instr2 to µop2, and instr3 to µop3 and µop4, then the micro-packet identifiers of µop1, µop2, µop3, and µop4 are all determined to be 01, the micro-dependency identifier of µop1 is 0, the micro-dependency identifier of µop2 is 0, and the micro-dependency identifiers of µop3 and µop4 are both 1. Figure 16 As shown.

[0223] 3. When the instruction decoding module 102 obtains the 3+1 (i.e., Len+1) = 4th instruction (i.e., Package Instr2) after Package Instr1 from the instruction sequence, it determines that the current instruction to be processed is Package Instr2, such as... Figure 16 As shown, the first 4 bits are Len, the last 3 bits are PackagedMark, and the middle 9 bits are OutputLabel.

[0224] 4. The information extractor of the instruction decoding module 102 extracts the PackageMark of Package Instr2, thereby determining that Package Instr2 is a package instruction. The instruction decoding module 102 determines that the subsequent two instructions (i.e., decimal 2 represented by binary 0010) are assembly instructions in the same package based on the Len extracted from Package Instr2 by the information extractor. It is determined that the micro-packaging identifiers of the micro-operations of the first assembly instruction (i.e., instr4) and the second assembly instruction (i.e., instr5) following Package Instr2 are identical. Based on the first bit of the OutputLabel extracted from Package Instr2 by the information extractor, the micro-dependency identifier of the micro-operation of the first assembly instruction (i.e., instr4) following Package Instr2 is determined to be 0. Based on the second bit of the OutputLabel extracted from Package Instr2 by the information extractor, the micro-dependency identifier of the micro-operation of the second assembly instruction (i.e., instr5) following Package Instr2 is determined to be 0.

[0225] If instruction decoding module 102 decodes instr4 into µop5 and instr5 into µop6, then it determines that the micro-packet identifiers of µop5 and µop6 are both 10, the micro-dependency identifier of µop5 is 0, and the micro-dependency identifier of µop6 is 0. Figure 16 As shown.

[0226] 5. When the instruction decoding module 102 obtains the 2nd + 1st (i.e., Len + 1) = 3rd instruction (i.e., instr6) after Package Instr2 from the instruction sequence, it determines that the current instruction to be processed is instr6, such as... Figure 16 As shown.

[0227] 6. The information extractor of instruction decoding module 102 extracts the last 3 bits of instr6. If they are not XXX, then instr6 is determined to be an assembly instruction. Therefore, the micro-packet identifier of the micro-operation of instr6 is determined to be 00, and the micro-dependency identifier of the micro-operation of instr6 is determined to be 0.

[0228] If instruction decoding module 102 decodes instr6 into µop7, then the micro-packet identifier of µop7 is determined to be 00, and the micro-dependency identifier of µop7 is determined to be 0. Figure 16 As shown.

[0229] 7. When the instruction decoding module 102 obtains the instruction following instr6 (i.e., instr7) from the instruction sequence, it determines that the current instruction to be processed is instr7, such as... Figure 16 As shown.

[0230] 8. The information extractor of instruction decoding module 102 extracts the last 3 bits of instr7. If they are not XXX, then instr7 is determined to be an assembly instruction. Therefore, the micro-packet flag of the micro-operation of instr7 is determined to be 00, and the micro-dependency flag of the micro-operation of instr7 is determined to be 0.

[0231] If instruction decoding module 102 decodes instr7 into µop8, then the micro-packet identifier of µop8 is determined to be 00, and the micro-dependency identifier of µop8 is determined to be 0. Figure 16 As shown.

[0232] 9. When the instruction decoding module 102 obtains the instruction following instr7 (i.e., instr8) from the instruction sequence, it determines that the current instruction to be processed is instr8, such as... Figure 16 As shown.

[0233] 10. The information extractor of instruction decoding module 102 extracts the last 3 bits of instr8. If they are not XXX, then instr8 is determined to be an assembly instruction. Therefore, the micro-packet identifier of the micro-operation of instr8 is determined to be 00, and the micro-dependency identifier of the micro-operation of instr8 is determined to be 0.

[0234] If instruction decoding module 102 decodes instr8 into µop9, µop10, and µop11, then it determines that the micropacket identifiers of µop9, µop10, and µop11 are all 00, and the micro-dependency identifiers of µop9, µop10, and µop11 are all 0. Figure 16 As shown.

[0235] The process of determining micro-packing identifiers and micro-dependency identifiers based on packing instructions can be aided by the compiler. Packing instructions are inserted into the generated assembly instructions. These packing instructions are used to mark the start of packing assembly instructions from the next instruction. The packing instructions also record the length of the pack and the OutputLabel of each instruction in the packing instructions. By inserting specific packing instructions into the assembly instructions, the design logic of the packer in the processor can be simplified and the processing speed can be improved.

[0236] It should be noted that, regardless of the method used to determine the micro-packet identifier and micro-dependency identifier, this embodiment does not limit the order of its execution process with the decoding process in step 902. The micro-packet identifier and micro-dependency identifier can be determined simultaneously with decoding, or they can be determined first and then decoded. The micro-packet identifier and micro-dependency identifier can be determined as long as the instruction decoding module 102 obtains a certain instruction in step 902.

[0237] In addition, micro-operation sequences (such as μops Queue) may include source register release identifiers in addition to micro-packing identifiers and micro-dependency identifiers for each micro-operation.

[0238] The source register release flag of a micro-operation is used to indicate whether the physical register of the corresponding source operand can be released after the micro-operation is executed.

[0239] If the instruction includes a release instruction, the source register release flag can be determined based on the release instruction. If the instruction does not include a release instruction, the source register release flag can be determined based on the micro-operation.

[0240] In specific implementation, whenever the instruction decoding module 102 obtains an instruction in step 901, if the instruction is a release instruction, the source register release flag of the micro-operation corresponding to the subsequent instN / 2 assembly instructions is determined based on the release instruction. If the instruction is an assembly instruction and is not involved in any release instruction, the source register release flag is determined based on the micro-operation corresponding to the assembly instruction.

[0241] The two implementation methods are explained below.

[0242] Determine the source register release flag based on the release instruction. Since the release instruction indicates whether the corresponding register is released after the assembly instruction is executed, and the assembly instruction is decoded into a micro-operation in step 902, and this micro-operation corresponds to the assembly instruction, whether the physical register of the source operand of the assembly instruction can be released is equivalent to whether the physical register of the source operand of the micro-operation of that assembly instruction can be released. Therefore, the value of the g-th 2-bit of any release instruction is the same as the source register release flag of the micro-operation corresponding to the g-th assembly instruction following any release instruction.

[0243] In practical implementation, the release extractor of the instruction decoding module 102 can extract information from each release instruction, and the instruction decoding module 102 can obtain the source register release flag of each micro-operation based on the extracted information. For example Figure 13As shown, if assembly instruction 1 (e.g., instr1) is decoded as μop1 in step 902, the release extractor of instruction decoding module 102 extracts the information in the release instruction, where 01 corresponds to instr1. Then the source register release flag of μop1 is also 01. If assembly instruction 2 (e.g., instr2 r2, r3, r4, where r2 and r3 are source registers) is decoded as μop2 (e.g., μop2 r2, r4, where r2 is the source operand and r4 is the destination operand) and μop3 (e.g., μop3 r3, r4, where r3 is the source operand and r4 is the destination operand) in step 902, whether r2 can be released after μop2 is executed depends on the value of the first bit of the two bits corresponding to assembly instruction 2 in the release instruction, and whether r3 can be released after μop3 is executed depends on the value of the second bit of the two bits corresponding to assembly instruction 2 in the release instruction. For example, the release extractor of instruction decoding module 102 extracts information from the release instruction, where 00 corresponds to instr2. Therefore, the first bit of the source register release flag of μop2 is 0 (this 0 is the first bit 0 in the 00 obtained from the release instruction). Since μop2 has only one source operand, the second bit of the source register release flag of μop2 is filled with a default value (such as 0) because there is no source operand, resulting in a source register release flag of μop2 being 00. Similarly, the first bit of the source register release flag of μop3 is 0 (this 0 is the second bit 0 in the 00 obtained from the release instruction). Since μop3 has only one source operand, the second bit of the source register release flag of μop3 is filled with a default value (such as 0) because there is no source operand, resulting in a source register release flag of μop3 being 00. Therefore, the source register release flag is a 2-bit flag, with each bit corresponding to whether the physical register of one source operand can be released. The value of this bit is the same as the value corresponding to the source operand in the release instruction.

[0244] Two columns of memory source register release flags can be added to micro-operation sequences (such as μops Queue), such as... Figure 17 In the instruction sequence, SL1 (occupying 1 bit) and SL2 (occupying 1 bit) represent whether the physical register of the first source operand can be freed, and SL2 represents whether the physical register of the second source operand can be freed. The process of forming a micro-operation sequence from an instruction sequence is as follows: Figure 18 As shown, the release extractor of the instruction decoding module 102 (such as...) Figure 18 The SrcRegReleaseExtracter extracts the release instruction information. The instruction decoding module 102 decodes the assembly instructions in the instruction sequence (such as Instr Queue) into micro-operations, and then extracts them according to the release extractor (such as SrcRegReleaseExtracter). Figure 18The information extracted by the SrcRegRelease Extractor determines the source register release flag for each micro-operation, forming a micro-operation sequence (such as a μops queue).

[0245] The source register release flag provided in this embodiment is achieved by inserting release instructions in the assembler and adding a release extractor (such as...) to the CPU. Figure 18 The SrcRegRelease Extractor is identified.

[0246] If the value of SL1 for a micro-operation is 1, it means that the physical register of the first source operand can be released early after the micro-operation is completed. If the value of SL1 is 0, it means that the physical register of the first source operand cannot be released early after the micro-operation is completed. If the value of SL2 for a micro-operation is 1, it means that the physical register of the second source operand can be released early after the micro-operation is completed. If the value of SL2 is 0, it means that the physical register of the second source operand cannot be released early after the micro-operation is completed.

[0247] The source register release flag is two bits because most micro-operations have only two source operands, and the two bits of the source register release flag correspond to the two source operands respectively, which can cover the source operands of most micro-operations. If there are three source operands, it is only necessary to mark whether the first two source operands can be released early.

[0248] Each time a micro-operation is obtained in step 902, its source register release flag is determined and added to the micro-operation sequence. Simultaneously with determining its source register release flag and adding it to the micro-operation sequence, the next micro-operation is obtained, thus forming a process where the micro-operations for determining the instruction sequence and the determination of their source register release flags are executed in parallel.

[0249] Determine the source register release flag based on the micro-operation. If any micro-operation involves at least two source operands, the source register release flag is used to indicate whether the registers corresponding to the first two source operands are released after any micro-operation is executed.

[0250] The source register release flag is two bits. The first bit indicates whether the register corresponding to the first source operand is released after the execution of any micro-operation. The second bit indicates whether the register corresponding to the second source operand is released after the execution of any micro-operation.

[0251] If the fifth flag (e.g., 1) indicates that any micro-operation can release the physical register of its corresponding source operand after execution, and the sixth flag (e.g., 0) indicates that any micro-operation cannot release the physical register of its corresponding source operand after execution, then for any micro-operation (e.g., μop10), if the first source operand is dependent on other micro-operations, then after μop10 is executed, its first source operand cannot be released because it is still dependent on other micro-operations. Therefore, the first bit of the source register release flag for any micro-operation (e.g., μop10) is 0. If the second source operand of any micro-operation (e.g., μop10) is not dependent on other micro-operations, then after μop10 is executed, its second source operand can be released early because it is not dependent on other micro-operations. Therefore, the second bit of the source register release flag for any micro-operation (e.g., μop10) is 1.

[0252] Two columns of memory source register release flags can be added to micro-operation sequences (such as μops Queue), such as... Figure 17 In the SL1 (occupying 1 bit) and SL2 (occupying 1 bit), SL1 is used to indicate whether the physical register of the first source operand can be released, and SL2 is used to indicate whether the physical register of the second source operand can be released.

[0253] In specific implementation, the release analysis module of instruction decoding module 102 (such as...) Figure 19 The Source Register Release Analyzer determines whether the first and second source operands of each micro-operation can be released after the micro-operation is executed, and then obtains the corresponding source register release flag, which is then filled into SL1 and SL2.

[0254] If the value of SL1 for a micro-operation is 1, it means that the physical register of the first source operand can be released early after the micro-operation is completed. If the value of SL1 is 0, it means that the physical register of the first source operand cannot be released early after the micro-operation is completed. If the value of SL2 for a micro-operation is 1, it means that the physical register of the second source operand can be released early after the micro-operation is completed. If the value of SL2 is 0, it means that the physical register of the second source operand cannot be released early after the micro-operation is completed.

[0255] The source register release flag is two bits because most micro-operations have only two source operands, and the two bits of the source register release flag correspond to the two source operands respectively, which can cover the source operands of most micro-operations. If there are three source operands, it is only necessary to mark whether the first two source operands can be released early.

[0256] Each time a micro-operation is obtained in step 902, its source register release flag is determined and added to the micro-operation sequence. Simultaneously with determining the source register release flag and adding it to the micro-operation sequence, step 902 obtains the next micro-operation. This results in step 902 executing the process of decoding the assembly instructions in the instruction sequence into micro-operations and determining the source register release flag in parallel.

[0257] In addition, micro-operation sequences (such as μops Queue) may include delay flags in addition to the source register release flags for each micro-operation.

[0258] The delay flag of a micro-operation indicates how many cycles after which the micro-operation can be dispatched. The delay flag of a micro-operation is determined by the execution time of the latest dispatched micro-operation that the micro-operation depends on. This delay flag is continuously updated in subsequent processing (once per cycle), and the delay flag is determined and updated for micro-operations newly added to the micro-operation sequence.

[0259] It should be noted that the delay flag is obtained after the assembly instructions are decoded into micro-operations in step 902, and the delay flag is stored in the micro-operation sequence.

[0260] The implementation process of the delay flag is as follows: When any micro-operation is placed into the micro-operation sequence, the instruction decoding module 102 determines whether all other micro-operations that the micro-operation depends on have been dispatched. If all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be the minimum value. If all other micro-operations have not been dispatched, the delay flag of the micro-operation is determined to be the maximum value.

[0261] In other words, when any micro-operation of any assembly instruction is obtained in step 902, it is determined whether all other micro-operations that the micro-operation depends on have been dispatched. If all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be at its minimum value. If all other micro-operations have not been dispatched, the delay flag of the micro-operation is determined to be at its maximum value.

[0262] For example, add a column for storing delay identifiers in a micro-operation sequence (such as a μops queue). The delay identifiers are stored in... Figure 20 The `DelayCycle` column is defined in the image. The delay flag occupies 3 bits, allowing for 8 possible values: 000 (0), 001 (1), 010 (2), 011 (3), 100 (4), 101 (5), 110 (6), and 111 (7). The minimum value is 0, and the maximum value is 7.

[0263] The dependencies between micro-instructions are implemented by constructing a Directed Acyclic Graph (DAG) using existing methods. Whenever a micro-operation is added to a sequence of micro-operations (such as a μops queue), a vertex is added to the DAG, corresponding to the added micro-operation. Then, edges are formed based on the dependencies between the added micro-operation and other micro-operations. For example... Figure 21 As shown, μop15 depends on μop13, and μop15 in Figure 21 The corresponding point B5, μop13 is in Figure 21 If the corresponding point is B3, then there is an edge between B3 and B5 pointing from B3 to B5. Thus, a DAG graph can represent all micro-operations and dependencies in a sequence of micro-operations (such as μopsQueue).

[0264] The DAG graph is used to determine all other micro-operations that any micro-operation depends on, and thus whether all other micro-operations have been dispatched.

[0265] Taking step 902 as an example, if any micro-operation is obtained as micro-operation 31, the instruction decoding module 102 determines all other micro-operations that micro-operation 31 depends on (such as micro-operation 32 and micro-operation 33), and determines whether micro-operation 32 has been dispatched and whether micro-operation 33 has been dispatched.

[0266] If micro-operation 32 has been dispatched and micro-operation 33 has been dispatched, meaning all other micro-operations have been dispatched, then the delay flag for micro-operation 32 is determined to be the minimum value (e.g., 0).

[0267] If micro-operation 32 has been dispatched but micro-operation 33 has not been dispatched, or micro-operation 32 has not been dispatched but micro-operation 33 has been dispatched, or micro-operation 32 has not been dispatched and micro-operation 33 has not been dispatched, i.e., all other micro-operations have not been dispatched, then the delay flag of micro-operation 32 is determined to be the maximum value (e.g., 7).

[0268] In addition, the instruction decoding module 102 updates the delay flag of each micro-operation in the micro-operation sequence (such as the μops Queue) in each cycle. For example, in each cycle, the delay flag of the second processing micro-operation in the micro-operation sequence is decremented by 1. The delay flag of the second processing micro-operation is greater than the minimum value + 1, and the delay flag of the second processing micro-operation is less than the maximum value.

[0269] If the minimum value is 0 and the maximum value is 7, the delay identifier of each micro-operation in the current period's micro-operation sequence (such as the μops Queue) is as follows: Figure 20As shown, 1 < the delay flag of the second processing micro-operation < 7. Therefore, in the next cycle, the delay flags of μop2, μop3, μop4, μop5, μop7, μop8, μop10, and μop11 are all greater than 1 and less than 7. Since μop2, μop3, μop4, μop5, μop7, μop8, μop10, and μop11 are the second processing micro-operations, in the next cycle, the delay flags of μop2, μop3, μop4, μop5, μop7, μop8, μop10, and μop11 will all be decremented by 1 to obtain new delay flags, as shown below. Figure 22 As shown.

[0270] This process does not update the delay flag when it is 0 because 0 is the minimum value, indicating that it is ready to be dispatched at any time. The delay flag when it is 7 is not updated because the micro-operations that this micro-operation depends on have not yet been dispatched; it will be updated after all dependent micro-operations have been dispatched.

[0271] Furthermore, whenever a micro-operation is dispatched in the micro-operation sequence (such as the μops Queue), the instruction decoding module 102 also updates the delay flag of each micro-operation in the micro-operation sequence (such as the μops Queue). For example, when any micro-operation in the micro-operation sequence is dispatched, it is determined whether a first processing micro-operation exists in the micro-operation sequence, wherein the first processing micro-operation depends on any micro-operation. If a first processing micro-operation exists, and all other micro-operations that the first processing micro-operation depends on have been dispatched, then the delay flag of the first processing micro-operation is determined to be the number of cycles required to execute any micro-operation.

[0272] Taking micro-operation 34 in the micro-operation sequence dispatched by instruction dispatch module 103 as an example, if none of the micro-operations in the current micro-operation sequence depend on micro-operation 34, then the delay flag of each micro-operation in the micro-operation sequence will not be updated. If micro-operation 35 in the current micro-operation sequence depends on micro-operation 34, then micro-operation 35 is the first micro-operation to be processed.

[0273] If micro-operation 35 (i.e., the first processing micro-operation) depends on micro-operations 34 and 36, but micro-operation 36 is not dispatched, then all other micro-operations that micro-operation 35 (i.e., the first processing micro-operation) depends on have not been dispatched, and the delay flag of micro-operation 35 (i.e., the first processing micro-operation) will not be updated in this case.

[0274] If micro-operation 35 (i.e., the first processing micro-operation) depends on micro-operations 34 and 36, and micro-operation 36 has been dispatched, then all other micro-operations that micro-operation 35 (i.e., the first processing micro-operation) depends on have been dispatched. At this time, micro-operation 34 is the latest dispatched micro-operation that micro-operation 35 depends on. The delay flag of micro-operation 34 is updated to the number of cycles (i.e., execution time) of executing micro-operation 34 (i.e., any micro-operation).

[0275] For example, when the dispatch queue is not full, the instruction dispatch module 103 selects one or more micro-operations from all micro-operation sequences (such as the μops queue) whose delay flag (such as DelayCycle) is equal to 0 and has the oldest history, and places these selected micro-operations into the dispatch queue for dispatch. After a micro-operation A is dispatched, all micro-operations that depend on it are scanned. If all other micro-operations that a scanned micro-operation B depends on have already been dispatched, the DelayCycle value of the scanned micro-operation B is changed from 7 to the execution cycle of micro-operation A (which is an integer less than 7). In subsequent cycles, the DelayCycle of micro-operation B is decremented each cycle. When the DelayCycle of micro-operation B is set to 0, it indicates that micro-operation B is ready and can be dispatched in the next cycle after the update.

[0276] By adding a delay flag (such as DelayCycle) to each micro-operation in the micro-operation sequence (such as μops Queue), the instruction dispatch module 103 (such as...) Figure 23 The Dispatch Unit in the system can precisely dispatch ready micro-operations, preventing too many micro-operations from being prematurely placed into the Dispatch Queue. This improves the utilization of the Dispatch Queue, avoiding the blocking of ready micro-operations by having unready micro-operations enter the Dispatch Queue prematurely.

[0277] In this embodiment, the delay flag indicates how many cycles are left before the corresponding micro-operation can be dispatched. If the delay flag is the minimum value (e.g., 0), it means that it is ready to be dispatched at any time. If the delay flag is the maximum value (e.g., 7), it means that it cannot be dispatched (because the other micro-operations it depends on have not been dispatched). If the delay flag is between the minimum and maximum values, then the delay flag indicates how many cycles are left before the micro-operation can be dispatched.

[0278] Furthermore, in the specific implementation, if the latency flag of a micro-operation is 0 and the dispatch queue (DispatchQueue) is not full, the micro-operation can be immediately placed into the dispatch queue (Dispatch Queue) for dispatch instead of being added to the micro-operation sequence (e.g., μops Queue). If the latency flag of a micro-operation is 0, but the dispatch queue (Dispatch Queue) is full, the micro-operation will be placed into the micro-operation sequence (e.g., μops Queue) to await dispatch. If the latency flag of a micro-operation is not 0, the micro-operation will be placed into the micro-operation sequence (e.g., μops Queue).

[0279] 904, Dispatch of micro-operations based on micro-packaging identifiers.

[0280] Step 904 can be implemented by the instruction dispatch module 103. In specific implementation, the instruction dispatch module 103 dispatches micro-operations based on the delay flag.

[0281] ① If the micro-packet identifier and micro-dependency identifier of each micro-operation are determined in step 902, but the delay identifier is not determined (in this case, it is not limited whether each micro-operation has a source register release identifier, that is, regardless of whether the source register release identifier of each micro-operation is determined in step 902, dispatch is performed through this process), then the micro-operation only has a micro-packet identifier and a micro-dependency identifier, or, the micro-operation only has a source register release identifier, a micro-packet identifier, and a micro-dependency identifier. Then, in step 904, when the dispatch queue is not full, the instruction dispatch module 103 will select the oldest micro-operation (e.g., Figure 14 The selected micro-operation (μop1) and all micro-operations with the same micro-package identifier are packaged and placed into the dispatch queue for dispatch.

[0282] like Figure 14 As shown, the instruction dispatch module 103 selects micro-operations that meet the execution conditions from the micro-operation sequence (such as μops Queue) as μop1. The micro-packaging identifier of μop1 is 01. Then, μop1, μop2, μop3 and μop4 with micro-packaging identifier 01 are packaged and dispatched.

[0283] The packaging process has no requirements for the running binary code or the compiler; it is a packaging operation performed by the CPU's internal hardware during execution.

[0284] ② If the delay identifier, micro-packing identifier, and micro-dependency identifier of each micro-operation are determined in step 902 (in this case, it is not limited whether each micro-operation has a source register release identifier, that is, regardless of whether the source register release identifier of each micro-operation is determined in step 902, dispatch is carried out through this process), then the micro-operation value has at least a source register release identifier, a micro-packing identifier, and a micro-dependency identifier. In step 904, when the dispatch queue is not full, the instruction dispatch module 103 will dispatch the third processing micro-operation and the fourth processing operation in the micro-operation sequence. For example, the instruction dispatch module 103 packs the third processing micro-operation and the fourth processing micro-operation into the dispatch queue for dispatch.

[0285] Among them, the delay identifier of the third processing micro-operation is the minimum value, and the third processing micro-operation is the oldest among all micro-operations with the minimum delay identifier.

[0286] The micro-packaging identifier of the fourth processing micro-operation is the same as that of the third processing micro-operation.

[0287] When dispatching, the micro-operation with the minimum delay value (e.g., 0) and other micro-operations in its packet are selected for dispatch. If there is only one micro-operation with the minimum delay value (e.g., 0), it will be treated as the third-processed micro-operation. If there are multiple micro-operations with the minimum delay value (e.g., 0), the oldest one (i.e., the one earliest placed in the micro-operation sequence (e.g., μops Queue)) will be selected as the third-processed micro-operation (e.g., ...). Figure 22 In μop1). If the micro-packet identifier of the third processing micro-operation is determined (e.g., the micro-packet identifier of μop1 is 01), then other micro-operations with a micro-packet identifier also of 01 are determined in the micro-operation sequence (e.g., μops Queue). Figure 22 The micro-operations in μop2, μop3, and μop4, which are also micro-packed with a micro-packet identifier of 01, are treated as the fourth processing micro-operations (i.e., the fourth processing micro-operations are μop2, μop3, and μop4). The third processing micro-operation (i.e., ...) is dispatched. Figure 22 μop1 in the middle) and with the fourth processing micro-operation (i.e. Figure 22 (μop2, μop3, μop4 in the packet). This will dispatch the oldest micro-operation with the lowest latency, along with all micro-operations in the same packet.

[0288] The packaging process has no requirements for the running binary code or the compiler; it is a packaging operation performed by the CPU's internal hardware during execution.

[0289] 905, execute the micro-operation of dispatch.

[0290] Step 905 can be implemented by instruction execution module 104. In specific implementation, instruction execution module 104 performs the dispatch micro-operation.

[0291] For example, instruction execution module 104 executes μop1, μop2, μop3, and μop4.

[0292] 906, perform graduation processing on completed micro-operations.

[0293] Step 906 can be implemented by the instruction graduation module 105. In specific implementation, the instruction graduation module 105 performs graduation processing on the completed micro-operations.

[0294] In addition, if step 902 determines the micro-dependency identifier of each micro-operation, that is, each micro-operation also includes a micro-dependency identifier, wherein the micro-dependency identifier of the micro-operation of any assembly instruction is the same as the instruction dependency identifier of any assembly instruction, then after the execution of the micro-operation is completed through step 905, the corresponding register will be released according to the micro-dependency identifier.

[0295] When releasing the corresponding register based on the micro-dependency identifier, the physical register of the target operand of the target micro-operation can be released after the micro-operation package graduates.

[0296] In this case, the target micro-operation is the dispatched micro-operation, and the micro-dependency identifier is a third identifier.

[0297] The third identifier indicates that the corresponding micro-operation is not dependent on micro-operations outside its package; that is, the third identifier is the default value of the micro-dependency identifier (e.g., 0). If the micro-dependency identifier of a micro-operation is the third identifier, it means that the target operand it generates is a local variable of its package, and the physical registers of the target operands of these micro-operations can be released after all micro-operations in that package have been completed. If the micro-dependency identifier of a micro-operation is the fourth identifier (e.g., 1), it means that the target operand it generates is dependent on micro-operations outside its package, therefore the physical registers of the target operands of these micro-operations cannot be released after all micro-operations in that package have been completed.

[0298] like Figure 22 As shown, taking the graduation of a packet consisting of μop1, μop2, μop3, and μop4 as an example, the micro-dependency flags of μop3 and μop4 are 1 (i.e., the fourth flag), and the micro-dependency flags of μop1 and μop2 are 0 (i.e., the third flag). After the packet is graduated, the physical registers of the target operands of μop1 and μop2 are released.

[0299] Furthermore, if step 902 also determines the source register release flag for each micro-operation, then after the micro-operation is executed in step 905, the corresponding register will be released according to the source register release flag. For example, the physical register of the target operand of the target micro-operation will be released.

[0300] In this case, the target operand is the source operand released after the execution of any micro-operation indicated by the source register release flag.

[0301] If the fifth flag (e.g., the fifth flag is 1) indicates that the assembly instruction can release the physical register of the corresponding source operand after execution, and the sixth flag (e.g., the sixth flag is 0) indicates that the assembly instruction cannot release the physical register of the corresponding source operand after execution. Therefore, the target micro-operation is a dispatched micro-operation, and the source register release flag is the fifth flag.

[0302] Since the source register release flag has two bits, each corresponding to a source operand, any dispatched micro-operation that has at least one bit as the fifth flag is the target micro-operation. Subsequent bits that are the fifth flag will release the physical register of the source operand corresponding to that bit.

[0303] like Figure 22 As shown, taking the packet graduation consisting of μop1, μop2, μop3, and μop4 as an example, in the source register release flags of μop3 and μop4, SL1 is 1 (i.e., the fifth flag), and in the source register release flag of μop4, SL2 is 1 (i.e., the fifth flag). SL1 corresponds to the first source operand, and SL2 corresponds to the second source operand. After the packet graduation, the physical registers of the first source operands of μop3 and μop4 are released, and the physical registers of the second source operand of μop4 are released.

[0304] It should be noted that if step 902 determines both the micro-dependency identifier and the source register release identifier for each micro-operation, the corresponding register can be released based on either the micro-dependency identifier or the source register release identifier. The choice of release method can be preset.

[0305] Physical registers are the most valuable and expensive storage units in a processor. The method in this embodiment can release physical registers in advance by using the source register release flag, thereby achieving reasonable management of physical registers, reducing the allocation pressure on physical registers for other out-of-order instructions or micro-operations, and improving the instruction parallel processing speed of modern out-of-order multi-issue processors. It has important practical value.

[0306] By releasing the extractor (e.g.) Figure 18 The SrcRegRelease Extractor extracts information from the instruction sequence (such as InstrQueue) and marks each micro-operation with a source register release flag. After the micro-operation is completed, the corresponding register is released in advance based on the source register release flag. This method is simple to implement, has low hardware manufacturing costs, and high hardware operating speed.

[0307] In existing technologies, micro-operations are processed one by one during the dispatch and graduation phases, which hinders further improvements in processor efficiency. The method provided in this embodiment can package multiple micro-operations into a single package, allowing for processing of multiple micro-operations per cycle in the subsequent dispatch and graduation phases, thus significantly improving CPU processing speed.

[0308] Furthermore, the allocation of physical registers can be reduced by packaging multiple micro-operations. Packing multiple assembly instructions that have no side effects and are interdependent allows for register reuse of local variables during the renaming phase, reducing physical register allocation. Simultaneously, these packaged sets of local micro-operations enable the instruction dispatch module 103 and instruction graduation module 105 to process more efficiently (treating the micro-operation set as a whole, grading all packaged sets of local micro-operations at once). During the dispatch and graduation phases, the CPU only focuses on the final output of the local micro-operation set, without needing to allocate physical registers for intermediate variables calculated within the local micro-operation set, thus reducing physical register allocation and improving dispatch and issue efficiency.

[0309] This embodiment provides an instruction processing method that acquires assembly instructions to form an instruction sequence; decodes the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence; determines the micro-packet identifier of each micro-operation in the micro-operation sequence; dispatches micro-operations according to the micro-packet identifier; executes the dispatched micro-operations; and performs graduation processing on the executed micro-operations. The method provided in this embodiment determines the micro-packet identifier of each micro-operation in the micro-operation sequence; dispatches micro-operations according to the micro-packet identifier; executes the dispatched micro-operations; and performs graduation processing, enabling micro-operations with the same micro-packet identifier to be processed through the same pipeline, instead of being processed separately for each micro-operation through a separate pipeline, thus improving execution efficiency.

[0310] Based on the same inventive concept of instruction processing methods, this embodiment provides an electronic device, which is as follows: Figure 24 As shown, it includes: memory 2401, processor 2402, and computer program.

[0311] The computer program is stored in memory 2401 and configured to be executed by processor 2402 to implement the above instruction processing method.

[0312] Specifically, Obtain assembly instructions and form an instruction sequence.

[0313] The assembly instructions in the instruction sequence are decoded into micro-operations to form a micro-operation sequence.

[0314] Determine the micro-packet identifier for each micro-operation in the micro-operation sequence.

[0315] Dispatch of micro-operations based on micro-packaging identifiers.

[0316] Perform micro-operations for dispatch.

[0317] Perform graduation processing on the completed micro-operations.

[0318] Among these, determining the micro-packet identifier for each micro-operation in the micro-operation sequence includes: The first micro-operation in the micro-operation sequence is determined as the current micro-operation.

[0319] The micro-operation package is initialized to empty.

[0320] Determine whether the current micro-operation has side effects.

[0321] If the current micro-operation has side effects, then the next micro-operation in the micro-operation sequence is determined as the current micro-operation, and the steps of initializing the micro-operation package to be empty and subsequent steps are repeated.

[0322] If the current micro-operation has no side effects, determine whether the current micro-operation meets the inclusion condition. If the current micro-operation does not meet the inclusion condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps. If the current micro-operation meets the inclusion condition, add the current micro-operation to the micro-operation package. If the micro-operation package meets the packaging condition, determine that the micro-packaging identifiers of the micro-operations in the micro-operation package are all the second identifier, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps. If the micro-operation package does not meet the packaging condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps.

[0323] The second identifier is different from the first identifier, and also different from the alignment identifier. The first identifier is the initial value of the micro-packet identifier for any micro-operation. The alignment identifier is the micro-packet identifier in the micro-operation sequence that is closest to the micro-operation within the micro-operation package and is not the first identifier.

[0324] Among them, the packaging conditions are: ,and, .

[0325] in, This represents the number of microoperations within the microoperation package. This represents the number of micro-operations within the micro-operation package that depend on external operations. This represents the number of micro-operations within the micro-operation package that are externally dependent. The preset first value, This is the preset first ratio.

[0326] The conditions for joining are as follows: The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is not depended upon by micro-operations outside the micro-operation package.

[0327] or, The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is depended upon by micro-operations outside the micro-operation package, and... .

[0328] in, This represents the number of micro-operations within the micro-operation package and the total number of current micro-operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations in the current micro-operation that depend on external operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations that the current micro-operation depends on externally. This is the preset second ratio.

[0329] or, The current micro-operation is not dependent on any micro-operations within the micro-operation package, and the current micro-operation is not dependent on any micro-operations outside the micro-operation package. Furthermore, the number of micro-operations within the micro-operation package is less than a preset second value.

[0330] The micro-operations within the micro-operation package also include micro-dependency identifiers.

[0331] In this package, the micro-dependency identifier of micro-operations that are externally dependent within the micro-operation package is the fourth identifier, while the micro-dependency identifier of micro-operations that are not externally dependent within the micro-operation package is the third identifier. The third identifier is different from the fourth identifier.

[0332] After executing the micro-operation of dispatch, it also includes: Release the corresponding register based on the micro-dependency identifier.

[0333] The micro-operations in the micro-operation sequence also include: delay identifiers.

[0334] Dispatch of micro-operations based on micro-packaging identifiers includes: The third processing micro-operation and the fourth processing micro-operation in the dispatch micro-operation sequence.

[0335] Among them, the delay identifier of the third processing micro-operation is the minimum value, and the third processing micro-operation is the oldest among all micro-operations with the minimum delay identifier.

[0336] The micro-packaging identifier of the fourth processing micro-operation is the same as that of the third processing micro-operation.

[0337] Specifically, when any micro-operation is placed into the micro-operation sequence, it is determined whether all other micro-operations that the micro-operation depends on have been dispatched. If all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be the minimum value. If not all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be the maximum value.

[0338] When any micro-operation in the micro-operation sequence is dispatched, it is determined whether a first processing micro-operation exists in the micro-operation sequence, wherein the first processing micro-operation depends on any micro-operation. If a first processing micro-operation exists, and all other micro-operations that the first processing micro-operation depends on have been dispatched, then the delay identifier of the first processing micro-operation is determined as the number of cycles required to execute any micro-operation.

[0339] In each cycle, the delay flag of the second processing micro-operation in the micro-operation sequence is decremented by 1. Specifically, the delay flag of the second processing micro-operation is greater than the minimum value + 1, and the delay flag of the second processing micro-operation is less than the maximum value.

[0340] The electronic device provided in this embodiment has a computer program executed by a processor to dispatch micro-operations based on micro-packet identifiers; execute the dispatched micro-operations; and perform graduation processing, so that micro-operations with the same micro-packet identifiers can be processed through the same pipeline, instead of each micro-operation being processed through a separate pipeline, thereby improving execution efficiency.

[0341] Based on the same inventive concept as the instruction processing method, this embodiment provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the above-described instruction processing method.

[0342] Specifically, Obtain assembly instructions and form an instruction sequence.

[0343] The assembly instructions in the instruction sequence are decoded into micro-operations to form a micro-operation sequence.

[0344] Determine the micro-packet identifier for each micro-operation in the micro-operation sequence.

[0345] Dispatch of micro-operations based on micro-packaging identifiers.

[0346] Perform micro-operations for dispatch.

[0347] Perform graduation processing on the completed micro-operations.

[0348] Among these, determining the micro-packet identifier for each micro-operation in the micro-operation sequence includes: The first micro-operation in the micro-operation sequence is determined as the current micro-operation.

[0349] The micro-operation package is initialized to empty.

[0350] Determine whether the current micro-operation has side effects.

[0351] If the current micro-operation has side effects, then the next micro-operation in the micro-operation sequence is determined as the current micro-operation, and the steps of initializing the micro-operation package to be empty and subsequent steps are repeated.

[0352] If the current micro-operation has no side effects, determine whether the current micro-operation meets the inclusion condition. If the current micro-operation does not meet the inclusion condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps. If the current micro-operation meets the inclusion condition, add the current micro-operation to the micro-operation package. If the micro-operation package meets the packaging condition, determine that the micro-packaging identifiers of the micro-operations in the micro-operation package are all the second identifier, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps. If the micro-operation package does not meet the packaging condition, determine the next micro-operation in the micro-operation sequence as the current micro-operation, and repeat the steps of initializing the micro-operation package to empty and subsequent steps.

[0353] The second identifier is different from the first identifier, and also different from the alignment identifier. The first identifier is the initial value of the micro-packet identifier for any micro-operation. The alignment identifier is the micro-packet identifier in the micro-operation sequence that is closest to the micro-operation within the micro-operation package and is not the first identifier.

[0354] Among them, the packaging conditions are: ,and, .

[0355] in, This represents the number of microoperations within the microoperation package. This represents the number of micro-operations within the micro-operation package that depend on external operations. This represents the number of micro-operations within the micro-operation package that are externally dependent. The preset first value, This is the preset first ratio.

[0356] The conditions for joining are as follows: The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is not depended upon by micro-operations outside the micro-operation package.

[0357] or, The current micro-operation is depended upon by micro-operations within the micro-operation package, and the current micro-operation is depended upon by micro-operations outside the micro-operation package, and... .

[0358] in, This represents the number of micro-operations within the micro-operation package and the total number of current micro-operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations in the current micro-operation that depend on external operations. This represents the number of micro-operations within the micro-operation package and the number of micro-operations that the current micro-operation depends on externally. This is the preset second ratio.

[0359] or, The current micro-operation is not dependent on any micro-operations within the micro-operation package, and the current micro-operation is not dependent on any micro-operations outside the micro-operation package. Furthermore, the number of micro-operations within the micro-operation package is less than a preset second value.

[0360] The micro-operations within the micro-operation package also include micro-dependency identifiers.

[0361] In this package, the micro-dependency identifier of micro-operations that are externally dependent within the micro-operation package is the fourth identifier, while the micro-dependency identifier of micro-operations that are not externally dependent within the micro-operation package is the third identifier. The third identifier is different from the fourth identifier.

[0362] After executing the micro-operation of dispatch, it also includes: Release the corresponding register based on the micro-dependency identifier.

[0363] The micro-operations in the micro-operation sequence also include: delay identifiers.

[0364] Dispatch of micro-operations based on micro-packaging identifiers includes: The third processing micro-operation and the fourth processing micro-operation in the dispatch micro-operation sequence.

[0365] Among them, the delay identifier of the third processing micro-operation is the minimum value, and the third processing micro-operation is the oldest among all micro-operations with the minimum delay identifier.

[0366] The micro-packaging identifier of the fourth processing micro-operation is the same as that of the third processing micro-operation.

[0367] Specifically, when any micro-operation is placed into the micro-operation sequence, it is determined whether all other micro-operations that the micro-operation depends on have been dispatched. If all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be the minimum value. If not all other micro-operations have been dispatched, the delay flag of the micro-operation is determined to be the maximum value.

[0368] When any micro-operation in the micro-operation sequence is dispatched, it is determined whether a first processing micro-operation exists in the micro-operation sequence, wherein the first processing micro-operation depends on any micro-operation. If a first processing micro-operation exists, and all other micro-operations that the first processing micro-operation depends on have been dispatched, then the delay identifier of the first processing micro-operation is determined as the number of cycles required to execute any micro-operation.

[0369] In each cycle, the delay flag of the second processing micro-operation in the micro-operation sequence is decremented by 1. Specifically, the delay flag of the second processing micro-operation is greater than the minimum value + 1, and the delay flag of the second processing micro-operation is less than the maximum value.

[0370] The computer-readable storage medium provided in this embodiment has a computer program thereon that is executed by a processor to dispatch micro-operations based on micro-package identifiers; execute the dispatched micro-operations; and perform graduation processing, so that micro-operations with the same micro-package identifier can be processed through the same pipeline, instead of each micro-operation being processed through a separate pipeline, thereby improving execution efficiency.

[0371] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented using various computer languages, such as the object-oriented programming language C++ and the hardware description language Verilog.

[0372] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0373] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0374] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0375] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0376] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0377] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An instruction processing method, characterized by, The method comprises: acquiring assembly instructions to form an instruction sequence; decoding the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence; determining a micro-packing identifier of each micro-operation in the micro-operation sequence; dispatching the micro-operations according to the micro-packing identifier; executing the dispatched micro-operations; graduating the executed micro-operations.

2. The method of claim 1, wherein, The determination of the micro-packing identifier of each micro-operation in the micro-operation sequence comprises: determining a first micro-operation in the micro-operation sequence as a current micro-operation; initializing a micro-operation package as empty; determining whether the current micro-operation has a side effect; if the current micro-operation has a side effect, determining a next micro-operation of the current micro-operation in the micro-operation sequence as the current micro-operation, and repeating the step of initializing the micro-operation package as empty and the subsequent steps; if the current micro-operation does not have a side effect, determining whether the current micro-operation meets a joining condition; if the current micro-operation does not meet the joining condition, determining a next micro-operation of the current micro-operation in the micro-operation sequence as the current micro-operation, and repeating the step of initializing the micro-operation package as empty and the subsequent steps; if the current micro-operation meets the joining condition, adding the current micro-operation to the micro-operation package, determining that the micro-packing identifier of each micro-operation in the micro-operation package is a second identifier if the micro-operation package meets a packing condition, determining a next micro-operation of the current micro-operation in the micro-operation sequence as the current micro-operation, and repeating the step of initializing the micro-operation package as empty and the subsequent steps, and determining a next micro-operation of the current micro-operation in the micro-operation sequence as the current micro-operation if the micro-operation package does not meet the packing condition, and repeating the step of initializing the micro-operation package as empty and the subsequent steps. The second identifier is different from the first identifier and different from a comparison identifier; the first identifier is an initial value of the micro-packing identifier of any micro-operation; and the comparison identifier is a micro-packing identifier that is the most recent and not the first identifier in the micro-operation sequence.

3. The method of claim 2, wherein, The packing condition is and ; wherein, is the number of micro-ops in the micro-op packet, is the number of micro-ops in the micro-op packet that depend on external micro-ops, is the number of micro-ops in the micro-op packet that are depended on by external micro-ops, is a predetermined first value, is a predetermined first ratio.

4. The method of claim 2, wherein, The joining condition is that: the current micro-operation is dependent on the micro-operations in the micro-operation package, and the current micro-operation is not dependent on the micro-operations outside the micro-operation package; or The current micro-operation is depended on by micro-operations within the micro-operation packet, and the current micro-operation is depended on by micro-operations outside the micro-operation packet, and ; wherein, is the total number of micro-ops in the micro-op packet and the current micro-op, is the number of micro-ops in the micro-op packet and the current micro-op that depend on external micro-ops, is the number of micro-ops in the micro-op packet and the current micro-op that are depended on by external micro-ops, is a preset second ratio; or the current micro-operation is not dependent on the micro-operations in the micro-operation package, the current micro-operation is not dependent on the micro-operations outside the micro-operation package, and the number of micro-operations in the micro-operation package is less than a preset second value.

5. The method of claim 2, wherein, The micro-operations in the micro-operation package further comprise a micro-dependence identifier; wherein the micro-dependence identifier of a micro-operation in the micro-operation package that is externally dependent is a fourth identifier, and the micro-dependence identifier of a micro-operation in the micro-operation package that is not externally dependent is a third identifier; the third identifier is different from the fourth identifier; The execution of the dispatched micro-operations further comprises: releasing the corresponding register according to the micro-dependence identifier.

6. The method of claim 1, wherein, Each micro-operation in the micro-operation sequence further comprises a delay identifier; The dispatching of the micro-operations according to the micro-packing identifier comprises: dispatching a third processing micro-operation and a fourth processing micro-operation in the micro-operation sequence; The delay identifier of the third processing micro-operation is the minimum value, and the third processing micro-operation is the oldest among all micro-operations with the minimum delay identifier; The fourth processing micro-operation has the same micro-packet identifier as the third processing micro-operation.

7. The method of claim 6, wherein, When any micro-operation is put into the micro-operation sequence, it is determined whether all other micro-operations on which the any micro-operation depends have been dispatched; if all other micro-operations have been dispatched, the delay identifier of the any micro-operation is determined to be the minimum value; if all other micro-operations have not been dispatched, the delay identifier of the any micro-operation is determined to be the maximum value; When any micro-operation in the micro-operation sequence is dispatched, it is determined whether there is a first processing micro-operation in the micro-operation sequence, wherein the first processing micro-operation depends on the any micro-operation; if there is a first processing micro-operation, and all other micro-operations on which the first processing micro-operation depends have been dispatched, the delay identifier of the first processing micro-operation is determined to be the number of cycles for executing the any micro-operation; The delay identifier of a second processing micro-operation in the micro-operation sequence is decremented by 1 each cycle; wherein the delay identifier of the second processing micro-operation is greater than the minimum value + 1, and the delay identifier of the second processing micro-operation is less than the maximum value.

8. An instruction processing apparatus, characterized by, The apparatus comprises: An instruction obtaining module configured to obtain assembly instructions to form an instruction sequence; An instruction decoding module configured to decode the assembly instructions in the instruction sequence into micro-operations to form a micro-operation sequence, and determine the micro-packet identifiers of the micro-operations in the micro-operation sequence; An instruction dispatching module configured to dispatch the micro-operations according to the micro-packet identifiers; An instruction executing module configured to execute the dispatched micro-operations; An instruction graduating module configured to perform graduation processing on the micro-operations whose execution is completed.

9. An electronic device, comprising: comprise: a memory; a processor; and a computer program; wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, having a computer program stored thereon; the computer program is executed by a processor to implement the method of any one of claims 1-7.

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