Data processing method and related device

Abstract

The data processing method is applied to a parameter tuning process of a processor, and comprises the following steps: determining a first instruction subset from a to-be-run first program instruction set; according to the first instruction subset, adjusting operation parameters of the processor; determining a second instruction subset from the second program instruction set; the number of instructions included in the first instruction subset and the number of instructions included in the second instruction subset are different, or the proportions of target type instructions in the first instruction subset and the second instruction subset are different; and adjusting operation parameters of the processor according to the second instruction subset. When the processor runs the instructions of different services, the instruction subsets of different specifications (including different numbers of instructions or different proportions of instructions of the same type) can be selected to perform parameter tuning of the processor, and the instruction subset more suitable for participating in parameter tuning of the processor can be selected; and thus, the parameter tuning effect of the processor is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method and related apparatus. Background Technology

[0002] To optimize processor parameters (e.g., central processing unit (CPU)), existing technologies involve capturing program slices (i.e., instruction subsets) of the set of instructions to be executed, and then adjusting the processor parameters based on these program slices. Specifically, by running program slices on the CPU of an electronic device, CPU performance can be evaluated, thereby enabling CPU parameter optimization.

[0003] However, as the business scenarios related to program instructions continue to expand, the optimization effect of existing technologies when using program slices to optimize processor parameters is poor. Summary of the Invention

[0004] This application provides a data processing method, apparatus, and computing device that can improve the effect of processor parameter tuning.

[0005] In a first aspect, a data processing method is provided, comprising: determining a first instruction subset from a first set of program instructions to be executed; adjusting the processor's operating parameters according to the first instruction subset; determining a second instruction subset from a second set of program instructions; wherein the second set of program instructions consists of program instructions to be executed after the first set of program instructions, and the first and second instruction subsets contain different numbers of instructions or have different proportions of target type instructions; and adjusting the processor's operating parameters according to the second instruction subset.

[0006] In different business scenarios, the characteristics (number of instructions or proportion of instructions of the same type) of the instruction subsets more suitable for parameter tuning are often different. For example, in big data business scenarios, a large number of instruction sets may be needed for processor parameter tuning. When the processor runs different businesses, the instruction subset selected for processor parameter tuning may be different. In this application, when the processor runs instructions for different businesses, instruction subsets of different specifications (different number of instructions or different proportion of instructions of the same type) can be selected for processor parameter tuning. This allows for the selection of instruction subsets more suitable for participating in processor parameter tuning, thereby improving the effect of processor parameter tuning.

[0007] The proportion of instructions of the target type can be the proportion of instructions of a preset type, and the target type can be the instruction type corresponding to the hot function.

[0008] In one possible implementation, determining the first instruction subset from the first set of program instructions to be executed includes:

[0009] Multiple instruction subsets are determined from a first set of program instructions to be executed; wherein, at least two instruction subsets in the first set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a first instruction subset is selected from the multiple instruction subsets determined from the first set of program instructions, or...

[0010] Determining the second instruction subset from the second set of program instructions to be executed includes:

[0011] Multiple instruction subsets are determined from the second set of program instructions to be executed; wherein, at least two instruction subsets in the second set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a second instruction subset is selected from the multiple instruction subsets determined from the second set of program instructions.

[0012] In existing technologies, the number of instructions included in the constructed program slice and the proportion of instructions of the same type (e.g., hot instructions, which are instructions that the processor needs to spend more computing power or time to execute) are fixed. However, in the embodiments of this application, the number of instructions or the proportion of instructions of the same type (e.g., hot instructions) included in the multiple instruction subsets determined from the first set of program instructions to be run are not exactly the same. The advantage of this approach is that the multiple instruction subsets determined from the first program instruction set serve as candidates for final processor parameter tuning. These candidates include instruction sets with different numbers of instructions or a percentage of preset instruction categories. Compared to code that always selects a fixed number and a fixed percentage of preset instruction categories, the candidate set in this embodiment has richer characteristics (it has diversity in the number of instructions or diversity in the percentage of instructions of the same type). In different business scenarios, the characteristics (number of instructions or percentage of instructions of the same type) of the instruction subsets more suitable for participating in parameter tuning are often different. For example, in big data business scenarios, it may be necessary to include a large number of instruction sets for processor parameter tuning. From the candidate set determined based on this embodiment (that is, the multiple instruction subsets determined from the first program instruction set), a more suitable instruction subset for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0013] In one possible implementation, the first instruction subset is one of the at least two instruction subsets of the first program instruction set.

[0014] In one possible implementation, the first instruction subset is one of the at least two instruction subsets of the second program instruction set.

[0015] In one possible implementation, the adjustment of the processor's operating parameters is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or,

[0016] The adjustments made to the processor's operating parameters are related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

[0017] Processor parameter tuning is related to the specifications of the selected program slice (e.g., the first instruction subset or the second instruction subset). The number of instructions contained in the program slice is a key factor influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the number of instructions contained in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0018] Processor parameter tuning is related to the specifications of the selected program slice (e.g., the first instruction subset or the second instruction subset). For a program slice, the proportion of its target type instructions is a key factor affecting whether it is more suitable to participate in processor parameter tuning. Therefore, when the proportion of the target type instructions of the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0019] Processor parameter tuning is related to the specifications of the selected program slice (e.g., the first instruction subset or the second instruction subset). For a program slice, the number of instructions it contains and the proportion of target type instructions are key factors influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the processor's operating parameters are adjusted using the number of instructions it contains and the proportion of target type instructions in the program slice, better tuning results can be obtained.

[0020] In one possible implementation, adjusting the operating parameters of the processor executing the first set of program instructions according to the first subset of instructions includes:

[0021] Based on the number of instructions included in the first instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0022] The mapping relationship between the number of instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset involved in processor parameter optimization (i.e., the first instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0023] In one possible implementation, adjusting the operating parameters of the processor executing the first set of program instructions according to the first subset of instructions includes:

[0024] Based on the proportion of target type instructions in the first instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0025] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the first instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0026] In one possible implementation, adjusting the operating parameters of the processor executing the first set of program instructions according to the first subset of instructions includes:

[0027] Based on the number of instructions included in the first instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0028] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the first instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0029] In one possible implementation, adjusting the processor's operating parameters according to the second subset of instructions includes:

[0030] Based on the number of instructions included in the second instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0031] The mapping relationship between the number of instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset involved in processor parameter optimization (i.e., the second instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0032] In one possible implementation, adjusting the processor's operating parameters according to the second subset of instructions includes:

[0033] Based on the proportion of target type instructions in the second instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0034] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the second instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for processor operating parameters, this embodiment only requires determining the adjustment method for processor operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0035] In one possible implementation, adjusting the processor's operating parameters according to the second subset of instructions includes:

[0036] Based on the number of instructions included in the second instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0037] In one possible implementation, the mapping relationship between the number of instructions in the instruction subset, the proportion of target type instructions, and the processor's operating parameters can be pre-configured. After determining the instruction subset participating in processor parameter optimization (i.e., the third instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset, the proportion of target type instructions, and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the mapping relationship based on the number of instructions in the target instruction subset and the proportion of target type instructions. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0038] In one possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set; or, the second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0039] In one possible implementation, the first instruction subset is selected from the plurality of instruction subsets of the first program instruction set based on the optimizability of the processor when running the instruction subset; or, the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set based on the optimizability of the processor when running the instruction subset; wherein the optimizability indicates the extent to which the performance of the processor is optimized by adjusting parameters of the processor or processor-related registers when running the instruction subset.

[0040] "Instruction subsets more suitable for processor parameter tuning" can be understood as follows: when a processor runs instruction subset A, its optimization potential is higher compared to running other instruction subsets. Therefore, "instruction subset A" is more suitable for participating in processor parameter tuning. The degree of optimization potential indicates the extent to which the processor's performance parameters can be optimized by adjusting the parameters of the processor or its related registers when running an instruction subset. For a given code set, adjusting the parameters of the processor or its related registers often results in a higher optimization potential for the processor's performance parameters (compared to other code sets). Code sets with these characteristics can be considered to have a significant impact on the processor's operating performance. Parameter tuning of the processor based on code sets with these characteristics will result in a better processor state, i.e., higher operating performance.

[0041] In one possible implementation, the first instruction subset is selected from a subset of instructions among multiple instruction subsets included in the first program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or, the second instruction subset is selected from a subset of instructions among multiple instruction subsets included in the second program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the multiple instruction subsets of the second program instruction set.

[0042] To ensure that the final selected instruction subset is suitable for processor parameter tuning, the number of candidate subsets needs to be large (the more candidate subsets, the greater the probability of selecting a better instruction subset). However, when the number of instruction subsets included in the candidate set (multiple instruction subsets) is too large (e.g., thousands), evaluating whether each instruction subset is suitable for processor parameter tuning requires a certain computational overhead, leading to a large overall computational overhead. Therefore, in this embodiment, the candidate set needs to be screened first to reduce the number of subsets included in the candidate set (i.e., selecting a portion of the instruction subsets from the multiple instruction subsets). Then, only a smaller number of candidate subsets need to be selected for processor parameter tuning (i.e., selecting the first or second instruction subset from this portion of the instruction subsets), thereby reducing the overall computational overhead.

[0043] In one possible implementation, the performance is expressed as instructions per cycle (IPC).

[0044] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0045] Secondly, this application provides a data processing method, comprising: determining multiple instruction subsets from a first set of program instructions to be run, wherein the number of instructions contained in the multiple instruction subsets is different or the proportion of instructions of the same type (e.g., hotspot instructions) is not completely the same; then selecting an instruction subset (e.g., a target instruction subset) that is more suitable for participating in processor parameter tuning from the determined multiple instruction subsets; and adjusting the running parameters of the processor running the first set of program instructions according to the target instruction subset.

[0046] In existing technologies, the number of instructions included in the constructed program slice and the proportion of instructions of the same type (e.g., hot instructions, which are instructions that the processor needs to spend more computing power or time to execute) are fixed. However, in the embodiments of this application, the number of instructions or the proportion of instructions of the same type (e.g., hot instructions) included in the multiple instruction subsets determined from the first set of program instructions to be run are not exactly the same. The advantage of this approach is that the multiple instruction subsets determined from the first program instruction set serve as candidates for final processor parameter tuning. These candidates include instruction sets with different numbers of instructions or a percentage of preset instruction categories. Compared to code that always selects a fixed number and a fixed percentage of preset instruction categories, the candidate set in this embodiment has richer characteristics (it has diversity in the number of instructions or diversity in the percentage of instructions of the same type). In different business scenarios, the characteristics (number of instructions or percentage of instructions of the same type) of the instruction subsets more suitable for participating in parameter tuning are often different. For example, in big data business scenarios, it may be necessary to include a large number of instruction sets for processor parameter tuning. From the candidate set determined based on this embodiment (that is, the multiple instruction subsets determined from the first program instruction set), a more suitable instruction subset for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0047] In one possible implementation, when adjusting the processor's operating parameters based on a target instruction subset, the specific adjustment can be based on the number of instructions included in the target instruction subset. In other words, the specific adjustment value is related to the number of instructions included in the target instruction subset.

[0048] Processor parameter tuning is related to the specifications of the selected program slice (e.g., target instruction subset). The number of instructions contained in the program slice is a key factor influencing whether it is more suitable for participating in processor parameter tuning. Therefore, when the number of instructions contained in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0049] In one possible implementation,

[0050] The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset; or,

[0051] The adjustments made to the processor's operating parameters are related to the proportion of target type instructions in the target instruction subset; or,

[0052] The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0053] Processor parameter tuning is related to the specifications of the selected program slice (e.g., a subset of target instructions). For a program slice, the proportion of its target type instructions is a key factor influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the proportion of the target type instructions in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0054] Processor parameter tuning is related to the specifications of the selected program slice (e.g., a subset of target instructions). For a program slice, the number of instructions it contains and the proportion of target type instructions are key factors influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the processor's operating parameters are adjusted using the number of instructions it contains and the proportion of target type instructions in the program slice, better tuning results can be obtained.

[0055] In one possible implementation, the processor's operating parameters can be adjusted according to the number of instructions included in the target instruction subset, through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0056] A mapping relationship between the number of instructions in an instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0057] In one possible implementation, the processor's operating parameters can be adjusted based on the proportion of target type instructions in the target instruction subset through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0058] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0059] In one possible implementation, the processor's operating parameters can be adjusted through a third mapping relationship based on the number of instructions included in the target instruction subset and the proportion of target type instructions; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0060] In one possible implementation, the mapping relationship between the number of instructions in the instruction subset, the proportion of target type instructions, and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) participating in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset, the proportion of target type instructions, and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the mapping relationship based on the number of instructions in the target instruction subset and the proportion of target type instructions. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0061] In one possible implementation, the target instruction subset is selected from a plurality of instruction subsets based on the degree of optimizability of the processor when running the instruction subset; wherein the degree of optimizability indicates the extent to which the processor's performance parameters are optimized by adjusting parameters of the processor or processor-related registers when running the instruction subset.

[0062] "Instruction subsets more suitable for processor parameter tuning" can be understood as follows: when a processor runs instruction subset A, its optimization potential is higher compared to running other instruction subsets. Therefore, "instruction subset A" is more suitable for participating in processor parameter tuning. The degree of optimization potential indicates the extent to which the processor's performance parameters can be optimized by adjusting the parameters of the processor or its related registers when running an instruction subset. For a given code set, adjusting the parameters of the processor or its related registers often results in a higher optimization potential for the processor's performance parameters (compared to other code sets). Code sets with these characteristics can be considered to have a significant impact on the processor's operating performance. Parameter tuning of the processor based on code sets with these characteristics will result in a better processor state, i.e., higher operating performance.

[0063] In one possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0064] In one possible implementation, selecting a target instruction subset from the plurality of instruction subsets includes: selecting a partial instruction subset from the plurality of instruction subsets; and selecting the target instruction subset from the partial instruction subset.

[0065] To ensure that the final selected target instruction subset is suitable for processor parameter tuning, the number of candidate subsets needs to be large (the more candidate subsets, the greater the probability of selecting a better instruction subset). However, when the number of instruction subsets included in the candidate set (multiple instruction subsets) is too large (e.g., thousands), evaluating whether each instruction subset is suitable for processor parameter tuning requires a certain computational overhead, leading to a large overall computational overhead. Therefore, in this embodiment, the candidate set needs to be screened first to reduce the number of subsets included in the candidate set (i.e., selecting a portion of the instruction subsets from the multiple instruction subsets). This allows for the selection of the target instruction subset from a smaller number of candidate subsets, thereby reducing the overall computational overhead.

[0066] In one possible implementation, the target instruction subset is selected from the instruction subset based on the degree of optimizability of the processor when executing each instruction subset in the instruction subset.

[0067] For a given set of code, adjusting the parameters of the processor or its related registers often results in a significant improvement in processor performance (compared to other code sets). Code sets exhibiting these characteristics can be considered to have a substantial impact on processor performance. Therefore, by selecting a target instruction subset from this subset based on the optimizability of each instruction subset executed by the processor, and then fine-tuning the processor parameters based on the target instruction subset, the processor can be placed in an optimal state, resulting in higher performance.

[0068] In one possible implementation, this subset of instructions consists of one or more subsets of instructions in each category of the clustering result obtained by clustering the multiple subsets of instructions.

[0069] To ensure that a suitable subset of instructions for processor parameter tuning can still be selected from the reduced set of instructions after narrowing down the number of instruction subsets included in the candidate set, it is necessary to ensure that suitable subsets of instructions for processor parameter tuning are not excluded when narrowing down the number of instruction subsets included in the candidate set (i.e., selecting a portion of the candidate set). The approach of this application is to identify a typical instruction subset from multiple instruction subsets as a narrowed candidate set. Here, a "typical instruction subset" can be understood as an instruction subset that can represent other instruction subsets of a certain category from multiple instruction subsets. That is, some instruction subsets in multiple instruction subsets are similar to each other, for example, they are the same or similar in characteristics such as IPC size, whether or not registers need to be read. In this case, these instruction subsets can be considered to be of the same category. Then, an instruction subset that can represent the category (e.g., the instruction subset located at the centroid) can be selected from the instruction subsets of the same category as the narrowed candidate set. If at least one instruction subset is selected from each category of instruction subsets, then there will be no omission of instruction subsets with certain characteristics in the narrowed candidate set.

[0070] In one possible implementation, the method further includes: obtaining multiple candidate instruction features for each instruction subset and the performance of the processor when running the instruction subset; selecting a subset of instruction features from the multiple candidate instruction features such that there are differences in the performance of instruction subsets of different categories in the clustering result obtained by clustering the multiple instruction subsets based on the subset of instruction features (for example, the difference in performance between instruction subsets of different categories is the largest, and the difference in performance between instruction subsets of the same category is the smallest).

[0071] The number of features in the instruction subset can be large (e.g., 100). The clustering process can be a multi-round process, in which the features of the instruction subset can be filtered in each round (e.g., the last round filters down to 10). Selecting different features will result in differences in the positional distribution of the instruction subset in the feature space. The purpose of filtering is to select certain features (that is, some instruction features in this embodiment). When clustering is performed based on these selected features, there are differences in the performance of instruction subsets of different categories in the clustering results (e.g., the performance difference between instruction subsets of different categories is the largest, and the performance difference between instruction subsets of the same category is the smallest).

[0072] In one possible implementation, this performance parameter is instructions per cycle (IPC).

[0073] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0074] Thirdly, this application provides a data processing apparatus, characterized in that it includes:

[0075] An instruction selection module is used to determine multiple instruction subsets from a first set of program instructions to be executed; wherein, at least two instruction subsets in the multiple instruction subsets contain different numbers of instructions or different proportions of target type instructions; and to select a target instruction subset from the multiple instruction subsets.

[0076] The parameter adjustment module is used to adjust the processor's operating parameters according to the target instruction subset.

[0077] In one possible implementation, the adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset; or,

[0078] The adjustments made to the processor's operating parameters are related to the proportion of target type instructions in the target instruction subset; or,

[0079] The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0080] In one possible implementation, the parameter adjustment module is specifically used to: adjust the processor's operating parameters according to the number of instructions included in the target instruction subset, through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0081] In one possible implementation, the parameter adjustment module is specifically used to: adjust the processor's operating parameters according to the proportion of target type instructions in the target instruction subset, through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0082] In one possible implementation, the parameter adjustment module is specifically used to: adjust the processor's operating parameters according to the number of instructions included in the target instruction subset and the proportion of target type instructions through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0083] In one possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0084] In one possible implementation, the target instruction subset is selected from a plurality of instruction subsets based on the degree of optimizability of the processor when running the instruction subset; wherein the degree of optimizability indicates the extent to which the processor's performance parameters are optimized by adjusting parameters of the processor or processor-related registers when running the instruction subset.

[0085] In one possible implementation, this instruction selects a module, specifically for:

[0086] Select a subset of instructions from the multiple subsets of instructions;

[0087] Select the target instruction subset from this instruction subset.

[0088] In one possible implementation, selecting the target instruction subset from the partial instruction subset includes:

[0089] The target instruction subset is selected from the partial instruction subset based on the degree of optimizability of the processor in running each instruction subset.

[0090] In one possible implementation, the target instruction subset is selected from a subset of the plurality of instruction subsets, the subset of instruction subsets including one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets.

[0091] In one possible implementation, the instruction selection module is specifically used for:

[0092] Obtain the characteristics of multiple candidate instructions for each instruction subset and the performance of the processor when running the instruction subset;

[0093] Select a subset of instruction features from the plurality of candidate instruction features, such that the performance of instruction subsets of different categories differs in the clustering results obtained by clustering the plurality of instruction subsets based on the subset of instruction features.

[0094] In one possible implementation, the performance is expressed as instructions per cycle (IPC).

[0095] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0096] Fourthly, this application provides a data processing apparatus, characterized in that the apparatus comprises:

[0097] The instruction selection module is used to determine a first instruction subset from a first set of program instructions and a second instruction subset from a second set of program instructions. The second set of program instructions is the program instructions that need to be executed after the first set of program instructions. The first and second instruction subsets include different numbers of instructions or different proportions of target type instructions in the first and second instruction subsets.

[0098] The parameter adjustment module is used to adjust the processor's operating parameters according to the first instruction subset and the second instruction subset.

[0099] In one possible implementation, this instruction selects a module, specifically for:

[0100] Multiple instruction subsets are determined from a first set of program instructions to be executed; wherein, at least two instruction subsets in the first set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a first instruction subset is selected from the multiple instruction subsets determined from the first set of program instructions, or...

[0101] Multiple instruction subsets are determined from the second set of program instructions to be executed; wherein, at least two instruction subsets in the second set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a second instruction subset is selected from the multiple instruction subsets determined from the second set of program instructions.

[0102] In one possible implementation, the adjustment of the processor's operating parameters is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or,

[0103] The adjustments made to the processor's operating parameters are related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

[0104] In one possible implementation, the parameter adjustment module is used for:

[0105] Based on the number of instructions included in the first instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or,

[0106] Based on the proportion of target type instructions in the first instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or,

[0107] Based on the number of instructions included in the first instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0108] In one possible implementation, the parameter adjustment module is used for:

[0109] Based on the number of instructions included in the second instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or,

[0110] Based on the proportion of target type instructions in the second instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or,

[0111] Based on the number of instructions included in the second instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0112] In one possible implementation, the first instruction subset is one of the at least two instruction subsets in the first set of program instructions; or...

[0113] The second instruction subset is one of the at least two instruction subsets in the second set of program instructions.

[0114] In one possible implementation, the first instruction subset is selected from the plurality of instruction subsets of the first program instruction set based on the degree of optimizability of the processor when running the instruction subset; or, the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set based on the degree of optimizability of the processor when running the instruction subset.

[0115] The degree of optimizability indicates the extent to which the performance of the processor can be optimized by adjusting the parameters of the processor or the processor-related registers when running a subset of instructions.

[0116] In one possible implementation, the first instruction subset is selected from a subset of instructions among multiple instruction subsets included in the first program instruction set, wherein the subset includes one or more instruction subsets from each category in the clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or,

[0117] The second instruction subset is selected from a subset of instructions from a plurality of instruction subsets included in the second program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets of the second program instruction set.

[0118] In one possible implementation, the performance is expressed as instructions per cycle (IPC).

[0119] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0120] Fifthly, a computing device is provided, comprising: a processor and a memory; the memory being used to store computer instructions, which, when executed by the processor, cause the data processing apparatus to perform the methods of any of the above aspects.

[0121] In a sixth aspect, a computer-readable storage medium is provided, which stores instructions that, when executed on a computer, cause the computer to perform the methods of any of the above aspects.

[0122] In a seventh aspect, a computer program product containing instructions is provided, which, when executed on a computer, enable the computer to perform the methods of any of the above aspects.

[0123] Eighthly, a chip system is provided, the chip system including a processor and a communication interface for communicating with a module other than the chip, the processor for running computer programs or instructions such that an apparatus on which the chip system is mounted can perform the methods of any of the above aspects.

[0124] A ninth aspect provides a computing device cluster, including at least one computing device, wherein any one computing device is used to run a computer program or instructions, such that the computing device cluster can perform the methods of any of the above aspects. Alternatively, some or all of the computing devices are used together to run a computer program or instructions, such that the computing device cluster can perform the methods of any of the above aspects.

[0125] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0126] Figure 1 This is a schematic diagram of an application architecture for this application;

[0127] Figure 2 A flowchart illustrating a data processing method provided in this application;

[0128] Figure 3A A schematic diagram illustrating a method for obtaining program slices provided in this application;

[0129] Figure 3B A schematic diagram illustrating processor parameter adjustment provided in this application;

[0130] Figure 4A A flowchart illustrating a data processing method provided in this application;

[0131] Figure 4B A schematic diagram illustrating a method for obtaining program slices provided in this application;

[0132] Figure 5 A schematic diagram of the structure of a data processing device provided in this application;

[0133] Figure 6 A schematic diagram of the structure of a computing device provided in this application;

[0134] Figure 7 This application provides a schematic diagram of the structure of a computing device cluster;

[0135] Figure 8 This application provides a schematic diagram of another computing device cluster structure.

[0136] Figure 9 This is a schematic diagram of the structure of a computer-readable storage medium provided in this application. Detailed Implementation

[0137] The embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are merely some, and not all, of the embodiments of this application. Those skilled in the art will recognize that, with the emergence of new application scenarios, the technical solutions provided by this application are also applicable to similar technical problems.

[0138] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such descriptions can be used interchangeably where appropriate to allow embodiments to be implemented in a sequence other than that illustrated or described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved. The division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interface, and the indirect coupling or communication connection between units may be electrical or other similar forms, none of which are limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed among multiple circuit units. Some or all of the units can be selected to achieve the purpose of the solution in this application according to actual needs.

[0139] The following describes the electronic device 100 involved in implementing the method provided in the embodiments of this application. The electronic device 100 may be a computer, workstation, smart terminal, server, or other types of electronic devices capable of automatically and rapidly performing large-scale numerical calculations and various information processing according to a pre-stored program. The embodiments of this application do not limit the scope of the electronic device 100.

[0140] like Figure 1As shown, the electronic device 100 includes a processor 101, system memory 102, non-volatile memory 103, network interface 104, and input / output device 105, as well as a bus 106 for coupling the processor 101, system memory 102, non-volatile memory 103, network interface 104, and input / output device 105.

[0141] The processor 101 is used to execute the data processing method involved in the embodiments of this application and to perform parameter tuning of the processor 101. It is understood that the electronic device 100 may also include multiple processors, and the processor 101 executes the data processing method involved in the embodiments of this application to perform parameter tuning of other multiple processors.

[0142] System memory 102 can be used to temporarily store instructions 107, and non-volatile memory 103 can be used to permanently store instructions 107. System memory 102 can be used to temporarily store data files obtained from electronic device 100 and parsing rules for parsing instructions from the data files, and non-volatile memory 103 can be used to permanently store data files obtained from electronic device 100 and parsing rules for parsing instructions from the data files.

[0143] The network interface 104 is used to communicate with other devices, such as electronic device 100, which can communicate with a server through the network interface 104.

[0144] Input / output device 105 can be used for user interaction with electronic device 100.

[0145] To optimize processor parameters (e.g., central processing unit (CPU)), related technologies involve capturing program slices (instruction subsets) of the set of instructions to be executed, and then adjusting the processor parameters based on these program slices. Specifically, a program slice refers to saving a portion of the instructions included in an application; optionally, it can be restored to at least one executable program consistent with the original execution logic of the application. Program slicing is widely used in CPU parameter tuning. By controlling the CPU of an electronic device to run program slices, the evaluation results corresponding to parameter tuning can be obtained, i.e., IPC (instructions per cycle), thereby evaluating CPU performance and achieving CPU parameter tuning.

[0146] However, in existing technologies, when determining program slices, fixed-size slices are often randomly selected from the instruction set. As the business scenarios related to program instructions become increasingly diverse, fixed-size program slices cannot be applied to every business scenario. Therefore, the slice determination method in related technologies leads to lower processor parameter tuning results.

[0147] Based on this, embodiments of this application provide a data processing method. The following is based on... Figure 2 The flowchart shown below is used to describe in detail the data processing method provided in the embodiments of this application. Figure 2 The method shown can be derived from Figure 1 The processor 101 of the illustrated electronic device 100 executes relevant instructions. In some embodiments, through... Figure 1 The processor 101 of the electronic device 100 shown can perform parameter tuning on the processor 101 by executing the data processing method provided in the embodiments of this application, and can also perform parameter tuning on other processors of the electronic device 100 or the processors of other electronic devices that communicate with the electronic device 100. Figure 2 The methods shown include:

[0148] 201. The processor determines multiple instruction subsets from the first set of program instructions to be executed; wherein, at least two instruction subsets in the multiple instruction subsets contain different numbers of instructions or different proportions of target type instructions.

[0149] In step 201, the execution subject (processor) can be the object to be subsequently optimized, that is, it can perform its own parameter optimization method and optimize its own parameters based on the execution result of the parameter optimization method, or it can perform its own parameter optimization method and optimize the parameters of other processors.

[0150] The first set of program instructions may be the instructions contained in the original program to be run.

[0151] For example, the first set of program instructions here can be as follows: Figure 3A The original program shown contains 90,000 instructions (original instruction stream data).

[0152] In a flame graph, instructions of the same type can be considered "hotspot instructions," meaning instructions that require significant computational or time overhead for the processor to execute. Hotspot instructions can be identified by the execution time of each type of instruction as indicated in the flame graph; instructions with longer execution times are considered hotspot instructions. A flame graph, as a visualization tool, displays the hierarchical structure and execution time of executed instructions. Each instruction in the flame graph is represented as a bar, and the width of the bar (or, depending on the presentation of the flame graph, other dimensions indicating execution time, such as height or length) represents the length of the instruction's execution time. A flame graph provides a very intuitive view of instructions and their execution times.

[0153] In this embodiment, multiple instruction subsets from the first program instruction set can be selected to construct a program slice. In existing technologies, the number of instructions included in the constructed program slice and the proportion of instructions of the same type (e.g., hot instructions, which are instructions that require more computing power or time to execute) are fixed. However, in this embodiment, multiple instruction subsets are determined from the first program instruction set, and the number of instructions or the proportion of instructions of the same type (e.g., hot instructions) contained in the multiple instruction subsets are not completely the same. Then, a more suitable instruction subset (e.g., target instruction subset) for participating in processor parameter tuning can be selected from the determined multiple instruction subsets to perform processor parameter tuning.

[0154] In this context, program slicing refers to saving a subset of the instructions in an application (which can be understood as a subset of the program's instruction set). For example, if an application has 100,000 instructions when executed completely, recording instructions 30,000 to 40,000 and reassembling them into a fragment of an executable program is called program slicing.

[0155] The advantage of this approach is that the multiple instruction subsets determined from the first program instruction set serve as candidates for final processor parameter tuning. These candidates include instruction sets with different numbers of instructions or a percentage of preset instruction categories. Compared to code that always selects a fixed number and a fixed percentage of preset instruction categories, the candidate set in this embodiment has richer characteristics (it has diversity in the number of instructions or diversity in the percentage of instructions of the same type). In different business scenarios, the characteristics (number of instructions or percentage of instructions of the same type) of the instruction subsets more suitable for participating in parameter tuning are often different. For example, in big data business scenarios, it may be necessary to include a large number of instruction sets for processor parameter tuning. From the candidate set determined based on this embodiment (that is, the multiple instruction subsets determined from the first program instruction set), a more suitable instruction subset for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0156] For example, refer to Figure 3A , Figure 3A The instruction set comprises 90,000 instructions. Instruction selection from this set yields three subsets: 19,000 to 22,000 instructions, 50,000 to 60,000 instructions, and 61,000 to 80,000 instructions. These three subsets contain different numbers of instructions, allowing for the selection of a more suitable subset for processor parameter tuning, thereby improving the effectiveness of parameter tuning.

[0157] It contains a large set of instructions, and the business scenarios include, but are not limited to, data and graphics processing scenarios, in-memory database scenarios, key-value storage scenarios, CPU and shared memory benchmarking scenarios, etc.

[0158] It should be understood that "instruction subsets more suitable for participating in processor parameter tuning" in the embodiments of this application can be interpreted as: the processor has a higher degree of optimizability when running instruction subsets, and the degree of optimizability indicates the extent to which the processor's performance can be optimized by adjusting the parameters of the processor or the processor-related registers when running instruction subsets. The following is a specific example to illustrate the degree of optimizability in the embodiments of this application:

[0159] When the parameters of the processor-related registers are set to parameter A, and the processor executes instruction subset A, the performance parameter value of the processor executing instruction subset A is X. By optimizing the parameters of the processor-related registers, for example, by changing the parameters of the processor-related registers from parameter A to parameter B (processor register parameter adjustments affect processor performance parameters), and then re-executing instruction subset A, the performance parameter value of the processor re-executing instruction subset A is Y. The difference between Y and X is the optimization magnitude of the performance parameter (due to the adjustment of the register parameters). Furthermore, there exists an optimal adjustment method for the processor-related registers that maximizes the optimization magnitude of Y compared to X. This maximum optimization magnitude can be considered as the performance optimization magnitude of the processor when executing that instruction subset. For multiple instruction subsets, the greater the performance optimization magnitude of the processor when executing that instruction subset, the higher the degree of optimization potential of the processor when executing the instruction subset.

[0160] For a given set of code, adjusting the parameters of the processor or its related registers often results in a significant improvement in processor performance (compared to other code sets). Code sets exhibiting these characteristics can be considered to have a substantial impact on processor performance. Therefore, based on the optimizability of each instruction subset within this set of instructions, selecting a target instruction subset and tuning the processor parameters according to that target instruction subset will result in a better processor performance, i.e., higher operating performance.

[0161] For example, multiple instruction subsets can be determined from the first set of program instructions to be executed by instruction instrumentation. Specifically, instruction instrumentation can be performed on the instruction set based on the load instruction flow, and the instruction truncation range can be adjusted according to the requirements of program slice granularity (in this embodiment, program slice granularity can also be referred to as the number of instructions included in the program slice) or typical instruction ratio (in this embodiment, typical instruction ratio can also be referred to as the ratio of target type instructions).

[0162] In one possible implementation, the user can input instruction information to indicate the number of instructions included in each instruction subset obtained by program slicing the instruction set, or the proportion of instructions of the same type. Then, when performing instruction instrumentation, the instruction set can be sliced ​​according to the instruction information.

[0163] In one possible implementation, the number of instructions among multiple instruction subsets can vary according to a certain gradient. For example, the number of instructions among multiple instruction subsets can include multiple values ​​between 1,000 and 20,000, which is equivalent to increasing the diversity of the number of instructions among multiple instruction subsets.

[0164] In one possible implementation, the proportion of preset instructions among multiple instruction subsets can vary according to a certain gradient. For example, the proportion of preset instructions among multiple instruction subsets can include multiple values ​​between 1% and 10%, which is equivalent to increasing the diversity of the proportion of preset instructions among multiple instruction subsets.

[0165] 202. The processor selects a target instruction subset from the plurality of instruction subsets.

[0166] In one possible implementation, a subset of instructions that is more suitable for participating in processor parameter tuning can be selected from multiple instruction subsets.

[0167] To ensure that the final selected target instruction subset is suitable for processor parameter tuning, the number of candidate subsets needs to be relatively large (the more candidate subsets, the greater the probability of selecting a better instruction subset). However, when the number of instruction subsets included in the candidate set (multiple instruction subsets) is too large (e.g., thousands), evaluating whether each instruction subset is suitable for processor parameter tuning requires a certain computational cost, resulting in a large overall computational cost. Therefore, in this embodiment, the candidate set needs to be screened first to reduce the number of instruction subsets included in the candidate set (that is, selecting a portion of the instruction subsets from the multiple instruction subsets). Then, only the instruction subsets for processor parameter tuning need to be selected from the candidate set containing a smaller number of instruction subsets (that is, selecting the target instruction subset from this portion of the instruction subsets), thereby reducing the overall computational cost.

[0168] In one possible implementation, the partial instruction subset consists of one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets.

[0169] To ensure that a suitable subset of instructions for processor parameter tuning can still be selected from the reduced candidate set after narrowing down the number of instruction subsets included in the candidate set, it is necessary to ensure that suitable subsets of instructions for processor parameter tuning are not excluded when narrowing down the candidate range of the candidate set (i.e., selecting a portion of the candidate set). The approach of this application is to identify typical instruction subsets from multiple instruction subsets as a reduced candidate set. Here, a "typical instruction subset" can be understood as an instruction subset that can represent other instruction subsets of a certain category from multiple instruction subsets. That is, some instruction subsets in multiple instruction subsets are similar to each other, for example, they are the same or similar in characteristics such as IPC size, whether or not registers need to be read. In this case, these instruction subsets can be considered to be of the same category. Then, an instruction subset that can represent the category (e.g., the instruction subset located at the centroid) can be selected from the instruction subsets of the same category as the reduced instruction set. If at least one instruction subset is selected from each category of instruction subsets, then there will be no omission of instruction subsets with certain characteristics in the reduced instruction set.

[0170] In one possible implementation, multiple candidate instruction features for each instruction subset and the processor's performance when running the instruction subset can be obtained; a subset of instruction features from the multiple candidate instruction features are selected such that the performance of instruction subsets of different categories differs in the clustering result obtained by clustering the multiple instruction subsets based on the subset of instruction features (for example, the performance difference between instruction subsets of different categories is the largest, and the performance difference between instruction subsets of the same category is the smallest).

[0171] The number of features in the instruction subset can be large (e.g., 100). The clustering process can be a multi-round process, and each round can filter the features of the instruction subset (e.g., the last round filters down to 10). Selecting different features will result in differences in the positional distribution of the instruction subset in the feature space. The purpose of filtering is to select certain features (that is, some instruction features in the embodiments of this application).

[0172] In determining the instruction subset that will ultimately participate in processor parameter optimization, a target instruction subset can be selected from multiple instruction subsets to participate in processor parameter optimization, based on the degree of optimizability of the processor when running the instruction subset.

[0173] When the candidate set is compressed (i.e., the number of instruction subsets included in the candidate set is reduced), a target instruction subset can be selected from the partial instruction subset based on the optimizability of each instruction subset in the processor's execution of the partial instruction subset.

[0174] For example, a performance parameter could be instructions per cycle (IPC), which represents the number of instructions executed by the processor per clock cycle.

[0175] In one possible implementation, when determining the optimizability of an instruction subset, the change in performance parameters of the processor running that subset can be observed by adjusting processor-related register parameters. For example, the greater the increase in IPC, the greater the optimizability. Let parameter A be the parameter of the processor-related registers. In this case, the processor runs instruction subset A, and the value of the performance parameter when running instruction subset A is X. By tuning the parameters of the processor-related registers, for example, adjusting them to parameter B, the processor runs instruction subset A again, and the value of the performance parameter when running instruction subset A is Y. The difference between Y and X represents the optimization magnitude of the performance parameter. Furthermore, there exists an optimal adjustment method for the processor-related registers that maximizes the optimization magnitude of Y compared to X. This maximum optimization magnitude can be considered the performance optimization magnitude of the processor when running that instruction subset. For multiple instruction subsets, the greater the performance optimization magnitude of the processor when running that subset, the higher the optimizability of the processor when running that subset. For example, a greater performance optimization magnitude could be achieved by increasing IPC significantly.

[0176] 203. The processor adjusts the operating parameters of the processor running the first set of program instructions according to the target instruction subset.

[0177] In one possible implementation, when adjusting the processor's operating parameters based on a target instruction subset, the specific adjustment can be based on the number of instructions included in the target instruction subset. In other words, the specific adjustment value is related to the number of instructions included in the target instruction subset.

[0178] Processor parameter tuning is related to the specifications of the selected program slice (e.g., target instruction subset). The number of instructions contained in the program slice is a key factor influencing whether it is more suitable for participating in processor parameter tuning. Therefore, when the number of instructions contained in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0179] In one possible implementation, when adjusting the processor's operating parameters based on a target instruction subset, the adjustments can be specifically based on the proportion of target type instructions within that subset. In other words, the specific adjustment value is related to the proportion of target type instructions in the target instruction subset.

[0180] Processor parameter tuning is related to the specifications of the selected program slice (e.g., a subset of target instructions). For a program slice, the proportion of its target type instructions is a key factor influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the proportion of the target type instructions in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0181] In one possible implementation, when adjusting the processor's operating parameters based on a target instruction subset, the adjustments can be made specifically based on the number of instructions included in the target instruction subset and the proportion of target type instructions. In other words, the specific adjustment value is related to the number of instructions included in the target instruction subset and the proportion of target type instructions within that subset.

[0182] Processor parameter tuning is related to the specifications of the selected program slice (e.g., a subset of target instructions). For a program slice, the number of instructions it contains and the proportion of target type instructions are key factors influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the processor's operating parameters are adjusted using the number of instructions it contains and the proportion of target type instructions in the program slice, better tuning results can be obtained.

[0183] In one possible implementation, the processor's operating parameters can be adjusted according to the number of instructions included in the target instruction subset, through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0184] A mapping relationship between the number of instructions in an instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0185] In one possible implementation, the processor's operating parameters can be adjusted based on the proportion of target type instructions in the target instruction subset through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0186] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0187] In one possible implementation, the processor's operating parameters can be adjusted through a third mapping relationship based on the number of instructions included in the target instruction subset and the proportion of target type instructions; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0188] In one possible implementation, the mapping relationship between the number of instructions in the instruction subset, the proportion of target type instructions, and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the target instruction subset) participating in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset, the proportion of target type instructions, and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the mapping relationship based on the number of instructions in the target instruction subset and the proportion of target type instructions. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0189] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0190] For example, refer to Figure 3B After determining the target instruction subset, the number of instructions (A3) and the proportion of instructions of the same type (B3) in the target instruction subset can be used to further refine the calculation. Figure 3B The mapping relationship (table) shown identifies the corresponding processor parameter as C3, and the processor parameters can then be adjusted based on C3.

[0191] Reference Figure 4A , Figure 4A Another illustration of the data processing method provided in the embodiments of this application, and Figure 3A The difference is, Figure 4A The process of performing parameter tuning on the processor twice is described, including:

[0192] 401. The processor determines a first subset of instructions from the first set of program instructions.

[0193] The process of determining the first instruction subset can be referred to Figure 2 The corresponding embodiment describes the process for determining the target instruction subset.

[0194] 402. The processor adjusts the operating parameters of the processor running the first program instruction set according to the first instruction subset.

[0195] 403. The processor determines a second instruction subset from the second program instruction set; wherein the second program instruction set is the program instructions to be executed after the first program instruction set, and the first instruction subset and the second instruction subset include different numbers of instructions, or the proportion of target type instructions in the first instruction subset and the second instruction subset is different.

[0196] The process for determining the second instruction subset can be referred to Figure 2 The corresponding embodiment describes the process for determining the target instruction subset.

[0197] In one possible implementation, the second set of program instructions and the first set of program instructions can be instructions from different applications.

[0198] In one possible implementation, the second set of program instructions and the first set of program instructions can be different sets of instructions in the same application.

[0199] 404. The processor adjusts the processor's operating parameters according to the second instruction subset.

[0200] For example, refer to Figure 4B The number of instructions included in the first instruction subset determined from the first program instruction set is different from the number of instructions included in the second instruction subset determined from the second program instruction set.

[0201] In one possible implementation, the first instruction subset is one of the at least two instruction subsets of the first program instruction set.

[0202] In one possible implementation, the first instruction subset is one of the at least two instruction subsets of the second program instruction set.

[0203] In different business scenarios, the characteristics (number of instructions or proportion of instructions of the same type) of the instruction subsets that are more suitable for participating in parameter tuning are often different. For example, in big data business scenarios, a large number of instruction sets may be needed for processor parameter tuning. In different processor optimization processes, this application can select instruction subsets of different specifications (different number of instructions or different proportion of instructions of the same type) to perform processor parameter tuning, thereby selecting instruction subsets that are more suitable for participating in processor parameter tuning and improving the effect of processor parameter tuning.

[0204] In one possible implementation, determining a first instruction subset from a first set of program instructions to be executed includes: determining multiple instruction subsets from the first set of program instructions to be executed; wherein at least two instruction subsets in the multiple instruction subsets have different numbers of instructions or different proportions of target type instructions, and selecting a first instruction subset from the multiple instruction subsets; or, determining a second instruction subset from a second set of program instructions to be executed by the processor includes: determining multiple instruction subsets from the second set of program instructions to be executed; wherein at least two instruction subsets in the multiple instruction subsets have different numbers of instructions or different proportions of target type instructions, and selecting a second instruction subset from the multiple instruction subsets.

[0205] In different business scenarios, the characteristics (number of instructions or proportion of instructions of the same type) of the instruction subsets that are more suitable for participating in parameter tuning are often different. For example, in big data business scenarios, a large number of instruction sets may be needed to perform processor parameter tuning. From the candidate set determined based on the embodiments of this application (that is, multiple instruction subsets determined from the first program instruction set, or multiple instruction subsets determined from the second program instruction set), a more suitable instruction subset for participating in processor parameter tuning can be selected, thereby improving the effect of processor parameter tuning.

[0206] In one possible implementation, adjusting the processor's operating parameters based on the first instruction subset includes: adjusting the processor's operating parameters based on the number of instructions included in the first instruction subset or the proportion of target type instructions; or, adjusting the processor's operating parameters based on the second instruction subset includes: adjusting the processor's operating parameters based on the number of instructions included in the second instruction subset or the proportion of target type instructions. In another possible implementation, selecting the first instruction subset from the plurality of instruction subsets includes: selecting a partial instruction subset from the plurality of instruction subsets, and then selecting the first instruction subset from the partial instruction subset; or, selecting the second instruction subset from the plurality of instruction subsets includes: selecting a partial instruction subset from the plurality of instruction subsets, and then selecting the second instruction subset from the partial instruction subset.

[0207] Processor parameter tuning is related to the specifications of the selected program slice (e.g., first instruction subset, second instruction subset). The number of instructions contained in the program slice is a key factor influencing whether it is more suitable to participate in processor parameter tuning. Therefore, when the number of instructions contained in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0208] Processor parameter tuning is related to the specifications of the selected program slice (e.g., first instruction subset, second instruction subset). For a program slice, the number of instructions it contains and the proportion of target type instructions are key factors affecting its suitability for processor parameter tuning. Therefore, when the number of instructions contained in the program slice and the proportion of target type instructions are used to adjust the processor's operating parameters, better tuning results can be obtained.

[0209] Processor parameter tuning is related to the specifications of the selected program slice (e.g., first instruction subset, second instruction subset). For a program slice, the proportion of target type instructions is a key factor affecting whether it is more suitable to participate in processor parameter tuning. Therefore, when the proportion of target type instructions in the program slice is used to adjust the processor's operating parameters, better tuning results can be obtained.

[0210] In one possible implementation, the processor's operating parameters can be adjusted according to the number of instructions included in the first instruction subset, through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0211] The mapping relationship between the number of instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset involved in processor parameter optimization (i.e., the first instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0212] In one possible implementation, the processor's operating parameters can be adjusted based on the proportion of target type instructions in the first instruction subset, using a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0213] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the first instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0214] In one possible implementation, the processor's operating parameters can be adjusted based on the number of instructions included in the first instruction subset and the proportion of target type instructions through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0215] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the first instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method of the processor's operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0216] In one possible implementation, the processor's operating parameters can be adjusted according to the number of instructions included in the second instruction subset, through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0217] The mapping relationship between the number of instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset involved in processor parameter optimization (i.e., the second instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the first mapping relationship based on the number of instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0218] In one possible implementation, the processor's operating parameters can be adjusted according to the proportion of target type instructions in the second instruction subset through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0219] The mapping relationship between the proportion of target type instructions in the instruction subset and the processor's operating parameters can be pre-configured. After determining the instruction subset (i.e., the second instruction subset) involved in processor parameter optimization, the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the proportion of target type instructions in the target instruction subset and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for processor operating parameters, this embodiment only requires determining the adjustment method for processor operating parameters from the first mapping relationship based on the proportion of target type instructions in the target instruction subset. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0220] In one possible implementation, the processor's operating parameters can be adjusted based on the number of instructions included in the second instruction subset and the proportion of target type instructions through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0221] In one possible implementation, the mapping relationship between the number of instructions in the instruction subset, the proportion of target type instructions, and the processor's operating parameters can be pre-configured. After determining the instruction subset participating in processor parameter optimization (i.e., the third instruction subset), the adjustment of the processor's operating parameters can be determined based on the mapping relationship between the number of instructions in the target instruction subset, the proportion of target type instructions, and the processor's operating parameters. Compared to existing technologies that require complex processing of program slices to determine the adjustment method for the processor's operating parameters, this embodiment only requires determining the adjustment method for the processor's operating parameters from the mapping relationship based on the number of instructions in the target instruction subset and the proportion of target type instructions. This reduces processing complexity and improves the processing speed and real-time performance of online processor tuning.

[0222] In one possible implementation, the first instruction subset is one of the at least two instruction subsets in the first program instruction set; or, the second instruction subset is one of the at least two instruction subsets in the second program instruction set.

[0223] In one possible implementation, the first instruction subset is selected from the plurality of instruction subsets of the first program instruction set based on the optimizability of the processor when running the instruction subset; or, the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set based on the optimizability of the processor when running the instruction subset; wherein the optimizability indicates the extent to which the performance of the processor is optimized by adjusting parameters of the processor or processor-related registers when running the instruction subset.

[0224] "Instruction subsets more suitable for processor parameter tuning" can be understood as follows: when a processor runs instruction subset A, its optimization potential is higher compared to running other instruction subsets. Therefore, "instruction subset A" is more suitable for participating in processor parameter tuning. The degree of optimization potential indicates the extent to which the processor's performance parameters can be optimized by adjusting the parameters of the processor or its related registers when running an instruction subset. For a given code set, adjusting the parameters of the processor or its related registers often results in a higher optimization potential for the processor's performance parameters (compared to other code sets). Code sets with these characteristics can be considered to have a significant impact on the processor's operating performance. Parameter tuning of the processor based on code sets with these characteristics will result in a better processor state, i.e., higher operating performance.

[0225] In one possible implementation, the first instruction subset is selected from a subset of instructions among multiple instruction subsets included in the first program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or, the second instruction subset is selected from a subset of instructions among multiple instruction subsets included in the second program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the multiple instruction subsets of the second program instruction set.

[0226] To ensure that the final selected instruction subset is suitable for processor parameter tuning, the number of candidate subsets needs to be large (the more candidate subsets, the greater the probability of selecting a better instruction subset). However, when the number of instruction subsets included in the candidate set (multiple instruction subsets) is too large (e.g., thousands), evaluating whether each instruction subset is suitable for processor parameter tuning requires a certain computational overhead, leading to a large overall computational overhead. Therefore, in this embodiment, the candidate set needs to be screened first to reduce the number of subsets included in the candidate set (i.e., selecting a portion of the instruction subsets from the multiple instruction subsets). Then, only a smaller number of candidate subsets need to be selected for processor parameter tuning (i.e., selecting the first or second instruction subset from this portion of the instruction subsets), thereby reducing the overall computational overhead.

[0227] The following describes a data processing apparatus provided in an embodiment of this application, referring to... Figure 5 This application provides a data processing apparatus 500, comprising:

[0228] Instruction selection module 501 is used to determine multiple instruction subsets from a first set of program instructions; wherein, at least two instruction subsets in the multiple instruction subsets include different numbers of instructions or different proportions of target type instructions; and to select a target instruction subset from the multiple instruction subsets.

[0229] The specific description of the instruction selection module 501 can be found in the description of steps 201 and 202 in the above embodiments, and the similarities will not be repeated here.

[0230] The parameter adjustment module 502 is used to adjust the operating parameters of the processor running the first program instruction set according to the target instruction subset.

[0231] The specific description of the parameter adjustment module 502 can be found in step 203 of the above embodiment, and the similarities will not be repeated here.

[0232] In one possible implementation, the adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset; or,

[0233] The adjustments made to the processor's operating parameters are related to the proportion of target type instructions in the target instruction subset; or,

[0234] The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

[0235] In one possible implementation, the parameter adjustment module 502 is specifically used to: adjust the processor's operating parameters according to the number of instructions included in the target instruction subset through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions.

[0236] In one possible implementation, the parameter adjustment module 502 is specifically used to: adjust the processor's operating parameters according to the proportion of target type instructions in the target instruction subset through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions.

[0237] In one possible implementation, the parameter adjustment module 502 is specifically used to: adjust the processor's operating parameters according to the number of instructions included in the target instruction subset and the proportion of target type instructions through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0238] In one possible implementation, the target instruction subset is one of the at least two instruction subsets.

[0239] In one possible implementation, the target instruction subset is selected from a plurality of instruction subsets based on the degree of optimizability of the processor when running the instruction subset; wherein the degree of optimizability indicates the extent to which the processor's performance parameters are optimized by adjusting parameters of the processor or processor-related registers when running the instruction subset.

[0240] In one possible implementation, the instruction selects module 501, specifically for:

[0241] Select a subset of instructions from the multiple subsets of instructions;

[0242] Select the target instruction subset from this instruction subset.

[0243] In one possible implementation, selecting the target instruction subset from the partial instruction subset includes:

[0244] The target instruction subset is selected from the partial instruction subset based on the degree of optimizability of the processor in running each instruction subset.

[0245] In one possible implementation, the target instruction subset is selected from a subset of the plurality of instruction subsets, the subset of instruction subsets including one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets.

[0246] In one possible implementation, the instruction selection module 501 is specifically used for:

[0247] Obtain the characteristics of multiple candidate instructions for each instruction subset and the performance of the processor when running the instruction subset;

[0248] Select a subset of instruction features from the plurality of candidate instruction features, such that the performance of instruction subsets of different categories differs in the clustering results obtained by clustering the plurality of instruction subsets based on the subset of instruction features.

[0249] In one possible implementation, the performance is expressed as instructions per cycle (IPC).

[0250] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage. In another possible implementation, the instruction selection module 501 is configured to determine a first instruction subset from a first program instruction set; and to determine a second instruction subset from a second program instruction set; wherein the second program instruction set comprises program instructions to be executed after the first program instruction set, and the first and second instruction subsets include different numbers of instructions, or the proportion of target type instructions in the first and second instruction subsets differs.

[0251] The specific description of the instruction selection module 501 can be found in the description of steps 401 and 403 in the above embodiments, and the similarities will not be repeated here.

[0252] The parameter adjustment module 502 is used to adjust the operating parameters of the processor according to the first instruction subset and the second instruction subset.

[0253] The specific description of the parameter adjustment module 502 can be found in the description of steps 402 and 404 in the above embodiments, and the similarities will not be repeated here.

[0254] In one possible implementation, the instruction selects module 501, specifically for:

[0255] Multiple instruction subsets are determined from a first set of program instructions to be executed; wherein, at least two instruction subsets in the first set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a first instruction subset is selected from the multiple instruction subsets determined from the first set of program instructions, or...

[0256] Multiple instruction subsets are determined from the second set of program instructions to be executed; wherein, at least two instruction subsets in the second set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a second instruction subset is selected from the multiple instruction subsets determined from the second set of program instructions.

[0257] In one possible implementation, the adjustment of the processor's operating parameters is related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or,

[0258] The adjustments made to the processor's operating parameters are related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

[0259] In one possible implementation, the parameter adjustment module 502 is used for:

[0260] Based on the number of instructions included in the first instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or,

[0261] Based on the proportion of target type instructions in the first instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or,

[0262] Based on the number of instructions included in the first instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0263] In one possible implementation, the parameter adjustment module 502 is used for:

[0264] Based on the number of instructions included in the second instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or,

[0265] Based on the proportion of target type instructions in the second instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or,

[0266] Based on the number of instructions included in the second instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

[0267] In one possible implementation, the first instruction subset is one of the at least two instruction subsets in the first set of program instructions; or...

[0268] The second instruction subset is one of the at least two instruction subsets in the second set of program instructions.

[0269] In one possible implementation, the first instruction subset is selected from the plurality of instruction subsets of the first program instruction set based on the degree of optimizability of the processor when running the instruction subset; or, the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set based on the degree of optimizability of the processor when running the instruction subset.

[0270] The degree of optimizability indicates the extent to which the performance of the processor can be optimized by adjusting the parameters of the processor or the processor-related registers when running a subset of instructions.

[0271] In one possible implementation, the first instruction subset is selected from a subset of instructions among multiple instruction subsets included in the first program instruction set, wherein the subset includes one or more instruction subsets from each category in the clustering result obtained by clustering the multiple instruction subsets of the first program instruction set; or,

[0272] The second instruction subset is selected from a subset of instructions from a plurality of instruction subsets included in the second program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets of the second program instruction set.

[0273] In one possible implementation, the performance is expressed as instructions per cycle (IPC).

[0274] In one possible implementation, the operating parameters include at least one of the processor's operating frequency and operating voltage.

[0275] Please see Figure 6 , Figure 6 A schematic diagram of the structure of a computing device provided in this application. Figure 6 The computing device 600 shown can be used to execute the data processing method provided in this application. For example... Figure 6As shown, the computing device 600 includes a bus 602, a processor 604, a memory 606, and a communication interface 608. The processor 604, the memory 606, and the communication interface 608 communicate with each other via the bus 602. The computing device 600 can be a server or a terminal device. It should be understood that this application does not limit the number of processors, accelerators, and memories in the computing device 600.

[0276] Bus 602 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 6 The bus 602 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 602 may include a path for transmitting information between various components of the computing device 600 (e.g., memory 606, processor 604, communication interface 608).

[0277] Processor 604 may include any one or more of the following: central processing unit (CPU), microprocessor (MP), digital signal processor (DSP), accelerator (e.g., graphics processing unit (GPU), neural network processing unit (NPU)).

[0278] Memory 606 may include volatile memory, such as random access memory (RAM). Processor 604 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0279] The memory 606 stores executable program code, which the processor 604 executes to implement the data processing method described above. In other words, the memory 606 stores program code for executing the data processing method.

[0280] The communication interface 608 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 600 and other devices or communication networks.

[0281] It should be understood that the computing device 600 according to this application is used to perform, for example... Figures 2 to 4A The data processing method can correspond to the corresponding subject in the method according to this application, and for the sake of brevity, it will not be described in detail here.

[0282] This application also provides a computing device cluster. The computing device cluster includes multiple computing devices. These computing devices can be servers, such as central servers, edge servers, or local servers in a local data center. In some embodiments, the computing devices can also be terminal devices such as desktop computers, laptops, or smartphones.

[0283] Please see Figure 7 , Figure 7 This is a schematic diagram of a computing device cluster provided in this application. Figure 7 As shown, the computing device cluster includes multiple computing devices 600. The memory 606 of the multiple computing devices 600 in the computing device cluster may store the same instructions for executing data processing methods. The different computing devices 600 in the computing device cluster may be connected via a local area network (LAN).

[0284] In some possible implementations, the memories 606 of the multiple computing devices 600 in the computing device cluster may also each store a portion of the instructions for executing the data processing method. In other words, the combination of multiple computing devices 600 can jointly execute the instructions of the data processing method to adjust the parameters of one of the computing devices (which may be the processor executing the data processing method or other processors).

[0285] It should be noted that the memory 606 in different computing devices 600 in the computing device cluster can store different instructions, which are used to execute some functions of the data processing method provided in the embodiments of this application.

[0286] In some possible implementations, one of the computing devices in the cluster or computing device 600 can act as a management node to execute the step of determining the processor adjustment parameters in the data processing method provided in this application, and perform parameter tuning on one or more other processors in the computing device cluster based on the execution result. For example, one of the computing devices in the cluster or computing device 600 can obtain the program instructions that one or more other processors in the cluster need to execute, determine the processor parameter adjustment strategy according to the program instructions, and perform parameter tuning on one or more other processors in the cluster based on the parameter adjustment strategy.

[0287] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN), etc. Figure 8 One possible implementation method is shown. Figure 8 This is a schematic diagram of another computing device cluster structure provided in this application. Figure 8 As shown, in the computing device cluster 800, two computing devices 600A and 600B are connected via a network. Specifically, they are connected to the network through the communication interfaces in each computing device.

[0288] It should be understood that the method in the embodiments of this application can be completed jointly by the processors of multiple computing devices, that is, using multiple computing devices for distributed computing, for example, Figure 8 The functions of computing device 600A shown can also be performed by multiple computing devices 600. Similarly, the functions of computing device 600B can also be performed by multiple computing devices 600.

[0289] In some possible implementations, one or more computing devices in the computing device cluster (e.g., 600A or 600B) can act as a management node to execute the step of determining the processor adjustment parameters in the data processing method provided in this application, and perform parameter tuning on one or more other processors in the computing device cluster based on the execution result. For example, one or more computing devices in the computing device cluster (e.g., 600A or 600B) can obtain the program instructions that one or more other processors in the computing device cluster need to execute, determine the processor parameter adjustment strategy according to the program instructions, and perform parameter tuning on one or more other processors in the computing device cluster based on the parameter adjustment strategy.

[0290] It should be understood that the computing device 600 in this application, Figure 7 The computing device cluster or computing device cluster 800 in this application may correspond to the computing device cluster in this application. Figure 6 The data processing apparatus in the present application can be used to execute the data processing apparatus in the present application. Figure 2 The corresponding main body of the data processing method. Furthermore, the above and other operations and / or functions of each module in the computing device 600 or computing device cluster 800 are respectively for implementing... Figure 2 For the sake of brevity, the corresponding process of the data processing method will not be elaborated here.

[0291] Please refer to Figure 9 , Figure 9 This is a schematic diagram of a computer-readable storage medium provided in this application. This application also provides a computer-readable storage medium in some embodiments, wherein the above-described... Figure 3AThe disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0292] Figure 9 A conceptual partial view of an example computer-readable storage medium arranged according to at least some of the embodiments shown herein is illustrated schematically. The example computer-readable storage medium includes a computer program for executing computer processes on a computing device.

[0293] In one embodiment, the computer-readable storage medium 900 is provided using a signal bearer medium 901. The signal bearer medium 901 may include one or more program instructions 902 that, when executed by one or more processors, can provide the above-mentioned... Figure 3A The described function or part of the function.

[0294] In some examples, the signal carrying medium 901 may include a computer-readable medium 903, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video optical disc (DVD), a digital magnetic tape, a memory, ROM, or RAM, etc.

[0295] In some embodiments, the signal-bearing medium 901 may comprise a computer-recordable medium 904, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and so on. In some embodiments, the signal-bearing medium 901 may comprise a communication medium 905, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, and so on). Therefore, for example, the signal-bearing medium 901 may be transmitted by a wireless communication medium 905 (e.g., a wireless communication medium conforming to the IEEE 1202.X standard or other transmission protocols).

[0296] One or more program instructions 902 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 902 conveyed to the computing device via a computer-readable medium 903, a computer-recordable medium 904, and / or a communication medium 905.

[0297] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0298] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods of the various embodiments of this application.

[0299] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0300] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, computer instructions can be transferred from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0301] The above are merely specific embodiments of this application. Variations or substitutions conceived by those skilled in the art based on the specific embodiments provided in this application should all be covered within the protection scope of this application.

Claims

1. A data processing method, characterized in that, The method includes: Determine a first subset of instructions from the first set of program instructions to be executed; Based on the first instruction subset, the operating parameters of the processor executing the first program instruction set are adjusted; A second instruction subset is determined from the second set of program instructions to be executed; wherein the second set of program instructions is the program instructions to be executed after the first set of program instructions, and the first and second instruction subsets include different numbers of instructions, or the proportion of target type instructions in the first and second instruction subsets is different; The processor's operating parameters are adjusted according to the second instruction subset.

2. The method according to claim 1, characterized in that, Determining the first instruction subset from the first set of program instructions to be executed includes: Multiple instruction subsets are determined from a first set of program instructions to be executed; wherein, at least two instruction subsets in the first set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a first instruction subset is selected from the multiple instruction subsets determined from the first set of program instructions, or... Determining the second instruction subset from the second set of program instructions to be executed includes: Multiple instruction subsets are determined from the second set of program instructions to be executed; wherein, at least two instruction subsets in the second set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a second instruction subset is selected from the multiple instruction subsets determined from the second set of program instructions.

3. The method according to claim 1 or 2, characterized in that, The adjustments made to the processor's operating parameters are related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or, The adjustments made to the processor's operating parameters are related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

4. The method according to any one of claims 1 to 3, characterized in that, The step of adjusting the operating parameters of the processor executing the first program instruction set according to the first instruction subset includes: Based on the number of instructions included in the first instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or, Based on the proportion of target type instructions in the first instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or, Based on the number of instructions included in the first instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

5. The method according to any one of claims 1 to 4, characterized in that, The step of adjusting the processor's operating parameters according to the second instruction subset includes: Based on the number of instructions included in the second instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or, Based on the proportion of target type instructions in the second instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or, Based on the number of instructions included in the second instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

6. The method according to any one of claims 2 to 5, characterized in that, The first instruction subset is one of the at least two instruction subsets in the first program instruction set; or, The second instruction subset is one of the at least two instruction subsets in the second set of program instructions.

7. The method according to any one of claims 1 to 6, characterized in that, The first instruction subset is selected from the plurality of instruction subsets of the first program instruction set based on the optimizability of the processor when running the instruction subset; or, the second instruction subset is selected from the plurality of instruction subsets of the second program instruction set based on the optimizability of the processor when running the instruction subset. The degree of optimizability indicates the extent to which the performance of the processor can be optimized by adjusting the parameters of the processor or the processor-related registers when running a subset of instructions.

8. The method according to any one of claims 1 to 7, characterized in that, The first instruction subset is selected from a subset of instructions from a plurality of instruction subsets included in the first program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets of the first program instruction set; or, The second instruction subset is selected from a subset of instructions from a plurality of instruction subsets included in the second program instruction set, wherein the subset of instructions includes one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets of the second program instruction set.

9. The method according to claim 7 or 8, characterized in that, The performance is expressed as instructions per cycle (IPC).

10. The method according to any one of claims 1 to 9, characterized in that, The operating parameters include at least one of the processor's operating frequency and operating voltage.

11. A data processing method, characterized in that, The method includes: Multiple instruction subsets are determined from the first set of program instructions to be executed; wherein, at least two instruction subsets contain different numbers of instructions or different proportions of target type instructions. Select a target instruction subset from the plurality of instruction subsets; Based on the target instruction subset, the operating parameters of the processor running the first program instruction set are adjusted.

12. The method according to claim 11, characterized in that, The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset; or, The adjustments made to the processor's operating parameters are related to the proportion of target type instructions in the target instruction subset; or, The adjustments made to the processor's operating parameters are related to the number of instructions included in the target instruction subset and the proportion of target type instructions.

13. The method according to claim 11 or 12, characterized in that, The step of adjusting the operating parameters of the processor executing the first program instruction set according to the target instruction subset includes: Based on the number of instructions included in the target instruction subset, the processor's operating parameters are adjusted through a first mapping relationship; the first mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions; or, Based on the proportion of target type instructions in the target instruction subset, the processor's operating parameters are adjusted through a second mapping relationship; the second mapping relationship indicates the correspondence between the processor's operating parameters and the proportion of target type instructions; or, Based on the number of instructions included in the target instruction subset and the proportion of target type instructions, the processor's operating parameters are adjusted through a third mapping relationship; the third mapping relationship indicates the correspondence between the processor's operating parameters and the number of instructions and the proportion of target type instructions.

14. The method according to any one of claims 11 to 13, characterized in that, The target instruction subset is selected from a subset of the plurality of instruction subsets, and the subset of instruction subsets includes one or more instruction subsets in each category of the clustering result obtained by clustering the plurality of instruction subsets.

15. The method according to claim 14, characterized in that, The method further includes: Obtain the characteristics of multiple candidate instructions for each instruction subset and the performance of the processor when running the instruction subset; Select a subset of instruction features from the plurality of candidate instruction features, such that there are differences between instruction subsets of different categories in the clustering results obtained by clustering the plurality of instruction subsets based on the subset of instruction features.

16. A data processing apparatus, characterized in that, include: The instruction selection module is used to determine a first instruction subset from a first set of program instructions and a second instruction subset from a second set of program instructions. The second set of program instructions is the program instructions that need to be executed after the first set of program instructions. The first and second instruction subsets include different numbers of instructions or different proportions of target type instructions in the first and second instruction subsets. The parameter adjustment module is used to adjust the processor's operating parameters according to the first instruction subset and the second instruction subset.

17. The apparatus according to claim 16, characterized in that, The instruction selection module is specifically used for: Multiple instruction subsets are determined from a first set of program instructions to be executed; wherein, at least two instruction subsets in the first set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a first instruction subset is selected from the multiple instruction subsets determined from the first set of program instructions, or... Multiple instruction subsets are determined from the second set of program instructions to be executed; wherein, at least two instruction subsets in the second set of program instructions contain different numbers of instructions or different proportions of target type instructions, and a second instruction subset is selected from the multiple instruction subsets determined from the second set of program instructions.

18. The apparatus according to claim 16 or 17, characterized in that, The adjustments made to the processor's operating parameters are related to the number of instructions included in the first instruction subset or the proportion of target type instructions in the first instruction subset; or, The adjustments made to the processor's operating parameters are related to the number of instructions included in the second instruction subset or the proportion of target type instructions in the second instruction subset.

19. A computing device, characterized in that, The device includes a memory and a processor; the memory stores code, and the processor is configured to execute the code, wherein when the code is executed, the computing device performs the method as described in any one of claims 1 to 15.

20. A computing device cluster, characterized in that, It includes one or more computing devices, each computing device including a processor and memory; The processor of the at least one computing device is configured to execute program code stored in the memory of the at least one computing device, so that the cluster of computing devices performs the operational steps of the method as described in any one of claims 1 to 15.

21. A computer program product, characterized in that, The computer program product stores program code, and the instructions, when executed by a computer, cause the computer to perform the method described in any one of claims 1 to 15.

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