A PCB schematic diagram picture labeling and data set generation method and system

Abstract

The application belongs to the technical field of electronic design automation, and discloses a PCB schematic diagram picture labeling and data set generation method and system. The method automatically reads a PCB schematic diagram picture through a YOLO model to generate a YOLO format file to obtain component information, then cuts the picture by using a QT tool and classifies based on a label, then carries out label inspection and labeling to generate a log file, and finally processes the log file to modify a YOLO format output label data set. The method greatly improves the labeling efficiency, reduces the labor cost and error rate, enhances the adaptability to different EDA tools for generating schematic diagrams, simplifies the construction of high-quality data sets, and thus accelerates the landing application of artificial intelligence in circuit design automation.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation technology, and in particular relates to a method and system for annotating PCB schematic images and generating datasets. Background Technology

[0002] In the field of Electronic Design Automation (EDA), printed circuit board (PCB) schematics are the key carriers of core circuit design information. They visually present crucial data such as component models, electrical connections, and functional definitions, serving as the foundation for the entire circuit design, simulation, manufacturing, and maintenance process. With the rapid development of electronic devices towards higher density, complexity, and integration, the number of components contained in PCB schematics is increasing exponentially. Accurately extracting component information from PCB schematics and generating standardized engineering files or netlists has become a core component supporting the automation of the entire EDA process. Currently, artificial intelligence (AI) technology is gradually being applied to information extraction from PCB schematics; however, the implementation of these technologies relies on high-quality labeled datasets. Existing dataset construction and component identification technologies still fall short of meeting the needs of AI model training and practical engineering applications.

[0003] However, existing technologies have many prominent problems in PCB schematic component identification and annotation dataset construction, mainly reflected in the limitations of core technology paths and key technology bottlenecks. In terms of technology paths, mainstream manual identification and template matching methods have significant drawbacks: manual identification relies on designers manually annotating the location, type, and attributes of components, which is not only extremely inefficient and costly in complex schematics containing thousands of components, but also prone to omissions and misjudgments due to information density and complex layouts. Furthermore, it lacks repeatability and programmatic traceability, failing to meet the needs of automated design. Template matching methods parse fixed-format schematics through a "template-rule" dual-constraint mechanism, but it is highly dependent on standardized formats. Faced with differentiated formats generated by different design tools such as Altium and Cadence, rules and templates need to be repeatedly adjusted, resulting in extremely high migration costs. It also struggles to handle complex scenarios such as high-density layouts, cross-page connectivity, and irregular arrangements, easily leading to anchor point drift and matching conflicts. In terms of technical bottlenecks, the dense arrangement of components, crisscrossing lines, and complex annotation information in PCB schematics lead to coupled challenges in region segmentation, feature extraction, and text localization. Furthermore, the diversity and uniqueness of component symbols due to differences in design tools, industry standards, and individual design styles further exacerbate the recognition difficulty. In addition, existing image processing technologies suffer from complex algorithms and long processing times when generating high-quality labeled datasets, while solutions such as purely manual verification and template matching have not yet overcome the inherent defects of low efficiency and insufficient accuracy.

[0004] It is evident that existing methods for annotating datasets have significant bottlenecks in the intelligent identification and annotation of components in PCB schematics, particularly in the efficient construction of high-quality annotated datasets. This severely restricts the application of artificial intelligence technology in the EDA field and the advancement of automated circuit design processes. Summary of the Invention

[0005] The purpose of this invention is to provide a method and system for annotating PCB schematic images and generating datasets. This method can solve the problems of low efficiency and low accuracy in manually annotating component datasets in complex PCB schematic images. This method can accelerate the application of artificial intelligence technology in the EDA field and promote the automation of circuit design processes.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for annotating PCB schematic images and generating datasets includes:

[0008] The PCB schematic image is read using the YOLO model to obtain a YOLO format file; wherein, the YOLO format file includes PCB component information;

[0009] The QT tool is used to read YOLO format files and PCB schematic images. Based on the labels, box coordinates and box size obtained from reading the YOLO format files, the PCB schematic images are cropped. The cropped images are then classified according to component label categories to obtain labeled images.

[0010] Perform label verification on all labeled images, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing label categories;

[0011] The log file was processed using QT tools to perform label classification, and the YOLO format file was modified based on the label classification results. The modified YOLO format file was then output as the label dataset.

[0012] Furthermore, the process involves performing label verification on all labeled images, generating label verification results, labeling the cropped images with label categories based on the label verification results, and generating a log file containing the label categories, which includes modified categories, relabeled categories, and deleted categories.

[0013] Furthermore, the process involves using QT tools to perform label classification on the log file, obtaining the label classification results, modifying the YOLO format file based on the results, and outputting the modified YOLO format file as the label dataset, including:

[0014] If the label category is "modify", then output the modified label result, modifying the corresponding label in the YOLO format file;

[0015] If the label category is "re-labeling", then output the re-labeling results and modify the corresponding box coordinates and box size in the YOLO format file;

[0016] If the label category is the delete category, output the deletion label results and delete the corresponding row of data in the YOLO format file;

[0017] The modified YOLO format file is output as a labeled dataset.

[0018] Furthermore,

[0019] If the tag category is "modify", then the modified tag result will be output, modifying the tags corresponding to the YOLO format file, including:

[0020] If the label category is "modify", the modified label result will be output. The YOLO format file will identify all boxes in the corresponding PCB schematic image and replace the original label with the new label in the YOLO format file.

[0021] If the label category is a re-labeling category, then the re-labeling result is output, and the coordinates and size of the corresponding boxes in the YOLO format file are modified, including:

[0022] If the label category is re-labeling, output the re-labeling results, modify the box coordinates and size using the LabelImg image annotation tool, and retain the original label. After modification, replace the original box coordinates and size in the YOLO format file.

[0023] If the label category is a deletion category, then the deletion label result will be output, deleting the corresponding row of data in the YOLO format file, including:

[0024] If the label category is the deletion category, the deletion label results will be output. All boxes in the corresponding PCB schematic image will be identified in the YOLO format file, and the corresponding matching rows in the YOLO format file will be deleted.

[0025] Furthermore, after reading the PCB schematic image using the YOLO model to obtain a YOLO format file, the process also includes:

[0026] The LabelImg image annotation tool was used to check for missing labels in the YOLO format file, resulting in a YOLO format file after the missing label check.

[0027] Furthermore, the step of using the LabelImg image annotation tool to perform component omission checks on the YOLO format file to obtain a YOLO format file after omission checks includes:

[0028] Import the YOLO format file into the LabelImg image annotation tool to check for missing component labels;

[0029] If there are missing labels for an entire row of components, perform a fill-in operation in the graphical interface and fill in a new row of components.

[0030] Furthermore, after using QT tools to perform label classification processing on the log file to obtain the label classification results, modifying the YOLO format file based on the label classification results, and outputting the modified YOLO format file as the label dataset, the process also includes:

[0031] The output labeled dataset is used as the training dataset to iteratively train the pre-built YOLO model to output a trained object detection model; the object detection model is used to preprocess new PCB schematic images.

[0032] Furthermore, the step of using a YOLO model to read the PCB schematic image to obtain a YOLO format file includes:

[0033] The YOLO model is used to identify components in PCB schematic images and generate YOLO format files.

[0034] Pair YOLO format files with PCB schematic images according to the same name principle to obtain a quick lookup table for rapid lookup during subsequent manual verification.

[0035] Furthermore, the method involves using QT tools to read YOLO format files and PCB schematic images, cropping the PCB schematic images based on the labels, box coordinates, and box sizes obtained from the YOLO format files, and then categorizing the cropped images according to component label categories, including:

[0036] The QT tool is used to read YOLO format files and PCB schematic images. Each line of data in the YOLO format file is parsed to obtain pixel coordinates. Based on the pixel coordinates, component miniatures are cropped from the PCB schematic images.

[0037] The component thumbnails are categorized according to different component label categories to obtain labeled images.

[0038] A PCB schematic image annotation and dataset generation system includes:

[0039] The reading module is used to read PCB schematic images using a YOLO model to obtain a YOLO format file; wherein the YOLO format file includes PCB component information;

[0040] The image cropping module is used to read YOLO format files and PCB schematic images using QT tools. It crops the PCB schematic images based on the labels, box coordinates, and box size obtained from the YOLO format files, and categorizes the cropped images according to component label categories to obtain labeled images.

[0041] The label verification module is used to perform label verification on images of all label categories, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing the label categories;

[0042] The dataset generation module uses QT tools to perform label classification on log files, obtain label classification results, modify YOLO format files based on the label classification results, and output the modified YOLO format files as label datasets.

[0043] Compared with existing technologies, the present invention has the following beneficial effects:

[0044] This invention provides a method for annotating PCB schematic images and generating datasets. It automatically reads PCB schematic images using a YOLO model to generate YOLO format files to obtain component information. Then, it uses a QT tool to crop the images and classify them based on labels. Subsequently, label verification and annotation are performed to generate log files. Finally, the log files are processed to modify the YOLO format and output a labeled dataset. The YOLO model achieves efficient component recognition, avoiding the inefficiency and errors of manual annotation. Meanwhile, the QT tool automates the cropping and classification process, improving processing speed. The label verification mechanism ensures data accuracy through validation. The overall process utilizes deep learning and graphical interface tools in collaboration, breaking the dependence of template matching on standard formats and effectively handling high-density layouts and design diversity. This method significantly improves annotation efficiency, reduces labor costs and error rates, enhances adaptability to schematic generation from different EDA tools, and simplifies the construction of high-quality datasets, thereby accelerating the application of artificial intelligence in automated circuit design. Attached Figure Description

[0045] Figure 1 This is a flowchart illustrating an implementation method for PCB schematic image annotation and dataset generation, provided in an embodiment of the present invention.

[0046] Figure 2 A flowchart illustrating a method for annotating PCB schematic images and generating datasets provided by this invention;

[0047] Figure 3 This is a schematic diagram of the structure of a PCB schematic image annotation and dataset generation system provided by the present invention. Detailed Implementation

[0048] To facilitate a deeper understanding of the technical solution of this invention, the following explanations are provided for the technical terms:

[0049] PCB: Full name Printed Circuit Board, also known as printed circuit board.

[0050] EDA stands for Electronic Design Automation.

[0051] QT tools: A collection of tools developed based on the Qt framework for building cross-platform graphical user interface applications; this invention refers to visual interface design tools.

[0052] LabelImg is an open-source graphical image annotation tool.

[0053] YOLO Model: YOLO stands for You Only Look Once, and it is a real-time object detection algorithm based on deep learning.

[0054] As mentioned in the background section, existing methods for annotating PCB schematics have the following drawbacks: First, purely manual verification of PCB schematics: This relies on manual labor, requires a certain level of circuit knowledge, involves repetitive work, is inefficient, and prone to errors. Second, template matching: This requires the pre-establishment of a symbol template library, but in scenarios with complex components, the number of templates grows exponentially, and the matching time is proportional to the number of templates, resulting in low efficiency and uncertain accuracy.

[0055] To achieve the above objectives, this embodiment provides a method for annotating PCB schematic images and generating datasets. This method utilizes YOLO and QT tools, combined with label verification techniques, to quickly generate high-quality YOLO-formatted PCB component annotation datasets to support AI model training and optimization. This method changes traditional annotation methods by using visual models and the developed annotation tool QT to minimize the number of manual checks, resulting in high-quality datasets. Simultaneously, through manual dataset cleaning, the dataset can be expanded and iteratively trained to continuously improve model performance.

[0056] like Figure 2 As shown, this embodiment provides a method for annotating PCB schematic images and generating datasets, including:

[0057] The PCB schematic image is read using the YOLO model to obtain a YOLO format file; wherein, the YOLO format file includes PCB component information;

[0058] The QT tool is used to read YOLO format files and PCB schematic images. Based on the labels, box coordinates and box size obtained from reading the YOLO format files, the PCB schematic images are cropped. The cropped images are then classified according to component label categories to obtain labeled images.

[0059] Perform label verification on all labeled images, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing label categories;

[0060] The log file was processed using QT tools to perform label classification, and the YOLO format file was modified based on the label classification results. The modified YOLO format file was then output as the label dataset.

[0061] The following description, in conjunction with the accompanying drawings, further illustrates the PCB schematic image annotation and dataset generation method provided in this embodiment:

[0062] like Figure 1As shown in the figure, this embodiment provides a method for annotating PCB schematic images and generating datasets. The specific steps are as follows:

[0063] Step 1: Use the YOLO model to read the PCB schematic image and obtain a YOLO format file containing PCB component information.

[0064] Step 2: Use the LabelImg image annotation tool to check the YOLO format file to determine if any components are missing labels. After checking, save it as a YOLO format file.

[0065] Step 3: Use QT tools to read the YOLO format file and the corresponding PCB schematic image. Crop the PCB schematic image according to the labels, box coordinates and box size in the YOLO format file. Sort the cropped images according to the component label categories and save them to their respective label folders.

[0066] Step 4: Use QT to open the respective tag folders and perform label verification on the cropped images (manual verification can be used here). This time, we only need to focus on whether it belongs to the tag. This labeling is divided into three categories: modification category, relabeling category, and deletion category, corresponding to "change_class", "relabel", and "delete" respectively. After completing the verification, click "auto-save" to automatically save the relevant log files in the current folder.

[0067] Step 5: Use QT tools to process the log file, processing the three categories "change_class", "relabel", and "delete" separately. For the "change_class" and "delete" categories, directly modify the label or delete the line in the YOLO format file. For the "relabel" category, use the LabelImg image annotation tool to reposition and resize the annotation box (box), and then modify it accordingly in the YOLO format file. Finally, output the modified YOLO format file to obtain a high-quality labeled dataset.

[0068] Step 6: Train the object detection model using the labeled dataset, and improve the pre-labeling accuracy through dataset expansion and iteration.

[0069] In this embodiment, the technical means of step 1 (using the YOLO model to pre-annotate the PCB schematic image and generate an initial YOLO format file) and step 2 (using the LabelImg tool to check for missing component labels and synchronously update the YOLO file) solve the technical problems of low efficiency and easy omissions in traditional manual annotation of PCB schematics, and achieve the effect of quickly generating a preliminary annotation dataset.

[0070] In this embodiment, the technical problems of difficult centralized processing of annotation errors and low verification efficiency are solved by using the technical means of step 3 (using a QT program to crop images according to YOLO labels and store them by category) and step 4 (manually classifying and verifying the cropped images and recording the three types of operations "change_class", "relabel", and "delete"), achieving the effect of accurate classification and efficient error correction. It can be seen that in existing methods, manual verification is usually performed on the entire schematic diagram, which is difficult to focus on when components are densely packed, making it difficult to detect mislabeling and incorrect labeling in a timely manner. This invention automatically crops the image of each labeled component using a QT program and stores it in the corresponding folder according to the label (step 3), allowing verification personnel to focus on viewing similar components, significantly reducing cognitive burden. Subsequently, in step 4 of this embodiment, the operator only needs to determine whether the image belongs to the current label and mark the problem using the three types of quick operations "change_class", "relabel", and "delete". The system automatically records the log file, avoiding repeated viewing and manual modification. This design transforms "global verification" into "centralized classification verification", greatly improving error correction efficiency and accuracy, and ensuring the consistency of dataset labels.

[0071] In this embodiment, the technical means of step 5 (automatically correcting YOLO annotations based on the log file: modifying categories, deleting invalid boxes, and relabeling positions) solves the technical problems of large workload and error susceptibility in manual annotation correction, achieving the effect of refined annotation files. Traditional manual correction requires editing the YOLO text file line by line or reselecting components, which is cumbersome and prone to introducing new errors. In step 5 of this embodiment, the QT program automatically parses the log file generated in step 4 and performs precise operations on the YOLO file based on the three types of records: "change_class", "delete", and "relabel": automatically replacing category IDs, deleting corresponding annotation lines, or calling LabelImg to redraw bounding boxes and update coordinates. This process does not require manual intervention in the text file, avoids formatting errors and coordinate deviations, and ensures that the correction results are completely consistent with visual verification. Through the "driven correction" mechanism, a leap from "manual line-by-line modification" to "batch automatic processing" is achieved, significantly improving the efficiency and reliability of annotation refinement.

[0072] In this embodiment, the technical problem of insufficient training data quality and difficulty in self-optimization of AI models is solved by using step 6 (iteratively training the YOLO model using the final high-quality dataset to improve pre-annotation accuracy), achieving the effect of continuous evolution of model accuracy. Conventional methods often use the initial labeled data to train the model at once, lacking a feedback mechanism, leading to solidified model performance. In step 6 of this embodiment, the high-quality label set after multiple rounds of manual verification and correction is used as training data to retrain the YOLO model and is used to pre-annotate newly acquired PCB schematics. As the number of iterations increases, the model's adaptability to component shapes and layout styles continuously improves, and the pre-annotation accuracy gradually increases, thereby reducing the workload of subsequent manual verification and forming a closed-loop optimization of "data → model → better data". This mechanism enables the system to have self-evolution capabilities, providing continuous power for realizing a fully automated PCB schematic annotation system, and significantly enhancing the system's engineering practicality and long-term value.

[0073] The following example further explains the PCB schematic image annotation and dataset generation method provided in this embodiment:

[0074] The hardware environment used in this embodiment includes an industrial-grade computer equipped with an Intel Core i7-12700H processor, 32GB of memory, and an NVIDIA RTX 3060 graphics card. The software environment includes a Windows 10 operating system, a Python 3.8 programming environment, a YOLOv5 model framework, a LabelImg 1.8.6 image annotation tool, and a series of tools developed based on QT 5.15 (CropWizard cropping tool, ClassChecker quick inspector, and YoloRefiner post-processing script). The PCB schematic image to be processed is a PNG file with a resolution of 1920×1080, containing common PCB components such as resistors, capacitors, inductors, and chips.

[0075] The method for annotating PCB schematic images and generating datasets includes the following steps: First, the PCB schematic image is read using the YOLO model to obtain a YOLO format file. During this process, the YOLOv5 model is used to identify components in the PCB schematic image, automatically generating a YOLO format file (with a .txt extension) that records component labels, normalized bounding box coordinates, and bounding box size. Then, this YOLO format file is paired one-to-one with the corresponding PCB schematic image based on the same name principle, and both are stored in a temporary folder `raw_labels / `, forming a quick reference table for subsequent manual verification. This ensures the accurate association between the annotation file and the image. The PCB component information contained in the YOLO format file includes component category labels, the relative position of the component in the image, and size parameters.

[0076] After obtaining the initial YOLO format file, the LabelImg image annotation tool is used to check for missing component labels to improve the completeness of the annotations. LabelImg is launched and switched to "YOLO mode." PCB schematic images and corresponding YOLO format files from the `raw_labels / ` folder are loaded in batches. Manual checks are performed on missing component labels. If entire rows of labels for components such as resistors and capacitors are missing, the missing components are directly filled in with boxes in the LabelImg graphical interface. After determining the coordinates and size of the component box, a new row of component information is filled. After verification, the "AutoSave" button is clicked, and LabelImg will overwrite and save the modified YOLO format file in the original path, resulting in the YOLO format file after the label check.

[0077] Next, the CropWizard cropping tool, developed based on QT, was used to read the YOLO format file and the corresponding PCB schematic image after the missing label check. Each line of data in the YOLO format file was parsed, and the actual pixel coordinates (x1, y1, x2, y2) were calculated in reverse based on the normalized box coordinates recorded in the file. Based on these pixel coordinates, small images of individual components were accurately cropped from the PCB schematic image, and each component small image was named in the format "label_img_name_serial_number_x1_y1_x2_y2.jpg". Subsequently, according to different component label categories (such as resistor R, capacitor C, chip U, etc.), the cropped component small images were stored in the corresponding label folders under the `cropped_labels / ` directory. At the same time, a `crop_log.csv` file was generated, which recorded the mapping relationship of "original image path → small image path → component category" in detail, providing a basis for subsequent data traceability. Finally, a collection of images classified by label was obtained.

[0078] To generate accurate annotation information, the ClassChecker quick inspector, developed based on QT, is launched. The folder corresponding to a specific label in the `cropped_labels / ` directory is loaded in the upper left sidebar of the tool. The tool will display all component images within that folder in the form of 50 small images per page. The inspector only needs to determine whether the currently displayed small image belongs to the corresponding label category of the folder and complete the label inspection operation using preset shortcut keys: If the component category of the small image is correct but the label is incorrect, the "change_class" operation is triggered by "right-click + 3", and the tool will pop up a new category selection window for the inspector to choose from; if the small image label is correct but the box position or size is inaccurate, the "relabel" operation is triggered by "right-click + 1", and the small image background automatically turns light yellow for distinction; if the small image is incorrectly labeled and should be deleted, the "delete" operation is triggered by "right-click + 2", and the small image background automatically turns light blue for distinction. After completing the verification of all small images in the current folder, click the "AutoSave" button. The tool will generate a `log.txt` file in the folder, recording the verification results of "small image name, label category, new label (if any)". The label category includes three types: modified category, re-labeled category, and deleted category.

[0079] A YOLORefiner post-processing script developed based on QT is used to classify the `log.txt` files in all tag folders. Based on the obtained tag classification results, the YOLO format files are modified accordingly: When the tag category is "modify", the script outputs the modified tag results, identifies all box annotation information of the PCB schematic image to which the small image belongs in the corresponding YOLO format file, replaces the original tag information with the new tag, and does not change the box coordinates and size; When the tag category is "relabel", the script outputs the relabel results, extracts the PCB schematic image corresponding to the small image and the relevant paragraphs in the original YOLO format file separately and saves them to the `relabel / ` folder, automatically launches the LabelImg tool to load the image and annotation information, and the verifier only needs to modify the box coordinates and size in LabelImg while retaining the original tag. After the modification is completed, click save, and the script automatically replaces the corresponding content in the original YOLO format file with the updated box coordinates and size; When the tag category is "delete", the script outputs the deleted annotation results, identifies all box annotation rows corresponding to the small image in the YOLO format file, and directly deletes the data in these matching rows. After all `log.txt` files are processed, the script organizes the verified valid component images under `cropped_labels / ` into the `final_dataset / images / ` directory according to their final categories. At the same time, it copies the modified YOLO format files to the `final_dataset / labels / ` directory, forming a clean YOLO format labeled dataset and outputting it.

[0080] The output labeled dataset is used as the training dataset and input into a pre-built YOLOv5 model for iterative training. The initial learning rate is set to 0.001, the batch size to 16, and the number of training epochs to 100. After every 20 training epochs, a validation set is used to test the accuracy. The learning rate is adaptively adjusted based on the test results. After training, a target detection model with high recognition accuracy is output. This target detection model can be directly used to preprocess newly acquired PCB schematic images to achieve rapid pre-annotation of new images. Subsequently, manual verification and correction are performed in conjunction with the method of this embodiment to form a closed-loop optimization mechanism of "data generation - model training - accuracy improvement".

[0081] For example, a systematic experiment was conducted on the PCB schematic image annotation and dataset generation method provided in the embodiment to verify the effectiveness and reliability of the method. The aim was to comprehensively evaluate the system's performance in annotation efficiency, dataset quality, and support for artificial intelligence model training. The experimental design, including data preparation, metric definition, implementation steps, and expected result analysis, is described in detail below.

[0082] S1. Obtain the dataset:

[0083] S1.1, Data Source:

[0084] The data comes from publicly available PCB circuit schematic images from PCB design websites or forums.

[0085] S1.2 Dataset Requirements:

[0086] Diversity requirements: Data should come from different PCB design software, such as JLCPCB, KiCAD, Altium, etc.

[0087] Clarity requirements: The schematic diagram image must be clear and complete. It may contain watermarks, but it must not obscure the components.

[0088] Application scenario requirements: The PCB has a wide variety of components, and the collected datasets contain data from different application scenarios, such as STM32 development, embedded systems, microcontrollers, power supply relationships, communication circuits, etc.

[0089] Data set size: Each scenario has at least 100 schematic images, with simple schematics (components 1-20) accounting for 30%, medium-sized schematics (21-50) accounting for 40%, and complex schematics (51-100) accounting for 30%.

[0090] Dataset partitioning: includes a training set for generating YOLO annotations and training the model, a validation set for verifying the quality of the annotation data generated by the system, and a test set for finally verifying the system's performance.

[0091] S1.3 Data preparation process:

[0092] S1.3.1 Download and collect the PCB schematic images required for each scenario.

[0093] S1.3.2 Image processing algorithm preprocessing: Images with low clarity, incompleteness, or severe watermark coverage are filtered out and then discarded.

[0094] S1.3.3. Divide the schematic diagrams into three categories: simple, medium, and complex, according to the number of components.

[0095] S2. Performance Evaluation Indicators:

[0096] S2.1, Labeling accuracy:

[0097] S2.1.1, Accuracy: The percentage of components correctly labeled in the YOLO files generated by the system.

[0098] S2.1.2 Recall rate: The proportion of actual components that are correctly labeled.

[0099] S2.1.3, F1-score: Harmonic average of precision and recall.

[0100] S2.2 Processing efficiency: The time (in seconds) for the system to process a single schematic file and generate YOLO annotations.

[0101] S2.3 YOLO Model Performance: Train the artificial intelligence model using the generated YOLO labeled dataset and evaluate its mean accuracy on the validation set.

[0102] S3. Experimental Procedure:

[0103] S3.1 Experimental Preparation: A total of 3,000 JLCPCB EDA Professional Edition project files covering 20 different scenarios were prepared. The schematic diagrams were classified according to their complexity, and each type of schematic diagram was further divided into a training set (70%), a validation set (15%), and a test set (15%).

[0104] S3.2 Experimental Procedure:

[0105] S3.2.1 Initial Model Pre-training:

[0106] A total of 200 files were manually labeled for different scenarios. After two rounds of checks to ensure complete accuracy, these files were used to pre-train the artificial intelligence model to obtain a preliminary model.

[0107] S3.2.2 Training Set Pre-labeling: Run the model on the schematic file in the training set to obtain a pre-labeled YOLO file. The pre-labeled YOLO file is then input into the system program to obtain a revised YOLO file.

[0108] S3.2.3. Record the processing time of each file for label quality assessment. Use the program's visualization function to compare and check the labels labeled by the program with those labeled manually, and calculate the precision, recall, and F1 score.

[0109] S3.2.4 Dataset Cleaning and Model Iteration: Manually clean the revised YOLO files to ensure high accuracy. Then, retrain the AI ​​model using the revised files as input to obtain the iterated AI model and the YOLO files labeled by the AI ​​model.

[0110] S3.2.5 Test Set Performance Verification: Calculate the mean accuracy on the validation set, input the newly obtained YOLO file into the system program, and iterate continuously, repeating the above process.

[0111] S3.3 Result Analysis:

[0112] S3.3.1, The annotation quality analysis is shown in Table 1:

[0113] Table 1 shows the results of the annotation quality analysis.

[0114]

[0115] As can be seen, in this experiment, the proposed method maintained a high recognition rate for components under schematic diagram backgrounds of varying complexity.

[0116] S3.3.2, Annotation efficiency analysis is shown in Tables 2 and 3:

[0117] Table 2 shows the results of the average processing time analysis.

[0118]

[0119] Table 3 shows the accuracy analysis results.

[0120]

[0121] Therefore, in this experiment, the method provided in this embodiment has an average processing time that is 2-3 times faster than traditional manual methods. Although the speed is not as fast as the OpenCV template matching method, the accuracy is far superior. Especially when facing complex scenarios, it is significantly better than traditional manual annotation and OpenCV template matching.

[0122] S3.3.2 The model performance analysis results are shown in Table 4:

[0123] Table 4 shows the average accuracy statistics.

[0124]

[0125] Through three iterations of training, the performance of the artificial intelligence model on the validation set gradually improved, indicating that the high-quality dataset generated by the method provided in this embodiment effectively improved the model performance.

[0126] In summary, the PCB schematic image annotation and dataset generation method provided in this embodiment has the following advantages:

[0127] First, it balances efficiency and accuracy: Through a semi-automated process of "YOLO pre-annotation + QT verification", this method improves the efficiency of traditional manual annotation by 2-3 times, while maintaining an extremely high annotation accuracy (reaching 98.2% even under complex schematic diagrams), which is significantly better than pure manual or template matching methods.

[0128] Second, a precise error correction mechanism: adopting a "classified centralized verification" mode, by cropping component images and reviewing them in groups by label, combined with three quick operations of "change_class / relabel / delete", global verification is transformed into targeted error correction, which greatly reduces the rate of missing labels and incorrect labels.

[0129] Third, automated closed-loop optimization: Construct an iterative framework of "data → model → better data": Retrain the YOLO model using the cleaned high-quality dataset to improve the pre-labeling accuracy from the initial 45% to 73%, forming a self-evolving labeling system.

[0130] Fourth, strong versatility and scalability: It does not depend on specific EDA tool formats and can be adapted to diverse design environments such as Altium, KiCAD, and JLCPCB; it continuously adapts to new component symbols and layout styles through iterative training, breaking through the migration cost bottleneck of traditional template matching methods.

[0131] like Figure 3 As shown, this embodiment also provides a PCB schematic image annotation and dataset generation system, including: a reading module, used to read PCB schematic images using a YOLO model to obtain YOLO format files; wherein, the YOLO format files include PCB component information;

[0132] The image cropping module is used to read YOLO format files and PCB schematic images using QT tools. It crops the PCB schematic images based on the labels, box coordinates, and box size obtained from the YOLO format files, and categorizes the cropped images according to component label categories to obtain labeled images.

[0133] The label verification module is used to perform label verification on images of all label categories, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing the label categories;

[0134] The dataset generation module uses QT tools to perform label classification on log files, obtain label classification results, modify YOLO format files based on the label classification results, and output the modified YOLO format files as label datasets.

[0135] The above embodiments are merely one of the implementation methods for achieving the technical solution of the present invention. The scope of protection claimed by the present invention is not limited to this embodiment, but also includes any variations, substitutions and other implementation methods that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention.

Claims

1. A method for annotating PCB schematic images and generating datasets, characterized in that, include: The PCB schematic image is read using the YOLO model to obtain a YOLO format file; wherein, the YOLO format file includes PCB component information; The LabelImg image annotation tool is used to check for missing labels in YOLO format files to obtain a YOLO format file after missing label checks. This includes: importing the YOLO format file into the LabelImg image annotation tool to check for missing labels; if there are missing labels for an entire row of components, the tool is used to fill in the missing labels in the graphical interface and create a new row of components. The QT tool is used to read the YOLO format file and PCB schematic image after missing label checks. Based on the labels, box coordinates, and box size obtained from the YOLO format file, the PCB schematic image is cropped. The cropped images are then categorized according to component label types to obtain label-categorized images. This process includes: reading the YOLO format file and PCB schematic image after missing label checks using QT; parsing each line of data in the YOLO format file to calculate pixel coordinates; cropping component thumbnails from the PCB schematic image based on these pixel coordinates; and categorizing these component thumbnails according to different component label types to obtain label-categorized images. Perform label verification on all labeled images, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing label categories; The log file was labeled using QT tools to obtain the label classification results. Based on these results, the YOLO format files after missing label checks were modified, and the modified YOLO format files were output as the label dataset. This included: if the label category was "modification," the modified label results were output, identifying all bounding boxes in the corresponding PCB schematic image within the YOLO format files after missing label checks, and replacing the original labels with new ones; if the label category was "re-annotation," the re-annotation results were output, modifying the bounding box coordinates and size using the LabelImg image annotation tool while retaining the original labels, and replacing the original bounding box coordinates and size in the YOLO format files after missing label checks; if the label category was "deletion," the deletion annotation results were output, identifying all bounding boxes in the corresponding PCB schematic image within the YOLO format files after missing label checks, and deleting the corresponding matching rows in the YOLO format files after missing label checks; the modified YOLO format files were then output as the label dataset. The output labeled dataset is used as the training dataset to iteratively train the pre-built YOLO model to output the trained object detection model; the object detection model is used to preprocess new PCB schematic images.

2. The method for annotating PCB schematic images and generating datasets according to claim 1, characterized in that, The process of reading PCB schematic images using a YOLO model to obtain YOLO format files includes: The YOLO model is used to identify components in PCB schematic images and generate YOLO format files. Pair YOLO format files with PCB schematic images according to the same name principle to obtain a quick lookup table for rapid lookup during subsequent manual verification.

3. A PCB schematic image annotation and dataset generation system, used to implement the PCB schematic image annotation and dataset generation method of claim 1, characterized in that, include: The reading module is used to read PCB schematic images using a YOLO model to obtain a YOLO format file; wherein the YOLO format file includes PCB component information; The process of reading the PCB schematic image using the YOLO model further includes: using the LabelImg image annotation tool to check for missing component labels in the YOLO format file, so as to obtain a YOLO format file after missing label check. The image cropping module is used to read the YOLO format file and PCB schematic image after missing label checking using QT tools. Based on the labels, box coordinates and box size obtained from the YOLO format file after missing label checking, the module crops the PCB schematic image and categorizes the cropped image according to the component label category to obtain labeled images. The label verification module is used to perform label verification on images of all label categories, generate label verification results, and label the cropped images with label categories based on the label verification results, generating a log file containing the label categories; The dataset generation module uses QT tools to perform label classification on log files, obtains the label classification results, modifies the YOLO format files after missing label checks based on the label classification results, and outputs the modified YOLO format files as the label dataset.

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