Control method and device of split type display system and split type display system

Abstract

The invention discloses a control method and device of a split type display system and the split type display system. The problem that in the prior art, a split type display system is inconvenient to operate is solved. The split type display system comprises a signal source, a transmission link and a display device, and the control method comprises the steps that in response to a display abnormal signal of the display device, a first reset operation of the display device is triggered; generating a state indication signal of the transmission link based on the first reset operation; and triggering a second reset operation of the transmission link under the condition that the state indication signal meets a preset condition.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a control method and apparatus for a split display system, and a split display system. Background Technology

[0002] With the development of display technology, split-type display systems have been widely used in commercial displays, conference systems, home theaters, and other scenarios due to their high flexibility and convenient installation. A typical split-type display system usually includes a signal source (such as a computer or player), a transmission link (such as long-distance cables, signal relays, or conversion devices), and a display device (such as a monitor or projector).

[0003] In practical applications, due to the long transmission distance, split-type display systems are prone to display abnormalities, such as no signal, black screen, distorted screen, and flickering. The traditional solution is for users to manually troubleshoot one by one: first restart the display device, and if that doesn't work, check and reconnect the transmission cable, or even restart the signal source. This process is cumbersome, time-consuming, and impractical for display devices installed in hard-to-reach locations (such as high up or embedded in a wall) or for remotely managed systems. Summary of the Invention

[0004] In view of this, the present application provides a control method and apparatus for a split display system, and a split display system, which solves the problem of inconvenient operation of the split display system in the prior art.

[0005] The first aspect of this application provides a control method for a split display system. The split display system includes a signal source, a transmission link, and a display device. The control method includes: triggering a first reset operation of the display device in response to a display abnormality signal of the display device; generating a status indication signal of the transmission link based on the first reset operation; and triggering a second reset operation of the transmission link when the status indication signal meets preset conditions.

[0006] In conjunction with the first aspect, in some possible implementations, the display device includes a bridge chip; triggering a first reset operation of the display device in response to a display abnormality signal of the display device includes: triggering a first reset operation of the bridge chip in response to a display abnormality signal of the display device.

[0007] In conjunction with the first aspect, in some possible implementations, the status indication signal includes a hot-plug detection signal of the bridging chip; when the status indication signal meets preset conditions, triggering a second reset operation of the transmission link includes: if a predetermined pulse pattern of the hot-plug detection signal is detected within a preset time window, triggering a second reset operation of the transmission link.

[0008] In conjunction with the first aspect, in some possible implementations, if a predetermined pulse pattern of the hot-plug detection signal is detected within a preset time window, triggering a second reset operation of the transmission link includes: if, within the preset time window, the hot-plug detection signal is detected to have a predetermined number of pull-down pulses, and the duration of the pull-down pulses is within a predetermined duration, triggering a second reset operation of the transmission link.

[0009] In conjunction with the first aspect, in some possible implementations, the scheduled time window includes 30 seconds; and / or, the scheduled quantity includes 2; and / or, the scheduled duration is greater than or equal to 1.5 seconds and less than or equal to 4 seconds.

[0010] In conjunction with the first aspect, in some possible implementations, the transmission link includes a display interface connection line, a signal re-timer connected to the display interface connection line, and a link controller; triggering a second reset operation of the transmission link when the status indication signal meets preset conditions includes: when the status indication signal meets preset conditions, the link controller triggers a second reset operation of the signal re-timer.

[0011] In conjunction with the first aspect, in some possible implementations, the control method also includes a USB power cable, with the USB power cable and the link controller electrically connected.

[0012] In conjunction with the first aspect, in some possible implementations, the control method further includes: stopping the execution of the first reset operation when the number of times the second reset operation is executed exceeds a predetermined number.

[0013] The second aspect of this application provides a control device for a split display system. The split display system includes a signal source, a transmission link, and a display device. The control device includes: a first trigger module configured to trigger a first reset operation of the display device in response to a display abnormality signal of the display device; a generation module configured to generate a status indication signal of the transmission link based on the first reset operation; and a second trigger module configured to trigger a second reset operation of the transmission link when the status indication signal meets preset conditions.

[0014] A third aspect of this application provides a split-type display system, including a signal source, a transmission link, and a display device; wherein, the signal source is configured to detect a display abnormality signal of the display device and trigger a first reset operation of the display device; the display device is configured to perform the first reset operation and generate a status indication signal of the transmission link based on the first reset operation; the transmission link includes a display interface connection line, and a link controller and a signal re-timer respectively connected to the display interface connection line, the link controller being configured to trigger a second reset operation of the signal re-timer when the status indication signal meets a preset condition.

[0015] According to the control method and apparatus of the split display system provided in the embodiments of this application, when the display device malfunctions, the first reset operation of the display device and the second reset operation of the transmission link are triggered in a chain. This realizes the automatic control of the automatic reset operation of the transmission link based on the reset operation of the display device, avoiding manual plugging and unplugging of the power cord and providing convenience for users. Attached Figure Description

[0016] Figure 1 This is an architecture diagram of the split display system provided in the first embodiment of this application.

[0017] Figure 2 Provided for an embodiment of this application Figure 1 The structural block diagram of the transmission link in the diagram.

[0018] Figure 3 A flowchart of the control method for the split-type display system provided in the first embodiment of this application.

[0019] Figure 4 A flowchart of a control method for a split-type display system provided in the second embodiment of this application.

[0020] Figure 5 This is a waveform diagram of a hot-plug check signal provided in an embodiment of this application.

[0021] Figure 6 A flowchart of a control method for a split-type display system provided in the third embodiment of this application.

[0022] Figure 7 This is a structural block diagram of the control device for a split-type display system provided in an embodiment of this application.

[0023] Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0024] Figure 9 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0025] In a split-display architecture, the signal source, which initiates video data, is connected to the display device, which presents the data, via a physical transmission link. While this architecture offers flexibility and high performance, it introduces inherent challenges for long-distance signal transmission. This is especially true when the display device is a head-mounted display or other device requiring free user movement, where the required cable length can reach 3 to 5 meters or even longer. In such applications, the Virtual Reality (DP) interface has become the mainstream choice due to its high bandwidth, low latency, and robust scalability (such as support for Multi-Stream Transmission). However, the high-speed signal in the Virtual Reality (DP) interface inevitably faces signal integrity degradation during long-distance copper cable transmission, primarily manifested as high-frequency attenuation, jitter accumulation, and inter-symbol interference, ultimately leading to video flickering, black screens, color distortion, or complete interruption.

[0026] To address this challenge, the industry has widely integrated DP signal retimers (DPRetimers) into long-distance DP cables. This device is a highly complex mixed-signal integrated circuit whose core functions are clock data recovery and signal regeneration. It doesn't simply amplify the signal; instead, through its internal, sophisticated clock data recovery circuitry, it extracts a clean digital clock and data from a severely distorted input waveform, and then uses this clock to generate a completely new, standard signal output conforming to DP electrical specifications, thus effectively "regenerating" signal quality. However, as a complex system comprising an analog front-end, digital state machine, and power management unit, the signal retimer itself may experience internal state machine "delocking," clock recovery circuitry loss of lock, or configuration register malfunction under conditions of long-term operation, power fluctuations, thermal stress, or extremely poor input signal quality, leading to malfunctions. In such cases, the most effective and thorough recovery method is to perform a complete power cycle reset, i.e., completely de-energizing it and then re-initializing it.

[0027] In related technologies, achieving this reset typically relies on the user manually physically unplugging and plugging in the cable or its associated power cord (such as a USB cable that powers the chip inside the cable). This method not only severely disrupts the user experience of immersive applications (such as VR), requiring the user to interrupt their current activity, but also has drawbacks such as damaging delicate connectors and being inconvenient or impermissible in certain professional environments. Furthermore, this is a passive, reactive maintenance method that cannot achieve proactive system health management and automated fault recovery.

[0028] In view of this, embodiments of this application provide a control method and apparatus for a split display system, and a split display system that achieves the reset of the DP cable through software control, avoiding the need for manual plugging and unplugging of the USB cable, thus bringing convenience to the user.

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0031] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0032] Figure 1 This is an architectural diagram of a split-type display system provided in the first embodiment of this application. This split-type display system can be used in scenarios with extremely high requirements for signal transmission reliability, such as virtual reality, augmented reality, professional graphics workstations, and medical image displays. Figure 1 As shown, the split display system 100 includes a signal source 10, a transmission link 20, and a display device 30, with the signal source 10 and the display device 30 connected through the transmission link 20.

[0033] The split-type display system 100 is essentially an information transmission chain that is primarily unidirectional (video data stream from signal source 10 to display device 30) and secondarily bidirectional (including status, control, and communication reverse channels).

[0034] The signal source 10 is the system's computing and rendering hub, responsible for generating and outputting the raw video data stream. Its specific form can be, but is not limited to, a personal computer, graphics workstation, game console, media player, or professional video server. The signal source 10 internally contains two key functional units: a graphics processing unit 11 (e.g., a graphics card) and a VR real-time program unit 12.

[0035] The graphics processing unit 11 is typically a high-performance graphics card or an integrated graphics core. Its core responsibility is to perform complex graphics rendering calculations, generate high-resolution, high-refresh-rate frame buffer data, and encapsulate the data into a serialized data stream according to the target display protocol (such as DisplayPort) specifications, before sending it out through the physical interface. This process involves multiple layers of the protocol stack, including color space conversion at the application layer, packet encapsulation at the transport layer, link training and management at the link layer, and encoding and driving at the physical layer.

[0036] Real-time program unit 12 is a software entity that runs on top of the signal source operating system. In VR / AR application scenarios, it is the VR runtime, such as the Pimax VR runtime. This unit is not only the application manager but also the system-level monitoring and decision-making hub in this solution. It maintains continuous communication with the display device 30 through an auxiliary communication line (such as USB) to monitor its health status (e.g., periodically receiving "video stream normal" heartbeat packets). Once its built-in fault detection logic determines that the system has a display abnormality, this unit will be responsible for initiating and coordinating the entire hierarchical recovery process, generating and sending control commands to the display device. Here, "real-time" emphasizes its rapid response and decision-making capabilities to changes in system state, rather than specifically referring to its requirement to run on a real-time operating system. In practical implementation, this unit typically comprises several sub-modules: a device monitoring module responsible for parsing heartbeat packets and status reports from the display device; a fault diagnosis module that determines the fault type and severity based on preset algorithms (such as timeout detection and bit error rate analysis); a recovery strategy engine that decides what recovery action to take (such as retraining or resetting the bridge chip); and a command distribution module responsible for encapsulating control commands into USB protocol packets and sending them out. Its "real-time" nature is reflected in its response latency being strictly controlled within an acceptable range for the user (e.g., the total time from detecting an anomaly to initiating the first reset command is less than 1 second), ensuring rapid fault recovery.

[0037] Display device 30 serves as the final point of video data presentation. For example, display device 30 may be a head-mounted display device. The core components of display device 30 include a bridge chip 31 and a main controller 32.

[0038] Bridge chip 31 is a key video interface processor. It is directly connected to the physical interface of transmission link 20 and is responsible for receiving high-speed serial signals (such as DP signals). Internally, it performs a series of complex processes: first, it recovers and decodes physical layer data; then, it parses protocol packets, separating video, audio, and auxiliary data; next, it may perform color space conversion, timing adjustment, and other processing; finally, it converts the processed pixel data into the native interface format required by the display panel (such as MIPI DSI, LVDS, or eDP). From a technological evolution perspective, bridge chips have evolved from simple protocol converters to highly integrated system-on-a-chip. Modern bridge chips typically integrate multiple clock domains, large-capacity buffer memory, programmable color processing units, and various panel interface controllers. For example, a typical DP to MIPI DSI bridge chip may contain: a DP receiver physical layer, a display protocol processing core, a frame buffer controller, a MIPI DSI host controller, and peripheral interfaces (such as SPI and I2C) for connecting external flash memory and the host controller. Furthermore, bridge chip 31 is responsible for managing and outputting hot-plug detection signals. The physical level of this signal directly reflects the state of the chip interface logic: when the chip is powered normally and the interface logic is ready, the HPD driver is high; when the chip is powered off or a serious logic error occurs, the HPD output becomes invalid (usually manifested as being pulled low by external circuitry). This characteristic is the basis for this solution to use HPD to transmit reset event information. The electrical characteristics of the HPD signal typically follow the DisplayPort standard specification. Under normal operating conditions, the display device pulls the HPD line to a specified high level (e.g., connected to a 3.3V power supply) through a pull-up resistor (e.g., 10kΩ). When the bridge chip is reset or powered off, its internal HPD output driver is turned off, and the level of the HPD line is determined by external circuitry. Typically, to ensure that the signal source can correctly detect a low level when the device is not connected, a weak pull-down resistor (e.g., 100kΩ) is designed at the signal source end. Therefore, when the bridge chip stops driving, the HPD line is pulled low by this pull-down resistor, resulting in a clear and measurable level change.

[0039] The main controller 32, serving as the system management core of the display device 30, can be a microcontroller or application processor. It is responsible for the overall operation of the device, including sensor data fusion and user interaction processing. In this solution, its newly added core function is as a reset instruction executor. It receives instructions from the real-time program unit 12 of the signal source 10 via an auxiliary communication line, parses them, and then precisely executes a power-off and power-on reset operation on the bridge chip 31 by controlling the GPIO operation of the bridge chip 31's hardware reset pin or controlling its power management circuit. There are several ways for the main controller 32 to execute the reset operation. One common method is to directly control the bridge chip's hardware reset pin. Most bridge chips provide one or more reset input pins (such as #RESET, #PWRDWN). The main controller 32 only needs to output a low-level pulse to this pin for a certain duration (e.g., 100 milliseconds) to trigger the chip's hard reset. Another method is to directly cut off its power supply by controlling a load switch or power management IC connected to the bridge chip's core power rail. This method is more thorough but requires additional power switching circuitry. Regardless of the method used, the main controller needs to precisely control the timing of the reset signal to ensure that the bridge chip has enough time to fully discharge, but not too long to avoid affecting the user experience. A typical reset pulse width is between 1.5 and 4 seconds. This time window ensures that the capacitor is fully discharged while avoiding being mistakenly interpreted as the device being permanently removed.

[0040] The transmission link 20 is the key innovation of this invention, which has evolved from a passive connection line into an active and intelligent signal integrity protection system. Figure 2 Provided for an embodiment of this application Figure 1 A block diagram of the transmission link structure. Combined with... Figure 1 and Figure 2 As shown, the transmission link 20 includes a DP connection line 21, a signal retimer 22, a link controller 23, and a power supply module 24.

[0041] The DP connector 21 is the physical transmission carrier for high-speed signals, typically composed of multiple pairs of differential copper wires with strictly controlled impedance. These include a main link channel for transmitting video data, an auxiliary channel for transmitting auxiliary data and managing the link, and a crucial hot-plug detection line. To ensure signal integrity, the DP connector 21 design must meet stringent specifications. The characteristic impedance of its differential pairs must be controlled within 100 ohms ± 10% to reduce signal reflection. Pair length matching must be extremely precise, with an internal delay difference typically required to be less than 5 picoseconds to avoid inter-symbol interference. Cable shielding design is also critical, typically employing a double-layer shielding structure of aluminum foil and braided copper mesh to simultaneously suppress high-frequency and low-frequency electromagnetic interference. Furthermore, as an extension of the cable, the connector's contact design, mating life, and electromagnetic compatibility performance also affect the overall transmission quality.

[0042] The signal retimer 22, or DP Retimer chip, is the core technology for long-distance, high-quality transmission. Essentially, it's a signal regenerator. Its workflow is as follows: First, an adjustable equalizer compensates for high-frequency losses caused by the cable; then, a clock data recovery circuit extracts a precise clock from the processed signal; finally, this recovered clock is used to resample the data stream, generating a new signal with extremely low jitter and good eye diagram opening. The device integrates a complex digital state machine to manage tasks such as adaptive equalization and link negotiation, which is why it may experience deadlocks and require reset. From a signal processing perspective, the DP Retimer performs a complete analog-to-digital-to-analog conversion process. The adaptive equalizer at the input (typically including CTLE continuous-time linear equalization and DFE decision feedback equalization) dynamically adjusts its frequency response to compensate for cable loss characteristics. The equalized analog signal is sampled by a high-speed analog-to-digital converter and converted into a digital data stream. The CDR module then extracts precise clock phase information from this data stream. Finally, the digital data is re-tied in the recovered clock domain and output as a new analog signal through a digital-to-analog converter and driver. The advantage of this process is that it completely removes the jitter (especially random jitter) accumulated during transmission, and the jitter of the output signal is determined only by the low-jitter clock source of the DP Retimer itself.

[0043] The link controller 23, the "brain" of the entire intelligent transmission link, is typically a low-power embedded microcontroller. It continuously and with high precision (e.g., every 10 milliseconds) samples the level of the HPD signal line. Internally, it runs a specific algorithm to identify whether the HPD signal conforms to a preset pulse pattern. Once a specific sequence that meets all conditions is identified, the link controller 23 determines that deep recovery needs to be performed and outputs a control signal. The algorithm implementation of the link controller 23 needs to balance accuracy and robustness. A typical implementation includes the following states: idle state, continuously monitoring the HPD level; edge detection state, starting pulse width timing upon detecting a falling edge; pulse verification state, verifying whether the pulse width is within the valid range (1.5-4 seconds) upon detecting a rising edge, and recording a valid event if so; window management state, managing a 30-second timing window and counting the number of valid pulses within the window; and conditional trigger state, performing a reset operation when the number of valid pulses within the window reaches a preset value (e.g., 2). To prevent false triggering, the algorithm usually also includes dejitter filtering to ignore millisecond-level glitches.

[0044] The power supply module 24 is responsible for obtaining 5V power from an auxiliary line (such as USB cable 40) and converting it to the operating voltage required by the link controller 23 and the signal re-timer 22. Its key feature is that, controlled by the link controller 23, it can independently cut off and restore the power supply to the signal re-timer 22, thereby achieving a hard reset. The power supply module 24 typically includes several sub-circuits: input filtering and voltage regulation circuitry to generate a stable and clean 3.3V or 1.8V voltage from the 5V power supplied by USB to power the link controller 23; a controlled load switch or MOSFET, whose gate is controlled by the GPIO of the link controller 23 to switch the power supply to the signal re-timer 22; and, if necessary, level conversion circuitry to ensure level compatibility of the control signals. When a reset is required, the link controller 23 pulls the control GPIO low for a sufficient time (e.g., 100-200 milliseconds) to ensure a sustained power-off, and then releases it to restore power.

[0045] like Figure 1As shown, the split display system 100 may also include a USB cable 40. The USB cable 40 plays a dual role in this system. On one hand, it serves as a power supply line, providing operating power to the internal circuitry of the display device 30 and the active devices in the transmission link 20. On the other hand, it serves as a bidirectional communication channel, establishing a reliable out-of-band communication link between the real-time program unit 12 of the signal source and the main controller 32 of the display device, independent of the high-speed video channel. This link is used to transmit device status reports, sensor data, and reset control commands, which are crucial in this solution. It should be noted that although USB is used as an example, this auxiliary channel concept can be extended to other interfaces that provide power and bidirectional communication capabilities, such as a USB Type-C interface with the PD protocol or Power over Ethernet. The role of the USB cable 40 in this application is "out-of-band management," that is, using a path independent of the main data channel (i.e., DP connection line 21) for system control and status monitoring. This design offers significant advantages: First, it does not consume valuable high-speed video bandwidth; second, even if the DP link is completely interrupted due to a fault, the USB cable may still remain operational, enabling the transmission of fault diagnosis and recovery commands; third, USB, as a mature and widely used interface, has very comprehensive driver support and communication protocol stack, reducing development complexity. In terms of specific communication protocol design, a set of control request and data report formats specifically for device management and fault recovery can be defined based on the standard USB HID or custom device classes.

[0046] The split display system 100 provided in this embodiment can automatically trigger the reset of the transmission link 20, avoiding the need to manually unplug and plug the power cord to reset the transmission link 20, thus providing convenience for users.

[0047] The control process for automatically resetting the transmission link 20 in the split display system 100 provided in this application embodiment will be described below with reference to specific embodiments.

[0048] Figure 3 A flowchart illustrating a control method for a split-type display system provided in the first embodiment of this application. This control method is applicable to… Figure 1 The shown is a split-type display system 100. (As shown...) Figure 3 As shown, the control method for the split-type display system includes: In step S310, in response to a display error signal from the display device 30, a first reset operation of the display device 30 is triggered. The triggering condition for step S310 is a "display error signal". There are various ways to obtain this signal.

[0049] For example, the display device 30 performs self-diagnosis. Specifically, the main controller 32 of the display device 30 continuously monitors the status of the video stream output by the bridging chip 31. When an input signal interruption is detected, or the bridging chip reports a link failure, the main controller 32 can actively report the anomaly to the signal source 10 via an auxiliary communication line. The main controller 32 can obtain the internal status of the bridging chip 31 by polling its status register. Many bridging chips 31 provide rich status registers to indicate link status, error count, input signal lock status, etc. The main controller 32 can periodically (e.g., every second) read these registers, and once it detects that flags such as "input signal loss," "link training failure," or "HDCP authentication error" are set, it can determine that an anomaly has occurred.

[0050] For example, signal source 10 actively probes. Specifically, the real-time program unit 12 of signal source 10 periodically polls or receives "heartbeat" status packets (e.g., a "STREAM_OK" report once per second) from display device 30 via an auxiliary communication line. If no valid status report is received within several consecutive cycles (e.g., 12 consecutive seconds), it is determined to be a display anomaly. This method is logically simple and reliable. This timeout-based heartbeat detection mechanism is a commonly used fault detection method in distributed systems. Choosing 12 seconds as the threshold is an engineering trade-off: too short a time (e.g., 1 second) is prone to false alarms due to system momentary lag or occasional loss of USB data packets; too long a time (e.g., 60 seconds) will make the fault response too slow, affecting the user experience. 12 seconds is roughly equivalent to missing 10-12 periodic heartbeat packets, which, after excluding accidental communication jitter, can reliably indicate persistent faults. The real-time program unit 12 maintains a "timestamp of the last received heartbeat" and continuously compares it with the current time. Once a timeout occurs, the subsequent process is triggered.

[0051] For example, there is feedback from the operating system / driver layer. The operating system graphics subsystem or graphics card driver of signal source 10 can also sense changes in the connection status of the display device. For example, when the system detects that the monitor is unresponsive, it can generate a corresponding event to notify the real-time program unit 12.

[0052] Once the "display error signal" is confirmed, the system immediately initiates the first reset operation on the display device 30.

[0053] Step S320: Generate a status indication signal for the transmission link based on the first reset operation.

[0054] During the first reset operation, the change in the HPD pin state of the bridge chip 31 is transmitted through the HPD line in the transmission link 20. Therefore, the hot-plug detection signal takes on a new meaning in this scenario—it is not merely an indication of the connection status, but also a "status indication signal" characterizing whether a specific reset event has occurred. The link controller 23 in the transmission link 20 continuously monitors this signal, providing raw data for the next intelligent decision. This embodies the design concept of "signal multiplexing." The original design purpose of the HPD signal was singular and clear: to indicate the physical connection status of the display device 30 to the signal source 10. This solution cleverly utilizes the physical characteristic that a reset of the bridge chip 31 inevitably leads to a change in the HPD level, "multiplexing" the HPD signal into an implicit communication channel. This channel is unidirectional (from the display device 30 to the link controller 23) and low-speed (one pulse transmits one bit of information), but its advantage lies in the fact that it requires no additional physical wiring, fully utilizing existing system resources to achieve zero-cost additional communication functionality.

[0055] Step S330: If the status indication signal meets the preset conditions, the second reset operation of the transmission link 20 is triggered.

[0056] This preset condition is used to rule out faults other than those in transmission link 20. Only when the preset condition is met does it mean that transmission link 20 has failed, thus requiring a second reset operation. The core logic of the preset condition lies in establishing a "fault reasoning chain." Its basic assumption is that if the display device 30 (e.g., bridging chip 31) itself has a problem, then after resetting it (the first reset operation), the problem should be resolved and the video stream should be restored. If the video stream is still not restored, and then (within a preset time window W) the system performs a second reset of bridging chip 31, this strongly suggests that the first reset failed to solve the problem. Two consecutive failed reset attempts greatly increase the possibility that the root cause of the fault is "upstream," that is, the problem may lie in transmission link 20, which is responsible for transmitting signals to bridging chip 31, especially the signal retimer 22 within it. Therefore, the preset condition (such as "two valid HPD pulses within 30 seconds") is actually a filter used to screen out fault scenarios where "bridging chip 31 reset is ineffective," and trigger a deep recovery operation for transmission link 20 accordingly.

[0057] According to the control method of the split display system provided in this embodiment, the DP cable is reset through software control, avoiding the need for manual plugging and unplugging of the USB cable, thus bringing convenience to the user.

[0058] Figure 4 A flowchart illustrating the control method for the split-type display system provided in the second embodiment of this application. Figure 4The control method of the split display system shown and Figure 3 The difference in the control method of the split display system shown is that, in this embodiment, step S310 is specifically executed as follows: In step S410, in response to the display abnormality signal of the display device 30, the first reset operation of the bridge chip 31 is triggered.

[0059] In this embodiment, the first reset operation is precisely targeted at the video processing unit within the display device, namely the bridge chip 31, rather than powering off the entire device. Its purpose is to attempt to eliminate any temporary software errors or state machine freezes that may exist on the display device side with minimal cost. The first reset operation can be performed in various ways.

[0060] For example, hardware reset pin control. Specifically, the main controller 32 sends a low-level pulse lasting several hundred milliseconds to the hardware reset pin of the bridge chip 31 via GPIO, forcing the chip's internal logic to restart. The advantage of this reset method is its speed and small impact range. The width of the reset pulse usually needs to be determined by referring to the bridge chip's datasheet to ensure sufficient time for all internal flip-flops to reset, but not too long. Typical reset pulse widths are between 100 and 500 milliseconds. During the reset, the bridge chip stops all outputs, including HPD signals and video data, but its power supply remains, so the communication interface with the main controller 32 (such as I2C) may still be accessible for monitoring the reset status.

[0061] For example, power cycle control. Specifically, the main controller 32 briefly cuts off the core power supply to the bridge chip 31 (e.g., for 2-3 seconds) by controlling a power switch, and then re-energizes it. This method is more thorough. Power cycle is the most thorough reset method because it clears the contents of all registers and static memory units inside the bridge chip 31, including volatile configurations and state machines that may fall into exceptions. When executing the power cycle, the main controller 32 needs to control a load switch connected to the core voltage rail of the bridge chip 31 (e.g., 1.0V, 1.2V). The power-off duration (2-3 seconds) needs to be long enough to ensure that all decoupling capacitors (typically tens of microfarads) on the power rail are fully discharged to near 0V, thus ensuring that the internal logic of the bridge chip 31 is completely powered down. After power-on, the bridge chip 31 undergoes a complete power-on reset sequence, including the startup of the internal regulator, the start-up of the clock oscillator, and the loading of firmware from non-volatile memory.

[0062] Regardless of the method used, the reset process of bridge chip 31 causes its HPD output to undergo a high-to-low and then high-back transition, generating a low-level pulse of a specific duration. This pulse forms the basis for subsequent steps. When bridge chip 31 is reset or powered off, its internal HPD output driver is disabled, and the HPD pin presents a high-impedance state. Since the HPD line is typically grounded through a pull-down resistor at signal source 10 (or transmission link 20), this pin transitions from a driven high level to a pulled-down low level. When the reset is complete, bridge chip 31 reinitializes and drives its HPD output high, causing the level to toggle again. Therefore, each complete reset of bridge chip 31 inevitably leaves a "footprint" on the HPD line—a complete high-to-low and then high pulse.

[0063] In this scenario, in one embodiment, the status indication signal includes a hot-plug detection signal (HPD) from the bridging chip 31. Each complete reset of the bridging chip 31 necessarily generates a complete HPD low-level pulse; this relationship is determined by the physical characteristics of the hardware circuitry. This physical characteristic forms the cornerstone of the overall reliability of the solution. It does not rely on any software protocols or complex handshake processes, but is guaranteed by the most basic circuit principles (driver enable / disable, pull-up / pull-down resistors). This means that as long as the hardware connection is correct, this "reset-pulse" correspondence is deterministic and unforgeable. The link controller 23 in the transmission link 20 can determine with 100% certainty that a reset event has occurred at the display device 30 by simply monitoring the level change of the HPD line, without relying on potentially erroneous or delayed software status reports.

[0064] Accordingly, step S330 is specifically executed as follows: Step S420: If a predetermined pulse pattern of the hot-plug detection signal is detected within a preset time window, the second reset operation of the transmission link 20 is triggered.

[0065] This is the most creative aspect of the invention. The link controller 23 does not trigger a reset of the signal retimer 22 upon detecting any arbitrary HPD pulse. Instead, it must wait for a highly specific pulse sequence that is extremely unlikely to be generated by a random event, using this as a safe and reliable "instruction" to execute the deep recovery operation.

[0066] For example, if a hot-plug detection signal is detected to have a predetermined number of pull-down pulses within a predetermined time window, and the duration of the pull-down pulses is within a predetermined duration, a second reset operation of the transmission link is triggered. The predetermined time window includes 30 seconds; and / or, the predetermined number includes 2; and / or, the predetermined duration is greater than or equal to 1.5 seconds and less than or equal to 4 seconds.

[0067] Figure 5 This is a waveform diagram of a hot-plug check signal provided in an embodiment of this application. Figure 5 As shown, within a preset time window W (e.g., starting from the first detected falling edge of HPD, with a total duration of 30 seconds), at least N (e.g., N=2) complete HPD low-level pulses must be observed. The low-level duration T_low of each pulse satisfies the condition that 1.5s ≤ T_low ≤ 4s. This range excludes glitches shorter than 1.5 seconds (such as electrostatic discharge) and permanent disconnections longer than 4 seconds (such as physical shutdown of the device). The specific values ​​of the time window W, the number of pulses, and the pulse width are carefully designed and balanced. A 30-second window is a reasonable upper limit for the system response cycle. If the system cannot establish a stable connection within 30 seconds after the first reset, it indicates that the problem may not be transient. Two pulses are a critical threshold. A single pulse may be a one-time reset attempt or an accidental event, but two pulses occurring within a short period of time clearly indicate the "retry after initial failure" pattern, which is highly consistent with the software-controlled automatic fault recovery process. The 1.5-second lower limit effectively filters out millisecond-level interference such as various electrical noises and momentary contact jitter; the 4-second upper limit excludes situations where the user actively shuts down the device or removes the device for an extended period. These three conditions together constitute a sophisticated "logic lock," which can only be opened by events that conform to a specific behavioral pattern, thereby ensuring the accuracy and security of the reset operation.

[0068] In one embodiment, the high-level duration between two adjacent pulses also has certain requirements, but it is usually an implicit condition. For example, it must be greater than a certain minimum value, such as 200ms, to ensure that they are two independent events. Increasing the minimum requirement for the high-level interval can further prevent a single long pulse (e.g., continuous low-level jitter due to power instability) from being misinterpreted as multiple short pulses. The minimum interval of 200ms ensures that there is sufficient time between two pulses for the bridge chip to at least complete partial initialization and attempt to drive HPD high, thereby confirming that these are two independent reset-recovery cycles, rather than noise from a single event.

[0069] The preset condition in step S330 is a complex logic judgment, including constraints in three dimensions, all of which must be satisfied simultaneously. Specifically, the time window W constraint starts a timing window W (e.g., set to 30 seconds) from the detection of the first qualified HPD falling edge. All judgments must be completed within this window. The pulse count constraint requires that at least N complete and valid HPD low pulses must be detected within the time window W (e.g., N=2). The pulse characteristic constraint requires that the low-level duration T_low of each counted pulse must fall within a preset closed interval [1.5s, 4.0s].

[0070] The design of these preset conditions embodies profound system logic and robustness considerations.

[0071] The time window is 30 seconds. This is a reasonable system response timeout period. If the system cannot recover on its own within 30 seconds after the first reset (indicating a need for a second reset), it strongly suggests that the fault may not lie in the display device itself. From the system interaction timing analysis, a complete "reset-reinitialization-link training-connection establishment" process, under ideal conditions, might only take a few seconds. If the system still needs to trigger a second reset within a 30-second window, it can almost certainly be concluded that the first reset failed to resolve the fundamental problem. The 30-second threshold provides the system with sufficient recovery time (avoiding accidental triggering during normal recovery) while also enabling timely detection of persistent faults requiring further intervention.

[0072] The number of pulses is no less than two. A single pulse may originate from the display device's autonomous reset attempt (i.e., the first reset operation itself). The second pulse, which occurs shortly afterward, clearly indicates that "the first reset attempt failed, and the system (software) automatically initiated a second attempt." This constitutes a strong logical basis for triggering a deeper level (transmission link) recovery operation. In software-controlled automated fault recovery processes, a retry mechanism is usually set up. For example, after triggering the first reset of the bridging chip 31, the VR real-time program will wait for one cycle (e.g., 12 seconds) to check whether recovery has occurred. If not, a second reset is triggered. Therefore, the pattern of "two valid pulses within 30 seconds" precisely matches the high-level behavior pattern of "software automatic retry." The link controller 23 does not need to understand the specific logic of the upper-layer software; it can infer the state of "the software has attempted recovery once but failed" simply by monitoring the underlying HPD signal pattern, and thus intelligently intervene to execute a deeper recovery operation.

[0073] The pulse width is between 1.5s and 4.0s. This range precisely filters out various types of interference. Pulses shorter than 1.5 seconds are likely glitches caused by electrical noise or poor contact; pulses longer than 4.0 seconds may indicate that the device has been physically shut down or removed. The 1.5-4 seconds range precisely covers the time required for a typical bridge chip to complete a full power cycle reset, allowing this condition to accurately capture software-controlled reset events. The power cycle reset time of bridge chip 31 is determined by several factors, including the response time of the power management circuitry, the discharge time of the chip's internal capacitors, and the firmware initialization time after power-on. 1.5-4 seconds is an empirical range that covers the typical behavior of most chips in this regard. By limiting the pulse width to this range, the system can effectively distinguish between "software-controlled, purposeful reset operations" and "HPD level changes caused by other reasons," further improving the accuracy of instruction recognition.

[0074] The link controller 23 will only perform a second reset operation if it determines that the currently monitored HPD signal sequence fully meets the aforementioned preset conditions. This reset involves controlling the power supply module 24 to cut off the power to the signal re-timer 22 for approximately 100-200 milliseconds, and then restoring power. This brief power outage is sufficient to clear all logic states within the re-timer chip. Upon power-up, it will perform a complete self-test and initialization, restoring the signal regeneration function. Subsequently, the entire DP physical link will undergo a brief interruption and retraining process. If the root cause of the fault lies in the abnormal state of the re-timer, the link is expected to recover during this process.

[0075] Figure 6 A flowchart illustrating the control method for a split-type display system provided in the third embodiment of this application. Figure 6 The control method of the split display system shown and Figure 3 , Figure 4 The difference in the control method of the split display system shown is that, in this embodiment, step S330 is specifically executed as follows: In step S510, if the status indication signal meets the preset conditions, the link controller 23 triggers the second reset operation of the signal re-timer 22.

[0076] Using the reset of the signal re-timer 22 as the reset of the transmission link 20 has several advantages. Firstly, the main function of the transmission link 20 is implemented by the signal re-timer 22; secondly, resetting the signal re-timer 22 restores the core function of the transmission link 20; and thirdly, other parts of the transmission link 20 (such as the MCU and DP connection line 21) typically do not require reset. This design demonstrates the precision and economy of fault recovery. In the transmission link 20, the DP connection line 21 is a passive physical medium, stateless, and does not require reset. The link controller (MCU) 23 is the unit responsible for management and decision-making; its software design should ensure high stability and require very little reset. Even in the event of an anomaly, it can self-recover through mechanisms such as a watchdog timer without external intervention. The signal re-timer 22 is the only active component in the link that contains a complex state machine and analog circuitry and is prone to "freezing". Therefore, focusing the "reset of transmission link 20" on the "reset of signal retimer 22" is equivalent to performing "surgery" directly on the "lesion" most likely to fail, exchanging the minimum system cost (brief signal interruption) for the maximum recovery probability, and avoiding the greater disturbance to the system caused by unnecessary global reset.

[0077] Based on the control method of the split display system provided in this embodiment, a hardware and software collaborative, layered and progressive intelligent fault recovery mechanism is constructed. This mechanism cleverly reuses the existing hot-plug detection signal as an out-of-band control channel. By precisely controlling the display device to generate a specific HPD pulse sequence, which is then decoded and responded to by the intelligent controller embedded in the transmission link, a deep reset operation on critical links such as the signal retimer is triggered without the need for physical plugging and unplugging. This avoids the reset operation process achieved by plugging and unplugging the power line of the transmission link 20, providing convenience for users.

[0078] In one embodiment, the control method for the split display system provided in any of the above embodiments further includes: stopping the execution of the first reset operation when the number of times the second reset operation is executed exceeds a predetermined number, in order to avoid entering an infinite loop.

[0079] To handle extreme situations such as permanent hardware damage, the system has a built-in protection mechanism. The error counter in the VR real-time program has an upper limit (e.g., 10 times), i.e., a predetermined number of attempts. If the system still fails to recover after 10 bridge chip 31 resets (corresponding to a maximum of 5 signal re-timer 22 resets), the program will determine that automatic recovery has failed and stop further reset attempts. At this point, it will log a detailed error log and display a clear fault message on the user interface (such as "Unable to restore display connection, please check the cable"), guiding the user to perform physical checks or seek technical support. This mechanism effectively prevents the system from getting stuck in a meaningless infinite reset loop.

[0080] The following example uses a split display system 100 with a VR headset as the display device 30. The working process of the split display system 100 includes: I. System initialization and normal monitoring phase.

[0081] 1. System startup and connection establishment.

[0082] At signal source 10, when the user launches a VR client (such as Pimax Play), the VR real-time program unit 12 loads and initializes. The VR headset is detected, and upon detection, a USB communication channel is established. Simultaneously, the graphics processing unit 11 begins transmitting video signals via the DP connection cable 21.

[0083] 2. Continuous monitoring under normal conditions.

[0084] On the VR headset side, the main controller 32 reports the video stream status ("STREAM_OK") to the signal source 10 once per second via the USB cable 40.

[0085] Signal source 10 checks every 12 seconds to see if it has received a normal video stream status report.

[0086] Link controller 23 monitors the HPD signal level and is in a state of waiting for a specific pulse sequence.

[0087] II. Fault Detection and Initial Response Phase.

[0088] 1. Initial anomaly detection (T=12 seconds).

[0089] If the VR real-time program unit 12 finds that it has not received any "STREAM_OK" report in the past 12 seconds, it determines that "display is abnormal" and sends the first reset command to the VR headset via USB cable 40.

[0090] 2. The VR headset receives and performs the first reset.

[0091] The VR headset's main controller 32 receives the first reset command, interprets it as a bridge chip reset request, and sends a "received first reset command" confirmation signal to the signal source 10 via USB cable 40. It then cuts off the power supply to the reset pin of the bridge chip 31.

[0092] When bridge chip 31 is powered off, its Hot Plug Detect (HPD) output pin goes low, generating an HPD pulse. The HPD signal is pulled low, initiating the first low-level pulse of 1.5-4 seconds. The actual duration of the low-level pulse is determined by the discharge time of the internal capacitor of bridge chip 31 (approximately 2-3 seconds).

[0093] The link controller 23 monitors the falling edge of the HPD, records the start time of the first pulse, and starts a 30-second monitoring window. When the first pulse ends, it measures the pulse duration and verifies that the duration is within 1.5-4 seconds, confirming that the first pulse is valid, and sets the pulse counter to 1.

[0094] Wait 2-3 seconds to ensure the bridge chip 31 is fully discharged, then restore power to the reset pin of the bridge chip 31. The bridge chip 31 is reinitialized, and the HPD pin returns to a high level. A "first reset complete" signal is sent to the signal source 10 via the USB cable 40.

[0095] III. Multi-level reset and coordinated recovery phase.

[0096] 1. Second anomaly detection.

[0097] At the end of another 12-second cycle, the VR real-time program unit 12 detected again that the video stream had not been restored, and sent the first reset command to the VR headset for the second time via the USB cable 40.

[0098] 2. Signal re-timer 22 triggers the second reset.

[0099] The VR headset executes the first reset operation a second time based on the first reset command, repeating the power-off-power-on process and generating a second 1.5-4s HPD low-level pulse.

[0100] If the link controller 23 detects the second HPD falling edge and it is still within the 30-second time window, it records the start time of the second pulse. When the second pulse ends, it measures the pulse duration and verifies that it is within 1.5-4 seconds, confirming the second pulse is valid, and sets the pulse counter to 2.

[0101] If all conditions are met, namely, the predetermined time window includes 30 seconds, the predetermined quantity includes 2, and the predetermined duration is greater than or equal to 1.5 seconds and less than or equal to 4 seconds, the power supply to the signal re-timer 22 is cut off, and after waiting for a period of time to ensure that the signal re-timer 22 is completely reset, the power supply to the signal re-timer 22 is restored, allowing the signal re-timer 22 to be reinitialized.

[0102] Link controller 23 clears the monitoring data and prepares for the next test.

[0103] Fourth, mechanisms for handling and protecting against extreme situations.

[0104] 1. Scenario involving multiple resets.

[0105] If the first reset of signal retimer 22 fails to resolve the issue, VR real-time program unit 12 will continue to detect and trigger bridge chip 31 to reset every 12 seconds. Every two resets of bridge chip 31 will trigger a reset of signal retimer 22.

[0106] The maximum number of resets for the bridge chip 31 is 10, and correspondingly, the maximum number of resets for the signal re-timer 22 is 5. Actual testing shows that usually one reset of the signal re-timer 22 is sufficient to resolve the issue.

[0107] 2. Protection mechanism activated.

[0108] If the display error persists after the bridge chip 31 has been reset 10 times, the VR real-time program unit 12 will stop automatically resetting the bridge chip 31, log the error, and notify the user, advising them to check the physical connections to prevent an infinite loop.

[0109] This application also provides a control device for a split-type display system. Figure 7 This is a structural block diagram of a control device for a split-type display system provided in an embodiment of this application. Figure 7 As shown, the control device 60 of the split-type display system includes: a first trigger module 61, a generation module 62, and a second trigger module 63. The first trigger module 61 is configured to trigger a first reset operation of the display device 30 in response to a display abnormality signal. The generation module 62 is configured to generate a status indication signal of the transmission link 20 based on the first reset operation. The second trigger module 63 is configured to trigger a second reset operation of the transmission link 20 when the status indication signal meets preset conditions.

[0110] In one embodiment, the display device 30 includes a bridge chip 31. A first trigger module 61 is specifically configured to trigger a first reset operation of the bridge chip 31 in response to a display abnormality signal from the display device 30.

[0111] In one embodiment, the status indication signal includes the HPD signal of the bridging chip 31. The second trigger module 63 is specifically configured to trigger a second reset operation of the transmission link 20 if a predetermined pulse pattern of the HPD signal is detected within a preset time window.

[0112] For example, if a hot-plug detection signal is detected with a predetermined number of pull-down pulses within a predetermined time window, and the duration of the pull-down pulses is within a predetermined duration, a second reset operation of the transmission link is triggered. The predetermined time window includes 30 seconds; and / or, the predetermined number includes 2; and / or, the predetermined duration is greater than or equal to 1.5 seconds and less than or equal to 4 seconds.

[0113] In one embodiment, the transmission link 20 includes a PD connection line 21, a signal re-timer 22 connected to the PD connection line 21, and a link controller 23. In this case, the second trigger module 63 is specifically configured to trigger a second reset operation of the signal re-timer 22 when the status indication signal meets a preset condition.

[0114] It should be noted that the control device 60 of the split display system provided in this application embodiment and the control method of the split display system provided in this application embodiment belong to the same inventive concept. Technical details not described in the control device embodiment of the split display system can be found in the control method embodiment of the split display system, and will not be repeated here.

[0115] This application also provides an electronic device. Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application. Figure 8 As shown, the electronic device 70 includes a processor 71 and a memory 72. The memory 72 stores a computer program, which, when executed by the processor 71, implements the control method of the split display system provided in any embodiment of this application. This electronic device can be a test device, a simulation platform, or any embedded device requiring service arbitration functionality.

[0116] The processor 71 may include one or more cores for processing data. The processor 71 connects to the display device 30 and the signal retimer 22 via various interfaces and lines. It executes various functions of the split-type display system's control method and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 72, and by calling data stored in the memory 72. Optionally, the processor 71 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 71 may integrate one or more of the following: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 71 and may be implemented separately using a communication chip.

[0117] The memory 72 may include random access memory (RAM) or read-only memory (ROM). The memory 72 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 72 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described below.

[0118] This application also provides a computer-readable storage medium. Figure 9 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. For example... Figure 9 As shown, a computer-readable storage medium 90 stores a computer program 91, which, when executed by a processor, is used to implement the control method of the split display system provided in any embodiment of the application.

[0119] The computer-readable storage medium 91 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 91 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 91 has storage space for program code that performs any of the method steps described above. This program code can be read from or written to one or more computer program products. The program code may be compressed, for example, in a suitable form.

[0120] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0121] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A control method of a split display system, characterized by, The split display system comprises a signal source, a transmission link and a display device, and the control method comprises: in response to a display abnormal signal of the display device, triggering a first reset operation of the display device; generating a state indication signal of the transmission link based on the first reset operation; if the state indication signal meets a preset condition, triggering a second reset operation of the transmission link.

2. The control method according to claim 1, characterized by, The display device comprises a bridge chip; and the response to the display abnormal signal of the display device to trigger the first reset operation of the display device comprises: in response to the display abnormal signal of the display device, triggering a first reset operation of the bridge chip.

3. The control method according to claim 2, characterized by, The state indication signal comprises a hot plug detection signal of the bridge chip; and if the state indication signal meets a preset condition, triggering a second reset operation of the transmission link comprises: if a predetermined pulse mode of the hot plug detection signal is monitored within a preset time window, triggering the second reset operation of the transmission link.

4. The control method according to claim 3, characterized by, If a predetermined time window is detected, the hot plug detection signal has a predetermined number of pull-down pulses, and the duration of the pull-down pulse is within a predetermined time range, the second reset operation of the transmission link is triggered. The predetermined time window comprises 30 seconds; and / or 5. The control method according to claim 4, characterized by The predetermined number comprises 2; and / or The predetermined time length is greater than or equal to 1.5 seconds and less than or equal to 4 seconds. The transmission link comprises a display interface connection line, a signal retimer and a link controller connected with the display interface connection line; and if the state indication signal meets a preset condition, triggering a second reset operation of the transmission link comprises:

6. The control method according to claim 1, characterized by if the state indication signal meets a preset condition, the link controller triggers a second reset operation of the signal retimer. Further comprising a USB power line, the USB power line and the link controller are electrically connected.

7. The control method according to claim 6, characterized by Further comprising:

8. The control method according to claim 1, characterized by, when the number of executions of the second reset operation is greater than a predetermined number, stopping executing the first reset operation. The split display system comprises a signal source, a transmission link and a display device, and the control device comprises:

9. A control device for a split display system, characterized by a first trigger module configured to trigger a first reset operation of the display device in response to a display abnormal signal of the display device; a generation module configured to generate a state indication signal of the transmission link based on the first reset operation; a second trigger module configured to trigger a second reset operation of the transmission link if the state indication signal meets a preset condition. comprises a signal source, a transmission link and a display device; wherein 10. A split display system, characterized by, the signal source is configured to detect a display abnormal signal of the display device and trigger a first reset operation of the display device; the display device is configured to execute the first reset operation and generate a state indication signal of the transmission link based on the first reset operation; ​ The transmission link comprises a display interface connection line, a link controller and a signal re-timer connected with the display interface connection line respectively, and the link controller is configured to trigger a second reset operation of the signal re-timer when the state indication signal meets a preset condition.

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